rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

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Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }	module rockettile_icache_tag_array_0( // @[DescribedSRAM.scala:17:26] input [5:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [167:0] RW0_wdata, output [167:0] RW0_rdata, input [7:0] RW0_wmask ); rockettile_icache_tag_array_ext rockettile_icache_tag_array_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_309( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) && (vcalloc_q.io.enq.ready \|\| !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_\|\|_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }	module IngressUnit_51( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_10, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_11, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_12, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_13, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_14, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_15, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_16, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_17, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_18, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_19, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_20, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_10, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_11, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_14, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_15, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_18, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_19, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_20, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_21, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [5:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_10; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_11; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_12; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_13; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_14; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_15; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_16; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_17; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_18; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_19; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_20; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_21; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 6'h28; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 6'h2B; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 6'h2E; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 6'h31; // @[IngressUnit.scala:30:72] wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_53( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File dcache.scala: //***************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc, Transpose} class BoomWritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new WritebackReq(edge.bundle))) val meta_read = Decoupled(new L1MetaReadReq) val resp = Output(Bool()) val idx = Output(Valid(UInt())) val data_req = Decoupled(new L1DataReadReq) val data_resp = Input(UInt(encRowBits.W)) val mem_grant = Input(Bool()) val release = Decoupled(new TLBundleC(edge.bundle)) val lsu_release = Decoupled(new TLBundleC(edge.bundle)) }) val req = Reg(new WritebackReq(edge.bundle)) val s_invalid :: s_fill_buffer :: s_lsu_release :: s_active :: s_grant :: Nil = Enum(5) val state = RegInit(s_invalid) val r1_data_req_fired = RegInit(false.B) val r2_data_req_fired = RegInit(false.B) val r1_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W)) val r2_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W)) val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W)) val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release) val wb_buffer = Reg(Vec(refillCycles, UInt(encRowBits.W))) val acked = RegInit(false.B) io.idx.valid := state =/= s_invalid io.idx.bits := req.idx io.release.valid := false.B io.release.bits := DontCare io.req.ready := false.B io.meta_read.valid := false.B io.meta_read.bits := DontCare io.data_req.valid := false.B io.data_req.bits := DontCare io.resp := false.B io.lsu_release.valid := false.B io.lsu_release.bits := DontCare val r_address = Cat(req.tag, req.idx) << blockOffBits val id = cfg.nMSHRs val probeResponse = edge.ProbeAck( fromSource = id.U, toAddress = r_address, lgSize = lgCacheBlockBytes.U, reportPermissions = req.param, data = wb_buffer(data_req_cnt)) val voluntaryRelease = edge.Release( fromSource = id.U, toAddress = r_address, lgSize = lgCacheBlockBytes.U, shrinkPermissions = req.param, data = wb_buffer(data_req_cnt))._2 when (state === s_invalid) { io.req.ready := true.B when (io.req.fire) { state := s_fill_buffer data_req_cnt := 0.U req := io.req.bits acked := false.B } } .elsewhen (state === s_fill_buffer) { io.meta_read.valid := data_req_cnt < refillCycles.U io.meta_read.bits.idx := req.idx io.meta_read.bits.tag := req.tag io.data_req.valid := data_req_cnt < refillCycles.U io.data_req.bits.way_en := req.way_en io.data_req.bits.addr := (if(refillCycles > 1) Cat(req.idx, data_req_cnt(log2Up(refillCycles)-1,0)) else req.idx) << rowOffBits r1_data_req_fired := false.B r1_data_req_cnt := 0.U r2_data_req_fired := r1_data_req_fired r2_data_req_cnt := r1_data_req_cnt when (io.data_req.fire && io.meta_read.fire) { r1_data_req_fired := true.B r1_data_req_cnt := data_req_cnt data_req_cnt := data_req_cnt + 1.U } when (r2_data_req_fired) { wb_buffer(r2_data_req_cnt) := io.data_resp when (r2_data_req_cnt === (refillCycles-1).U) { io.resp := true.B state := s_lsu_release data_req_cnt := 0.U } } } .elsewhen (state === s_lsu_release) { io.lsu_release.valid := true.B io.lsu_release.bits := probeResponse when (io.lsu_release.fire) { state := s_active } } .elsewhen (state === s_active) { io.release.valid := data_req_cnt < refillCycles.U io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse) when (io.mem_grant) { acked := true.B } when (io.release.fire) { data_req_cnt := data_req_cnt + 1.U } when ((data_req_cnt === (refillCycles-1).U) && io.release.fire) { state := Mux(req.voluntary, s_grant, s_invalid) } } .elsewhen (state === s_grant) { when (io.mem_grant) { acked := true.B } when (acked) { state := s_invalid } } } class BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new TLBundleB(edge.bundle))) val rep = Decoupled(new TLBundleC(edge.bundle)) val meta_read = Decoupled(new L1MetaReadReq) val meta_write = Decoupled(new L1MetaWriteReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val way_en = Input(UInt(nWays.W)) val wb_rdy = Input(Bool()) // Is writeback unit currently busy? If so need to retry meta read when its done val mshr_rdy = Input(Bool()) // Is MSHR ready for this request to proceed? val mshr_wb_rdy = Output(Bool()) // Should we block MSHR writebacks while we finish our own? val block_state = Input(new ClientMetadata()) val lsu_release = Decoupled(new TLBundleC(edge.bundle)) val state = Output(Valid(UInt(coreMaxAddrBits.W))) }) val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_mshr_resp :: s_lsu_release :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: s_meta_write_resp :: Nil) = Enum(11) val state = RegInit(s_invalid) val req = Reg(new TLBundleB(edge.bundle)) val req_idx = req.address(idxMSB, idxLSB) val req_tag = req.address >> untagBits val way_en = Reg(UInt()) val tag_matches = way_en.orR val old_coh = Reg(new ClientMetadata) val miss_coh = ClientMetadata.onReset val reply_coh = Mux(tag_matches, old_coh, miss_coh) val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param) io.state.valid := state =/= s_invalid io.state.bits := req.address io.req.ready := state === s_invalid io.rep.valid := state === s_release io.rep.bits := edge.ProbeAck(req, report_param) assert(!io.rep.valid \|\| !edge.hasData(io.rep.bits), "ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it") io.meta_read.valid := state === s_meta_read io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := ~(0.U(nWays.W)) io.meta_write.valid := state === s_meta_write io.meta_write.bits.way_en := way_en io.meta_write.bits.idx := req_idx io.meta_write.bits.tag := req_tag io.meta_write.bits.data.tag := req_tag io.meta_write.bits.data.coh := new_coh io.wb_req.valid := state === s_writeback_req io.wb_req.bits.source := req.source io.wb_req.bits.idx := req_idx io.wb_req.bits.tag := req_tag io.wb_req.bits.param := report_param io.wb_req.bits.way_en := way_en io.wb_req.bits.voluntary := false.B io.mshr_wb_rdy := !state.isOneOf(s_release, s_writeback_req, s_writeback_resp, s_meta_write, s_meta_write_resp) io.lsu_release.valid := state === s_lsu_release io.lsu_release.bits := edge.ProbeAck(req, report_param) // state === s_invalid when (state === s_invalid) { when (io.req.fire) { state := s_meta_read req := io.req.bits } } .elsewhen (state === s_meta_read) { when (io.meta_read.fire) { state := s_meta_resp } } .elsewhen (state === s_meta_resp) { // we need to wait one cycle for the metadata to be read from the array state := s_mshr_req } .elsewhen (state === s_mshr_req) { old_coh := io.block_state way_en := io.way_en // if the read didn't go through, we need to retry state := Mux(io.mshr_rdy && io.wb_rdy, s_mshr_resp, s_meta_read) } .elsewhen (state === s_mshr_resp) { state := Mux(tag_matches && is_dirty, s_writeback_req, s_lsu_release) } .elsewhen (state === s_lsu_release) { when (io.lsu_release.fire) { state := s_release } } .elsewhen (state === s_release) { when (io.rep.ready) { state := Mux(tag_matches, s_meta_write, s_invalid) } } .elsewhen (state === s_writeback_req) { when (io.wb_req.fire) { state := s_writeback_resp } } .elsewhen (state === s_writeback_resp) { // wait for the writeback request to finish before updating the metadata when (io.wb_req.ready) { state := s_meta_write } } .elsewhen (state === s_meta_write) { when (io.meta_write.fire) { state := s_meta_write_resp } } .elsewhen (state === s_meta_write_resp) { state := s_invalid } } class BoomL1MetaReadReq(implicit p: Parameters) extends BoomBundle()(p) { val req = Vec(memWidth, new L1MetaReadReq) } class BoomL1DataReadReq(implicit p: Parameters) extends BoomBundle()(p) { val req = Vec(memWidth, new L1DataReadReq) val valid = Vec(memWidth, Bool()) } abstract class AbstractBoomDataArray(implicit p: Parameters) extends BoomModule with HasL1HellaCacheParameters { val io = IO(new BoomBundle { val read = Input(Vec(memWidth, Valid(new L1DataReadReq))) val write = Input(Valid(new L1DataWriteReq)) val resp = Output(Vec(memWidth, Vec(nWays, Bits(encRowBits.W)))) val nacks = Output(Vec(memWidth, Bool())) }) def pipeMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) } class BoomDuplicatedDataArray(implicit p: Parameters) extends AbstractBoomDataArray { val waddr = io.write.bits.addr >> rowOffBits for (j <- 0 until memWidth) { val raddr = io.read(j).bits.addr >> rowOffBits for (w <- 0 until nWays) { val array = DescribedSRAM( name = s"array_${w}_${j}", desc = "Non-blocking DCache Data Array", size = nSets * refillCycles, data = Vec(rowWords, Bits(encDataBits.W)) ) when (io.write.bits.way_en(w) && io.write.valid) { val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits(i+1)-1,encDataBitsi))) array.write(waddr, data, io.write.bits.wmask.asBools) } io.resp(j)(w) := RegNext(array.read(raddr, io.read(j).bits.way_en(w) && io.read(j).valid).asUInt) } io.nacks(j) := false.B } } class BoomBankedDataArray(implicit p: Parameters) extends AbstractBoomDataArray { val nBanks = boomParams.numDCacheBanks val bankSize = nSets * refillCycles / nBanks require (nBanks >= memWidth) require (bankSize > 0) val bankBits = log2Ceil(nBanks) val bankOffBits = log2Ceil(rowWords) + log2Ceil(wordBytes) val bidxBits = log2Ceil(bankSize) val bidxOffBits = bankOffBits + bankBits //---------------------------------------------------------------------------------------------------- val s0_rbanks = if (nBanks > 1) VecInit(io.read.map(r => (r.bits.addr >> bankOffBits)(bankBits-1,0))) else VecInit(0.U) val s0_wbank = if (nBanks > 1) (io.write.bits.addr >> bankOffBits)(bankBits-1,0) else 0.U val s0_ridxs = VecInit(io.read.map(r => (r.bits.addr >> bidxOffBits)(bidxBits-1,0))) val s0_widx = (io.write.bits.addr >> bidxOffBits)(bidxBits-1,0) val s0_read_valids = VecInit(io.read.map(_.valid)) val s0_bank_conflicts = pipeMap(w => (0 until w).foldLeft(false.B)((c,i) => c \|\| io.read(i).valid && s0_rbanks(i) === s0_rbanks(w))) val s0_do_bank_read = s0_read_valids zip s0_bank_conflicts map {case (v,c) => v && !c} val s0_bank_read_gnts = Transpose(VecInit(s0_rbanks zip s0_do_bank_read map {case (b,d) => VecInit((UIntToOH(b) & Fill(nBanks,d)).asBools)})) val s0_bank_write_gnt = (UIntToOH(s0_wbank) & Fill(nBanks, io.write.valid)).asBools //---------------------------------------------------------------------------------------------------- val s1_rbanks = RegNext(s0_rbanks) val s1_ridxs = RegNext(s0_ridxs) val s1_read_valids = RegNext(s0_read_valids) val s1_pipe_selection = pipeMap(i => VecInit(PriorityEncoderOH(pipeMap(j => if (j < i) s1_read_valids(j) && s1_rbanks(j) === s1_rbanks(i) else if (j == i) true.B else false.B)))) val s1_ridx_match = pipeMap(i => pipeMap(j => if (j < i) s1_ridxs(j) === s1_ridxs(i) else if (j == i) true.B else false.B)) val s1_nacks = pipeMap(w => s1_read_valids(w) && (s1_pipe_selection(w).asUInt & ~s1_ridx_match(w).asUInt).orR) val s1_bank_selection = pipeMap(w => Mux1H(s1_pipe_selection(w), s1_rbanks)) //---------------------------------------------------------------------------------------------------- val s2_bank_selection = RegNext(s1_bank_selection) val s2_nacks = RegNext(s1_nacks) for (w <- 0 until nWays) { val s2_bank_reads = Reg(Vec(nBanks, Bits(encRowBits.W))) for (b <- 0 until nBanks) { val array = DescribedSRAM( name = s"array_${w}_${b}", desc = "Non-blocking DCache Data Array", size = bankSize, data = Vec(rowWords, Bits(encDataBits.W)) ) val ridx = Mux1H(s0_bank_read_gnts(b), s0_ridxs) val way_en = Mux1H(s0_bank_read_gnts(b), io.read.map(_.bits.way_en)) s2_bank_reads(b) := array.read(ridx, way_en(w) && s0_bank_read_gnts(b).reduce(_\|\|_)).asUInt when (io.write.bits.way_en(w) && s0_bank_write_gnt(b)) { val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits(i+1)-1,encDataBitsi))) array.write(s0_widx, data, io.write.bits.wmask.asBools) } } for (i <- 0 until memWidth) { io.resp(i)(w) := s2_bank_reads(s2_bank_selection(i)) } } io.nacks := s2_nacks } /** * Top level class wrapping a non-blocking dcache. * * @param hartid hardware thread for the cache / class BoomNonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule { private val tileParams = p(TileKey) protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${staticIdForMetadataUseOnly} DCache", sourceId = IdRange(0, 1 max (cfg.nMSHRs + 1)), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${staticIdForMetadataUseOnly} DCache MMIO", sourceId = IdRange(cfg.nMSHRs + 1, cfg.nMSHRs + 1 + cfg.nMMIOs), requestFifo = true)) val node = TLClientNode(Seq(TLMasterPortParameters.v1( cacheClientParameters ++ mmioClientParameters, minLatency = 1))) lazy val module = new BoomNonBlockingDCacheModule(this) def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireT \|\| !m.executable \|\| m.regionType >= RegionType.TRACKED \|\| m.regionType <= RegionType.IDEMPOTENT) require(!tileParams.core.haveCFlush \|\| cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class BoomDCacheBundle(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { val lsu = Flipped(new LSUDMemIO) } class BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters with HasBoomCoreParameters { implicit val edge = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new BoomDCacheBundle) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees ${m.nodePath.map(_.name)}") } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val t_replay :: t_probe :: t_wb :: t_mshr_meta_read :: t_lsu :: t_prefetch :: Nil = Enum(6) val wb = Module(new BoomWritebackUnit) val prober = Module(new BoomProbeUnit) val mshrs = Module(new BoomMSHRFile) mshrs.io.clear_all := io.lsu.force_order mshrs.io.brupdate := io.lsu.brupdate mshrs.io.exception := io.lsu.exception mshrs.io.rob_pnr_idx := io.lsu.rob_pnr_idx mshrs.io.rob_head_idx := io.lsu.rob_head_idx // tags def onReset = L1Metadata(0.U, ClientMetadata.onReset) val meta = Seq.fill(memWidth) { Module(new L1MetadataArray(onReset _)) } val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2)) // 0 goes to MSHR refills, 1 goes to prober val metaReadArb = Module(new Arbiter(new BoomL1MetaReadReq, 6)) // 0 goes to MSHR replays, 1 goes to prober, 2 goes to wb, 3 goes to MSHR meta read, // 4 goes to pipeline, 5 goes to prefetcher metaReadArb.io.in := DontCare for (w <- 0 until memWidth) { meta(w).io.write.valid := metaWriteArb.io.out.fire meta(w).io.write.bits := metaWriteArb.io.out.bits meta(w).io.read.valid := metaReadArb.io.out.valid meta(w).io.read.bits := metaReadArb.io.out.bits.req(w) } metaReadArb.io.out.ready := meta.map(_.io.read.ready).reduce(_\|\|_) metaWriteArb.io.out.ready := meta.map(_.io.write.ready).reduce(_\|\|_) // data val data = Module(if (boomParams.numDCacheBanks == 1) new BoomDuplicatedDataArray else new BoomBankedDataArray) val dataWriteArb = Module(new Arbiter(new L1DataWriteReq, 2)) // 0 goes to pipeline, 1 goes to MSHR refills val dataReadArb = Module(new Arbiter(new BoomL1DataReadReq, 3)) // 0 goes to MSHR replays, 1 goes to wb, 2 goes to pipeline dataReadArb.io.in := DontCare for (w <- 0 until memWidth) { data.io.read(w).valid := dataReadArb.io.out.bits.valid(w) && dataReadArb.io.out.valid data.io.read(w).bits := dataReadArb.io.out.bits.req(w) } dataReadArb.io.out.ready := true.B data.io.write.valid := dataWriteArb.io.out.fire data.io.write.bits := dataWriteArb.io.out.bits dataWriteArb.io.out.ready := true.B // ------------ // New requests io.lsu.req.ready := metaReadArb.io.in(4).ready && dataReadArb.io.in(2).ready metaReadArb.io.in(4).valid := io.lsu.req.valid dataReadArb.io.in(2).valid := io.lsu.req.valid for (w <- 0 until memWidth) { // Tag read for new requests metaReadArb.io.in(4).bits.req(w).idx := io.lsu.req.bits(w).bits.addr >> blockOffBits metaReadArb.io.in(4).bits.req(w).way_en := DontCare metaReadArb.io.in(4).bits.req(w).tag := DontCare // Data read for new requests dataReadArb.io.in(2).bits.valid(w) := io.lsu.req.bits(w).valid dataReadArb.io.in(2).bits.req(w).addr := io.lsu.req.bits(w).bits.addr dataReadArb.io.in(2).bits.req(w).way_en := ~0.U(nWays.W) } // ------------ // MSHR Replays val replay_req = Wire(Vec(memWidth, new BoomDCacheReq)) replay_req := DontCare replay_req(0).uop := mshrs.io.replay.bits.uop replay_req(0).addr := mshrs.io.replay.bits.addr replay_req(0).data := mshrs.io.replay.bits.data replay_req(0).is_hella := mshrs.io.replay.bits.is_hella mshrs.io.replay.ready := metaReadArb.io.in(0).ready && dataReadArb.io.in(0).ready // Tag read for MSHR replays // We don't actually need to read the metadata, for replays we already know our way metaReadArb.io.in(0).valid := mshrs.io.replay.valid metaReadArb.io.in(0).bits.req(0).idx := mshrs.io.replay.bits.addr >> blockOffBits metaReadArb.io.in(0).bits.req(0).way_en := DontCare metaReadArb.io.in(0).bits.req(0).tag := DontCare // Data read for MSHR replays dataReadArb.io.in(0).valid := mshrs.io.replay.valid dataReadArb.io.in(0).bits.req(0).addr := mshrs.io.replay.bits.addr dataReadArb.io.in(0).bits.req(0).way_en := mshrs.io.replay.bits.way_en dataReadArb.io.in(0).bits.valid := widthMap(w => (w == 0).B) // ----------- // MSHR Meta read val mshr_read_req = Wire(Vec(memWidth, new BoomDCacheReq)) mshr_read_req := DontCare mshr_read_req(0).uop := NullMicroOp mshr_read_req(0).addr := Cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx) << blockOffBits mshr_read_req(0).data := DontCare mshr_read_req(0).is_hella := false.B metaReadArb.io.in(3).valid := mshrs.io.meta_read.valid metaReadArb.io.in(3).bits.req(0) := mshrs.io.meta_read.bits mshrs.io.meta_read.ready := metaReadArb.io.in(3).ready // ----------- // Write-backs val wb_fire = wb.io.meta_read.fire && wb.io.data_req.fire val wb_req = Wire(Vec(memWidth, new BoomDCacheReq)) wb_req := DontCare wb_req(0).uop := NullMicroOp wb_req(0).addr := Cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr) wb_req(0).data := DontCare wb_req(0).is_hella := false.B // Couple the two decoupled interfaces of the WBUnit's meta_read and data_read // Tag read for write-back metaReadArb.io.in(2).valid := wb.io.meta_read.valid metaReadArb.io.in(2).bits.req(0) := wb.io.meta_read.bits wb.io.meta_read.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready // Data read for write-back dataReadArb.io.in(1).valid := wb.io.data_req.valid dataReadArb.io.in(1).bits.req(0) := wb.io.data_req.bits dataReadArb.io.in(1).bits.valid := widthMap(w => (w == 0).B) wb.io.data_req.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire)) // ------- // Prober val prober_fire = prober.io.meta_read.fire val prober_req = Wire(Vec(memWidth, new BoomDCacheReq)) prober_req := DontCare prober_req(0).uop := NullMicroOp prober_req(0).addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << blockOffBits prober_req(0).data := DontCare prober_req(0).is_hella := false.B // Tag read for prober metaReadArb.io.in(1).valid := prober.io.meta_read.valid metaReadArb.io.in(1).bits.req(0) := prober.io.meta_read.bits prober.io.meta_read.ready := metaReadArb.io.in(1).ready // Prober does not need to read data array // ------- // Prefetcher val prefetch_fire = mshrs.io.prefetch.fire val prefetch_req = Wire(Vec(memWidth, new BoomDCacheReq)) prefetch_req := DontCare prefetch_req(0) := mshrs.io.prefetch.bits // Tag read for prefetch metaReadArb.io.in(5).valid := mshrs.io.prefetch.valid metaReadArb.io.in(5).bits.req(0).idx := mshrs.io.prefetch.bits.addr >> blockOffBits metaReadArb.io.in(5).bits.req(0).way_en := DontCare metaReadArb.io.in(5).bits.req(0).tag := DontCare mshrs.io.prefetch.ready := metaReadArb.io.in(5).ready // Prefetch does not need to read data array val s0_valid = Mux(io.lsu.req.fire, VecInit(io.lsu.req.bits.map(_.valid)), Mux(mshrs.io.replay.fire \|\| wb_fire \|\| prober_fire \|\| prefetch_fire \|\| mshrs.io.meta_read.fire, VecInit(1.U(memWidth.W).asBools), VecInit(0.U(memWidth.W).asBools))) val s0_req = Mux(io.lsu.req.fire , VecInit(io.lsu.req.bits.map(_.bits)), Mux(wb_fire , wb_req, Mux(prober_fire , prober_req, Mux(prefetch_fire , prefetch_req, Mux(mshrs.io.meta_read.fire, mshr_read_req , replay_req))))) val s0_type = Mux(io.lsu.req.fire , t_lsu, Mux(wb_fire , t_wb, Mux(prober_fire , t_probe, Mux(prefetch_fire , t_prefetch, Mux(mshrs.io.meta_read.fire, t_mshr_meta_read , t_replay))))) // Does this request need to send a response or nack val s0_send_resp_or_nack = Mux(io.lsu.req.fire, s0_valid, VecInit(Mux(mshrs.io.replay.fire && isRead(mshrs.io.replay.bits.uop.mem_cmd), 1.U(memWidth.W), 0.U(memWidth.W)).asBools)) val s1_req = RegNext(s0_req) for (w <- 0 until memWidth) s1_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s0_req(w).uop) val s2_store_failed = Wire(Bool()) val s1_valid = widthMap(w => RegNext(s0_valid(w) && !IsKilledByBranch(io.lsu.brupdate, s0_req(w).uop) && !(io.lsu.exception && s0_req(w).uop.uses_ldq) && !(s2_store_failed && io.lsu.req.fire && s0_req(w).uop.uses_stq), init=false.B)) for (w <- 0 until memWidth) assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid))) val s1_addr = s1_req.map(_.addr) val s1_nack = s1_addr.map(a => a(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready) val s1_send_resp_or_nack = RegNext(s0_send_resp_or_nack) val s1_type = RegNext(s0_type) val s1_mshr_meta_read_way_en = RegNext(mshrs.io.meta_read.bits.way_en) val s1_replay_way_en = RegNext(mshrs.io.replay.bits.way_en) // For replays, the metadata isn't written yet val s1_wb_way_en = RegNext(wb.io.data_req.bits.way_en) // tag check def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f)) val s1_tag_eq_way = widthMap(i => wayMap((w: Int) => meta(i).io.resp(w).tag === (s1_addr(i) >> untagBits)).asUInt) val s1_tag_match_way = widthMap(i => Mux(s1_type === t_replay, s1_replay_way_en, Mux(s1_type === t_wb, s1_wb_way_en, Mux(s1_type === t_mshr_meta_read, s1_mshr_meta_read_way_en, wayMap((w: Int) => s1_tag_eq_way(i)(w) && meta(i).io.resp(w).coh.isValid()).asUInt)))) val s1_wb_idx_matches = widthMap(i => (s1_addr(i)(untagBits-1,blockOffBits) === wb.io.idx.bits) && wb.io.idx.valid) val s2_req = RegNext(s1_req) val s2_type = RegNext(s1_type) val s2_valid = widthMap(w => RegNext(s1_valid(w) && !io.lsu.s1_kill(w) && !IsKilledByBranch(io.lsu.brupdate, s1_req(w).uop) && !(io.lsu.exception && s1_req(w).uop.uses_ldq) && !(s2_store_failed && (s1_type === t_lsu) && s1_req(w).uop.uses_stq))) for (w <- 0 until memWidth) s2_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s1_req(w).uop) val s2_tag_match_way = RegNext(s1_tag_match_way) val s2_tag_match = s2_tag_match_way.map(_.orR) val s2_hit_state = widthMap(i => Mux1H(s2_tag_match_way(i), wayMap((w: Int) => RegNext(meta(i).io.resp(w).coh)))) val s2_has_permission = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._1) val s2_new_hit_state = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._3) val s2_hit = widthMap(w => (s2_tag_match(w) && s2_has_permission(w) && s2_hit_state(w) === s2_new_hit_state(w) && !mshrs.io.block_hit(w)) \|\| s2_type.isOneOf(t_replay, t_wb)) val s2_nack = Wire(Vec(memWidth, Bool())) assert(!(s2_type === t_replay && !s2_hit(0)), "Replays should always hit") assert(!(s2_type === t_wb && !s2_hit(0)), "Writeback should always see data hit") val s2_wb_idx_matches = RegNext(s1_wb_idx_matches) // lr/sc val debug_sc_fail_addr = RegInit(0.U) val debug_sc_fail_cnt = RegInit(0.U(8.W)) val lrsc_count = RegInit(0.U(log2Ceil(lrscCycles).W)) val lrsc_valid = lrsc_count > lrscBackoff.U val lrsc_addr = Reg(UInt()) val s2_lr = s2_req(0).uop.mem_cmd === M_XLR && (!RegNext(s1_nack(0)) \|\| s2_type === t_replay) val s2_sc = s2_req(0).uop.mem_cmd === M_XSC && (!RegNext(s1_nack(0)) \|\| s2_type === t_replay) val s2_lrsc_addr_match = widthMap(w => lrsc_valid && lrsc_addr === (s2_req(w).addr >> blockOffBits)) val s2_sc_fail = s2_sc && !s2_lrsc_addr_match(0) when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U } when (s2_valid(0) && ((s2_type === t_lsu && s2_hit(0) && !s2_nack(0)) \|\| (s2_type === t_replay && s2_req(0).uop.mem_cmd =/= M_FLUSH_ALL))) { when (s2_lr) { lrsc_count := (lrscCycles - 1).U lrsc_addr := s2_req(0).addr >> blockOffBits } when (lrsc_count > 0.U) { lrsc_count := 0.U } } for (w <- 0 until memWidth) { when (s2_valid(w) && s2_type === t_lsu && !s2_hit(w) && !(s2_has_permission(w) && s2_tag_match(w)) && s2_lrsc_addr_match(w) && !s2_nack(w)) { lrsc_count := 0.U } } when (s2_valid(0)) { when (s2_req(0).addr === debug_sc_fail_addr) { when (s2_sc_fail) { debug_sc_fail_cnt := debug_sc_fail_cnt + 1.U } .elsewhen (s2_sc) { debug_sc_fail_cnt := 0.U } } .otherwise { when (s2_sc_fail) { debug_sc_fail_addr := s2_req(0).addr debug_sc_fail_cnt := 1.U } } } assert(debug_sc_fail_cnt < 100.U, "L1DCache failed too many SCs in a row") val s2_data = Wire(Vec(memWidth, Vec(nWays, UInt(encRowBits.W)))) for (i <- 0 until memWidth) { for (w <- 0 until nWays) { s2_data(i)(w) := data.io.resp(i)(w) } } val s2_data_muxed = widthMap(w => Mux1H(s2_tag_match_way(w), s2_data(w))) val s2_word_idx = widthMap(w => if (rowWords == 1) 0.U else s2_req(w).addr(log2Up(rowWordswordBytes)-1, log2Up(wordBytes))) // replacement policy val replacer = cacheParams.replacement val s1_replaced_way_en = UIntToOH(replacer.way) val s2_replaced_way_en = UIntToOH(RegNext(replacer.way)) val s2_repl_meta = widthMap(i => Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegNext(meta(i).io.resp(w))).toSeq)) // nack because of incoming probe val s2_nack_hit = RegNext(VecInit(s1_nack)) // Nack when we hit something currently being evicted val s2_nack_victim = widthMap(w => s2_valid(w) && s2_hit(w) && mshrs.io.secondary_miss(w)) // MSHRs not ready for request val s2_nack_miss = widthMap(w => s2_valid(w) && !s2_hit(w) && !mshrs.io.req(w).ready) // Bank conflict on data arrays val s2_nack_data = widthMap(w => data.io.nacks(w)) // Can't allocate MSHR for same set currently being written back val s2_nack_wb = widthMap(w => s2_valid(w) && !s2_hit(w) && s2_wb_idx_matches(w)) s2_nack := widthMap(w => (s2_nack_miss(w) \|\| s2_nack_hit(w) \|\| s2_nack_victim(w) \|\| s2_nack_data(w) \|\| s2_nack_wb(w)) && s2_type =/= t_replay) val s2_send_resp = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && !s2_nack(w) && (s2_hit(w) \|\| (mshrs.io.req(w).fire && isWrite(s2_req(w).uop.mem_cmd) && !isRead(s2_req(w).uop.mem_cmd))))) val s2_send_nack = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && s2_nack(w))) for (w <- 0 until memWidth) assert(!(s2_send_resp(w) && s2_send_nack(w))) // hits always send a response // If MSHR is not available, LSU has to replay this request later // If MSHR is available and this is only a store(not a amo), we don't need to wait for resp later s2_store_failed := s2_valid(0) && s2_nack(0) && s2_send_nack(0) && s2_req(0).uop.uses_stq // Miss handling for (w <- 0 until memWidth) { mshrs.io.req(w).valid := s2_valid(w) && !s2_hit(w) && !s2_nack_hit(w) && !s2_nack_victim(w) && !s2_nack_data(w) && !s2_nack_wb(w) && s2_type.isOneOf(t_lsu, t_prefetch) && !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) && !(io.lsu.exception && s2_req(w).uop.uses_ldq) && (isPrefetch(s2_req(w).uop.mem_cmd) \|\| isRead(s2_req(w).uop.mem_cmd) \|\| isWrite(s2_req(w).uop.mem_cmd)) assert(!(mshrs.io.req(w).valid && s2_type === t_replay), "Replays should not need to go back into MSHRs") mshrs.io.req(w).bits := DontCare mshrs.io.req(w).bits.uop := s2_req(w).uop mshrs.io.req(w).bits.uop.br_mask := GetNewBrMask(io.lsu.brupdate, s2_req(w).uop) mshrs.io.req(w).bits.addr := s2_req(w).addr mshrs.io.req(w).bits.tag_match := s2_tag_match(w) mshrs.io.req(w).bits.old_meta := Mux(s2_tag_match(w), L1Metadata(s2_repl_meta(w).tag, s2_hit_state(w)), s2_repl_meta(w)) mshrs.io.req(w).bits.way_en := Mux(s2_tag_match(w), s2_tag_match_way(w), s2_replaced_way_en) mshrs.io.req(w).bits.data := s2_req(w).data mshrs.io.req(w).bits.is_hella := s2_req(w).is_hella mshrs.io.req_is_probe(w) := s2_type === t_probe && s2_valid(w) } mshrs.io.meta_resp.valid := !s2_nack_hit(0) \|\| prober.io.mshr_wb_rdy mshrs.io.meta_resp.bits := Mux1H(s2_tag_match_way(0), RegNext(meta(0).io.resp)) when (mshrs.io.req.map(_.fire).reduce(_\|\|_)) { replacer.miss } tl_out.a <> mshrs.io.mem_acquire // probes and releases prober.io.req.valid := tl_out.b.valid && !lrsc_valid tl_out.b.ready := prober.io.req.ready && !lrsc_valid prober.io.req.bits := tl_out.b.bits prober.io.way_en := s2_tag_match_way(0) prober.io.block_state := s2_hit_state(0) metaWriteArb.io.in(1) <> prober.io.meta_write prober.io.mshr_rdy := mshrs.io.probe_rdy prober.io.wb_rdy := (prober.io.meta_write.bits.idx =/= wb.io.idx.bits) \|\| !wb.io.idx.valid mshrs.io.prober_state := prober.io.state // refills when (tl_out.d.bits.source === cfg.nMSHRs.U) { // This should be ReleaseAck tl_out.d.ready := true.B mshrs.io.mem_grant.valid := false.B mshrs.io.mem_grant.bits := DontCare } .otherwise { // This should be GrantData mshrs.io.mem_grant <> tl_out.d } dataWriteArb.io.in(1) <> mshrs.io.refill metaWriteArb.io.in(0) <> mshrs.io.meta_write tl_out.e <> mshrs.io.mem_finish // writebacks val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle), 2)) // 0 goes to prober, 1 goes to MSHR evictions wbArb.io.in(0) <> prober.io.wb_req wbArb.io.in(1) <> mshrs.io.wb_req wb.io.req <> wbArb.io.out wb.io.data_resp := s2_data_muxed(0) mshrs.io.wb_resp := wb.io.resp wb.io.mem_grant := tl_out.d.fire && tl_out.d.bits.source === cfg.nMSHRs.U val lsu_release_arb = Module(new Arbiter(new TLBundleC(edge.bundle), 2)) io.lsu.release <> lsu_release_arb.io.out lsu_release_arb.io.in(0) <> wb.io.lsu_release lsu_release_arb.io.in(1) <> prober.io.lsu_release TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep) io.lsu.perf.release := edge.done(tl_out.c) io.lsu.perf.acquire := edge.done(tl_out.a) // load data gen val s2_data_word_prebypass = widthMap(w => s2_data_muxed(w) >> Cat(s2_word_idx(w), 0.U(log2Ceil(coreDataBits).W))) val s2_data_word = Wire(Vec(memWidth, UInt())) val loadgen = (0 until memWidth).map { w => new LoadGen(s2_req(w).uop.mem_size, s2_req(w).uop.mem_signed, s2_req(w).addr, s2_data_word(w), s2_sc && (w == 0).B, wordBytes) } // Mux between cache responses and uncache responses val cache_resp = Wire(Vec(memWidth, Valid(new BoomDCacheResp))) for (w <- 0 until memWidth) { cache_resp(w).valid := s2_valid(w) && s2_send_resp(w) cache_resp(w).bits.uop := s2_req(w).uop cache_resp(w).bits.data := loadgen(w).data \| s2_sc_fail cache_resp(w).bits.is_hella := s2_req(w).is_hella } val uncache_resp = Wire(Valid(new BoomDCacheResp)) uncache_resp.bits := mshrs.io.resp.bits uncache_resp.valid := mshrs.io.resp.valid mshrs.io.resp.ready := !(cache_resp.map(_.valid).reduce(_&&_)) // We can backpressure the MSHRs, but not cache hits val resp = WireInit(cache_resp) var uncache_responding = false.B for (w <- 0 until memWidth) { val uncache_respond = !cache_resp(w).valid && !uncache_responding when (uncache_respond) { resp(w) := uncache_resp } uncache_responding = uncache_responding \|\| uncache_respond } for (w <- 0 until memWidth) { io.lsu.resp(w).valid := resp(w).valid && !(io.lsu.exception && resp(w).bits.uop.uses_ldq) && !IsKilledByBranch(io.lsu.brupdate, resp(w).bits.uop) io.lsu.resp(w).bits := UpdateBrMask(io.lsu.brupdate, resp(w).bits) io.lsu.nack(w).valid := s2_valid(w) && s2_send_nack(w) && !(io.lsu.exception && s2_req(w).uop.uses_ldq) && !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) io.lsu.nack(w).bits := UpdateBrMask(io.lsu.brupdate, s2_req(w)) assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu)) } // Store/amo hits val s3_req = RegNext(s2_req(0)) val s3_valid = RegNext(s2_valid(0) && s2_hit(0) && isWrite(s2_req(0).uop.mem_cmd) && !s2_sc_fail && !(s2_send_nack(0) && s2_nack(0))) for (w <- 1 until memWidth) { assert(!(s2_valid(w) && s2_hit(w) && isWrite(s2_req(w).uop.mem_cmd) && !s2_sc_fail && !(s2_send_nack(w) && s2_nack(w))), "Store must go through 0th pipe in L1D") } // For bypassing val s4_req = RegNext(s3_req) val s4_valid = RegNext(s3_valid) val s5_req = RegNext(s4_req) val s5_valid = RegNext(s4_valid) val s3_bypass = widthMap(w => s3_valid && ((s2_req(w).addr >> wordOffBits) === (s3_req.addr >> wordOffBits))) val s4_bypass = widthMap(w => s4_valid && ((s2_req(w).addr >> wordOffBits) === (s4_req.addr >> wordOffBits))) val s5_bypass = widthMap(w => s5_valid && ((s2_req(w).addr >> wordOffBits) === (s5_req.addr >> wordOffBits))) // Store -> Load bypassing for (w <- 0 until memWidth) { s2_data_word(w) := Mux(s3_bypass(w), s3_req.data, Mux(s4_bypass(w), s4_req.data, Mux(s5_bypass(w), s5_req.data, s2_data_word_prebypass(w)))) } val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := new StoreGen(s2_req(0).uop.mem_size, s2_req(0).addr, 0.U, xLen/8).mask amoalu.io.cmd := s2_req(0).uop.mem_cmd amoalu.io.lhs := s2_data_word(0) amoalu.io.rhs := s2_req(0).data s3_req.data := amoalu.io.out val s3_way = RegNext(s2_tag_match_way(0)) dataWriteArb.io.in(0).valid := s3_valid dataWriteArb.io.in(0).bits.addr := s3_req.addr dataWriteArb.io.in(0).bits.wmask := UIntToOH(s3_req.addr.extract(rowOffBits-1,offsetlsb)) dataWriteArb.io.in(0).bits.data := Fill(rowWords, s3_req.data) dataWriteArb.io.in(0).bits.way_en := s3_way io.lsu.ordered := mshrs.io.fence_rdy && !s1_valid.reduce(_\|\|_) && !s2_valid.reduce(_\|\|_) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module BoomWritebackUnit( // @[dcache.scala:24:7] input clock, // @[dcache.scala:24:7] input reset, // @[dcache.scala:24:7] output io_req_ready, // @[dcache.scala:25:14] input io_req_valid, // @[dcache.scala:25:14] input [19:0] io_req_bits_tag, // @[dcache.scala:25:14] input [5:0] io_req_bits_idx, // @[dcache.scala:25:14] input [1:0] io_req_bits_source, // @[dcache.scala:25:14] input [2:0] io_req_bits_param, // @[dcache.scala:25:14] input [3:0] io_req_bits_way_en, // @[dcache.scala:25:14] input io_req_bits_voluntary, // @[dcache.scala:25:14] input io_meta_read_ready, // @[dcache.scala:25:14] output io_meta_read_valid, // @[dcache.scala:25:14] output [5:0] io_meta_read_bits_idx, // @[dcache.scala:25:14] output [19:0] io_meta_read_bits_tag, // @[dcache.scala:25:14] output io_resp, // @[dcache.scala:25:14] output io_idx_valid, // @[dcache.scala:25:14] output [5:0] io_idx_bits, // @[dcache.scala:25:14] input io_data_req_ready, // @[dcache.scala:25:14] output io_data_req_valid, // @[dcache.scala:25:14] output [3:0] io_data_req_bits_way_en, // @[dcache.scala:25:14] output [11:0] io_data_req_bits_addr, // @[dcache.scala:25:14] input [63:0] io_data_resp, // @[dcache.scala:25:14] input io_mem_grant, // @[dcache.scala:25:14] input io_release_ready, // @[dcache.scala:25:14] output io_release_valid, // @[dcache.scala:25:14] output [2:0] io_release_bits_opcode, // @[dcache.scala:25:14] output [2:0] io_release_bits_param, // @[dcache.scala:25:14] output [31:0] io_release_bits_address, // @[dcache.scala:25:14] output [63:0] io_release_bits_data, // @[dcache.scala:25:14] input io_lsu_release_ready, // @[dcache.scala:25:14] output io_lsu_release_valid, // @[dcache.scala:25:14] output [2:0] io_lsu_release_bits_param, // @[dcache.scala:25:14] output [31:0] io_lsu_release_bits_address, // @[dcache.scala:25:14] output [63:0] io_lsu_release_bits_data // @[dcache.scala:25:14] ); reg [2:0] state; // @[dcache.scala:39:22] wire io_req_valid_0 = io_req_valid; // @[dcache.scala:24:7] wire [19:0] io_req_bits_tag_0 = io_req_bits_tag; // @[dcache.scala:24:7] wire [5:0] io_req_bits_idx_0 = io_req_bits_idx; // @[dcache.scala:24:7] wire [1:0] io_req_bits_source_0 = io_req_bits_source; // @[dcache.scala:24:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[dcache.scala:24:7] wire [3:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[dcache.scala:24:7] wire io_req_bits_voluntary_0 = io_req_bits_voluntary; // @[dcache.scala:24:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[dcache.scala:24:7] wire io_data_req_ready_0 = io_data_req_ready; // @[dcache.scala:24:7] wire [63:0] io_data_resp_0 = io_data_resp; // @[dcache.scala:24:7] wire io_mem_grant_0 = io_mem_grant; // @[dcache.scala:24:7] wire io_release_ready_0 = io_release_ready; // @[dcache.scala:24:7] wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:24:7] wire [26:0] _r_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _r_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [8:0] r_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire _voluntaryRelease_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _voluntaryRelease_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire [2:0] voluntaryRelease_opcode = 3'h7; // @[Edges.scala:396:17] wire [2:0] io_lsu_release_bits_opcode = 3'h5; // @[dcache.scala:24:7] wire [2:0] probeResponse_opcode = 3'h5; // @[Edges.scala:433:17] wire io_release_bits_corrupt = 1'h0; // @[dcache.scala:24:7] wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:24:7] wire probeResponse_corrupt = 1'h0; // @[Edges.scala:433:17] wire _voluntaryRelease_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _voluntaryRelease_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _voluntaryRelease_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire voluntaryRelease_corrupt = 1'h0; // @[Edges.scala:396:17] wire _io_release_bits_T_corrupt = 1'h0; // @[dcache.scala:124:27] wire [1:0] io_release_bits_source = 2'h2; // @[dcache.scala:24:7] wire [1:0] io_lsu_release_bits_source = 2'h2; // @[dcache.scala:24:7] wire [1:0] probeResponse_source = 2'h2; // @[Edges.scala:433:17] wire [1:0] voluntaryRelease_source = 2'h2; // @[Edges.scala:396:17] wire [1:0] _io_release_bits_T_source = 2'h2; // @[dcache.scala:124:27] wire [3:0] io_release_bits_size = 4'h6; // @[dcache.scala:24:7] wire [3:0] io_lsu_release_bits_size = 4'h6; // @[dcache.scala:24:7] wire [3:0] probeResponse_size = 4'h6; // @[Edges.scala:433:17] wire [3:0] voluntaryRelease_size = 4'h6; // @[Edges.scala:396:17] wire [3:0] _io_release_bits_T_size = 4'h6; // @[dcache.scala:124:27] wire [3:0] io_meta_read_bits_way_en = 4'h0; // @[dcache.scala:24:7] wire io_req_ready_0 = ~(\|state); // @[dcache.scala:24:7, :39:22, :49:31, :80:15] wire _io_idx_valid_T; // @[dcache.scala:49:31] wire [11:0] _io_data_req_bits_addr_T_2; // @[dcache.scala:97:43] wire [2:0] _io_release_bits_T_opcode; // @[dcache.scala:124:27] wire [2:0] _io_release_bits_T_param; // @[dcache.scala:124:27] wire [31:0] _io_release_bits_T_address; // @[dcache.scala:124:27] wire [63:0] _io_release_bits_T_data; // @[dcache.scala:124:27] wire [2:0] probeResponse_param; // @[Edges.scala:433:17] wire [31:0] probeResponse_address; // @[Edges.scala:433:17] wire [63:0] probeResponse_data; // @[Edges.scala:433:17] wire [5:0] io_meta_read_bits_idx_0; // @[dcache.scala:24:7] wire [19:0] io_meta_read_bits_tag_0; // @[dcache.scala:24:7] wire io_meta_read_valid_0; // @[dcache.scala:24:7] wire io_idx_valid_0; // @[dcache.scala:24:7] wire [5:0] io_idx_bits_0; // @[dcache.scala:24:7] wire [3:0] io_data_req_bits_way_en_0; // @[dcache.scala:24:7] wire [11:0] io_data_req_bits_addr_0; // @[dcache.scala:24:7] wire io_data_req_valid_0; // @[dcache.scala:24:7] wire [2:0] io_release_bits_opcode_0; // @[dcache.scala:24:7] wire [2:0] io_release_bits_param_0; // @[dcache.scala:24:7] wire [31:0] io_release_bits_address_0; // @[dcache.scala:24:7] wire [63:0] io_release_bits_data_0; // @[dcache.scala:24:7] wire io_release_valid_0; // @[dcache.scala:24:7] wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:24:7] wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:24:7] wire [63:0] io_lsu_release_bits_data_0; // @[dcache.scala:24:7] wire io_lsu_release_valid_0; // @[dcache.scala:24:7] wire io_resp_0; // @[dcache.scala:24:7] reg [19:0] req_tag; // @[dcache.scala:37:16] assign io_meta_read_bits_tag_0 = req_tag; // @[dcache.scala:24:7, :37:16] reg [5:0] req_idx; // @[dcache.scala:37:16] assign io_meta_read_bits_idx_0 = req_idx; // @[dcache.scala:24:7, :37:16] assign io_idx_bits_0 = req_idx; // @[dcache.scala:24:7, :37:16] reg [1:0] req_source; // @[dcache.scala:37:16] reg [2:0] req_param; // @[dcache.scala:37:16] assign probeResponse_param = req_param; // @[Edges.scala:433:17] wire [2:0] voluntaryRelease_param = req_param; // @[Edges.scala:396:17] reg [3:0] req_way_en; // @[dcache.scala:37:16] assign io_data_req_bits_way_en_0 = req_way_en; // @[dcache.scala:24:7, :37:16] reg req_voluntary; // @[dcache.scala:37:16] reg r1_data_req_fired; // @[dcache.scala:40:34] reg r2_data_req_fired; // @[dcache.scala:41:34] reg [3:0] r1_data_req_cnt; // @[dcache.scala:42:28] reg [3:0] r2_data_req_cnt; // @[dcache.scala:43:28] reg [3:0] data_req_cnt; // @[dcache.scala:44:29] wire _T_14 = io_release_ready_0 & io_release_valid_0; // @[Decoupled.scala:51:35] wire r_beats1_opdata = io_release_bits_opcode_0[0]; // @[Edges.scala:102:36] wire [8:0] r_beats1 = r_beats1_opdata ? 9'h7 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire last_beat = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire all_beats_done = last_beat & _T_14; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] beat_count = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [63:0] wb_buffer_0; // @[dcache.scala:46:22] reg [63:0] wb_buffer_1; // @[dcache.scala:46:22] reg [63:0] wb_buffer_2; // @[dcache.scala:46:22] reg [63:0] wb_buffer_3; // @[dcache.scala:46:22] reg [63:0] wb_buffer_4; // @[dcache.scala:46:22] reg [63:0] wb_buffer_5; // @[dcache.scala:46:22] reg [63:0] wb_buffer_6; // @[dcache.scala:46:22] reg [63:0] wb_buffer_7; // @[dcache.scala:46:22] reg acked; // @[dcache.scala:47:22] assign _io_idx_valid_T = \|state; // @[dcache.scala:39:22, :49:31] assign io_idx_valid_0 = _io_idx_valid_T; // @[dcache.scala:24:7, :49:31] wire [25:0] _r_address_T = {req_tag, req_idx}; // @[dcache.scala:37:16, :63:22] wire [31:0] r_address = {_r_address_T, 6'h0}; // @[dcache.scala:63:{22,41}] assign probeResponse_address = r_address; // @[Edges.scala:433:17] wire [31:0] _voluntaryRelease_legal_T_1 = r_address; // @[Parameters.scala:137:31] wire [31:0] voluntaryRelease_address = r_address; // @[Edges.scala:396:17] wire [2:0] _probeResponse_T = data_req_cnt[2:0]; // @[dcache.scala:44:29] wire [2:0] _voluntaryRelease_T = data_req_cnt[2:0]; // @[dcache.scala:44:29] wire [2:0] _io_data_req_bits_addr_T = data_req_cnt[2:0]; // @[dcache.scala:44:29, :96:56] assign io_lsu_release_bits_param_0 = probeResponse_param; // @[Edges.scala:433:17] assign io_lsu_release_bits_address_0 = probeResponse_address; // @[Edges.scala:433:17] assign io_lsu_release_bits_data_0 = probeResponse_data; // @[Edges.scala:433:17] wire [7:0][63:0] _GEN = {{wb_buffer_7}, {wb_buffer_6}, {wb_buffer_5}, {wb_buffer_4}, {wb_buffer_3}, {wb_buffer_2}, {wb_buffer_1}, {wb_buffer_0}}; // @[Edges.scala:441:15] assign probeResponse_data = _GEN[_probeResponse_T]; // @[Edges.scala:433:17, :441:15] wire [32:0] _voluntaryRelease_legal_T_2 = {1'h0, _voluntaryRelease_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_3 = _voluntaryRelease_legal_T_2 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_4 = _voluntaryRelease_legal_T_3; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_5 = _voluntaryRelease_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _voluntaryRelease_legal_T_6 = {r_address[31:17], r_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] _voluntaryRelease_legal_T_7 = {1'h0, _voluntaryRelease_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_8 = _voluntaryRelease_legal_T_7 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_9 = _voluntaryRelease_legal_T_8; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_10 = _voluntaryRelease_legal_T_9 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _voluntaryRelease_legal_T_11 = {r_address[31:28], r_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] _voluntaryRelease_legal_T_12 = {1'h0, _voluntaryRelease_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_13 = _voluntaryRelease_legal_T_12 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_14 = _voluntaryRelease_legal_T_13; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_15 = _voluntaryRelease_legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _voluntaryRelease_legal_T_16 = _voluntaryRelease_legal_T_5 \| _voluntaryRelease_legal_T_10; // @[Parameters.scala:685:42] wire _voluntaryRelease_legal_T_17 = _voluntaryRelease_legal_T_16 \| _voluntaryRelease_legal_T_15; // @[Parameters.scala:685:42] wire [31:0] _voluntaryRelease_legal_T_21 = {r_address[31:28], r_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] _voluntaryRelease_legal_T_22 = {1'h0, _voluntaryRelease_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_23 = _voluntaryRelease_legal_T_22 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_24 = _voluntaryRelease_legal_T_23; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_25 = _voluntaryRelease_legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _voluntaryRelease_legal_T_26 = r_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _voluntaryRelease_legal_T_27 = {1'h0, _voluntaryRelease_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_28 = _voluntaryRelease_legal_T_27 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_29 = _voluntaryRelease_legal_T_28; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_30 = _voluntaryRelease_legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _voluntaryRelease_legal_T_31 = _voluntaryRelease_legal_T_25 \| _voluntaryRelease_legal_T_30; // @[Parameters.scala:685:42] wire _voluntaryRelease_legal_T_32 = _voluntaryRelease_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire voluntaryRelease_legal = _voluntaryRelease_legal_T_32; // @[Parameters.scala:684:54, :686:26] wire [63:0] voluntaryRelease_data; // @[Edges.scala:396:17] assign voluntaryRelease_data = _GEN[_voluntaryRelease_T]; // @[Edges.scala:396:17, :404:15, :441:15] wire _T_3 = state == 3'h1; // @[dcache.scala:39:22, :88:22] wire _io_meta_read_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40] assign io_meta_read_valid_0 = (\|state) & _T_3 & _io_meta_read_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :54:22, :80:30, :88:{22,41}, :89:{24,40}] wire _io_data_req_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40, :93:39] assign io_data_req_valid_0 = (\|state) & _T_3 & _io_data_req_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :56:22, :80:30, :88:{22,41}, :93:{23,39}] wire [8:0] _io_data_req_bits_addr_T_1 = {req_idx, _io_data_req_bits_addr_T}; // @[dcache.scala:37:16, :96:{34,56}] assign _io_data_req_bits_addr_T_2 = {_io_data_req_bits_addr_T_1, 3'h0}; // @[dcache.scala:96:34, :97:43] assign io_data_req_bits_addr_0 = _io_data_req_bits_addr_T_2; // @[dcache.scala:24:7, :97:43] wire [4:0] _GEN_0 = {1'h0, data_req_cnt} + 5'h1; // @[dcache.scala:44:29, :106:36] wire [4:0] _data_req_cnt_T; // @[dcache.scala:106:36] assign _data_req_cnt_T = _GEN_0; // @[dcache.scala:106:36] wire [4:0] _data_req_cnt_T_2; // @[dcache.scala:130:36] assign _data_req_cnt_T_2 = _GEN_0; // @[dcache.scala:106:36, :130:36] wire [3:0] _data_req_cnt_T_1 = _data_req_cnt_T[3:0]; // @[dcache.scala:106:36] wire _T_8 = r2_data_req_cnt == 4'h7; // @[dcache.scala:43:28, :110:29] assign io_resp_0 = (\|state) & _T_3 & r2_data_req_fired & _T_8; // @[dcache.scala:24:7, :39:22, :41:34, :49:31, :58:22, :80:30, :88:{22,41}, :108:30, :110:{29,53}] wire _T_9 = state == 3'h2; // @[dcache.scala:39:22, :116:22] assign io_lsu_release_valid_0 = ~(~(\|state) \| _T_3) & _T_9; // @[dcache.scala:24:7, :39:22, :49:31, :59:24, :80:{15,30}, :88:{22,41}, :116:{22,41}] wire _T_11 = state == 3'h3; // @[dcache.scala:39:22, :122:22] wire _io_release_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40, :123:38] wire _GEN_1 = _T_3 \| _T_9; // @[dcache.scala:51:22, :88:{22,41}, :116:{22,41}, :122:36] assign io_release_valid_0 = ~(~(\|state) \| _GEN_1) & _T_11 & _io_release_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :51:22, :80:{15,30}, :88:41, :116:41, :122:{22,36}, :123:{22,38}] assign _io_release_bits_T_opcode = {1'h1, req_voluntary, 1'h1}; // @[dcache.scala:37:16, :124:27] assign _io_release_bits_T_param = req_voluntary ? voluntaryRelease_param : probeResponse_param; // @[Edges.scala:396:17, :433:17] assign _io_release_bits_T_address = req_voluntary ? voluntaryRelease_address : probeResponse_address; // @[Edges.scala:396:17, :433:17] assign _io_release_bits_T_data = req_voluntary ? voluntaryRelease_data : probeResponse_data; // @[Edges.scala:396:17, :433:17] assign io_release_bits_opcode_0 = _io_release_bits_T_opcode; // @[dcache.scala:24:7, :124:27] assign io_release_bits_param_0 = _io_release_bits_T_param; // @[dcache.scala:24:7, :124:27] assign io_release_bits_address_0 = _io_release_bits_T_address; // @[dcache.scala:24:7, :124:27] assign io_release_bits_data_0 = _io_release_bits_T_data; // @[dcache.scala:24:7, :124:27] wire [3:0] _data_req_cnt_T_3 = _data_req_cnt_T_2[3:0]; // @[dcache.scala:130:36] wire [2:0] _state_T = {req_voluntary, 2'h0}; // @[dcache.scala:37:16, :133:19] wire _T_16 = state == 3'h4; // @[dcache.scala:39:22, :135:22] wire _T_2 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_2 = (\|state) & _T_3; // @[dcache.scala:39:22, :41:34, :49:31, :80:30, :88:{22,41}] wire _T_6 = io_data_req_ready_0 & io_data_req_valid_0 & io_meta_read_ready_0 & io_meta_read_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[dcache.scala:24:7] if (~(\|state) & _T_2) begin // @[Decoupled.scala:51:35] req_tag <= io_req_bits_tag_0; // @[dcache.scala:24:7, :37:16] req_idx <= io_req_bits_idx_0; // @[dcache.scala:24:7, :37:16] req_source <= io_req_bits_source_0; // @[dcache.scala:24:7, :37:16] req_param <= io_req_bits_param_0; // @[dcache.scala:24:7, :37:16] req_way_en <= io_req_bits_way_en_0; // @[dcache.scala:24:7, :37:16] req_voluntary <= io_req_bits_voluntary_0; // @[dcache.scala:24:7, :37:16] end if (_GEN_2) begin // @[dcache.scala:41:34, :43:28, :80:30, :88:41] r1_data_req_cnt <= _T_6 ? data_req_cnt : 4'h0; // @[Decoupled.scala:51:35] r2_data_req_cnt <= r1_data_req_cnt; // @[dcache.scala:42:28, :43:28] end if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h0) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_0 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h1) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_1 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h2) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_2 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h3) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_3 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h4) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_4 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h5) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_5 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h6) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_6 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((\|state) & _T_3 & r2_data_req_fired & (&(r2_data_req_cnt[2:0]))) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_7 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if (reset) begin // @[dcache.scala:24:7] state <= 3'h0; // @[dcache.scala:39:22] r1_data_req_fired <= 1'h0; // @[dcache.scala:40:34] r2_data_req_fired <= 1'h0; // @[dcache.scala:41:34] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] r_counter <= 9'h0; // @[Edges.scala:229:27] acked <= 1'h0; // @[dcache.scala:47:22] end else begin // @[dcache.scala:24:7] if (\|state) begin // @[dcache.scala:39:22, :49:31] if (_T_3) begin // @[dcache.scala:88:22] if (r2_data_req_fired & _T_8) begin // @[dcache.scala:39:22, :41:34, :108:30, :110:{29,53}, :112:15] state <= 3'h2; // @[dcache.scala:39:22] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] end else if (_T_6) // @[Decoupled.scala:51:35] data_req_cnt <= _data_req_cnt_T_1; // @[dcache.scala:44:29, :106:36] end else begin // @[dcache.scala:88:22] if (_T_9) begin // @[dcache.scala:116:22] if (io_lsu_release_ready_0 & io_lsu_release_valid_0) // @[Decoupled.scala:51:35] state <= 3'h3; // @[dcache.scala:39:22] end else if (_T_11) begin // @[dcache.scala:122:22] if (data_req_cnt == 4'h7 & _T_14) // @[Decoupled.scala:51:35] state <= _state_T; // @[dcache.scala:39:22, :133:19] end else if (_T_16 & acked) // @[dcache.scala:39:22, :47:22, :135:{22,35}, :139:18, :140:13] state <= 3'h0; // @[dcache.scala:39:22] if (_T_9 \| ~(_T_11 & _T_14)) begin // @[Decoupled.scala:51:35] end else // @[dcache.scala:44:29, :116:41, :122:36] data_req_cnt <= _data_req_cnt_T_3; // @[dcache.scala:44:29, :130:36] end if (~_GEN_1) // @[dcache.scala:51:22, :88:41, :116:41, :122:36] acked <= _T_11 ? io_mem_grant_0 \| acked : _T_16 & io_mem_grant_0 \| acked; // @[dcache.scala:24:7, :47:22, :122:{22,36}, :126:25, :127:13, :135:{22,35}, :136:25, :137:13] end else begin // @[dcache.scala:49:31] if (_T_2) begin // @[Decoupled.scala:51:35] state <= 3'h1; // @[dcache.scala:39:22] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] end acked <= ~_T_2 & acked; // @[Decoupled.scala:51:35] end if (_GEN_2) begin // @[dcache.scala:41:34, :80:30, :88:41] r1_data_req_fired <= _T_6; // @[Decoupled.scala:51:35] r2_data_req_fired <= r1_data_req_fired; // @[dcache.scala:40:34, :41:34] end if (_T_14) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] end always @(posedge) assign io_req_ready = io_req_ready_0; // @[dcache.scala:24:7] assign io_meta_read_valid = io_meta_read_valid_0; // @[dcache.scala:24:7] assign io_meta_read_bits_idx = io_meta_read_bits_idx_0; // @[dcache.scala:24:7] assign io_meta_read_bits_tag = io_meta_read_bits_tag_0; // @[dcache.scala:24:7] assign io_resp = io_resp_0; // @[dcache.scala:24:7] assign io_idx_valid = io_idx_valid_0; // @[dcache.scala:24:7] assign io_idx_bits = io_idx_bits_0; // @[dcache.scala:24:7] assign io_data_req_valid = io_data_req_valid_0; // @[dcache.scala:24:7] assign io_data_req_bits_way_en = io_data_req_bits_way_en_0; // @[dcache.scala:24:7] assign io_data_req_bits_addr = io_data_req_bits_addr_0; // @[dcache.scala:24:7] assign io_release_valid = io_release_valid_0; // @[dcache.scala:24:7] assign io_release_bits_opcode = io_release_bits_opcode_0; // @[dcache.scala:24:7] assign io_release_bits_param = io_release_bits_param_0; // @[dcache.scala:24:7] assign io_release_bits_address = io_release_bits_address_0; // @[dcache.scala:24:7] assign io_release_bits_data = io_release_bits_data_0; // @[dcache.scala:24:7] assign io_lsu_release_valid = io_lsu_release_valid_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_param = io_lsu_release_bits_param_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_address = io_lsu_release_bits_address_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_data = io_lsu_release_bits_data_0; // @[dcache.scala:24:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_470( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tilelink.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLMasterToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2)) a.io.protocol <> io.tilelink.a io.tilelink.b <> b.io.protocol c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol e.io.protocol <> io.tilelink.e io.flits.a <> a.io.flit b.io.flit <> io.flits.b io.flits.c <> c.io.flit d.io.flit <> io.flits.d io.flits.e <> e.io.flit } class TLMasterACDToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) a.io.protocol <> io.tilelink.a c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol io.flits.a <> a.io.flit io.flits.c <> c.io.flit d.io.flit <> io.flits.d } class TLMasterBEToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0)) io.tilelink.b <> b.io.protocol e.io.protocol <> io.tilelink.e b.io.flit <> io.flits.b io.flits.e <> e.io.flit } class TLSlaveToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val b = Decoupled(new IngressFlit(flitWidth)) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) io.tilelink.a <> a.io.protocol b.io.protocol <> io.tilelink.b io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d io.tilelink.e <> e.io.protocol a.io.flit <> io.flits.a io.flits.b <> b.io.flit c.io.flit <> io.flits.c io.flits.d <> d.io.flit e.io.flit <> io.flits.e } class TLSlaveACDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart)) io.tilelink.a <> a.io.protocol io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d a.io.flit <> io.flits.a c.io.flit <> io.flits.c io.flits.d <> d.io.flit } class TLSlaveBEToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val b = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) b.io.protocol <> io.tilelink.b io.tilelink.e <> e.io.protocol io.flits.b <> b.io.flit e.io.flit <> io.flits.e } class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle { val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) }) val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) }) } trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper { def edgesIn: Seq[TLEdge] def edgesOut: Seq[TLEdge] def edgeInNodes: Seq[Int] def edgeOutNodes: Seq[Int] require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size) def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle)) def genBundle = new TLBundle(wideBundle) def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut) } object TLConnect { def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = { l.valid := r.valid r.ready := l.ready l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll } } // BEGIN: TileLinkProtocolParams case class TileLinkABCDEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int] ) extends TileLinkProtocolParams { // END: TileLinkProtocolParams val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten val nVirtualNetworks = 5 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A (if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B (if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D (if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { edgesIn.zipWithIndex.map { case (e,i) => val nif_master = Module(new TLMasterToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 3 + edgesIn.size * 2 + egressOffset, minPayloadWidth )) nif_master.io.tilelink := DontCare nif_master.io.tilelink.a.valid := false.B nif_master.io.tilelink.c.valid := false.B nif_master.io.tilelink.e.valid := false.B TLConnect(nif_master.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master.io.tilelink.b) TLConnect(nif_master.io.tilelink.c, protocol.in(i).c) TLConnect(nif_master.io.tilelink.e, protocol.in(i).e) } ingresses(i * 3 + 0).flit <> nif_master.io.flits.a ingresses(i * 3 + 1).flit <> nif_master.io.flits.c ingresses(i * 3 + 2).flit <> nif_master.io.flits.e nif_master.io.flits.b <> egresses(i * 2 + 0).flit nif_master.io.flits.d <> egresses(i * 2 + 1).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave = Module(new TLSlaveToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 2 + egressOffset, minPayloadWidth )) nif_slave.io.tilelink := DontCare nif_slave.io.tilelink.b.valid := false.B nif_slave.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a) TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b) TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c) TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e) } ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit } } } } } case class TileLinkACDProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val nVirtualNetworks = 3 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A (if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_acd = Module(new TLMasterACDToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 2 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_acd.io.tilelink := DontCare nif_master_acd.io.tilelink.a.valid := false.B nif_master_acd.io.tilelink.c.valid := false.B nif_master_acd.io.tilelink.e.valid := false.B TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c) } ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_acd = Module(new TLSlaveACDToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_acd.io.tilelink := DontCare nif_slave_acd.io.tilelink.b.valid := false.B nif_slave_acd.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a) TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c) } ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit } }} } } case class TileLinkBEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val nVirtualNetworks = 2 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B (if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_be = Module(new TLMasterBEToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 1 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_be.io.tilelink := DontCare nif_master_be.io.tilelink.a.valid := false.B nif_master_be.io.tilelink.c.valid := false.B nif_master_be.io.tilelink.e.valid := false.B if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b) TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e) } ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_be = Module(new TLSlaveBEToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_be.io.tilelink := DontCare nif_slave_be.io.tilelink.b.valid := false.B nif_slave_be.io.tilelink.d.valid := false.B if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e) TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b) } ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit } }} } } abstract class TLNoCLike(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") // TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers port.managers map { manager => manager.v1copy(fifoId = None) } } ) } ) } abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) { val edgesIn: Seq[TLEdge] val edgesOut: Seq[TLEdge] val nodeMapping: DiplomaticNetworkNodeMapping val nocName: String lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name))) lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name))) lazy val edgeInNodes = nodeMapping.getNodesIn(inNames) lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames) def printNodeMappings() { println(s"Constellation: TLNoC $nocName inwards mapping:") for ((n, i) <- inNames zip edgeInNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } println(s"Constellation: TLNoC $nocName outwards mapping:") for ((n, i) <- outNames zip edgeOutNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } } } trait TLNoCParams // Instantiates a private TLNoC. Replaces the TLXbar // BEGIN: TLNoCParams case class SimpleTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, nocParams: NoCParams = NoCParams(), ) extends TLNoCParams class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { // END: TLNoCParams override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val noc = Module(new ProtocolNoC(ProtocolNoCParams( params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC), Seq(protocolParams), inlineNoC = inlineNoC ))) noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } } case class SplitACDxBETLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, acdNoCParams: NoCParams = NoCParams(), beNoCParams: NoCParams = NoCParams(), beDivision: Int = 2 ) extends TLNoCParams class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val acdProtocolParams = TileLinkACDProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val beProtocolParams = TileLinkBEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC), Seq(acdProtocolParams), inlineNoC = inlineNoC ))) val be_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC), Seq(beProtocolParams), widthDivision = params.beDivision, inlineNoC = inlineNoC ))) acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } }} be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.b <> r.b l.e <> r.e } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.b <> r.b l.e <> r.e } }} } } case class GlobalTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping ) extends TLNoCParams // Maps this interconnect onto a global NoC class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike { lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) printNodeMappings() val io_global = IO(Flipped(protocolParams.genIO())) io_global match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } }	module TLMasterToNoC_2( // @[Tilelink.scala:37:7] input clock, // @[Tilelink.scala:37:7] input reset, // @[Tilelink.scala:37:7] output io_tilelink_a_ready, // @[Tilelink.scala:44:14] input io_tilelink_a_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:44:14] input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_d_ready, // @[Tilelink.scala:44:14] output io_tilelink_d_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_d_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_sink, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:44:14] input io_flits_a_ready, // @[Tilelink.scala:44:14] output io_flits_a_valid, // @[Tilelink.scala:44:14] output io_flits_a_bits_head, // @[Tilelink.scala:44:14] output io_flits_a_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:44:14] output [3:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_b_ready, // @[Tilelink.scala:44:14] input io_flits_b_valid, // @[Tilelink.scala:44:14] input io_flits_b_bits_head, // @[Tilelink.scala:44:14] input io_flits_b_bits_tail, // @[Tilelink.scala:44:14] output io_flits_d_ready, // @[Tilelink.scala:44:14] input io_flits_d_valid, // @[Tilelink.scala:44:14] input io_flits_d_bits_head, // @[Tilelink.scala:44:14] input io_flits_d_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_d_bits_payload // @[Tilelink.scala:44:14] ); TLAToNoC_2 a ( // @[Tilelink.scala:54:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:54:17] TLBFromNoC b ( // @[Tilelink.scala:55:17] .clock (clock), .reset (reset), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail) ); // @[Tilelink.scala:55:17] TLDFromNoC d ( // @[Tilelink.scala:57:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:68:14] ); // @[Tilelink.scala:57:17] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RegisterFile.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import freechips.rocketchip.util._ import saturn.common._ class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { val io = IO(new ArbiterIO(new VectorReadReq, n)) val arb = Module(new RRArbiter(new VectorReadReq, n)) io <> arb.io val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) //assert(PopCount(oldest_oh) <= 1.U) when (oldest_oh.orR) { io.chosen := VecInit(oldest_oh).asUInt io.out.valid := true.B io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) for (i <- 0 until n) { io.in(i).ready := oldest_oh(i) && io.out.ready } } } class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Vec(n, Flipped(new VectorReadIO)) val out = Vec(banks, new VectorReadIO) }) val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } for (i <- 0 until banks) { io.out(i).req <> arbs(i).io.out } val bankOffset = log2Ceil(banks) for (i <- 0 until n) { val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) for (j <- 0 until banks) { arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest } io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) } } class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val read = Vec(reads, Flipped(new VectorReadIO)) val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) val write = Input(Valid(new VectorWrite(dLen))) val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) }) val ll_write_valid = RegInit(false.B) val ll_write_bits = Reg(new VectorWrite(dLen)) val vrf = Mem(rows, Vec(dLen, Bool())) val v0_mask = Mem(maskRows, Vec(dLen, Bool())) for (read <- io.read) { read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) read.resp := DontCare when (read.req.valid) { read.resp := vrf.read(read.req.bits.eg).asUInt } } for (mask_read <- io.mask_read) { mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) mask_read.resp := DontCare when (mask_read.req.valid) { mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt } } val write = WireInit(io.write) io.ll_write.ready := false.B if (vParams.vrfHiccupBuffer) { when (!io.write.valid) { // drain hiccup buffer write.valid := ll_write_valid \|\| io.ll_write.valid write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) ll_write_valid := false.B when (io.ll_write.valid && ll_write_valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } .elsewhen (!ll_write_valid) { // fill hiccup buffer when (io.ll_write.valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } } else { when (!io.write.valid) { io.ll_write.ready := true.B write.valid := io.ll_write.valid write.bits := io.ll_write.bits } } when (write.valid) { vrf.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) when (write.bits.eg < maskRows.U) { v0_mask.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) } } } class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val nBanks = vParams.vrfBanking // Support 1, 2, and 4 banks for the VRF require(nBanks == 1 \|\| nBanks == 2 \|\| nBanks == 4) val io = IO(new Bundle { val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) }) val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } reads.zipWithIndex.foreach { case (rc, i) => val xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.read(i) <> xbar.io.out(j) } xbar.io.in <> io.read(i) } maskReads.zipWithIndex.foreach { case (rc, i) => val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.mask_read(i) <> mask_xbar.io.out(j) } mask_xbar.io.in <> io.mask_read(i) } io.ll_writes.foreach(_.ready := false.B) vrf.zipWithIndex.foreach { case (rf, i) => val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) val bank_write_valid = bank_match.orR rf.io.write.valid := bank_write_valid rf.io.write.bits.data := bank_write_data rf.io.write.bits.mask := bank_write_mask rf.io.write.bits.eg := bank_write_eg >> vrfBankBits when (bank_write_valid) { PopCount(bank_match) === 1.U } val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) rf.io.ll_write <> ll_arb.io.out io.ll_writes.zipWithIndex.foreach { case (w, j) => ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits ll_arb.io.in(j).bits.data := w.bits.data ll_arb.io.in(j).bits.mask := w.bits.mask when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { w.ready := true.B } } } }	module RegisterReadXbar_3( // @[RegisterFile.scala:27:7] input clock, // @[RegisterFile.scala:27:7] output io_in_0_req_ready, // @[RegisterFile.scala:28:14] input io_in_0_req_valid, // @[RegisterFile.scala:28:14] input io_in_0_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_0_resp, // @[RegisterFile.scala:28:14] output io_in_1_req_ready, // @[RegisterFile.scala:28:14] input io_in_1_req_valid, // @[RegisterFile.scala:28:14] input io_in_1_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_1_resp, // @[RegisterFile.scala:28:14] output io_in_2_req_ready, // @[RegisterFile.scala:28:14] input io_in_2_req_valid, // @[RegisterFile.scala:28:14] input io_in_2_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_2_resp, // @[RegisterFile.scala:28:14] output io_in_3_req_ready, // @[RegisterFile.scala:28:14] input io_in_3_req_valid, // @[RegisterFile.scala:28:14] input io_in_3_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_3_resp, // @[RegisterFile.scala:28:14] output io_in_4_req_ready, // @[RegisterFile.scala:28:14] input io_in_4_req_valid, // @[RegisterFile.scala:28:14] input [4:0] io_in_4_req_bits_eg, // @[RegisterFile.scala:28:14] output [63:0] io_in_4_resp, // @[RegisterFile.scala:28:14] input io_out_0_req_ready, // @[RegisterFile.scala:28:14] output [4:0] io_out_0_req_bits_eg, // @[RegisterFile.scala:28:14] input [63:0] io_out_0_resp, // @[RegisterFile.scala:28:14] input io_out_1_req_ready, // @[RegisterFile.scala:28:14] output [4:0] io_out_1_req_bits_eg, // @[RegisterFile.scala:28:14] input [63:0] io_out_1_resp // @[RegisterFile.scala:28:14] ); wire _arbs_1_io_in_4_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_4_ready; // @[RegisterFile.scala:33:38] wire [4:0] arbs_1_io_in_4_bits_eg = {1'h0, io_in_4_req_bits_eg[4:1]}; // @[RegisterFile.scala:44:{32,56}] OldestRRArbiter_6 arbs_0 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (io_in_0_req_ready), .io_in_0_valid (io_in_0_req_valid), .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (io_in_1_req_ready), .io_in_1_valid (io_in_1_req_valid), .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (io_in_2_req_ready), .io_in_2_valid (io_in_2_req_valid), .io_in_2_bits_oldest (io_in_2_req_bits_oldest), .io_in_3_ready (io_in_3_req_ready), .io_in_3_valid (io_in_3_req_valid), .io_in_3_bits_oldest (io_in_3_req_bits_oldest), .io_in_4_ready (_arbs_0_io_in_4_ready), .io_in_4_valid (io_in_4_req_valid & ~(io_in_4_req_bits_eg[0])), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_4_bits_eg (arbs_1_io_in_4_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_0_req_ready), .io_out_bits_eg (io_out_0_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter_6 arbs_1 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (/* unused /), .io_in_0_valid (1'h0), .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (/ unused /), .io_in_1_valid (1'h0), .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (/ unused /), .io_in_2_valid (1'h0), .io_in_2_bits_oldest (io_in_2_req_bits_oldest), .io_in_3_ready (/ unused */), .io_in_3_valid (1'h0), .io_in_3_bits_oldest (io_in_3_req_bits_oldest), .io_in_4_ready (_arbs_1_io_in_4_ready), .io_in_4_valid (io_in_4_req_valid & io_in_4_req_bits_eg[0]), // @[RegisterFile.scala:41:82, :43:52] .io_in_4_bits_eg (arbs_1_io_in_4_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_1_req_ready), .io_out_bits_eg (io_out_1_req_bits_eg) ); // @[RegisterFile.scala:33:38] assign io_in_0_resp = io_out_0_resp; // @[RegisterFile.scala:27:7] assign io_in_1_resp = io_out_0_resp; // @[RegisterFile.scala:27:7] assign io_in_2_resp = io_out_0_resp; // @[RegisterFile.scala:27:7] assign io_in_3_resp = io_out_0_resp; // @[RegisterFile.scala:27:7] assign io_in_4_req_ready = ~(io_in_4_req_bits_eg[0]) & _arbs_0_io_in_4_ready \| io_in_4_req_bits_eg[0] & _arbs_1_io_in_4_ready; // @[Mux.scala:30:73] assign io_in_4_resp = (io_in_4_req_bits_eg[0] ? 64'h0 : io_out_0_resp) \| (io_in_4_req_bits_eg[0] ? io_out_1_resp : 64'h0); // @[Mux.scala:30:73] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_314( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_58 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_29( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_277 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_278 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_279 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_280 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DivSqrtRecFN_small.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2017 SiFive, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of SiFive nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ /* s = sigWidth c_i = newBit Division: width of a is (s+2) Normal ------ (qi + ci * 2^(-i))b <= a q0 = 0 r0 = a q(i+1) = qi + ci2^(-i) ri = a - qib r(i+1) = a - q(i+1)b = a - qib - ci2^(-i)b r(i+1) = ri - ci2^(-i)b ci = ri >= 2^(-i)b summary_i = ri != 0 i = 0 to s+1 (s+1)th bit plus summary_(i+1) gives enough information for rounding If (a < b), then we need to calculate (s+2)th bit and summary_(i+1) because we need s bits ignoring the leading zero. (This is skipCycle2 part of Hauser's code.) Hauser ------ sig_i = qi rem_i = 2^(i-2)ri cycle_i = s+3-i sig_0 = 0 rem_0 = a/4 cycle_0 = s+3 bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits) sig(i+1) = sig(i) + cibit_i rem(i+1) = 2rem_i - cib/2 ci = 2rem_i >= b/2 bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits) cycle(i+1) = cycle_i-1 summary_1 = a <> b summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0 Proof: 2^ir(i+1) = 2^iri - cib. Qed ci = 2^iri >= b. Qed summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0 Now, note that all of ck's cannot be 0, since that means a is 0. So when you traverse through a chain of 0 ck's, from the end, eventually, you reach a non-zero cj. That is exactly the value of ri as the reminder remains the same. When all ck's are 0 except c0 (which must be 1) then summary_1 is set correctly according to r1 = a-b != 0. So summary(i+1) is always set correctly according to r(i+1) Square root: width of a is (s+1) Normal ------ (xi + ci2^(-i))^2 <= a xi^2 + ci2^(-i)(2xi+ci2^(-i)) <= a x0 = 0 x(i+1) = xi + ci2^(-i) ri = a - xi^2 r(i+1) = a - x(i+1)^2 = a - (xi^2 + ci2^(-i)(2xi+ci2^(-i))) = ri - ci2^(-i)(2xi+ci2^(-i)) = ri - ci2^(-i)(2xi+2^(-i)) // ci is always 0 or 1 ci = ri >= 2^(-i)(2xi + 2^(-i)) summary_i = ri != 0 i = 0 to s+1 For odd expression, do 2 steps initially. (s+1)th bit plus summary_(i+1) gives enough information for rounding. Hauser ------ sig_i = xi rem_i = ri2^(i-1) cycle_i = s+2-i bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation) sig_0 = 0 rem_0 = a/2 cycle_0 = s+2 bit_0 = 1 (= 2^s in terms of bit representation) sig(i+1) = sig_i + ci * bit_i rem(i+1) = 2rem_i - ci(2sig_i + bit_i) ci = 2sig_i + bit_i <= 2rem_i bit_i = 2^(cycle_i-2) (in terms of bit representation) cycle(i+1) = cycle_i-1 summary_1 = a - (2^s) (in terms of bit representation) summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0 Proof: ci = 2sig_i + bit_i <= 2rem_i ci = 2xi + 2^(-i) <= ri2^i. Qed sig(i+1) = sig_i + ci * bit_i x(i+1) = xi + ci2^(-i). Qed rem(i+1) = 2rem_i - ci(2sig_i + bit_i) r(i+1)2^i = ri2^i - ci(2xi + 2^(-i)) r(i+1) = ri - ci2^(-i)(2xi + 2^(-i)). Qed Same argument as before for summary. ------------------------------ Note that all registers are updated normally until cycle == 2. At cycle == 2, rem is not updated, but all other registers are updated normally. But, cycle == 1 does not read rem to calculate anything (note that final summary is calculated using the values at cycle = 2). / package hardfloat import chisel3._ import chisel3.util._ import consts._ /---------------------------------------------------------------------------- \| Computes a division or square root for floating-point in recoded form. \| Multiple clock cycles are needed for each division or square-root operation, \| except possibly in special cases. ----------------------------------------------------------------------------/ class DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /-------------------------------------------------------------------- --------------------------------------------------------------------/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val roundingMode = Input(UInt(3.W)) /-------------------------------------------------------------------- --------------------------------------------------------------------/ val rawOutValid_div = Output(Bool()) val rawOutValid_sqrt = Output(Bool()) val roundingModeOut = Output(UInt(3.W)) val invalidExc = Output(Bool()) val infiniteExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W)) val inReady = RegInit(true.B) // <-> (cycleNum <= 1) val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1) val sqrtOp_Z = Reg(Bool()) val majorExc_Z = Reg(Bool()) //*** REDUCE 3 BITS TO 2-BIT CODE: val isNaN_Z = Reg(Bool()) val isInf_Z = Reg(Bool()) val isZero_Z = Reg(Bool()) val sign_Z = Reg(Bool()) val sExp_Z = Reg(SInt((expWidth + 2).W)) val fractB_Z = Reg(UInt(sigWidth.W)) val roundingMode_Z = Reg(UInt(3.W)) /------------------------------------------------------------------------ \| (The most-significant and least-significant bits of 'rem_Z' are needed \| only for square roots.) ------------------------------------------------------------------------/ val rem_Z = Reg(UInt((sigWidth + 2).W)) val notZeroRem_Z = Reg(Bool()) val sigX_Z = Reg(UInt((sigWidth + 2).W)) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val rawA_S = io.a val rawB_S = io.b //* IMPROVE THESE: val notSigNaNIn_invalidExc_S_div = (rawA_S.isZero && rawB_S.isZero) \|\| (rawA_S.isInf && rawB_S.isInf) val notSigNaNIn_invalidExc_S_sqrt = ! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign val majorExc_S = Mux(io.sqrtOp, isSigNaNRawFloat(rawA_S) \|\| notSigNaNIn_invalidExc_S_sqrt, isSigNaNRawFloat(rawA_S) \|\| isSigNaNRawFloat(rawB_S) \|\| notSigNaNIn_invalidExc_S_div \|\| (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero) ) val isNaN_S = Mux(io.sqrtOp, rawA_S.isNaN \|\| notSigNaNIn_invalidExc_S_sqrt, rawA_S.isNaN \|\| rawB_S.isNaN \|\| notSigNaNIn_invalidExc_S_div ) val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf \|\| rawB_S.isZero) val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero \|\| rawB_S.isInf) val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign) val specialCaseA_S = rawA_S.isNaN \|\| rawA_S.isInf \|\| rawA_S.isZero val specialCaseB_S = rawB_S.isNaN \|\| rawB_S.isInf \|\| rawB_S.isZero val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) val sExpQuot_S_div = rawA_S.sExp +& Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt //* IS THIS OPTIMAL?: val sSatExpQuot_S_div = Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div), 6.U, sExpQuot_S_div(expWidth + 1, expWidth - 2) ), sExpQuot_S_div(expWidth - 3, 0) ).asSInt val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0) val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val idle = cycleNum === 0.U val entering = inReady && io.inValid val entering_normalCase = entering && normalCase_S val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B when (! idle \|\| entering) { def computeCycleNum(f: UInt => UInt): UInt = { Mux(entering & ! normalCase_S, f(1.U), 0.U) \| Mux(entering_normalCase, Mux(io.sqrtOp, Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)), f((sigWidth + 2).U) ), 0.U ) \| Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) \| Mux(skipCycle2, f(1.U), 0.U) } inReady := computeCycleNum(_ <= 1.U).asBool rawOutValid := computeCycleNum(_ === 1.U).asBool cycleNum := computeCycleNum(x => x) } io.inReady := inReady /------------------------------------------------------------------------ ------------------------------------------------------------------------/ when (entering) { sqrtOp_Z := io.sqrtOp majorExc_Z := majorExc_S isNaN_Z := isNaN_S isInf_Z := isInf_S isZero_Z := isZero_S sign_Z := sign_S sExp_Z := Mux(io.sqrtOp, (rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S, sSatExpQuot_S_div ) roundingMode_Z := io.roundingMode } when (entering \|\| ! inReady && sqrtOp_Z) { fractB_Z := Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) \| Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) \| Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) \| Mux(! inReady /* sqrtOp_Z / && processTwoBits, fractB_Z>>2, 0.U) \| Mux(! inReady / sqrtOp_Z / && ! processTwoBits, fractB_Z>>1, 0.U) } /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val rem = Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) \| Mux(inReady && oddSqrt_S, Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U, rawA_S.sig(sigWidth - 3, 0)<<3 ), 0.U ) \| Mux(! inReady, rem_Z<<1, 0.U) val bitMask = (1.U<<cycleNum)>>2 val trialTerm = Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) \| Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) \| Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) \| Mux(! inReady, fractB_Z, 0.U) \| Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) \| Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U) val trialRem = rem.zext -& trialTerm.zext val newBit = (0.S <= trialRem) val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0) val rem2 = nextRem_Z<<1 val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 \| sigX_Z<<1, fractB_Z \| (1.U << sigWidth)) val trialTerm2_newBit1 = trialTerm2_newBit0 \| Mux(sqrtOp_Z, fractB_Z<<1, 0.U) val trialRem2 = Mux(newBit, (trialRem<<1) - trialTerm2_newBit1.zext, (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) val newBit2 = (0.S <= trialRem2) val nextNotZeroRem_Z = Mux(inReady \|\| newBit, trialRem =/= 0.S, notZeroRem_Z) val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z) processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) \|\| processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) \|\| !(processTwoBits && newBit2) && nextNotZeroRem_Z val nextRem_Z_2 = Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) \| Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) \| Mux(!processTwoBits, nextRem_Z, 0.U) when (entering \|\| ! inReady) { notZeroRem_Z := nextNotZeroRem_Z_2 rem_Z := nextRem_Z_2 sigX_Z := Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) \| Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) \| Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) \| Mux(! inReady, sigX_Z, 0.U) \| Mux(! inReady && newBit, bitMask, 0.U) \| Mux(processTwoBits && newBit2, bitMask>>1, 0.U) } /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.rawOutValid_div := rawOutValid && ! sqrtOp_Z io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z io.roundingModeOut := roundingMode_Z io.invalidExc := majorExc_Z && isNaN_Z io.infiniteExc := majorExc_Z && ! isNaN_Z io.rawOut.isNaN := isNaN_Z io.rawOut.isInf := isInf_Z io.rawOut.isZero := isZero_Z io.rawOut.sign := sign_Z io.rawOut.sExp := sExp_Z io.rawOut.sig := sigX_Z<<1 \| notZeroRem_Z } /---------------------------------------------------------------------------- ----------------------------------------------------------------------------/ class DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /-------------------------------------------------------------------- --------------------------------------------------------------------/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) /-------------------------------------------------------------------- --------------------------------------------------------------------/ val rawOutValid_div = Output(Bool()) val rawOutValid_sqrt = Output(Bool()) val roundingModeOut = Output(UInt(3.W)) val invalidExc = Output(Bool()) val infiniteExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val divSqrtRawFN = Module(new DivSqrtRawFN_small(expWidth, sigWidth, options)) io.inReady := divSqrtRawFN.io.inReady divSqrtRawFN.io.inValid := io.inValid divSqrtRawFN.io.sqrtOp := io.sqrtOp divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) divSqrtRawFN.io.roundingMode := io.roundingMode io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt io.roundingModeOut := divSqrtRawFN.io.roundingModeOut io.invalidExc := divSqrtRawFN.io.invalidExc io.infiniteExc := divSqrtRawFN.io.infiniteExc io.rawOut := divSqrtRawFN.io.rawOut } /---------------------------------------------------------------------------- ----------------------------------------------------------------------------/ class DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /-------------------------------------------------------------------- --------------------------------------------------------------------/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) /-------------------------------------------------------------------- --------------------------------------------------------------------*/ val outValid_div = Output(Bool()) val outValid_sqrt = Output(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val divSqrtRecFNToRaw = Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options)) io.inReady := divSqrtRecFNToRaw.io.inReady divSqrtRecFNToRaw.io.inValid := io.inValid divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp divSqrtRecFNToRaw.io.a := io.a divSqrtRecFNToRaw.io.b := io.b divSqrtRecFNToRaw.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module DivSqrtRecFM_small_e8_s24_2( // @[DivSqrtRecFN_small.scala:468:5] input clock, // @[DivSqrtRecFN_small.scala:468:5] input reset, // @[DivSqrtRecFN_small.scala:468:5] output io_inReady, // @[DivSqrtRecFN_small.scala:472:16] input io_inValid, // @[DivSqrtRecFN_small.scala:472:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:472:16] input [32:0] io_a, // @[DivSqrtRecFN_small.scala:472:16] input [32:0] io_b, // @[DivSqrtRecFN_small.scala:472:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:472:16] output io_outValid_div, // @[DivSqrtRecFN_small.scala:472:16] output io_outValid_sqrt, // @[DivSqrtRecFN_small.scala:472:16] output [32:0] io_out, // @[DivSqrtRecFN_small.scala:472:16] output [4:0] io_exceptionFlags // @[DivSqrtRecFN_small.scala:472:16] ); wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_invalidExc; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_infiniteExc; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_isNaN; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_isInf; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_isZero; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_sign; // @[DivSqrtRecFN_small.scala:493:15] wire [9:0] _divSqrtRecFNToRaw_io_rawOut_sExp; // @[DivSqrtRecFN_small.scala:493:15] wire [26:0] _divSqrtRecFNToRaw_io_rawOut_sig; // @[DivSqrtRecFN_small.scala:493:15] wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:468:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:468:5] wire [32:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:468:5] wire [32:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:468:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:468:5] wire io_detectTininess = 1'h1; // @[DivSqrtRecFN_small.scala:468:5, :472:16, :508:15] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5] wire io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5] wire io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5] wire [32:0] io_out_0; // @[DivSqrtRecFN_small.scala:468:5] wire [4:0] io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5] DivSqrtRecFMToRaw_small_e8_s24_2 divSqrtRecFNToRaw ( // @[DivSqrtRecFN_small.scala:493:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:468:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:468:5] .io_a (io_a_0), // @[DivSqrtRecFN_small.scala:468:5] .io_b (io_b_0), // @[DivSqrtRecFN_small.scala:468:5] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:468:5] .io_rawOutValid_div (io_outValid_div_0), .io_rawOutValid_sqrt (io_outValid_sqrt_0), .io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut), .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc), .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc), .io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN), .io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf), .io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero), .io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign), .io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp), .io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig) ); // @[DivSqrtRecFN_small.scala:493:15] RoundRawFNToRecFN_e8_s24_5 roundRawFNToRecFN ( // @[DivSqrtRecFN_small.scala:508:15] .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc), // @[DivSqrtRecFN_small.scala:493:15] .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc), // @[DivSqrtRecFN_small.scala:493:15] .io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN), // @[DivSqrtRecFN_small.scala:493:15] .io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf), // @[DivSqrtRecFN_small.scala:493:15] .io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero), // @[DivSqrtRecFN_small.scala:493:15] .io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign), // @[DivSqrtRecFN_small.scala:493:15] .io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp), // @[DivSqrtRecFN_small.scala:493:15] .io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig), // @[DivSqrtRecFN_small.scala:493:15] .io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut), // @[DivSqrtRecFN_small.scala:493:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[DivSqrtRecFN_small.scala:508:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_outValid_div = io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_outValid_sqrt = io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_out = io_out_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_332( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_130( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth2 - 1)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) \|\| (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf \|\| io.b.isInf val notNaN_isZeroOut = io.a.isZero \|\| io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth2 - 1, 0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.invalidExc := isSigNaNRawFloat(io.a) \|\| isSigNaNRawFloat(io.b) \|\| notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN \|\| io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulRawFN_14( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = \|_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_14 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn \|\| noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }	module TLNoC_router_2ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_2 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_2_flit_ready (auto_routers_ingress_nodes_in_2_flit_ready), .auto_ingress_nodes_in_2_flit_valid (auto_routers_ingress_nodes_in_2_flit_valid), .auto_ingress_nodes_in_2_flit_bits_head (auto_routers_ingress_nodes_in_2_flit_bits_head), .auto_ingress_nodes_in_2_flit_bits_payload (auto_routers_ingress_nodes_in_2_flit_bits_payload), .auto_ingress_nodes_in_2_flit_bits_egress_id (auto_routers_ingress_nodes_in_2_flit_bits_egress_id), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File rename-busytable.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Rename BusyTable //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util._ import boom.v3.common._ import boom.v3.util._ import org.chipsalliance.cde.config.Parameters class BusyResp extends Bundle { val prs1_busy = Bool() val prs2_busy = Bool() val prs3_busy = Bool() } class RenameBusyTable( val plWidth: Int, val numPregs: Int, val numWbPorts: Int, val bypass: Boolean, val float: Boolean) (implicit p: Parameters) extends BoomModule { val pregSz = log2Ceil(numPregs) val io = IO(new BoomBundle()(p) { val ren_uops = Input(Vec(plWidth, new MicroOp)) val busy_resps = Output(Vec(plWidth, new BusyResp)) val rebusy_reqs = Input(Vec(plWidth, Bool())) val wb_pdsts = Input(Vec(numWbPorts, UInt(pregSz.W))) val wb_valids = Input(Vec(numWbPorts, Bool())) val debug = new Bundle { val busytable = Output(Bits(numPregs.W)) } }) val busy_table = RegInit(0.U(numPregs.W)) // Unbusy written back registers. val busy_table_wb = busy_table & ~(io.wb_pdsts zip io.wb_valids) .map {case (pdst, valid) => UIntToOH(pdst) & Fill(numPregs, valid.asUInt)}.reduce(_\|_) // Rebusy newly allocated registers. val busy_table_next = busy_table_wb \| (io.ren_uops zip io.rebusy_reqs) .map {case (uop, req) => UIntToOH(uop.pdst) & Fill(numPregs, req.asUInt)}.reduce(_\|_) busy_table := busy_table_next // Read the busy table. for (i <- 0 until plWidth) { val prs1_was_bypassed = (0 until i).map(j => io.ren_uops(i).lrs1 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_\|\|_) val prs2_was_bypassed = (0 until i).map(j => io.ren_uops(i).lrs2 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_\|\|_) val prs3_was_bypassed = (0 until i).map(j => io.ren_uops(i).lrs3 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_\|\|_) io.busy_resps(i).prs1_busy := busy_table(io.ren_uops(i).prs1) \|\| prs1_was_bypassed && bypass.B io.busy_resps(i).prs2_busy := busy_table(io.ren_uops(i).prs2) \|\| prs2_was_bypassed && bypass.B io.busy_resps(i).prs3_busy := busy_table(io.ren_uops(i).prs3) \|\| prs3_was_bypassed && bypass.B if (!float) io.busy_resps(i).prs3_busy := false.B } io.debug.busytable := busy_table }	module RenameBusyTable_2( // @[rename-busytable.scala:27:7] input clock, // @[rename-busytable.scala:27:7] input reset, // @[rename-busytable.scala:27:7] input [6:0] io_ren_uops_0_uopc, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_0_inst, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_0_debug_inst, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_rvc, // @[rename-busytable.scala:37:14] input [39:0] io_ren_uops_0_debug_pc, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_0_iq_type, // @[rename-busytable.scala:37:14] input [9:0] io_ren_uops_0_fu_code, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_0_ctrl_br_type, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_ctrl_op1_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_0_ctrl_op2_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_0_ctrl_imm_sel, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_ctrl_op_fcn, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ctrl_fcn_dw, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_0_ctrl_csr_cmd, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ctrl_is_load, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ctrl_is_sta, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ctrl_is_std, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_iw_state, // @[rename-busytable.scala:37:14] input io_ren_uops_0_iw_p1_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_0_iw_p2_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_br, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_jalr, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_jal, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_sfb, // @[rename-busytable.scala:37:14] input [15:0] io_ren_uops_0_br_mask, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_0_br_tag, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_ftq_idx, // @[rename-busytable.scala:37:14] input io_ren_uops_0_edge_inst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_0_pc_lob, // @[rename-busytable.scala:37:14] input io_ren_uops_0_taken, // @[rename-busytable.scala:37:14] input [19:0] io_ren_uops_0_imm_packed, // @[rename-busytable.scala:37:14] input [11:0] io_ren_uops_0_csr_addr, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_0_rob_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_ldq_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_stq_idx, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_rxq_idx, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_0_pdst, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_0_prs1, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_0_prs2, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_ppred, // @[rename-busytable.scala:37:14] input io_ren_uops_0_prs1_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_0_prs2_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ppred_busy, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_0_stale_pdst, // @[rename-busytable.scala:37:14] input io_ren_uops_0_exception, // @[rename-busytable.scala:37:14] input [63:0] io_ren_uops_0_exc_cause, // @[rename-busytable.scala:37:14] input io_ren_uops_0_bypassable, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_mem_cmd, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_mem_size, // @[rename-busytable.scala:37:14] input io_ren_uops_0_mem_signed, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_fence, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_fencei, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_amo, // @[rename-busytable.scala:37:14] input io_ren_uops_0_uses_ldq, // @[rename-busytable.scala:37:14] input io_ren_uops_0_uses_stq, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_sys_pc2epc, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_unique, // @[rename-busytable.scala:37:14] input io_ren_uops_0_flush_on_commit, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ldst_is_rs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_0_ldst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_0_lrs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_0_lrs2, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_0_lrs3, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ldst_val, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_dst_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_lrs1_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_lrs2_rtype, // @[rename-busytable.scala:37:14] input io_ren_uops_0_frs3_en, // @[rename-busytable.scala:37:14] input io_ren_uops_0_fp_val, // @[rename-busytable.scala:37:14] input io_ren_uops_0_fp_single, // @[rename-busytable.scala:37:14] input io_ren_uops_0_xcpt_pf_if, // @[rename-busytable.scala:37:14] input io_ren_uops_0_xcpt_ae_if, // @[rename-busytable.scala:37:14] input io_ren_uops_0_xcpt_ma_if, // @[rename-busytable.scala:37:14] input io_ren_uops_0_bp_debug_if, // @[rename-busytable.scala:37:14] input io_ren_uops_0_bp_xcpt_if, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_debug_fsrc, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_debug_tsrc, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_uopc, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_1_inst, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_1_debug_inst, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_rvc, // @[rename-busytable.scala:37:14] input [39:0] io_ren_uops_1_debug_pc, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_1_iq_type, // @[rename-busytable.scala:37:14] input [9:0] io_ren_uops_1_fu_code, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_1_ctrl_br_type, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_ctrl_op1_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_1_ctrl_op2_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_1_ctrl_imm_sel, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_ctrl_op_fcn, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ctrl_fcn_dw, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_1_ctrl_csr_cmd, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ctrl_is_load, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ctrl_is_sta, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ctrl_is_std, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_iw_state, // @[rename-busytable.scala:37:14] input io_ren_uops_1_iw_p1_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_1_iw_p2_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_br, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_jalr, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_jal, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_sfb, // @[rename-busytable.scala:37:14] input [15:0] io_ren_uops_1_br_mask, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_1_br_tag, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_ftq_idx, // @[rename-busytable.scala:37:14] input io_ren_uops_1_edge_inst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_1_pc_lob, // @[rename-busytable.scala:37:14] input io_ren_uops_1_taken, // @[rename-busytable.scala:37:14] input [19:0] io_ren_uops_1_imm_packed, // @[rename-busytable.scala:37:14] input [11:0] io_ren_uops_1_csr_addr, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_rob_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_ldq_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_stq_idx, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_rxq_idx, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_pdst, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_prs1, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_prs2, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_ppred, // @[rename-busytable.scala:37:14] input io_ren_uops_1_prs1_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_1_prs2_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ppred_busy, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_stale_pdst, // @[rename-busytable.scala:37:14] input io_ren_uops_1_exception, // @[rename-busytable.scala:37:14] input [63:0] io_ren_uops_1_exc_cause, // @[rename-busytable.scala:37:14] input io_ren_uops_1_bypassable, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_mem_cmd, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_mem_size, // @[rename-busytable.scala:37:14] input io_ren_uops_1_mem_signed, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_fence, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_fencei, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_amo, // @[rename-busytable.scala:37:14] input io_ren_uops_1_uses_ldq, // @[rename-busytable.scala:37:14] input io_ren_uops_1_uses_stq, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_sys_pc2epc, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_unique, // @[rename-busytable.scala:37:14] input io_ren_uops_1_flush_on_commit, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ldst_is_rs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_1_ldst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_1_lrs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_1_lrs2, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_1_lrs3, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ldst_val, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_dst_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_lrs1_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_lrs2_rtype, // @[rename-busytable.scala:37:14] input io_ren_uops_1_frs3_en, // @[rename-busytable.scala:37:14] input io_ren_uops_1_fp_val, // @[rename-busytable.scala:37:14] input io_ren_uops_1_fp_single, // @[rename-busytable.scala:37:14] input io_ren_uops_1_xcpt_pf_if, // @[rename-busytable.scala:37:14] input io_ren_uops_1_xcpt_ae_if, // @[rename-busytable.scala:37:14] input io_ren_uops_1_xcpt_ma_if, // @[rename-busytable.scala:37:14] input io_ren_uops_1_bp_debug_if, // @[rename-busytable.scala:37:14] input io_ren_uops_1_bp_xcpt_if, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_debug_fsrc, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_debug_tsrc, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_uopc, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_2_inst, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_2_debug_inst, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_rvc, // @[rename-busytable.scala:37:14] input [39:0] io_ren_uops_2_debug_pc, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_2_iq_type, // @[rename-busytable.scala:37:14] input [9:0] io_ren_uops_2_fu_code, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_2_ctrl_br_type, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_ctrl_op1_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_2_ctrl_op2_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_2_ctrl_imm_sel, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_ctrl_op_fcn, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ctrl_fcn_dw, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_2_ctrl_csr_cmd, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ctrl_is_load, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ctrl_is_sta, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ctrl_is_std, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_iw_state, // @[rename-busytable.scala:37:14] input io_ren_uops_2_iw_p1_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_2_iw_p2_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_br, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_jalr, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_jal, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_sfb, // @[rename-busytable.scala:37:14] input [15:0] io_ren_uops_2_br_mask, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_2_br_tag, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_ftq_idx, // @[rename-busytable.scala:37:14] input io_ren_uops_2_edge_inst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_2_pc_lob, // @[rename-busytable.scala:37:14] input io_ren_uops_2_taken, // @[rename-busytable.scala:37:14] input [19:0] io_ren_uops_2_imm_packed, // @[rename-busytable.scala:37:14] input [11:0] io_ren_uops_2_csr_addr, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_rob_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_ldq_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_stq_idx, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_rxq_idx, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_pdst, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_prs1, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_prs2, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_ppred, // @[rename-busytable.scala:37:14] input io_ren_uops_2_prs1_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_2_prs2_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ppred_busy, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_stale_pdst, // @[rename-busytable.scala:37:14] input io_ren_uops_2_exception, // @[rename-busytable.scala:37:14] input [63:0] io_ren_uops_2_exc_cause, // @[rename-busytable.scala:37:14] input io_ren_uops_2_bypassable, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_mem_cmd, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_mem_size, // @[rename-busytable.scala:37:14] input io_ren_uops_2_mem_signed, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_fence, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_fencei, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_amo, // @[rename-busytable.scala:37:14] input io_ren_uops_2_uses_ldq, // @[rename-busytable.scala:37:14] input io_ren_uops_2_uses_stq, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_sys_pc2epc, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_unique, // @[rename-busytable.scala:37:14] input io_ren_uops_2_flush_on_commit, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ldst_is_rs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_2_ldst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_2_lrs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_2_lrs2, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_2_lrs3, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ldst_val, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_dst_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_lrs1_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_lrs2_rtype, // @[rename-busytable.scala:37:14] input io_ren_uops_2_frs3_en, // @[rename-busytable.scala:37:14] input io_ren_uops_2_fp_val, // @[rename-busytable.scala:37:14] input io_ren_uops_2_fp_single, // @[rename-busytable.scala:37:14] input io_ren_uops_2_xcpt_pf_if, // @[rename-busytable.scala:37:14] input io_ren_uops_2_xcpt_ae_if, // @[rename-busytable.scala:37:14] input io_ren_uops_2_xcpt_ma_if, // @[rename-busytable.scala:37:14] input io_ren_uops_2_bp_debug_if, // @[rename-busytable.scala:37:14] input io_ren_uops_2_bp_xcpt_if, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_debug_fsrc, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_debug_tsrc, // @[rename-busytable.scala:37:14] output io_busy_resps_0_prs1_busy, // @[rename-busytable.scala:37:14] output io_busy_resps_0_prs2_busy, // @[rename-busytable.scala:37:14] output io_busy_resps_1_prs1_busy, // @[rename-busytable.scala:37:14] output io_busy_resps_1_prs2_busy, // @[rename-busytable.scala:37:14] output io_busy_resps_2_prs1_busy, // @[rename-busytable.scala:37:14] output io_busy_resps_2_prs2_busy, // @[rename-busytable.scala:37:14] input io_rebusy_reqs_0, // @[rename-busytable.scala:37:14] input io_rebusy_reqs_1, // @[rename-busytable.scala:37:14] input io_rebusy_reqs_2, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_0, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_1, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_2, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_3, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_4, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_5, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_6, // @[rename-busytable.scala:37:14] input io_wb_valids_0, // @[rename-busytable.scala:37:14] input io_wb_valids_1, // @[rename-busytable.scala:37:14] input io_wb_valids_2, // @[rename-busytable.scala:37:14] input io_wb_valids_3, // @[rename-busytable.scala:37:14] input io_wb_valids_4, // @[rename-busytable.scala:37:14] input io_wb_valids_5, // @[rename-busytable.scala:37:14] input io_wb_valids_6, // @[rename-busytable.scala:37:14] output [99:0] io_debug_busytable // @[rename-busytable.scala:37:14] ); wire [6:0] io_ren_uops_0_uopc_0 = io_ren_uops_0_uopc; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_0_inst_0 = io_ren_uops_0_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_0_debug_inst_0 = io_ren_uops_0_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_rvc_0 = io_ren_uops_0_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_0_debug_pc_0 = io_ren_uops_0_debug_pc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_iq_type_0 = io_ren_uops_0_iq_type; // @[rename-busytable.scala:27:7] wire [9:0] io_ren_uops_0_fu_code_0 = io_ren_uops_0_fu_code; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_ctrl_br_type_0 = io_ren_uops_0_ctrl_br_type; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_ctrl_op1_sel_0 = io_ren_uops_0_ctrl_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_ctrl_op2_sel_0 = io_ren_uops_0_ctrl_op2_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_ctrl_imm_sel_0 = io_ren_uops_0_ctrl_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ctrl_op_fcn_0 = io_ren_uops_0_ctrl_op_fcn; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ctrl_fcn_dw_0 = io_ren_uops_0_ctrl_fcn_dw; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_ctrl_csr_cmd_0 = io_ren_uops_0_ctrl_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ctrl_is_load_0 = io_ren_uops_0_ctrl_is_load; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ctrl_is_sta_0 = io_ren_uops_0_ctrl_is_sta; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ctrl_is_std_0 = io_ren_uops_0_ctrl_is_std; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_iw_state_0 = io_ren_uops_0_iw_state; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p1_poisoned_0 = io_ren_uops_0_iw_p1_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p2_poisoned_0 = io_ren_uops_0_iw_p2_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_br_0 = io_ren_uops_0_is_br; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_jalr_0 = io_ren_uops_0_is_jalr; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_jal_0 = io_ren_uops_0_is_jal; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sfb_0 = io_ren_uops_0_is_sfb; // @[rename-busytable.scala:27:7] wire [15:0] io_ren_uops_0_br_mask_0 = io_ren_uops_0_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_br_tag_0 = io_ren_uops_0_br_tag; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ftq_idx_0 = io_ren_uops_0_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_edge_inst_0 = io_ren_uops_0_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_pc_lob_0 = io_ren_uops_0_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_taken_0 = io_ren_uops_0_taken; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_0_imm_packed_0 = io_ren_uops_0_imm_packed; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_0_csr_addr_0 = io_ren_uops_0_csr_addr; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_rob_idx_0 = io_ren_uops_0_rob_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ldq_idx_0 = io_ren_uops_0_ldq_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_stq_idx_0 = io_ren_uops_0_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_rxq_idx_0 = io_ren_uops_0_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_pdst_0 = io_ren_uops_0_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs1_0 = io_ren_uops_0_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs2_0 = io_ren_uops_0_prs2; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ppred_0 = io_ren_uops_0_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs1_busy_0 = io_ren_uops_0_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs2_busy_0 = io_ren_uops_0_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ppred_busy_0 = io_ren_uops_0_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_stale_pdst_0 = io_ren_uops_0_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_exception_0 = io_ren_uops_0_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_0_exc_cause_0 = io_ren_uops_0_exc_cause; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bypassable_0 = io_ren_uops_0_bypassable; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_mem_cmd_0 = io_ren_uops_0_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_mem_size_0 = io_ren_uops_0_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_mem_signed_0 = io_ren_uops_0_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_fence_0 = io_ren_uops_0_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_fencei_0 = io_ren_uops_0_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_amo_0 = io_ren_uops_0_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_uses_ldq_0 = io_ren_uops_0_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_uses_stq_0 = io_ren_uops_0_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sys_pc2epc_0 = io_ren_uops_0_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_unique_0 = io_ren_uops_0_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_flush_on_commit_0 = io_ren_uops_0_flush_on_commit; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ldst_is_rs1_0 = io_ren_uops_0_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_ldst_0 = io_ren_uops_0_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs1_0 = io_ren_uops_0_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs2_0 = io_ren_uops_0_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs3_0 = io_ren_uops_0_lrs3; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ldst_val_0 = io_ren_uops_0_ldst_val; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_dst_rtype_0 = io_ren_uops_0_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_lrs1_rtype_0 = io_ren_uops_0_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_lrs2_rtype_0 = io_ren_uops_0_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_frs3_en_0 = io_ren_uops_0_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_val_0 = io_ren_uops_0_fp_val; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_single_0 = io_ren_uops_0_fp_single; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_pf_if_0 = io_ren_uops_0_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_ae_if_0 = io_ren_uops_0_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_ma_if_0 = io_ren_uops_0_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bp_debug_if_0 = io_ren_uops_0_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bp_xcpt_if_0 = io_ren_uops_0_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_debug_fsrc_0 = io_ren_uops_0_debug_fsrc; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_debug_tsrc_0 = io_ren_uops_0_debug_tsrc; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_uopc_0 = io_ren_uops_1_uopc; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_1_inst_0 = io_ren_uops_1_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_1_debug_inst_0 = io_ren_uops_1_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_rvc_0 = io_ren_uops_1_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_1_debug_pc_0 = io_ren_uops_1_debug_pc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_iq_type_0 = io_ren_uops_1_iq_type; // @[rename-busytable.scala:27:7] wire [9:0] io_ren_uops_1_fu_code_0 = io_ren_uops_1_fu_code; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_ctrl_br_type_0 = io_ren_uops_1_ctrl_br_type; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_ctrl_op1_sel_0 = io_ren_uops_1_ctrl_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_ctrl_op2_sel_0 = io_ren_uops_1_ctrl_op2_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_ctrl_imm_sel_0 = io_ren_uops_1_ctrl_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ctrl_op_fcn_0 = io_ren_uops_1_ctrl_op_fcn; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ctrl_fcn_dw_0 = io_ren_uops_1_ctrl_fcn_dw; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_ctrl_csr_cmd_0 = io_ren_uops_1_ctrl_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ctrl_is_load_0 = io_ren_uops_1_ctrl_is_load; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ctrl_is_sta_0 = io_ren_uops_1_ctrl_is_sta; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ctrl_is_std_0 = io_ren_uops_1_ctrl_is_std; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_iw_state_0 = io_ren_uops_1_iw_state; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p1_poisoned_0 = io_ren_uops_1_iw_p1_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p2_poisoned_0 = io_ren_uops_1_iw_p2_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_br_0 = io_ren_uops_1_is_br; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_jalr_0 = io_ren_uops_1_is_jalr; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_jal_0 = io_ren_uops_1_is_jal; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sfb_0 = io_ren_uops_1_is_sfb; // @[rename-busytable.scala:27:7] wire [15:0] io_ren_uops_1_br_mask_0 = io_ren_uops_1_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_br_tag_0 = io_ren_uops_1_br_tag; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ftq_idx_0 = io_ren_uops_1_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_edge_inst_0 = io_ren_uops_1_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_pc_lob_0 = io_ren_uops_1_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_taken_0 = io_ren_uops_1_taken; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_1_imm_packed_0 = io_ren_uops_1_imm_packed; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_1_csr_addr_0 = io_ren_uops_1_csr_addr; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_rob_idx_0 = io_ren_uops_1_rob_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ldq_idx_0 = io_ren_uops_1_ldq_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_stq_idx_0 = io_ren_uops_1_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_rxq_idx_0 = io_ren_uops_1_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_pdst_0 = io_ren_uops_1_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs1_0 = io_ren_uops_1_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs2_0 = io_ren_uops_1_prs2; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ppred_0 = io_ren_uops_1_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs1_busy_0 = io_ren_uops_1_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs2_busy_0 = io_ren_uops_1_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ppred_busy_0 = io_ren_uops_1_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_stale_pdst_0 = io_ren_uops_1_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_exception_0 = io_ren_uops_1_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_1_exc_cause_0 = io_ren_uops_1_exc_cause; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bypassable_0 = io_ren_uops_1_bypassable; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_mem_cmd_0 = io_ren_uops_1_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_mem_size_0 = io_ren_uops_1_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_mem_signed_0 = io_ren_uops_1_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_fence_0 = io_ren_uops_1_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_fencei_0 = io_ren_uops_1_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_amo_0 = io_ren_uops_1_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_uses_ldq_0 = io_ren_uops_1_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_uses_stq_0 = io_ren_uops_1_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sys_pc2epc_0 = io_ren_uops_1_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_unique_0 = io_ren_uops_1_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_flush_on_commit_0 = io_ren_uops_1_flush_on_commit; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ldst_is_rs1_0 = io_ren_uops_1_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_ldst_0 = io_ren_uops_1_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs1_0 = io_ren_uops_1_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs2_0 = io_ren_uops_1_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs3_0 = io_ren_uops_1_lrs3; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ldst_val_0 = io_ren_uops_1_ldst_val; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_dst_rtype_0 = io_ren_uops_1_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_lrs1_rtype_0 = io_ren_uops_1_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_lrs2_rtype_0 = io_ren_uops_1_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_frs3_en_0 = io_ren_uops_1_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_val_0 = io_ren_uops_1_fp_val; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_single_0 = io_ren_uops_1_fp_single; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_pf_if_0 = io_ren_uops_1_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_ae_if_0 = io_ren_uops_1_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_ma_if_0 = io_ren_uops_1_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bp_debug_if_0 = io_ren_uops_1_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bp_xcpt_if_0 = io_ren_uops_1_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_debug_fsrc_0 = io_ren_uops_1_debug_fsrc; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_debug_tsrc_0 = io_ren_uops_1_debug_tsrc; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_uopc_0 = io_ren_uops_2_uopc; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_2_inst_0 = io_ren_uops_2_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_2_debug_inst_0 = io_ren_uops_2_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_rvc_0 = io_ren_uops_2_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_2_debug_pc_0 = io_ren_uops_2_debug_pc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_2_iq_type_0 = io_ren_uops_2_iq_type; // @[rename-busytable.scala:27:7] wire [9:0] io_ren_uops_2_fu_code_0 = io_ren_uops_2_fu_code; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_2_ctrl_br_type_0 = io_ren_uops_2_ctrl_br_type; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_ctrl_op1_sel_0 = io_ren_uops_2_ctrl_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_2_ctrl_op2_sel_0 = io_ren_uops_2_ctrl_op2_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_2_ctrl_imm_sel_0 = io_ren_uops_2_ctrl_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_ctrl_op_fcn_0 = io_ren_uops_2_ctrl_op_fcn; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ctrl_fcn_dw_0 = io_ren_uops_2_ctrl_fcn_dw; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_2_ctrl_csr_cmd_0 = io_ren_uops_2_ctrl_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ctrl_is_load_0 = io_ren_uops_2_ctrl_is_load; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ctrl_is_sta_0 = io_ren_uops_2_ctrl_is_sta; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ctrl_is_std_0 = io_ren_uops_2_ctrl_is_std; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_iw_state_0 = io_ren_uops_2_iw_state; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_iw_p1_poisoned_0 = io_ren_uops_2_iw_p1_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_iw_p2_poisoned_0 = io_ren_uops_2_iw_p2_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_br_0 = io_ren_uops_2_is_br; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_jalr_0 = io_ren_uops_2_is_jalr; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_jal_0 = io_ren_uops_2_is_jal; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_sfb_0 = io_ren_uops_2_is_sfb; // @[rename-busytable.scala:27:7] wire [15:0] io_ren_uops_2_br_mask_0 = io_ren_uops_2_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_2_br_tag_0 = io_ren_uops_2_br_tag; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_ftq_idx_0 = io_ren_uops_2_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_edge_inst_0 = io_ren_uops_2_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_2_pc_lob_0 = io_ren_uops_2_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_taken_0 = io_ren_uops_2_taken; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_2_imm_packed_0 = io_ren_uops_2_imm_packed; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_2_csr_addr_0 = io_ren_uops_2_csr_addr; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_rob_idx_0 = io_ren_uops_2_rob_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_ldq_idx_0 = io_ren_uops_2_ldq_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_stq_idx_0 = io_ren_uops_2_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_rxq_idx_0 = io_ren_uops_2_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_pdst_0 = io_ren_uops_2_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_prs1_0 = io_ren_uops_2_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_prs2_0 = io_ren_uops_2_prs2; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_ppred_0 = io_ren_uops_2_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_prs1_busy_0 = io_ren_uops_2_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_prs2_busy_0 = io_ren_uops_2_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ppred_busy_0 = io_ren_uops_2_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_stale_pdst_0 = io_ren_uops_2_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_exception_0 = io_ren_uops_2_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_2_exc_cause_0 = io_ren_uops_2_exc_cause; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_bypassable_0 = io_ren_uops_2_bypassable; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_mem_cmd_0 = io_ren_uops_2_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_mem_size_0 = io_ren_uops_2_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_mem_signed_0 = io_ren_uops_2_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_fence_0 = io_ren_uops_2_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_fencei_0 = io_ren_uops_2_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_amo_0 = io_ren_uops_2_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_uses_ldq_0 = io_ren_uops_2_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_uses_stq_0 = io_ren_uops_2_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_sys_pc2epc_0 = io_ren_uops_2_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_unique_0 = io_ren_uops_2_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_flush_on_commit_0 = io_ren_uops_2_flush_on_commit; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ldst_is_rs1_0 = io_ren_uops_2_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_2_ldst_0 = io_ren_uops_2_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_2_lrs1_0 = io_ren_uops_2_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_2_lrs2_0 = io_ren_uops_2_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_2_lrs3_0 = io_ren_uops_2_lrs3; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ldst_val_0 = io_ren_uops_2_ldst_val; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_dst_rtype_0 = io_ren_uops_2_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_lrs1_rtype_0 = io_ren_uops_2_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_lrs2_rtype_0 = io_ren_uops_2_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_frs3_en_0 = io_ren_uops_2_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_fp_val_0 = io_ren_uops_2_fp_val; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_fp_single_0 = io_ren_uops_2_fp_single; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_xcpt_pf_if_0 = io_ren_uops_2_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_xcpt_ae_if_0 = io_ren_uops_2_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_xcpt_ma_if_0 = io_ren_uops_2_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_bp_debug_if_0 = io_ren_uops_2_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_bp_xcpt_if_0 = io_ren_uops_2_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_debug_fsrc_0 = io_ren_uops_2_debug_fsrc; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_debug_tsrc_0 = io_ren_uops_2_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_0_0 = io_rebusy_reqs_0; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_1_0 = io_rebusy_reqs_1; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_2_0 = io_rebusy_reqs_2; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_0_0 = io_wb_pdsts_0; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_1_0 = io_wb_pdsts_1; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_2_0 = io_wb_pdsts_2; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_3_0 = io_wb_pdsts_3; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_4_0 = io_wb_pdsts_4; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_5_0 = io_wb_pdsts_5; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_6_0 = io_wb_pdsts_6; // @[rename-busytable.scala:27:7] wire io_wb_valids_0_0 = io_wb_valids_0; // @[rename-busytable.scala:27:7] wire io_wb_valids_1_0 = io_wb_valids_1; // @[rename-busytable.scala:27:7] wire io_wb_valids_2_0 = io_wb_valids_2; // @[rename-busytable.scala:27:7] wire io_wb_valids_3_0 = io_wb_valids_3; // @[rename-busytable.scala:27:7] wire io_wb_valids_4_0 = io_wb_valids_4; // @[rename-busytable.scala:27:7] wire io_wb_valids_5_0 = io_wb_valids_5; // @[rename-busytable.scala:27:7] wire io_wb_valids_6_0 = io_wb_valids_6; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_busy_resps_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_busy_resps_2_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire _io_busy_resps_0_prs1_busy_T_2 = 1'h0; // @[rename-busytable.scala:67:88] wire _io_busy_resps_0_prs2_busy_T_2 = 1'h0; // @[rename-busytable.scala:68:88] wire _io_busy_resps_0_prs3_busy_T_2 = 1'h0; // @[rename-busytable.scala:69:88] wire _io_busy_resps_1_prs1_busy_T_2 = 1'h0; // @[rename-busytable.scala:67:88] wire _io_busy_resps_1_prs2_busy_T_2 = 1'h0; // @[rename-busytable.scala:68:88] wire _io_busy_resps_1_prs3_busy_T_2 = 1'h0; // @[rename-busytable.scala:69:88] wire _io_busy_resps_2_prs1_busy_T_2 = 1'h0; // @[rename-busytable.scala:67:88] wire _io_busy_resps_2_prs2_busy_T_2 = 1'h0; // @[rename-busytable.scala:68:88] wire _io_busy_resps_2_prs3_busy_T_2 = 1'h0; // @[rename-busytable.scala:69:88] wire [6:0] io_ren_uops_0_prs3 = 7'h0; // @[rename-busytable.scala:27:7, :37:14] wire [6:0] io_ren_uops_1_prs3 = 7'h0; // @[rename-busytable.scala:27:7, :37:14] wire [6:0] io_ren_uops_2_prs3 = 7'h0; // @[rename-busytable.scala:27:7, :37:14] wire _io_busy_resps_0_prs1_busy_T_3; // @[rename-busytable.scala:67:67] wire _io_busy_resps_0_prs2_busy_T_3; // @[rename-busytable.scala:68:67] wire _io_busy_resps_1_prs1_busy_T_3; // @[rename-busytable.scala:67:67] wire _io_busy_resps_1_prs2_busy_T_3; // @[rename-busytable.scala:68:67] wire _io_busy_resps_2_prs1_busy_T_3; // @[rename-busytable.scala:67:67] wire _io_busy_resps_2_prs2_busy_T_3; // @[rename-busytable.scala:68:67] wire io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_2_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_2_prs2_busy_0; // @[rename-busytable.scala:27:7] wire [99:0] io_debug_busytable_0; // @[rename-busytable.scala:27:7] reg [99:0] busy_table; // @[rename-busytable.scala:48:27] assign io_debug_busytable_0 = busy_table; // @[rename-busytable.scala:27:7, :48:27] wire [99:0] _io_busy_resps_0_prs3_busy_T = busy_table; // @[rename-busytable.scala:48:27, :69:45] wire [99:0] _io_busy_resps_1_prs3_busy_T = busy_table; // @[rename-busytable.scala:48:27, :69:45] wire [99:0] _io_busy_resps_2_prs3_busy_T = busy_table; // @[rename-busytable.scala:48:27, :69:45] wire [127:0] _busy_table_wb_T = 128'h1 << io_wb_pdsts_0_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_1 = {100{io_wb_valids_0_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_2 = {28'h0, _busy_table_wb_T[99:0] & _busy_table_wb_T_1}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_3 = 128'h1 << io_wb_pdsts_1_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_4 = {100{io_wb_valids_1_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_5 = {28'h0, _busy_table_wb_T_3[99:0] & _busy_table_wb_T_4}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_6 = 128'h1 << io_wb_pdsts_2_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_7 = {100{io_wb_valids_2_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_8 = {28'h0, _busy_table_wb_T_6[99:0] & _busy_table_wb_T_7}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_9 = 128'h1 << io_wb_pdsts_3_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_10 = {100{io_wb_valids_3_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_11 = {28'h0, _busy_table_wb_T_9[99:0] & _busy_table_wb_T_10}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_12 = 128'h1 << io_wb_pdsts_4_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_13 = {100{io_wb_valids_4_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_14 = {28'h0, _busy_table_wb_T_12[99:0] & _busy_table_wb_T_13}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_15 = 128'h1 << io_wb_pdsts_5_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_16 = {100{io_wb_valids_5_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_17 = {28'h0, _busy_table_wb_T_15[99:0] & _busy_table_wb_T_16}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_18 = 128'h1 << io_wb_pdsts_6_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_19 = {100{io_wb_valids_6_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_20 = {28'h0, _busy_table_wb_T_18[99:0] & _busy_table_wb_T_19}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_21 = _busy_table_wb_T_2 \| _busy_table_wb_T_5; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_22 = _busy_table_wb_T_21 \| _busy_table_wb_T_8; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_23 = _busy_table_wb_T_22 \| _busy_table_wb_T_11; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_24 = _busy_table_wb_T_23 \| _busy_table_wb_T_14; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_25 = _busy_table_wb_T_24 \| _busy_table_wb_T_17; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_26 = _busy_table_wb_T_25 \| _busy_table_wb_T_20; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_27 = ~_busy_table_wb_T_26; // @[rename-busytable.scala:50:36, :51:88] wire [127:0] busy_table_wb = {28'h0, _busy_table_wb_T_27[99:0] & busy_table}; // @[rename-busytable.scala:48:27, :50:{34,36}, :51:48] wire [127:0] _busy_table_next_T = 128'h1 << io_ren_uops_0_pdst_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_next_T_1 = {100{io_rebusy_reqs_0_0}}; // @[rename-busytable.scala:27:7, :54:55] wire [127:0] _busy_table_next_T_2 = {28'h0, _busy_table_next_T[99:0] & _busy_table_next_T_1}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_3 = 128'h1 << io_ren_uops_1_pdst_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_next_T_4 = {100{io_rebusy_reqs_1_0}}; // @[rename-busytable.scala:27:7, :54:55] wire [127:0] _busy_table_next_T_5 = {28'h0, _busy_table_next_T_3[99:0] & _busy_table_next_T_4}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_6 = 128'h1 << io_ren_uops_2_pdst_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_next_T_7 = {100{io_rebusy_reqs_2_0}}; // @[rename-busytable.scala:27:7, :54:55] wire [127:0] _busy_table_next_T_8 = {28'h0, _busy_table_next_T_6[99:0] & _busy_table_next_T_7}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_9 = _busy_table_next_T_2 \| _busy_table_next_T_5; // @[rename-busytable.scala:54:{49,87}] wire [127:0] _busy_table_next_T_10 = _busy_table_next_T_9 \| _busy_table_next_T_8; // @[rename-busytable.scala:54:{49,87}] wire [127:0] busy_table_next = busy_table_wb \| _busy_table_next_T_10; // @[rename-busytable.scala:50:34, :53:39, :54:87] wire [99:0] _io_busy_resps_0_prs1_busy_T = busy_table >> io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :48:27, :67:45] wire _io_busy_resps_0_prs1_busy_T_1 = _io_busy_resps_0_prs1_busy_T[0]; // @[rename-busytable.scala:67:45] assign _io_busy_resps_0_prs1_busy_T_3 = _io_busy_resps_0_prs1_busy_T_1; // @[rename-busytable.scala:67:{45,67}] assign io_busy_resps_0_prs1_busy_0 = _io_busy_resps_0_prs1_busy_T_3; // @[rename-busytable.scala:27:7, :67:67] wire [99:0] _io_busy_resps_0_prs2_busy_T = busy_table >> io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :48:27, :68:45] wire _io_busy_resps_0_prs2_busy_T_1 = _io_busy_resps_0_prs2_busy_T[0]; // @[rename-busytable.scala:68:45] assign _io_busy_resps_0_prs2_busy_T_3 = _io_busy_resps_0_prs2_busy_T_1; // @[rename-busytable.scala:68:{45,67}] assign io_busy_resps_0_prs2_busy_0 = _io_busy_resps_0_prs2_busy_T_3; // @[rename-busytable.scala:27:7, :68:67] wire _io_busy_resps_0_prs3_busy_T_1 = _io_busy_resps_0_prs3_busy_T[0]; // @[rename-busytable.scala:69:45] wire _io_busy_resps_0_prs3_busy_T_3 = _io_busy_resps_0_prs3_busy_T_1; // @[rename-busytable.scala:69:{45,67}] wire _prs1_was_bypassed_T = io_ren_uops_1_lrs1_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :61:27] wire _prs1_was_bypassed_T_1 = _prs1_was_bypassed_T & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :61:{27,51}] wire prs1_was_bypassed = _prs1_was_bypassed_T_1; // @[rename-busytable.scala:61:{51,92}] wire _prs2_was_bypassed_T = io_ren_uops_1_lrs2_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :63:27] wire _prs2_was_bypassed_T_1 = _prs2_was_bypassed_T & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :63:{27,51}] wire prs2_was_bypassed = _prs2_was_bypassed_T_1; // @[rename-busytable.scala:63:{51,92}] wire _prs3_was_bypassed_T = io_ren_uops_1_lrs3_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :65:27] wire _prs3_was_bypassed_T_1 = _prs3_was_bypassed_T & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :65:{27,51}] wire prs3_was_bypassed = _prs3_was_bypassed_T_1; // @[rename-busytable.scala:65:{51,92}] wire [99:0] _io_busy_resps_1_prs1_busy_T = busy_table >> io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :48:27, :67:45] wire _io_busy_resps_1_prs1_busy_T_1 = _io_busy_resps_1_prs1_busy_T[0]; // @[rename-busytable.scala:67:45] assign _io_busy_resps_1_prs1_busy_T_3 = _io_busy_resps_1_prs1_busy_T_1; // @[rename-busytable.scala:67:{45,67}] assign io_busy_resps_1_prs1_busy_0 = _io_busy_resps_1_prs1_busy_T_3; // @[rename-busytable.scala:27:7, :67:67] wire [99:0] _io_busy_resps_1_prs2_busy_T = busy_table >> io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :48:27, :68:45] wire _io_busy_resps_1_prs2_busy_T_1 = _io_busy_resps_1_prs2_busy_T[0]; // @[rename-busytable.scala:68:45] assign _io_busy_resps_1_prs2_busy_T_3 = _io_busy_resps_1_prs2_busy_T_1; // @[rename-busytable.scala:68:{45,67}] assign io_busy_resps_1_prs2_busy_0 = _io_busy_resps_1_prs2_busy_T_3; // @[rename-busytable.scala:27:7, :68:67] wire _io_busy_resps_1_prs3_busy_T_1 = _io_busy_resps_1_prs3_busy_T[0]; // @[rename-busytable.scala:69:45] wire _io_busy_resps_1_prs3_busy_T_3 = _io_busy_resps_1_prs3_busy_T_1; // @[rename-busytable.scala:69:{45,67}] wire _prs1_was_bypassed_T_2 = io_ren_uops_2_lrs1_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :61:27] wire _prs1_was_bypassed_T_3 = _prs1_was_bypassed_T_2 & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :61:{27,51}] wire _prs1_was_bypassed_T_6 = _prs1_was_bypassed_T_3; // @[rename-busytable.scala:61:{51,92}] wire _prs1_was_bypassed_T_4 = io_ren_uops_2_lrs1_0 == io_ren_uops_1_ldst_0; // @[rename-busytable.scala:27:7, :61:27] wire _prs1_was_bypassed_T_5 = _prs1_was_bypassed_T_4 & io_rebusy_reqs_1_0; // @[rename-busytable.scala:27:7, :61:{27,51}] wire prs1_was_bypassed_1 = _prs1_was_bypassed_T_6 \| _prs1_was_bypassed_T_5; // @[rename-busytable.scala:61:{51,92}] wire _prs2_was_bypassed_T_2 = io_ren_uops_2_lrs2_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :63:27] wire _prs2_was_bypassed_T_3 = _prs2_was_bypassed_T_2 & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :63:{27,51}] wire _prs2_was_bypassed_T_6 = _prs2_was_bypassed_T_3; // @[rename-busytable.scala:63:{51,92}] wire _prs2_was_bypassed_T_4 = io_ren_uops_2_lrs2_0 == io_ren_uops_1_ldst_0; // @[rename-busytable.scala:27:7, :63:27] wire _prs2_was_bypassed_T_5 = _prs2_was_bypassed_T_4 & io_rebusy_reqs_1_0; // @[rename-busytable.scala:27:7, :63:{27,51}] wire prs2_was_bypassed_1 = _prs2_was_bypassed_T_6 \| _prs2_was_bypassed_T_5; // @[rename-busytable.scala:63:{51,92}] wire _prs3_was_bypassed_T_2 = io_ren_uops_2_lrs3_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :65:27] wire _prs3_was_bypassed_T_3 = _prs3_was_bypassed_T_2 & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :65:{27,51}] wire _prs3_was_bypassed_T_6 = _prs3_was_bypassed_T_3; // @[rename-busytable.scala:65:{51,92}] wire _prs3_was_bypassed_T_4 = io_ren_uops_2_lrs3_0 == io_ren_uops_1_ldst_0; // @[rename-busytable.scala:27:7, :65:27] wire _prs3_was_bypassed_T_5 = _prs3_was_bypassed_T_4 & io_rebusy_reqs_1_0; // @[rename-busytable.scala:27:7, :65:{27,51}] wire prs3_was_bypassed_1 = _prs3_was_bypassed_T_6 \| _prs3_was_bypassed_T_5; // @[rename-busytable.scala:65:{51,92}] wire [99:0] _io_busy_resps_2_prs1_busy_T = busy_table >> io_ren_uops_2_prs1_0; // @[rename-busytable.scala:27:7, :48:27, :67:45] wire _io_busy_resps_2_prs1_busy_T_1 = _io_busy_resps_2_prs1_busy_T[0]; // @[rename-busytable.scala:67:45] assign _io_busy_resps_2_prs1_busy_T_3 = _io_busy_resps_2_prs1_busy_T_1; // @[rename-busytable.scala:67:{45,67}] assign io_busy_resps_2_prs1_busy_0 = _io_busy_resps_2_prs1_busy_T_3; // @[rename-busytable.scala:27:7, :67:67] wire [99:0] _io_busy_resps_2_prs2_busy_T = busy_table >> io_ren_uops_2_prs2_0; // @[rename-busytable.scala:27:7, :48:27, :68:45] wire _io_busy_resps_2_prs2_busy_T_1 = _io_busy_resps_2_prs2_busy_T[0]; // @[rename-busytable.scala:68:45] assign _io_busy_resps_2_prs2_busy_T_3 = _io_busy_resps_2_prs2_busy_T_1; // @[rename-busytable.scala:68:{45,67}] assign io_busy_resps_2_prs2_busy_0 = _io_busy_resps_2_prs2_busy_T_3; // @[rename-busytable.scala:27:7, :68:67] wire _io_busy_resps_2_prs3_busy_T_1 = _io_busy_resps_2_prs3_busy_T[0]; // @[rename-busytable.scala:69:45] wire _io_busy_resps_2_prs3_busy_T_3 = _io_busy_resps_2_prs3_busy_T_1; // @[rename-busytable.scala:69:{45,67}] always @(posedge clock) begin // @[rename-busytable.scala:27:7] if (reset) // @[rename-busytable.scala:27:7] busy_table <= 100'h0; // @[rename-busytable.scala:48:27] else // @[rename-busytable.scala:27:7] busy_table <= busy_table_next[99:0]; // @[rename-busytable.scala:48:27, :53:39, :56:14] always @(posedge) assign io_busy_resps_0_prs1_busy = io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_0_prs2_busy = io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_1_prs1_busy = io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_1_prs2_busy = io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_2_prs1_busy = io_busy_resps_2_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_2_prs2_busy = io_busy_resps_2_prs2_busy_0; // @[rename-busytable.scala:27:7] assign io_debug_busytable = io_debug_busytable_0; // @[rename-busytable.scala:27:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }	module EgressUnit_31( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [36:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [36:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30]
Generate the Verilog code corresponding to the following Chisel files. File ShiftQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ /** Implements the same interface as chisel3.util.Queue, but uses a shift * register internally. It is less energy efficient whenever the queue * has more than one entry populated, but is faster on the dequeue side. * It is efficient for usually-empty flow-through queues. */ class ShiftQueue[T <: Data](gen: T, val entries: Int, pipe: Boolean = false, flow: Boolean = false) extends Module { val io = IO(new QueueIO(gen, entries) { val mask = Output(UInt(entries.W)) }) private val valid = RegInit(VecInit(Seq.fill(entries) { false.B })) private val elts = Reg(Vec(entries, gen)) for (i <- 0 until entries) { def paddedValid(i: Int) = if (i == -1) true.B else if (i == entries) false.B else valid(i) val wdata = if (i == entries-1) io.enq.bits else Mux(valid(i+1), elts(i+1), io.enq.bits) val wen = Mux(io.deq.ready, paddedValid(i+1) \|\| io.enq.fire && ((i == 0 && !flow).B \|\| valid(i)), io.enq.fire && paddedValid(i-1) && !valid(i)) when (wen) { elts(i) := wdata } valid(i) := Mux(io.deq.ready, paddedValid(i+1) \|\| io.enq.fire && ((i == 0 && !flow).B \|\| valid(i)), io.enq.fire && paddedValid(i-1) \|\| valid(i)) } io.enq.ready := !valid(entries-1) io.deq.valid := valid(0) io.deq.bits := elts.head if (flow) { when (io.enq.valid) { io.deq.valid := true.B } when (!valid(0)) { io.deq.bits := io.enq.bits } } if (pipe) { when (io.deq.ready) { io.enq.ready := true.B } } io.mask := valid.asUInt io.count := PopCount(io.mask) } object ShiftQueue { def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false, flow: Boolean = false): DecoupledIO[T] = { val q = Module(new ShiftQueue(enq.bits.cloneType, entries, pipe, flow)) q.io.enq <> enq q.io.deq } }	module ShiftQueue( // @[ShiftQueue.scala:12:7] input clock, // @[ShiftQueue.scala:12:7] input reset, // @[ShiftQueue.scala:12:7] output io_enq_ready, // @[ShiftQueue.scala:17:14] input io_enq_valid, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_taken, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] input [47:0] io_enq_bits_btb_target, // @[ShiftQueue.scala:17:14] input [4:0] io_enq_bits_btb_entry, // @[ShiftQueue.scala:17:14] input [7:0] io_enq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] input [48:0] io_enq_bits_pc, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_data, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_replay, // @[ShiftQueue.scala:17:14] input io_deq_ready, // @[ShiftQueue.scala:17:14] output io_deq_valid, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_taken, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] output [47:0] io_deq_bits_btb_target, // @[ShiftQueue.scala:17:14] output [4:0] io_deq_bits_btb_entry, // @[ShiftQueue.scala:17:14] output [7:0] io_deq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] output [48:0] io_deq_bits_pc, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_data, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_gf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_replay, // @[ShiftQueue.scala:17:14] output [4:0] io_mask // @[ShiftQueue.scala:17:14] ); wire io_enq_valid_0 = io_enq_valid; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_cfiType_0 = io_enq_bits_btb_cfiType; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_taken_0 = io_enq_bits_btb_taken; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_mask_0 = io_enq_bits_btb_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bridx_0 = io_enq_bits_btb_bridx; // @[ShiftQueue.scala:12:7] wire [47:0] io_enq_bits_btb_target_0 = io_enq_bits_btb_target; // @[ShiftQueue.scala:12:7] wire [4:0] io_enq_bits_btb_entry_0 = io_enq_bits_btb_entry; // @[ShiftQueue.scala:12:7] wire [7:0] io_enq_bits_btb_bht_history_0 = io_enq_bits_btb_bht_history; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bht_value_0 = io_enq_bits_btb_bht_value; // @[ShiftQueue.scala:12:7] wire [48:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_data_0 = io_enq_bits_data; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_pf_inst_0 = io_enq_bits_xcpt_pf_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_ae_inst_0 = io_enq_bits_xcpt_ae_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_replay_0 = io_enq_bits_replay; // @[ShiftQueue.scala:12:7] wire io_deq_ready_0 = io_deq_ready; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_gf_inst = 1'h0; // @[ShiftQueue.scala:12:7] wire _valid_WIRE_0 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_1 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_2 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_3 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_4 = 1'h0; // @[ShiftQueue.scala:21:38] wire _io_enq_ready_T; // @[ShiftQueue.scala:40:19] wire [2:0] _io_count_T_12; // @[ShiftQueue.scala:54:23] wire [4:0] _io_mask_T; // @[ShiftQueue.scala:53:20] wire io_enq_ready_0; // @[ShiftQueue.scala:12:7] wire [7:0] io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] wire [47:0] io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] wire [4:0] io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] wire [48:0] io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] wire io_deq_valid_0; // @[ShiftQueue.scala:12:7] wire [2:0] io_count; // @[ShiftQueue.scala:12:7] wire [4:0] io_mask_0; // @[ShiftQueue.scala:12:7] reg valid_0; // @[ShiftQueue.scala:21:30] wire _wen_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_0_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :36:67] reg valid_1; // @[ShiftQueue.scala:21:30] wire _wen_T_9 = valid_1; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_1_T_1 = valid_1; // @[ShiftQueue.scala:21:30, :36:67] reg valid_2; // @[ShiftQueue.scala:21:30] wire _wen_T_17 = valid_2; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_2_T_1 = valid_2; // @[ShiftQueue.scala:21:30, :36:67] reg valid_3; // @[ShiftQueue.scala:21:30] wire _wen_T_25 = valid_3; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_3_T_1 = valid_3; // @[ShiftQueue.scala:21:30, :36:67] reg valid_4; // @[ShiftQueue.scala:21:30] wire _wen_T_33 = valid_4; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_4_T_1 = valid_4; // @[ShiftQueue.scala:21:30, :36:67] reg [1:0] elts_0_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_0_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bridx; // @[ShiftQueue.scala:22:25] reg [47:0] elts_0_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_0_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_0_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [48:0] elts_0_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_mask; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_0_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_1_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bridx; // @[ShiftQueue.scala:22:25] reg [47:0] elts_1_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_1_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_1_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [48:0] elts_1_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_mask; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_1_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_2_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bridx; // @[ShiftQueue.scala:22:25] reg [47:0] elts_2_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_2_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_2_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [48:0] elts_2_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_mask; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_2_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_3_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bridx; // @[ShiftQueue.scala:22:25] reg [47:0] elts_3_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_3_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_3_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [48:0] elts_3_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_mask; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_3_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_4_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bridx; // @[ShiftQueue.scala:22:25] reg [47:0] elts_4_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_4_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_4_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [48:0] elts_4_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_mask; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_4_replay; // @[ShiftQueue.scala:22:25] wire [1:0] wdata_btb_cfiType = valid_1 ? elts_1_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_taken = valid_1 ? elts_1_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_btb_mask = valid_1 ? elts_1_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bridx = valid_1 ? elts_1_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [47:0] wdata_btb_target = valid_1 ? elts_1_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_btb_entry = valid_1 ? elts_1_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_btb_bht_history = valid_1 ? elts_1_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bht_value = valid_1 ? elts_1_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [48:0] wdata_pc = valid_1 ? elts_1_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_data = valid_1 ? elts_1_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_mask = valid_1 ? elts_1_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_pf_inst = valid_1 ? elts_1_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_gf_inst = valid_1 & elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_xcpt_ae_inst = valid_1 ? elts_1_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_replay = valid_1 ? elts_1_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _GEN = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _wen_T; // @[Decoupled.scala:51:35] assign _wen_T = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_4; // @[Decoupled.scala:51:35] assign _wen_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T; // @[Decoupled.scala:51:35] assign _valid_0_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T_4; // @[Decoupled.scala:51:35] assign _valid_0_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_8; // @[Decoupled.scala:51:35] assign _wen_T_8 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_12; // @[Decoupled.scala:51:35] assign _wen_T_12 = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T; // @[Decoupled.scala:51:35] assign _valid_1_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T_4; // @[Decoupled.scala:51:35] assign _valid_1_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_16; // @[Decoupled.scala:51:35] assign _wen_T_16 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_20; // @[Decoupled.scala:51:35] assign _wen_T_20 = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T; // @[Decoupled.scala:51:35] assign _valid_2_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T_4; // @[Decoupled.scala:51:35] assign _valid_2_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_24; // @[Decoupled.scala:51:35] assign _wen_T_24 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_28; // @[Decoupled.scala:51:35] assign _wen_T_28 = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T; // @[Decoupled.scala:51:35] assign _valid_3_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T_4; // @[Decoupled.scala:51:35] assign _valid_3_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_32; // @[Decoupled.scala:51:35] assign _wen_T_32 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_36; // @[Decoupled.scala:51:35] assign _wen_T_36 = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T; // @[Decoupled.scala:51:35] assign _valid_4_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T_4; // @[Decoupled.scala:51:35] assign _valid_4_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Decoupled.scala:51:35] wire _wen_T_3 = valid_1 \| _wen_T_2; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_5 = _wen_T_4; // @[Decoupled.scala:51:35] wire _wen_T_6 = ~valid_0; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_7 = _wen_T_5 & _wen_T_6; // @[ShiftQueue.scala:31:{23,43,46}] wire wen = io_deq_ready_0 ? _wen_T_3 : _wen_T_7; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_0_T_2 = _valid_0_T & _valid_0_T_1; // @[Decoupled.scala:51:35] wire _valid_0_T_3 = valid_1 \| _valid_0_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_0_T_5 = _valid_0_T_4; // @[Decoupled.scala:51:35] wire _valid_0_T_6 = _valid_0_T_5 \| valid_0; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_0_T_7 = io_deq_ready_0 ? _valid_0_T_3 : _valid_0_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_1_btb_cfiType = valid_2 ? elts_2_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_taken = valid_2 ? elts_2_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_btb_mask = valid_2 ? elts_2_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bridx = valid_2 ? elts_2_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [47:0] wdata_1_btb_target = valid_2 ? elts_2_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_1_btb_entry = valid_2 ? elts_2_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_1_btb_bht_history = valid_2 ? elts_2_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bht_value = valid_2 ? elts_2_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [48:0] wdata_1_pc = valid_2 ? elts_2_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_data = valid_2 ? elts_2_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_mask = valid_2 ? elts_2_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_pf_inst = valid_2 ? elts_2_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_gf_inst = valid_2 & elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_1_xcpt_ae_inst = valid_2 ? elts_2_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_replay = valid_2 ? elts_2_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_10 = _wen_T_8 & _wen_T_9; // @[Decoupled.scala:51:35] wire _wen_T_11 = valid_2 \| _wen_T_10; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_13 = _wen_T_12 & valid_0; // @[Decoupled.scala:51:35] wire _wen_T_14 = ~valid_1; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_15 = _wen_T_13 & _wen_T_14; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_1 = io_deq_ready_0 ? _wen_T_11 : _wen_T_15; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_1_T_2 = _valid_1_T & _valid_1_T_1; // @[Decoupled.scala:51:35] wire _valid_1_T_3 = valid_2 \| _valid_1_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_1_T_5 = _valid_1_T_4 & valid_0; // @[Decoupled.scala:51:35] wire _valid_1_T_6 = _valid_1_T_5 \| valid_1; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_1_T_7 = io_deq_ready_0 ? _valid_1_T_3 : _valid_1_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_2_btb_cfiType = valid_3 ? elts_3_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_taken = valid_3 ? elts_3_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_btb_mask = valid_3 ? elts_3_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bridx = valid_3 ? elts_3_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [47:0] wdata_2_btb_target = valid_3 ? elts_3_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_2_btb_entry = valid_3 ? elts_3_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_2_btb_bht_history = valid_3 ? elts_3_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bht_value = valid_3 ? elts_3_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [48:0] wdata_2_pc = valid_3 ? elts_3_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_data = valid_3 ? elts_3_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_mask = valid_3 ? elts_3_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_pf_inst = valid_3 ? elts_3_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_gf_inst = valid_3 & elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_2_xcpt_ae_inst = valid_3 ? elts_3_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_replay = valid_3 ? elts_3_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_18 = _wen_T_16 & _wen_T_17; // @[Decoupled.scala:51:35] wire _wen_T_19 = valid_3 \| _wen_T_18; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_21 = _wen_T_20 & valid_1; // @[Decoupled.scala:51:35] wire _wen_T_22 = ~valid_2; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_23 = _wen_T_21 & _wen_T_22; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_2 = io_deq_ready_0 ? _wen_T_19 : _wen_T_23; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_2_T_2 = _valid_2_T & _valid_2_T_1; // @[Decoupled.scala:51:35] wire _valid_2_T_3 = valid_3 \| _valid_2_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_2_T_5 = _valid_2_T_4 & valid_1; // @[Decoupled.scala:51:35] wire _valid_2_T_6 = _valid_2_T_5 \| valid_2; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_2_T_7 = io_deq_ready_0 ? _valid_2_T_3 : _valid_2_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_3_btb_cfiType = valid_4 ? elts_4_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_taken = valid_4 ? elts_4_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_btb_mask = valid_4 ? elts_4_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bridx = valid_4 ? elts_4_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [47:0] wdata_3_btb_target = valid_4 ? elts_4_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_3_btb_entry = valid_4 ? elts_4_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_3_btb_bht_history = valid_4 ? elts_4_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bht_value = valid_4 ? elts_4_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [48:0] wdata_3_pc = valid_4 ? elts_4_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_data = valid_4 ? elts_4_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_mask = valid_4 ? elts_4_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_pf_inst = valid_4 ? elts_4_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_gf_inst = valid_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_3_xcpt_ae_inst = valid_4 ? elts_4_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_replay = valid_4 ? elts_4_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_26 = _wen_T_24 & _wen_T_25; // @[Decoupled.scala:51:35] wire _wen_T_27 = valid_4 \| _wen_T_26; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_29 = _wen_T_28 & valid_2; // @[Decoupled.scala:51:35] wire _wen_T_30 = ~valid_3; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_31 = _wen_T_29 & _wen_T_30; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_3 = io_deq_ready_0 ? _wen_T_27 : _wen_T_31; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_3_T_2 = _valid_3_T & _valid_3_T_1; // @[Decoupled.scala:51:35] wire _valid_3_T_3 = valid_4 \| _valid_3_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_3_T_5 = _valid_3_T_4 & valid_2; // @[Decoupled.scala:51:35] wire _valid_3_T_6 = _valid_3_T_5 \| valid_3; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_3_T_7 = io_deq_ready_0 ? _valid_3_T_3 : _valid_3_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire _wen_T_34 = _wen_T_32 & _wen_T_33; // @[Decoupled.scala:51:35] wire _wen_T_35 = _wen_T_34; // @[ShiftQueue.scala:30:{28,43}] wire _wen_T_37 = _wen_T_36 & valid_3; // @[Decoupled.scala:51:35] wire _wen_T_38 = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_39 = _wen_T_37 & _wen_T_38; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_4 = io_deq_ready_0 ? _wen_T_35 : _wen_T_39; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_4_T_2 = _valid_4_T & _valid_4_T_1; // @[Decoupled.scala:51:35] wire _valid_4_T_3 = _valid_4_T_2; // @[ShiftQueue.scala:36:{28,43}] wire _valid_4_T_5 = _valid_4_T_4 & valid_3; // @[Decoupled.scala:51:35] wire _valid_4_T_6 = _valid_4_T_5 \| valid_4; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_4_T_7 = io_deq_ready_0 ? _valid_4_T_3 : _valid_4_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] assign _io_enq_ready_T = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46, :40:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[ShiftQueue.scala:12:7, :40:19] assign io_deq_valid_0 = io_enq_valid_0 \| valid_0; // @[ShiftQueue.scala:12:7, :21:30, :41:16, :45:{25,40}] assign io_deq_bits_btb_cfiType_0 = valid_0 ? elts_0_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_taken_0 = valid_0 ? elts_0_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_mask_0 = valid_0 ? elts_0_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bridx_0 = valid_0 ? elts_0_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_target_0 = valid_0 ? elts_0_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_entry_0 = valid_0 ? elts_0_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_history_0 = valid_0 ? elts_0_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_value_0 = valid_0 ? elts_0_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_pc_0 = valid_0 ? elts_0_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_data_0 = valid_0 ? elts_0_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_mask_0 = valid_0 ? elts_0_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_pf_inst_0 = valid_0 ? elts_0_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_gf_inst_0 = valid_0 & elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_ae_inst_0 = valid_0 ? elts_0_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_replay_0 = valid_0 ? elts_0_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] wire [1:0] io_mask_lo = {valid_1, valid_0}; // @[ShiftQueue.scala:21:30, :53:20] wire [1:0] io_mask_hi_hi = {valid_4, valid_3}; // @[ShiftQueue.scala:21:30, :53:20] wire [2:0] io_mask_hi = {io_mask_hi_hi, valid_2}; // @[ShiftQueue.scala:21:30, :53:20] assign _io_mask_T = {io_mask_hi, io_mask_lo}; // @[ShiftQueue.scala:53:20] assign io_mask_0 = _io_mask_T; // @[ShiftQueue.scala:12:7, :53:20] wire _io_count_T = io_mask_0[0]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_1 = io_mask_0[1]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_2 = io_mask_0[2]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_3 = io_mask_0[3]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_4 = io_mask_0[4]; // @[ShiftQueue.scala:12:7, :54:23] wire [1:0] _io_count_T_5 = {1'h0, _io_count_T} + {1'h0, _io_count_T_1}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_6 = _io_count_T_5; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_7 = {1'h0, _io_count_T_3} + {1'h0, _io_count_T_4}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_8 = _io_count_T_7; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_9 = {2'h0, _io_count_T_2} + {1'h0, _io_count_T_8}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_10 = _io_count_T_9[1:0]; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_11 = {1'h0, _io_count_T_6} + {1'h0, _io_count_T_10}; // @[ShiftQueue.scala:54:23] assign _io_count_T_12 = _io_count_T_11; // @[ShiftQueue.scala:54:23] assign io_count = _io_count_T_12; // @[ShiftQueue.scala:12:7, :54:23] always @(posedge clock) begin // @[ShiftQueue.scala:12:7] if (reset) begin // @[ShiftQueue.scala:12:7] valid_0 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_1 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_2 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_3 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_4 <= 1'h0; // @[ShiftQueue.scala:21:30] end else begin // @[ShiftQueue.scala:12:7] valid_0 <= _valid_0_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_1 <= _valid_1_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_2 <= _valid_2_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_3 <= _valid_3_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_4 <= _valid_4_T_7; // @[ShiftQueue.scala:21:30, :35:10] end if (wen) begin // @[ShiftQueue.scala:29:10] elts_0_btb_cfiType <= wdata_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_taken <= wdata_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_mask <= wdata_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bridx <= wdata_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_target <= wdata_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_entry <= wdata_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_history <= wdata_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_value <= wdata_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_0_pc <= wdata_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_0_data <= wdata_data; // @[ShiftQueue.scala:22:25, :27:57] elts_0_mask <= wdata_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_pf_inst <= wdata_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_gf_inst <= wdata_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_ae_inst <= wdata_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_replay <= wdata_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_1) begin // @[ShiftQueue.scala:29:10] elts_1_btb_cfiType <= wdata_1_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_taken <= wdata_1_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_mask <= wdata_1_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bridx <= wdata_1_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_target <= wdata_1_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_entry <= wdata_1_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_history <= wdata_1_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_value <= wdata_1_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_1_pc <= wdata_1_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_1_data <= wdata_1_data; // @[ShiftQueue.scala:22:25, :27:57] elts_1_mask <= wdata_1_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_pf_inst <= wdata_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_gf_inst <= wdata_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_ae_inst <= wdata_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_replay <= wdata_1_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_2) begin // @[ShiftQueue.scala:29:10] elts_2_btb_cfiType <= wdata_2_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_taken <= wdata_2_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_mask <= wdata_2_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bridx <= wdata_2_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_target <= wdata_2_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_entry <= wdata_2_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_history <= wdata_2_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_value <= wdata_2_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_2_pc <= wdata_2_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_2_data <= wdata_2_data; // @[ShiftQueue.scala:22:25, :27:57] elts_2_mask <= wdata_2_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_pf_inst <= wdata_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_gf_inst <= wdata_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_ae_inst <= wdata_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_replay <= wdata_2_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_3) begin // @[ShiftQueue.scala:29:10] elts_3_btb_cfiType <= wdata_3_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_taken <= wdata_3_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_mask <= wdata_3_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bridx <= wdata_3_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_target <= wdata_3_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_entry <= wdata_3_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_history <= wdata_3_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_value <= wdata_3_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_3_pc <= wdata_3_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_3_data <= wdata_3_data; // @[ShiftQueue.scala:22:25, :27:57] elts_3_mask <= wdata_3_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_pf_inst <= wdata_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_gf_inst <= wdata_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_ae_inst <= wdata_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_replay <= wdata_3_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_4) begin // @[ShiftQueue.scala:29:10] elts_4_btb_cfiType <= io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_taken <= io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_mask <= io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bridx <= io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_target <= io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_entry <= io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_history <= io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_value <= io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_pc <= io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_data <= io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_mask <= io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_pf_inst <= io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_replay <= io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :22:25] end elts_4_xcpt_gf_inst <= ~wen_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :29:10, :32:{16,26}] always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[ShiftQueue.scala:12:7] assign io_deq_valid = io_deq_valid_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_cfiType = io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_taken = io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_mask = io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bridx = io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_target = io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_entry = io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_history = io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_value = io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_pc = io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_pf_inst = io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_gf_inst = io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_ae_inst = io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_replay = io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] assign io_mask = io_mask_0; // @[ShiftQueue.scala:12:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_146( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_156 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundRawFNToRecFN_e8_s24_110( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_110 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_56( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File tage.scala: package boom.v4.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f2_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)l, histLength)-1, il) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val us = SyncReadMem(nRows, Vec(bankWidth2, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) us.suggestName(s"tage_u_${histLength}") table.suggestName(s"tage_table_${histLength}") val mems = Seq((f"tage_l$histLength", nRows, bankWidth tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry)) val s2_req_rus = Wire(Vec(bankWidth2, Bool())) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f2_resp(w).valid := s2_req_rhits(w) io.f2_resp(w).bits.u := Cat(s2_req_rus(w2+1), s2_req_rus(w2)) io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val clear_u_mask = VecInit((0 until bankWidth2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) val wen = WireInit(doing_reset \|\| io.update_mask.reduce(_\|\|_)) val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid) when (RegNext(wen) && singlePorted.B) { s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry)) } .otherwise { s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry))) } when (wen) { val widx = Mux(doing_reset, reset_idx, update_idx) val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))) val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt) table.write(widx, wdata, wmask.asBools) } val update_u_mask = VecInit((0 until bankWidth2) map {i => io.update_u_mask(i / 2)}) val update_u_wen = WireInit(doing_reset \|\| doing_clear_u \|\| update_u_mask.reduce(_\|\|_)) val u_rdata = if (singlePorted) { us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid) } else { us.read(s1_hashed_idx, io.f1_req_valid) } s2_req_rus := u_rdata when (update_u_wen) { val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx)) val wdata = Mux(doing_reset \|\| doing_clear_u, VecInit(0.U((bankWidth2).W).asBools), VecInit(io.update_u.asUInt.asBools)) val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt)) us.write(widx, wdata, wmask.asBools) } val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_\|\|_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag } when (io.update_mask.reduce(_\|\|_)) { when (wrbypass_hits.reduce(_\|\|_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048, singlePorted: Boolean = false ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc)) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f2_resps = VecInit(tables.map(_.io.f2_resp)) val f3_resps = RegNext(f2_resps) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var s2_provided = false.B var s2_provider = 0.U var s2_alt_provided = false.B var s2_alt_provider = 0.U for (i <- 0 until tageNTables) { val hit = f2_resps(i)(w).valid s2_alt_provided = s2_alt_provided \|\| (s2_provided && hit) s2_provided = s2_provided \|\| hit s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider) s2_provider = Mux(hit, i.U, s2_provider) } val s3_provided = RegNext(s2_provided) val s3_provider = RegNext(s2_provider) val s3_alt_provided = RegNext(s2_alt_provided) val s3_alt_provider = RegNext(s2_alt_provider) val prov = RegNext(f2_resps(s2_provider)(w).bits) val alt = RegNext(f2_resps(s2_alt_provider)(w).bits) io.resp.f3(w).taken := Mux(s3_provided, Mux(prov.ctr === 3.U \|\| prov.ctr === 4.U, Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken), prov.ctr(2)), io.resp_in(0).f3(w).taken ) f3_meta.provider(w).valid := s3_provided f3_meta.provider(w).bits := s3_provider f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken f3_meta.provider_u(w) := prov.u f3_meta.provider_ctr(w) := prov.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }	module TageTable_4( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f2_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14] output io_f2_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14] output io_f2_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14] output io_f2_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire [51:0] _tage_table_32_R0_data; // @[tage.scala:90:27] wire [7:0] _tage_u_32_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26] wire [12:0] _wdata_WIRE_0 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_1 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_2 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_3 = 13'h0; // @[tage.scala:130:41] wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34] wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58] wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34] wire s2_req_rhits_0; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_1; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_2; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_3; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34] wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26] wire [7:0] _reset_idx_T = _GEN + {7'h0, doing_reset}; // @[tage.scala:72:28, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [6:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2 = io_f1_req_ghist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3 = io_f1_req_ghist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [3:0] idx_history_hist_chunks_4 = io_f1_req_ghist_0[31:28]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_1 = _idx_history_T ^ idx_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_2 = _idx_history_T_1 ^ idx_history_hist_chunks_3; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history = {_idx_history_T_2[6:4], _idx_history_T_2[3:0] ^ idx_history_hist_chunks_4}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T = io_f1_req_pc_0[39:11]; // @[frontend.scala:149:35] wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[10:4] ^ idx_history}; // @[frontend.scala:149:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99] wire [6:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12] wire [8:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2 = io_f1_req_ghist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [4:0] tag_history_hist_chunks_3 = io_f1_req_ghist_0[31:27]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_1 = _tag_history_T ^ tag_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history = {_tag_history_T_1[8:5], _tag_history_T_1[4:0] ^ tag_history_hist_chunks_3}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_1 = {_tag_T[28:9], _tag_T[8:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] s1_tag = _tag_T_1[8:0]; // @[tage.scala:62:{50,64}] wire wdata_1_0; // @[tage.scala:145:20] wire wdata_1_1; // @[tage.scala:145:20] wire wdata_1_2; // @[tage.scala:145:20] wire wdata_1_3; // @[tage.scala:145:20] wire wdata_1_4; // @[tage.scala:145:20] wire wdata_1_5; // @[tage.scala:145:20] wire wdata_1_6; // @[tage.scala:145:20] wire wdata_1_7; // @[tage.scala:145:20] wire s2_req_rus_0 = _tage_u_32_R0_data[0]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_1 = _tage_u_32_R0_data[1]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_2 = _tage_u_32_R0_data[2]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_3 = _tage_u_32_R0_data[3]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_4 = _tage_u_32_R0_data[4]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_5 = _tage_u_32_R0_data[5]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_6 = _tage_u_32_R0_data[6]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_7 = _tage_u_32_R0_data[7]; // @[tage.scala:89:27, :99:24] wire [12:0] wdata_0; // @[tage.scala:130:20] wire [12:0] wdata_1; // @[tage.scala:130:20] wire [12:0] wdata_2; // @[tage.scala:130:20] wire [12:0] wdata_3; // @[tage.scala:130:20] reg [8:0] s2_tag; // @[tage.scala:96:29] assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26] wire s2_req_rtage_0_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_0_tag; // @[tage.scala:98:26] wire s2_req_rtage_1_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_1_tag; // @[tage.scala:98:26] wire s2_req_rtage_2_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_2_tag; // @[tage.scala:98:26] wire s2_req_rtage_3_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_3_tag; // @[tage.scala:98:26] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29] assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29] assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29] assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29] assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31] wire _clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31, :114:31] wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}] wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}] wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109] wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109] wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109] wire [6:0] idx_history_hist_chunks_0_1 = io_update_hist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1_1 = io_update_hist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2_1 = io_update_hist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3_1 = io_update_hist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [3:0] idx_history_hist_chunks_4_1 = io_update_hist_0[31:28]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T_3 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_4 = _idx_history_T_3 ^ idx_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_5 = _idx_history_T_4 ^ idx_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history_1 = {_idx_history_T_5[6:4], _idx_history_T_5[3:0] ^ idx_history_hist_chunks_4_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_2 = io_update_pc_0[39:11]; // @[frontend.scala:149:35] wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[10:4] ^ idx_history_1}; // @[frontend.scala:149:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [8:0] tag_history_hist_chunks_0_1 = io_update_hist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1_1 = io_update_hist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2_1 = io_update_hist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [4:0] tag_history_hist_chunks_3_1 = io_update_hist_0[31:27]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T_2 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_3 = _tag_history_T_2 ^ tag_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history_1 = {_tag_history_T_3[8:5], _tag_history_T_3[4:0] ^ tag_history_hist_chunks_3_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_3 = {_tag_T_2[28:9], _tag_T_2[8:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] update_tag = _tag_T_3[8:0]; // @[tage.scala:62:{50,64}] wire [8:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26] wire _wen_T = io_update_mask_0_0 \| io_update_mask_1_0; // @[tage.scala:24:7, :121:60] wire _wen_T_1 = _wen_T \| io_update_mask_2_0; // @[tage.scala:24:7, :121:60] wire _wen_T_2 = _wen_T_1 \| io_update_mask_3_0; // @[tage.scala:24:7, :121:60] wire _wen_T_3 = doing_reset \| _wen_T_2; // @[tage.scala:72:28, :121:{34,60}] wire wen = _wen_T_3; // @[tage.scala:121:{21,34}] reg REG; // @[tage.scala:123:16] assign s2_req_rtage_0_ctr = _tage_table_32_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_tag = _tage_table_32_R0_data[11:3]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_valid = _tage_table_32_R0_data[12]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_ctr = _tage_table_32_R0_data[15:13]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_tag = _tage_table_32_R0_data[24:16]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_valid = _tage_table_32_R0_data[25]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_ctr = _tage_table_32_R0_data[28:26]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_tag = _tage_table_32_R0_data[37:29]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_valid = _tage_table_32_R0_data[38]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_ctr = _tage_table_32_R0_data[41:39]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_tag = _tage_table_32_R0_data[50:42]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_valid = _tage_table_32_R0_data[51]; // @[tage.scala:90:27, :98:26, :126:49] wire [6:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19] wire [9:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}] assign wdata_0 = doing_reset ? 13'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}] assign wdata_1 = doing_reset ? 13'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}] assign wdata_2 = doing_reset ? 13'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}] assign wdata_3 = doing_reset ? 13'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}] wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70] wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70] wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70] wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}] wire _GEN_0 = doing_reset \| doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43] wire _update_u_wen_T; // @[tage.scala:136:43] assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43] wire _wdata_T_4; // @[tage.scala:145:33] assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33] wire _update_u_wen_T_1 = update_u_mask_0 \| update_u_mask_1; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_2 = _update_u_wen_T_1 \| update_u_mask_2; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_3 = _update_u_wen_T_2 \| update_u_mask_3; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_4 = _update_u_wen_T_3 \| update_u_mask_4; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_5 = _update_u_wen_T_4 \| update_u_mask_5; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_6 = _update_u_wen_T_5 \| update_u_mask_6; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_7 = _update_u_wen_T_6 \| update_u_mask_7; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_8 = _update_u_wen_T \| _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}] wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}] wire [7:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47] wire [7:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}] wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110] wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110] wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110] wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}] wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}] wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}] wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}] wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}] wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}] wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}] wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}] assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}] assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}] assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}] assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}] assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}] assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}] assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}] assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}] wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106] wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106] wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106] wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}] wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}] reg [8:0] wrbypass_tags_0; // @[tage.scala:154:29] reg [8:0] wrbypass_tags_1; // @[tage.scala:154:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:155:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:155:29] reg [2:0] wrbypass_0_0; // @[tage.scala:156:29] reg [2:0] wrbypass_0_1; // @[tage.scala:156:29] reg [2:0] wrbypass_0_2; // @[tage.scala:156:29] reg [2:0] wrbypass_0_3; // @[tage.scala:156:29] reg [2:0] wrbypass_1_0; // @[tage.scala:156:29] reg [2:0] wrbypass_1_1; // @[tage.scala:156:29] reg [2:0] wrbypass_1_2; // @[tage.scala:156:29] reg [2:0] wrbypass_1_3; // @[tage.scala:156:29] reg wrbypass_enq_idx; // @[tage.scala:157:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37] wire wrbypass_hit = wrbypass_hits_0 \| wrbypass_hits_1; // @[tage.scala:159:33, :164:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}] wire _T_31 = _wen_T \| io_update_mask_2_0 \| io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_31 \| wrbypass_hit \| wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] wire _GEN_15 = ~_T_31 \| wrbypass_hit \| ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_31 \| wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39] end else // @[tage.scala:157:33, :180:38, :181:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29] REG <= wen; // @[tage.scala:121:21, :123:16] if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29] if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29] if (~_T_31 \| _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] end else begin // @[tage.scala:156:29, :180:38, :181:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end always @(posedge) tage_u_32 tage_u_32 ( // @[tage.scala:89:27] .R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_u_32_R0_data), .W0_addr (widx_1[6:0]), // @[tage.scala:144:19, :147:13] .W0_en (update_u_wen), // @[tage.scala:136:30] .W0_clk (clock), .W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20] .W0_mask (wmask_1) // @[tage.scala:146:20] ); // @[tage.scala:89:27] tage_table_32 tage_table_32 ( // @[tage.scala:90:27] .R0_addr (_rdata_WIRE), // @[tage.scala:122:99] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_table_32_R0_data), .W0_addr (widx), // @[tage.scala:129:19] .W0_en (wen), // @[tage.scala:121:21] .W0_clk (clock), .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20] .W0_mask (wmask) // @[tage.scala:131:20] ); // @[tage.scala:90:27] assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_11( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1492 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1492; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1492; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1565 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1565; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1565; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1565; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1418 = _T_1492 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1418 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1418 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1418 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1418 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1418 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1464 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1464 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1433 = _T_1565 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1433 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1433 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1433 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1536 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1536 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1518 = _T_1565 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1518 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1518 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1518 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } def logCritical(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } } def logWaveStyle(format: String, args: Bits)(implicit p: Parameters) { } } object CompressAccelParams { } File CompressedBitsBuffer.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig, HellaCacheArbiter} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.tilelink._ class WriteBitsBundle(val dataWidth: Int) extends Bundle { val data = UInt(dataWidth.W) val validbits = UInt(log2Ceil(dataWidth + 1).W) val end_of_message = Bool() } class BitsConsumerBundle(val dataWidth: Int) extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) val consumed_bytes = Input(UInt(log2Ceil(dataWidth + 1).W)) val avail_bytes = Output(UInt(log2Ceil(dataWidth + 1).W)) val data = Output(UInt(dataWidth.W)) val last_chunk = Output(Bool()) } class CompressedBitsBuffIO(val dataWidth: Int) extends Bundle { val writes_in = Flipped(Decoupled(new WriteBitsBundle(dataWidth))) val consumer = new BitsConsumerBundle(dataWidth) } // input interface is just like memwriter except that it is in bit granularity instead of byte granularity // output interface is just like memloader class CompressedBitsBuff(val unroll_cnt: Int, val max_bits_per_code: Int)(implicit p: Parameters) extends Module { // val HUF_CODE_MAX_BITS = 11 val dataWidth = max_bits_per_code * unroll_cnt val dataWidthByteAligned = if (dataWidth % 8 == 0) dataWidth else (dataWidth/8 + 1) * 8 // 8 byte interface val NUM_QUEUES = if (dataWidthByteAligned <= 64) { 64 } else if (dataWidthByteAligned <= 128) { 128 } else if (dataWidthByteAligned <= 256) { 256 } else { 0 // doens't make sense } val QUEUE_DEPTH = 16 assert(NUM_QUEUES >= dataWidthByteAligned) val io = IO(new CompressedBitsBuffIO(NUM_QUEUES)) val incoming_writes = Module(new Queue(new WriteBitsBundle(NUM_QUEUES), 8)) incoming_writes.io.enq <> io.writes_in // val data = UInt(dataWidth.W) // val validbits = UInt(log2Ceil(dataWidth + 1).W) // val end_of_message = Bool() val buf_lens_q = Module(new Queue(UInt(64.W), 10)) val buf_lens_tracker = RegInit(0.U(64.W)) when (incoming_writes.io.deq.fire) { when (incoming_writes.io.deq.bits.end_of_message) { buf_lens_tracker := 0.U } .otherwise { buf_lens_tracker := buf_lens_tracker + incoming_writes.io.deq.bits.validbits } } val buffers = Seq.fill(NUM_QUEUES)(Module(new Queue(UInt(1.W), QUEUE_DEPTH)).io) val write_start_idx = RegInit(0.U(log2Up(NUM_QUEUES + 1).W)) val bits_to_write = incoming_writes.io.deq.bits.validbits val wrap_len_idx_wide = write_start_idx + bits_to_write val wrap_len_idx_end = wrap_len_idx_wide % NUM_QUEUES.U val wrapped = wrap_len_idx_wide >= NUM_QUEUES.U val all_queues_ready = buffers.map(_.enq.ready).reduce(_ && _) val end_of_buf = incoming_writes.io.deq.bits.end_of_message val account_for_buf_length = (!end_of_buf) \|\| (end_of_buf && buf_lens_q.io.enq.ready) val input_fire_all_queues = DecoupledHelper( all_queues_ready, account_for_buf_length, incoming_writes.io.deq.valid) incoming_writes.io.deq.ready := input_fire_all_queues.fire(incoming_writes.io.deq.valid) val write_data_bit_vec = Wire(Vec(NUM_QUEUES, UInt(1.W))) write_data_bit_vec.foreach(x => x := 0.U) for (i <- 0 until NUM_QUEUES) { val corresponding_buf_idx = (i.U +& write_start_idx) % NUM_QUEUES.U write_data_bit_vec(corresponding_buf_idx) := incoming_writes.io.deq.bits.data >> i.U } for (i <- 0 until NUM_QUEUES) { val use_this_queue = Mux(wrapped, (i.U < wrap_len_idx_end) \|\| (i.U >= write_start_idx), (i.U >= write_start_idx) && (i.U < wrap_len_idx_end) ) buffers(i).enq.valid := input_fire_all_queues.fire && use_this_queue buffers(i).enq.bits := write_data_bit_vec(i) } buf_lens_q.io.enq.valid := input_fire_all_queues.fire(account_for_buf_length) && end_of_buf buf_lens_q.io.enq.bits := buf_lens_tracker +& incoming_writes.io.deq.bits.validbits when (buf_lens_q.io.enq.fire) { CompressAccelLogger.logInfo("BITBUFF_BUFLEN_ENQ_FIRE, total_bits: %d\n", buf_lens_q.io.enq.bits) } when (input_fire_all_queues.fire) { write_start_idx := wrap_len_idx_end CompressAccelLogger.logInfo("BITBUF_WRITEFIRE\n") CompressAccelLogger.logInfo("write_start_idx: %d, written_bits: %d\n", write_start_idx, bits_to_write) } val read_start_idx = RegInit(0.U(log2Up(NUM_QUEUES + 1).W)) val bufVecData = Wire(Vec(NUM_QUEUES, UInt(1.W))) val bufVecReadys = Wire(Vec(NUM_QUEUES, Bool())) val bufVecValids = Wire(Vec(NUM_QUEUES, Bool())) bufVecReadys.foreach(x => x := false.B) for (i <- 0 until NUM_QUEUES) { bufVecData(i) := buffers(i).deq.bits bufVecValids(i) := buffers(i).deq.valid buffers(i).deq.ready := bufVecReadys(i) } val remapVecData = Wire(Vec(NUM_QUEUES, UInt(1.W))) val remapVecReadys = Wire(Vec(NUM_QUEUES, Bool())) val remapVecValids = Wire(Vec(NUM_QUEUES, Bool())) for (i <- 0 until NUM_QUEUES) { val remap_idx = (i.U +& read_start_idx) % NUM_QUEUES.U remapVecData(i) := bufVecData(remap_idx) remapVecValids(i) := bufVecValids(remap_idx) bufVecReadys(remap_idx) := remapVecReadys(i) } val count_valid_bits = remapVecValids.map(_.asUInt).reduce(_ +& _) val count_valid_bytes = count_valid_bits >> 3.U val remain_valid_bits = count_valid_bits - (count_valid_bytes << 3.U) val byte_aligned = (remain_valid_bits === 0.U) val len_already_consumed = RegInit(0.U(64.W)) val unconsumed_bits_so_far = buf_lens_q.io.deq.bits - len_already_consumed val last_chunk = buf_lens_q.io.deq.valid && (unconsumed_bits_so_far <= NUM_QUEUES.U) val avail_bytes = Mux((last_chunk && !byte_aligned), count_valid_bytes + 1.U, count_valid_bytes) val enough_data = avail_bytes =/= 0.U val count_valid_bits_u8 = Wire(UInt(8.W)) count_valid_bits_u8 := count_valid_bits val valid_bit_mask = (1.U << count_valid_bits_u8) - 1.U io.consumer.data := Cat(remapVecData.reverse) & valid_bit_mask io.consumer.avail_bytes := avail_bytes io.consumer.last_chunk := last_chunk val read_fire = DecoupledHelper( io.consumer.ready, enough_data) io.consumer.valid := read_fire.fire(io.consumer.ready) val consumed_bits_wide = io.consumer.consumed_bytes << 3.U val consumed_bits_overflow = consumed_bits_wide > count_valid_bits val consumed_bits = Mux(last_chunk && !byte_aligned && consumed_bits_overflow, count_valid_bits, consumed_bits_wide) val buf_last = buf_lens_q.io.deq.valid && (buf_lens_q.io.deq.bits === (len_already_consumed + consumed_bits)) val nxt_len_already_consumed = Mux(buf_last, 0.U, len_already_consumed + consumed_bits) when (read_fire.fire) { read_start_idx := (read_start_idx +& consumed_bits) % NUM_QUEUES.U when (buf_last) { len_already_consumed := 0.U } .otherwise { len_already_consumed := nxt_len_already_consumed } } for (i <- 0 until NUM_QUEUES) { remapVecReadys(i) := (i.U < consumed_bits) && read_fire.fire } buf_lens_q.io.deq.ready := read_fire.fire && buf_last // connecting ready & valid...? when (read_fire.fire) { CompressAccelLogger.logInfo("BITBUF_RDFIRE\n") CompressAccelLogger.logInfo("consumer.data: 0x%x\n", io.consumer.data) CompressAccelLogger.logInfo("consumer.last_chunk: %d\n", io.consumer.last_chunk) CompressAccelLogger.logInfo("consumer.avail_bytes: %d\n", io.consumer.avail_bytes) CompressAccelLogger.logInfo("consumer.consumed_bytes: %d\n", io.consumer.consumed_bytes) CompressAccelLogger.logInfo("consumed_bits_wide: %d\n", consumed_bits_wide) CompressAccelLogger.logInfo("consumed_bits_overflow: %d\n", consumed_bits_overflow) CompressAccelLogger.logInfo("consumed_bits: %d\n", consumed_bits) CompressAccelLogger.logInfo("buf_last: %d\n", buf_last) CompressAccelLogger.logInfo("read_start_idx: %d\n", read_start_idx) CompressAccelLogger.logInfo("count_valid_bits: %d\n", count_valid_bits) CompressAccelLogger.logInfo("count_valid_bytes: %d\n", count_valid_bytes) CompressAccelLogger.logInfo("remain_valid_bits: %d\n", remain_valid_bits) CompressAccelLogger.logInfo("byte_aligned: %d\n", byte_aligned) CompressAccelLogger.logInfo("len_already_consumed: %d\n", len_already_consumed) CompressAccelLogger.logInfo("nxt_len_already_consumed: %d\n", nxt_len_already_consumed) CompressAccelLogger.logInfo("unconsumed_bits_so_far: %d\n", unconsumed_bits_so_far) CompressAccelLogger.logInfo("last_chunk: %d\n", last_chunk) CompressAccelLogger.logInfo("valid_bit_mask: 0x%x\n", valid_bit_mask) for (i <- 0 until NUM_QUEUES) { CompressAccelLogger.logInfo("bufVecReadys(%d): %d\n", i.U, bufVecReadys(i)) } for (i <- 0 until NUM_QUEUES) { CompressAccelLogger.logInfo("bufVecValids(%d): %d\n", i.U, bufVecValids(i)) } } for (i <- 0 until NUM_QUEUES) { when (buffers(i).deq.fire) { CompressAccelLogger.logInfo("buffer(%d) fired\n", i.U) } } when (buf_lens_q.io.deq.fire) { CompressAccelLogger.logInfo("BITBUFF buf_lens_q dequeued\n") } }	module CompressedBitsBuff( // @[CompressedBitsBuffer.scala:38:7] input clock, // @[CompressedBitsBuffer.scala:38:7] input reset, // @[CompressedBitsBuffer.scala:38:7] output io_writes_in_ready, // @[CompressedBitsBuffer.scala:56:14] input io_writes_in_valid, // @[CompressedBitsBuffer.scala:56:14] input [63:0] io_writes_in_bits_data, // @[CompressedBitsBuffer.scala:56:14] input [6:0] io_writes_in_bits_validbits, // @[CompressedBitsBuffer.scala:56:14] input io_writes_in_bits_end_of_message, // @[CompressedBitsBuffer.scala:56:14] output io_consumer_valid, // @[CompressedBitsBuffer.scala:56:14] input io_consumer_ready, // @[CompressedBitsBuffer.scala:56:14] input [6:0] io_consumer_consumed_bytes, // @[CompressedBitsBuffer.scala:56:14] output [6:0] io_consumer_avail_bytes, // @[CompressedBitsBuffer.scala:56:14] output [63:0] io_consumer_data, // @[CompressedBitsBuffer.scala:56:14] output io_consumer_last_chunk // @[CompressedBitsBuffer.scala:56:14] ); wire _Queue16_UInt1_63_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_63_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_62_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_62_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_61_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_61_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_60_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_60_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_59_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_59_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_58_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_58_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_57_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_57_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_56_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_56_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_55_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_55_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_54_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_54_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_53_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_53_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_52_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_52_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_51_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_51_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_50_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_50_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_49_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_49_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_48_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_48_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_47_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_47_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_46_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_46_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_45_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_45_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_44_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_44_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_43_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_43_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_42_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_42_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_41_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_41_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_40_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_40_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_39_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_39_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_38_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_38_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_37_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_37_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_36_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_36_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_35_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_35_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_34_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_34_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_33_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_33_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_32_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_32_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_31_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_31_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_30_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_30_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_29_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_29_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_28_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_28_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_27_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_27_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_26_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_26_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_25_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_25_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_24_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_24_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_23_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_23_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_22_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_22_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_21_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_21_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_20_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_20_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_19_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_19_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_18_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_18_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_17_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_17_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_16_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_16_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_15_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_15_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_14_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_14_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_13_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_13_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_12_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_12_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_11_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_11_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_10_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_10_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_9_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_9_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_8_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_8_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_7_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_7_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_6_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_6_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_5_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_5_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_4_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_4_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_3_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_3_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_2_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_2_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_1_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_1_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _buf_lens_q_io_enq_ready; // @[CompressedBitsBuffer.scala:65:26] wire _buf_lens_q_io_deq_valid; // @[CompressedBitsBuffer.scala:65:26] wire [63:0] _buf_lens_q_io_deq_bits; // @[CompressedBitsBuffer.scala:65:26] wire _incoming_writes_io_deq_valid; // @[CompressedBitsBuffer.scala:58:31] wire [63:0] _incoming_writes_io_deq_bits_data; // @[CompressedBitsBuffer.scala:58:31] wire [6:0] _incoming_writes_io_deq_bits_validbits; // @[CompressedBitsBuffer.scala:58:31] wire _incoming_writes_io_deq_bits_end_of_message; // @[CompressedBitsBuffer.scala:58:31] wire io_writes_in_valid_0 = io_writes_in_valid; // @[CompressedBitsBuffer.scala:38:7] wire [63:0] io_writes_in_bits_data_0 = io_writes_in_bits_data; // @[CompressedBitsBuffer.scala:38:7] wire [6:0] io_writes_in_bits_validbits_0 = io_writes_in_bits_validbits; // @[CompressedBitsBuffer.scala:38:7] wire io_writes_in_bits_end_of_message_0 = io_writes_in_bits_end_of_message; // @[CompressedBitsBuffer.scala:38:7] wire io_consumer_ready_0 = io_consumer_ready; // @[CompressedBitsBuffer.scala:38:7] wire [6:0] io_consumer_consumed_bytes_0 = io_consumer_consumed_bytes; // @[CompressedBitsBuffer.scala:38:7] wire enough_data; // @[CompressedBitsBuffer.scala:162:33] wire last_chunk; // @[CompressedBitsBuffer.scala:157:44] wire io_writes_in_ready_0; // @[CompressedBitsBuffer.scala:38:7] wire io_consumer_valid_0; // @[CompressedBitsBuffer.scala:38:7] wire [6:0] io_consumer_avail_bytes_0; // @[CompressedBitsBuffer.scala:38:7] wire [63:0] io_consumer_data_0; // @[CompressedBitsBuffer.scala:38:7] wire io_consumer_last_chunk_0; // @[CompressedBitsBuffer.scala:38:7] reg [63:0] buf_lens_tracker; // @[CompressedBitsBuffer.scala:66:33] wire [64:0] _GEN = {1'h0, buf_lens_tracker} + {58'h0, _incoming_writes_io_deq_bits_validbits}; // @[CompressedBitsBuffer.scala:58:31, :66:33, :72:44] wire [64:0] _buf_lens_tracker_T; // @[CompressedBitsBuffer.scala:72:44] assign _buf_lens_tracker_T = _GEN; // @[CompressedBitsBuffer.scala:72:44] wire [64:0] _buf_lens_q_io_enq_bits_T; // @[CompressedBitsBuffer.scala:113:46] assign _buf_lens_q_io_enq_bits_T = _GEN; // @[CompressedBitsBuffer.scala:72:44, :113:46] wire [63:0] _buf_lens_tracker_T_1 = _buf_lens_tracker_T[63:0]; // @[CompressedBitsBuffer.scala:72:44] reg [6:0] write_start_idx; // @[CompressedBitsBuffer.scala:77:32] wire [7:0] _corresponding_buf_idx_T = {1'h0, write_start_idx}; // @[CompressedBitsBuffer.scala:77:32, :80:43, :99:38] wire [7:0] _wrap_len_idx_wide_T = _corresponding_buf_idx_T + {1'h0, _incoming_writes_io_deq_bits_validbits}; // @[CompressedBitsBuffer.scala:58:31, :80:43, :99:38] wire [6:0] wrap_len_idx_wide = _wrap_len_idx_wide_T[6:0]; // @[CompressedBitsBuffer.scala:80:43] wire [6:0] wrap_len_idx_end = wrap_len_idx_wide % 7'h40; // @[CompressedBitsBuffer.scala:80:43, :81:44] wire wrapped = wrap_len_idx_wide[6]; // @[CompressedBitsBuffer.scala:80:43, :82:35] wire _all_queues_ready_T = _Queue16_UInt1_io_enq_ready & _Queue16_UInt1_1_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue16_UInt1_2_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue16_UInt1_3_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue16_UInt1_4_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue16_UInt1_5_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue16_UInt1_6_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue16_UInt1_7_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue16_UInt1_8_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue16_UInt1_9_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue16_UInt1_10_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue16_UInt1_11_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue16_UInt1_12_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue16_UInt1_13_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue16_UInt1_14_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue16_UInt1_15_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue16_UInt1_16_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue16_UInt1_17_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue16_UInt1_18_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue16_UInt1_19_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue16_UInt1_20_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue16_UInt1_21_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue16_UInt1_22_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue16_UInt1_23_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue16_UInt1_24_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue16_UInt1_25_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue16_UInt1_26_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue16_UInt1_27_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue16_UInt1_28_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue16_UInt1_29_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue16_UInt1_30_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_30 = _all_queues_ready_T_29 & _Queue16_UInt1_31_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_31 = _all_queues_ready_T_30 & _Queue16_UInt1_32_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_32 = _all_queues_ready_T_31 & _Queue16_UInt1_33_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_33 = _all_queues_ready_T_32 & _Queue16_UInt1_34_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_34 = _all_queues_ready_T_33 & _Queue16_UInt1_35_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_35 = _all_queues_ready_T_34 & _Queue16_UInt1_36_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_36 = _all_queues_ready_T_35 & _Queue16_UInt1_37_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_37 = _all_queues_ready_T_36 & _Queue16_UInt1_38_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_38 = _all_queues_ready_T_37 & _Queue16_UInt1_39_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_39 = _all_queues_ready_T_38 & _Queue16_UInt1_40_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_40 = _all_queues_ready_T_39 & _Queue16_UInt1_41_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_41 = _all_queues_ready_T_40 & _Queue16_UInt1_42_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_42 = _all_queues_ready_T_41 & _Queue16_UInt1_43_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_43 = _all_queues_ready_T_42 & _Queue16_UInt1_44_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_44 = _all_queues_ready_T_43 & _Queue16_UInt1_45_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_45 = _all_queues_ready_T_44 & _Queue16_UInt1_46_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_46 = _all_queues_ready_T_45 & _Queue16_UInt1_47_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_47 = _all_queues_ready_T_46 & _Queue16_UInt1_48_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_48 = _all_queues_ready_T_47 & _Queue16_UInt1_49_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_49 = _all_queues_ready_T_48 & _Queue16_UInt1_50_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_50 = _all_queues_ready_T_49 & _Queue16_UInt1_51_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_51 = _all_queues_ready_T_50 & _Queue16_UInt1_52_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_52 = _all_queues_ready_T_51 & _Queue16_UInt1_53_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_53 = _all_queues_ready_T_52 & _Queue16_UInt1_54_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_54 = _all_queues_ready_T_53 & _Queue16_UInt1_55_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_55 = _all_queues_ready_T_54 & _Queue16_UInt1_56_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_56 = _all_queues_ready_T_55 & _Queue16_UInt1_57_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_57 = _all_queues_ready_T_56 & _Queue16_UInt1_58_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_58 = _all_queues_ready_T_57 & _Queue16_UInt1_59_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_59 = _all_queues_ready_T_58 & _Queue16_UInt1_60_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_60 = _all_queues_ready_T_59 & _Queue16_UInt1_61_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_61 = _all_queues_ready_T_60 & _Queue16_UInt1_62_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire all_queues_ready = _all_queues_ready_T_61 & _Queue16_UInt1_63_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _account_for_buf_length_T = ~_incoming_writes_io_deq_bits_end_of_message; // @[CompressedBitsBuffer.scala:58:31, :87:33] wire _account_for_buf_length_T_1 = _incoming_writes_io_deq_bits_end_of_message & _buf_lens_q_io_enq_ready; // @[CompressedBitsBuffer.scala:58:31, :65:26, :87:61] wire account_for_buf_length = _account_for_buf_length_T \| _account_for_buf_length_T_1; // @[CompressedBitsBuffer.scala:87:{33,46,61}] wire _incoming_writes_io_deq_ready_T = all_queues_ready & account_for_buf_length; // @[Misc.scala:26:53] wire write_data_bit_vec_0; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_1; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_2; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_3; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_4; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_5; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_6; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_7; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_8; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_9; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_10; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_11; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_12; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_13; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_14; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_15; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_16; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_17; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_18; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_19; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_20; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_21; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_22; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_23; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_24; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_25; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_26; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_27; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_28; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_29; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_30; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_31; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_32; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_33; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_34; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_35; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_36; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_37; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_38; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_39; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_40; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_41; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_42; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_43; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_44; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_45; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_46; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_47; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_48; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_49; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_50; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_51; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_52; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_53; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_54; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_55; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_56; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_57; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_58; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_59; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_60; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_61; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_62; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_63; // @[CompressedBitsBuffer.scala:96:32] wire [7:0] _GEN_0 = _corresponding_buf_idx_T % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx = _GEN_0[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T; // @[CompressedBitsBuffer.scala:100:83] wire [7:0] _corresponding_buf_idx_T_1 = _corresponding_buf_idx_T + 8'h1; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_1 = _corresponding_buf_idx_T_1 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_1 = _GEN_1[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_1 = {1'h0, _incoming_writes_io_deq_bits_data[63:1]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_2 = _corresponding_buf_idx_T + 8'h2; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_2 = _corresponding_buf_idx_T_2 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_2 = _GEN_2[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_2 = {2'h0, _incoming_writes_io_deq_bits_data[63:2]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_3 = _corresponding_buf_idx_T + 8'h3; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_3 = _corresponding_buf_idx_T_3 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_3 = _GEN_3[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_3 = {3'h0, _incoming_writes_io_deq_bits_data[63:3]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_4 = _corresponding_buf_idx_T + 8'h4; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_4 = _corresponding_buf_idx_T_4 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_4 = _GEN_4[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_4 = {4'h0, _incoming_writes_io_deq_bits_data[63:4]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_5 = _corresponding_buf_idx_T + 8'h5; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_5 = _corresponding_buf_idx_T_5 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_5 = _GEN_5[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_5 = {5'h0, _incoming_writes_io_deq_bits_data[63:5]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_6 = _corresponding_buf_idx_T + 8'h6; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_6 = _corresponding_buf_idx_T_6 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_6 = _GEN_6[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_6 = {6'h0, _incoming_writes_io_deq_bits_data[63:6]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_7 = _corresponding_buf_idx_T + 8'h7; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_7 = _corresponding_buf_idx_T_7 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_7 = _GEN_7[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_7 = {7'h0, _incoming_writes_io_deq_bits_data[63:7]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_8 = _corresponding_buf_idx_T + 8'h8; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_8 = _corresponding_buf_idx_T_8 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_8 = _GEN_8[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_8 = {8'h0, _incoming_writes_io_deq_bits_data[63:8]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_9 = _corresponding_buf_idx_T + 8'h9; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_9 = _corresponding_buf_idx_T_9 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_9 = _GEN_9[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_9 = {9'h0, _incoming_writes_io_deq_bits_data[63:9]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_10 = _corresponding_buf_idx_T + 8'hA; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_10 = _corresponding_buf_idx_T_10 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_10 = _GEN_10[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_10 = {10'h0, _incoming_writes_io_deq_bits_data[63:10]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_11 = _corresponding_buf_idx_T + 8'hB; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_11 = _corresponding_buf_idx_T_11 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_11 = _GEN_11[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_11 = {11'h0, _incoming_writes_io_deq_bits_data[63:11]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_12 = _corresponding_buf_idx_T + 8'hC; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_12 = _corresponding_buf_idx_T_12 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_12 = _GEN_12[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_12 = {12'h0, _incoming_writes_io_deq_bits_data[63:12]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_13 = _corresponding_buf_idx_T + 8'hD; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_13 = _corresponding_buf_idx_T_13 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_13 = _GEN_13[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_13 = {13'h0, _incoming_writes_io_deq_bits_data[63:13]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_14 = _corresponding_buf_idx_T + 8'hE; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_14 = _corresponding_buf_idx_T_14 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_14 = _GEN_14[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_14 = {14'h0, _incoming_writes_io_deq_bits_data[63:14]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_15 = _corresponding_buf_idx_T + 8'hF; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_15 = _corresponding_buf_idx_T_15 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_15 = _GEN_15[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_15 = {15'h0, _incoming_writes_io_deq_bits_data[63:15]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_16 = _corresponding_buf_idx_T + 8'h10; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_16 = _corresponding_buf_idx_T_16 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_16 = _GEN_16[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_16 = {16'h0, _incoming_writes_io_deq_bits_data[63:16]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_17 = _corresponding_buf_idx_T + 8'h11; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_17 = _corresponding_buf_idx_T_17 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_17 = _GEN_17[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_17 = {17'h0, _incoming_writes_io_deq_bits_data[63:17]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_18 = _corresponding_buf_idx_T + 8'h12; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_18 = _corresponding_buf_idx_T_18 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_18 = _GEN_18[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_18 = {18'h0, _incoming_writes_io_deq_bits_data[63:18]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_19 = _corresponding_buf_idx_T + 8'h13; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_19 = _corresponding_buf_idx_T_19 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_19 = _GEN_19[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_19 = {19'h0, _incoming_writes_io_deq_bits_data[63:19]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_20 = _corresponding_buf_idx_T + 8'h14; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_20 = _corresponding_buf_idx_T_20 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_20 = _GEN_20[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_20 = {20'h0, _incoming_writes_io_deq_bits_data[63:20]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_21 = _corresponding_buf_idx_T + 8'h15; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_21 = _corresponding_buf_idx_T_21 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_21 = _GEN_21[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_21 = {21'h0, _incoming_writes_io_deq_bits_data[63:21]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_22 = _corresponding_buf_idx_T + 8'h16; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_22 = _corresponding_buf_idx_T_22 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_22 = _GEN_22[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_22 = {22'h0, _incoming_writes_io_deq_bits_data[63:22]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_23 = _corresponding_buf_idx_T + 8'h17; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_23 = _corresponding_buf_idx_T_23 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_23 = _GEN_23[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_23 = {23'h0, _incoming_writes_io_deq_bits_data[63:23]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_24 = _corresponding_buf_idx_T + 8'h18; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_24 = _corresponding_buf_idx_T_24 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_24 = _GEN_24[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_24 = {24'h0, _incoming_writes_io_deq_bits_data[63:24]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_25 = _corresponding_buf_idx_T + 8'h19; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_25 = _corresponding_buf_idx_T_25 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_25 = _GEN_25[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_25 = {25'h0, _incoming_writes_io_deq_bits_data[63:25]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_26 = _corresponding_buf_idx_T + 8'h1A; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_26 = _corresponding_buf_idx_T_26 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_26 = _GEN_26[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_26 = {26'h0, _incoming_writes_io_deq_bits_data[63:26]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_27 = _corresponding_buf_idx_T + 8'h1B; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_27 = _corresponding_buf_idx_T_27 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_27 = _GEN_27[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_27 = {27'h0, _incoming_writes_io_deq_bits_data[63:27]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_28 = _corresponding_buf_idx_T + 8'h1C; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_28 = _corresponding_buf_idx_T_28 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_28 = _GEN_28[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_28 = {28'h0, _incoming_writes_io_deq_bits_data[63:28]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_29 = _corresponding_buf_idx_T + 8'h1D; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_29 = _corresponding_buf_idx_T_29 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_29 = _GEN_29[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_29 = {29'h0, _incoming_writes_io_deq_bits_data[63:29]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_30 = _corresponding_buf_idx_T + 8'h1E; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_30 = _corresponding_buf_idx_T_30 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_30 = _GEN_30[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_30 = {30'h0, _incoming_writes_io_deq_bits_data[63:30]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_31 = _corresponding_buf_idx_T + 8'h1F; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_31 = _corresponding_buf_idx_T_31 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_31 = _GEN_31[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_31 = {31'h0, _incoming_writes_io_deq_bits_data[63:31]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_32 = _corresponding_buf_idx_T + 8'h20; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_32 = _corresponding_buf_idx_T_32 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_32 = _GEN_32[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_32 = {32'h0, _incoming_writes_io_deq_bits_data[63:32]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_33 = _corresponding_buf_idx_T + 8'h21; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_33 = _corresponding_buf_idx_T_33 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_33 = _GEN_33[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_33 = {33'h0, _incoming_writes_io_deq_bits_data[63:33]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_34 = _corresponding_buf_idx_T + 8'h22; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_34 = _corresponding_buf_idx_T_34 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_34 = _GEN_34[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_34 = {34'h0, _incoming_writes_io_deq_bits_data[63:34]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_35 = _corresponding_buf_idx_T + 8'h23; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_35 = _corresponding_buf_idx_T_35 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_35 = _GEN_35[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_35 = {35'h0, _incoming_writes_io_deq_bits_data[63:35]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_36 = _corresponding_buf_idx_T + 8'h24; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_36 = _corresponding_buf_idx_T_36 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_36 = _GEN_36[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_36 = {36'h0, _incoming_writes_io_deq_bits_data[63:36]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_37 = _corresponding_buf_idx_T + 8'h25; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_37 = _corresponding_buf_idx_T_37 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_37 = _GEN_37[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_37 = {37'h0, _incoming_writes_io_deq_bits_data[63:37]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_38 = _corresponding_buf_idx_T + 8'h26; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_38 = _corresponding_buf_idx_T_38 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_38 = _GEN_38[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_38 = {38'h0, _incoming_writes_io_deq_bits_data[63:38]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_39 = _corresponding_buf_idx_T + 8'h27; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_39 = _corresponding_buf_idx_T_39 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_39 = _GEN_39[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_39 = {39'h0, _incoming_writes_io_deq_bits_data[63:39]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_40 = _corresponding_buf_idx_T + 8'h28; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_40 = _corresponding_buf_idx_T_40 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_40 = _GEN_40[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_40 = {40'h0, _incoming_writes_io_deq_bits_data[63:40]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_41 = _corresponding_buf_idx_T + 8'h29; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_41 = _corresponding_buf_idx_T_41 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_41 = _GEN_41[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_41 = {41'h0, _incoming_writes_io_deq_bits_data[63:41]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_42 = _corresponding_buf_idx_T + 8'h2A; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_42 = _corresponding_buf_idx_T_42 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_42 = _GEN_42[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_42 = {42'h0, _incoming_writes_io_deq_bits_data[63:42]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_43 = _corresponding_buf_idx_T + 8'h2B; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_43 = _corresponding_buf_idx_T_43 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_43 = _GEN_43[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_43 = {43'h0, _incoming_writes_io_deq_bits_data[63:43]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_44 = _corresponding_buf_idx_T + 8'h2C; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_44 = _corresponding_buf_idx_T_44 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_44 = _GEN_44[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_44 = {44'h0, _incoming_writes_io_deq_bits_data[63:44]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_45 = _corresponding_buf_idx_T + 8'h2D; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_45 = _corresponding_buf_idx_T_45 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_45 = _GEN_45[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_45 = {45'h0, _incoming_writes_io_deq_bits_data[63:45]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_46 = _corresponding_buf_idx_T + 8'h2E; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_46 = _corresponding_buf_idx_T_46 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_46 = _GEN_46[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_46 = {46'h0, _incoming_writes_io_deq_bits_data[63:46]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_47 = _corresponding_buf_idx_T + 8'h2F; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_47 = _corresponding_buf_idx_T_47 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_47 = _GEN_47[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_47 = {47'h0, _incoming_writes_io_deq_bits_data[63:47]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_48 = _corresponding_buf_idx_T + 8'h30; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_48 = _corresponding_buf_idx_T_48 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_48 = _GEN_48[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_48 = {48'h0, _incoming_writes_io_deq_bits_data[63:48]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_49 = _corresponding_buf_idx_T + 8'h31; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_49 = _corresponding_buf_idx_T_49 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_49 = _GEN_49[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_49 = {49'h0, _incoming_writes_io_deq_bits_data[63:49]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_50 = _corresponding_buf_idx_T + 8'h32; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_50 = _corresponding_buf_idx_T_50 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_50 = _GEN_50[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_50 = {50'h0, _incoming_writes_io_deq_bits_data[63:50]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_51 = _corresponding_buf_idx_T + 8'h33; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_51 = _corresponding_buf_idx_T_51 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_51 = _GEN_51[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_51 = {51'h0, _incoming_writes_io_deq_bits_data[63:51]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_52 = _corresponding_buf_idx_T + 8'h34; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_52 = _corresponding_buf_idx_T_52 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_52 = _GEN_52[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_52 = {52'h0, _incoming_writes_io_deq_bits_data[63:52]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_53 = _corresponding_buf_idx_T + 8'h35; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_53 = _corresponding_buf_idx_T_53 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_53 = _GEN_53[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_53 = {53'h0, _incoming_writes_io_deq_bits_data[63:53]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_54 = _corresponding_buf_idx_T + 8'h36; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_54 = _corresponding_buf_idx_T_54 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_54 = _GEN_54[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_54 = {54'h0, _incoming_writes_io_deq_bits_data[63:54]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_55 = _corresponding_buf_idx_T + 8'h37; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_55 = _corresponding_buf_idx_T_55 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_55 = _GEN_55[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_55 = {55'h0, _incoming_writes_io_deq_bits_data[63:55]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_56 = _corresponding_buf_idx_T + 8'h38; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_56 = _corresponding_buf_idx_T_56 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_56 = _GEN_56[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_56 = {56'h0, _incoming_writes_io_deq_bits_data[63:56]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_57 = _corresponding_buf_idx_T + 8'h39; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_57 = _corresponding_buf_idx_T_57 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_57 = _GEN_57[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_57 = {57'h0, _incoming_writes_io_deq_bits_data[63:57]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_58 = _corresponding_buf_idx_T + 8'h3A; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_58 = _corresponding_buf_idx_T_58 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_58 = _GEN_58[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_58 = {58'h0, _incoming_writes_io_deq_bits_data[63:58]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_59 = _corresponding_buf_idx_T + 8'h3B; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_59 = _corresponding_buf_idx_T_59 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_59 = _GEN_59[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_59 = {59'h0, _incoming_writes_io_deq_bits_data[63:59]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_60 = _corresponding_buf_idx_T + 8'h3C; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_60 = _corresponding_buf_idx_T_60 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_60 = _GEN_60[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_60 = {60'h0, _incoming_writes_io_deq_bits_data[63:60]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_61 = _corresponding_buf_idx_T + 8'h3D; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_61 = _corresponding_buf_idx_T_61 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_61 = _GEN_61[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_61 = {61'h0, _incoming_writes_io_deq_bits_data[63:61]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_62 = _corresponding_buf_idx_T + 8'h3E; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_62 = _corresponding_buf_idx_T_62 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_62 = _GEN_62[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_62 = {62'h0, _incoming_writes_io_deq_bits_data[63:62]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_63 = _corresponding_buf_idx_T + 8'h3F; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_63 = _corresponding_buf_idx_T_63 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_63 = _GEN_63[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_63 = {63'h0, _incoming_writes_io_deq_bits_data[63]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] assign write_data_bit_vec_0 = corresponding_buf_idx_63[5:0] == 6'h0 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h0 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h0 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h0 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h0 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h0 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h0 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h0 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h0 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h0 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h0 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h0 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h0 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h0 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h0 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h0 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h0 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h0 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h0 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h0 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h0 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h0 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h0 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h0 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h0 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h0 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h0 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h0 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h0 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h0 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h0 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h0 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h0 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h0 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h0 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h0 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h0 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h0 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h0 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h0 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h0 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h0 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h0 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h0 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h0 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h0 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h0 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h0 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h0 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h0 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h0 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h0 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h0 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h0 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h0 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h0 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h0 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h0 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h0 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h0 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h0 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h0 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h0 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h0 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_1 = corresponding_buf_idx_63[5:0] == 6'h1 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_2 = corresponding_buf_idx_63[5:0] == 6'h2 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_3 = corresponding_buf_idx_63[5:0] == 6'h3 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_4 = corresponding_buf_idx_63[5:0] == 6'h4 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h4 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h4 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h4 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h4 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h4 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h4 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h4 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h4 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h4 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h4 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h4 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h4 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h4 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h4 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h4 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h4 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h4 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h4 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h4 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h4 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h4 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h4 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h4 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h4 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h4 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h4 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h4 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h4 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h4 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h4 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h4 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h4 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h4 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h4 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h4 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h4 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h4 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h4 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h4 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h4 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h4 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h4 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h4 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h4 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h4 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h4 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h4 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h4 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h4 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h4 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h4 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h4 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h4 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h4 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h4 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h4 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h4 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h4 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h4 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h4 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h4 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h4 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h4 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_5 = corresponding_buf_idx_63[5:0] == 6'h5 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h5 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h5 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h5 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h5 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h5 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h5 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h5 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h5 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h5 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h5 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h5 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h5 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h5 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h5 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h5 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h5 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h5 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h5 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h5 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h5 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h5 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h5 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h5 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h5 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h5 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h5 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h5 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h5 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h5 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h5 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h5 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h5 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h5 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h5 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h5 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h5 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h5 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h5 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h5 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h5 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h5 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h5 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h5 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h5 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h5 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h5 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h5 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h5 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h5 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h5 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h5 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h5 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h5 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h5 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h5 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h5 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h5 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h5 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h5 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h5 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h5 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h5 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h5 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_6 = corresponding_buf_idx_63[5:0] == 6'h6 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h6 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h6 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h6 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h6 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h6 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h6 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h6 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h6 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h6 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h6 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h6 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h6 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h6 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h6 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h6 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h6 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h6 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h6 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h6 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h6 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h6 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h6 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h6 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h6 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h6 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h6 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h6 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h6 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h6 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h6 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h6 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h6 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h6 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h6 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h6 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h6 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h6 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h6 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h6 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h6 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h6 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h6 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h6 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h6 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h6 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h6 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h6 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h6 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h6 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h6 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h6 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h6 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h6 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h6 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h6 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h6 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h6 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h6 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h6 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h6 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h6 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h6 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h6 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_7 = corresponding_buf_idx_63[5:0] == 6'h7 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h7 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h7 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h7 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h7 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h7 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h7 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h7 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h7 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h7 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h7 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h7 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h7 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h7 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h7 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h7 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h7 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h7 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h7 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h7 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h7 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h7 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h7 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h7 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h7 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h7 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h7 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h7 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h7 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h7 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h7 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h7 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h7 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h7 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h7 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h7 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h7 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h7 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h7 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h7 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h7 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h7 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h7 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h7 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h7 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h7 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h7 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h7 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h7 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h7 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h7 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h7 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h7 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h7 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h7 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h7 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h7 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h7 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h7 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h7 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h7 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h7 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h7 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h7 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_8 = corresponding_buf_idx_63[5:0] == 6'h8 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h8 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h8 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h8 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h8 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h8 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h8 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h8 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h8 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h8 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h8 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h8 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h8 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h8 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h8 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h8 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h8 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h8 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h8 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h8 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h8 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h8 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h8 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h8 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h8 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h8 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h8 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h8 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h8 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h8 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h8 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h8 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h8 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h8 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h8 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h8 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h8 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h8 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h8 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h8 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h8 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h8 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h8 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h8 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h8 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h8 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h8 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h8 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h8 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h8 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h8 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h8 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h8 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h8 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h8 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h8 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h8 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h8 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h8 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h8 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h8 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h8 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h8 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h8 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_9 = corresponding_buf_idx_63[5:0] == 6'h9 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h9 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h9 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h9 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h9 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h9 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h9 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h9 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h9 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h9 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h9 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h9 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h9 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h9 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h9 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h9 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h9 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h9 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h9 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h9 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h9 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h9 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h9 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h9 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h9 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h9 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h9 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h9 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h9 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h9 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h9 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h9 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h9 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h9 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h9 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h9 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h9 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h9 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h9 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h9 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h9 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h9 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h9 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h9 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h9 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h9 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h9 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h9 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h9 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h9 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h9 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h9 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h9 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h9 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h9 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h9 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h9 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h9 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h9 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h9 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h9 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h9 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h9 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h9 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_10 = corresponding_buf_idx_63[5:0] == 6'hA ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hA ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hA ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hA ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hA ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hA ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hA ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hA ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hA ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hA ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hA ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hA ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hA ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hA ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hA ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hA ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hA ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hA ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hA ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hA ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hA ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hA ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hA ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hA ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hA ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hA ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hA ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hA ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hA ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hA ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hA ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hA ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hA ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hA ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hA ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hA ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hA ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hA ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hA ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hA ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hA ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hA ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hA ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hA ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hA ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hA ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hA ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hA ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hA ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hA ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hA ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hA ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hA ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hA ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hA ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hA ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hA ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hA ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hA ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hA ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hA ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hA ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hA ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hA & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_11 = corresponding_buf_idx_63[5:0] == 6'hB ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hB ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hB ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hB ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hB ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hB ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hB ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hB ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hB ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hB ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hB ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hB ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hB ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hB ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hB ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hB ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hB ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hB ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hB ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hB ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hB ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hB ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hB ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hB ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hB ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hB ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hB ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hB ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hB ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hB ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hB ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hB ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hB ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hB ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hB ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hB ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hB ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hB ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hB ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hB ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hB ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hB ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hB ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hB ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hB ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hB ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hB ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hB ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hB ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hB ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hB ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hB ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hB ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hB ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hB ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hB ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hB ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hB ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hB ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hB ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hB ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hB ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hB ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hB & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_12 = corresponding_buf_idx_63[5:0] == 6'hC ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hC ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hC ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hC ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hC ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hC ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hC ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hC ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hC ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hC ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hC ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hC ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hC ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hC ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hC ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hC ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hC ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hC ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hC ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hC ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hC ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hC ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hC ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hC ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hC ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hC ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hC ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hC ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hC ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hC ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hC ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hC ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hC ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hC ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hC ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hC ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hC ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hC ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hC ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hC ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hC ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hC ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hC ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hC ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hC ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hC ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hC ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hC ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hC ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hC ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hC ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hC ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hC ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hC ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hC ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hC ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hC ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hC ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hC ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hC ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hC ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hC ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hC ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hC & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_13 = corresponding_buf_idx_63[5:0] == 6'hD ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hD ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hD ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hD ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hD ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hD ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hD ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hD ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hD ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hD ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hD ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hD ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hD ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hD ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hD ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hD ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hD ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hD ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hD ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hD ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hD ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hD ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hD ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hD ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hD ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hD ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hD ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hD ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hD ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hD ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hD ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hD ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hD ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hD ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hD ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hD ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hD ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hD ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hD ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hD ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hD ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hD ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hD ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hD ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hD ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hD ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hD ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hD ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hD ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hD ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hD ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hD ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hD ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hD ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hD ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hD ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hD ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hD ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hD ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hD ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hD ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hD ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hD ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hD & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_14 = corresponding_buf_idx_63[5:0] == 6'hE ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hE ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hE ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hE ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hE ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hE ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hE ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hE ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hE ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hE ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hE ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hE ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hE ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hE ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hE ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hE ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hE ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hE ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hE ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hE ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hE ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hE ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hE ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hE ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hE ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hE ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hE ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hE ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hE ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hE ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hE ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hE ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hE ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hE ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hE ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hE ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hE ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hE ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hE ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hE ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hE ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hE ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hE ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hE ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hE ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hE ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hE ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hE ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hE ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hE ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hE ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hE ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hE ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hE ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hE ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hE ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hE ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hE ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hE ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hE ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hE ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hE ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hE ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hE & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_15 = corresponding_buf_idx_63[5:0] == 6'hF ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hF ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hF ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hF ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hF ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hF ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hF ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hF ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hF ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hF ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hF ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hF ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hF ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hF ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hF ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hF ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hF ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hF ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hF ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hF ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hF ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hF ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hF ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hF ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hF ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hF ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hF ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hF ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hF ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hF ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hF ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hF ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hF ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hF ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hF ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hF ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hF ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hF ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hF ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hF ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hF ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hF ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hF ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hF ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hF ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hF ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hF ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hF ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hF ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hF ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hF ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hF ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hF ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hF ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hF ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hF ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hF ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hF ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hF ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hF ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hF ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hF ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hF ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hF & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_16 = corresponding_buf_idx_63[5:0] == 6'h10 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h10 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h10 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h10 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h10 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h10 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h10 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h10 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h10 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h10 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h10 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h10 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h10 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h10 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h10 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h10 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h10 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h10 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h10 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h10 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h10 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h10 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h10 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h10 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h10 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h10 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h10 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h10 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h10 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h10 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h10 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h10 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h10 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h10 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h10 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h10 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h10 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h10 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h10 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h10 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h10 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h10 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h10 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h10 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h10 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h10 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h10 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h10 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h10 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h10 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h10 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h10 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h10 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h10 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h10 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h10 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h10 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h10 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h10 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h10 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h10 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h10 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h10 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h10 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_17 = corresponding_buf_idx_63[5:0] == 6'h11 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h11 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h11 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h11 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h11 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h11 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h11 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h11 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h11 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h11 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h11 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h11 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h11 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h11 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h11 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h11 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h11 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h11 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h11 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h11 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h11 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h11 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h11 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h11 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h11 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h11 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h11 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h11 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h11 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h11 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h11 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h11 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h11 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h11 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h11 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h11 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h11 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h11 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h11 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h11 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h11 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h11 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h11 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h11 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h11 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h11 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h11 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h11 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h11 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h11 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h11 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h11 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h11 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h11 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h11 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h11 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h11 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h11 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h11 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h11 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h11 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h11 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h11 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h11 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_18 = corresponding_buf_idx_63[5:0] == 6'h12 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h12 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h12 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h12 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h12 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h12 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h12 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h12 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h12 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h12 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h12 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h12 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h12 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h12 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h12 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h12 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h12 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h12 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h12 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h12 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h12 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h12 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h12 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h12 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h12 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h12 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h12 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h12 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h12 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h12 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h12 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h12 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h12 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h12 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h12 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h12 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h12 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h12 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h12 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h12 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h12 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h12 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h12 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h12 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h12 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h12 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h12 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h12 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h12 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h12 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h12 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h12 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h12 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h12 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h12 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h12 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h12 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h12 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h12 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h12 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h12 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h12 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h12 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h12 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_19 = corresponding_buf_idx_63[5:0] == 6'h13 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h13 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h13 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h13 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h13 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h13 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h13 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h13 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h13 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h13 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h13 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h13 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h13 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h13 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h13 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h13 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h13 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h13 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h13 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h13 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h13 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h13 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h13 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h13 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h13 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h13 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h13 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h13 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h13 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h13 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h13 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h13 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h13 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h13 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h13 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h13 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h13 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h13 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h13 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h13 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h13 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h13 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h13 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h13 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h13 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h13 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h13 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h13 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h13 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h13 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h13 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h13 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h13 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h13 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h13 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h13 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h13 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h13 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h13 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h13 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h13 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h13 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h13 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h13 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_20 = corresponding_buf_idx_63[5:0] == 6'h14 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h14 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h14 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h14 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h14 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h14 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h14 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h14 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h14 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h14 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h14 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h14 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h14 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h14 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h14 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h14 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h14 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h14 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h14 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h14 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h14 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h14 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h14 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h14 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h14 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h14 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h14 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h14 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h14 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h14 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h14 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h14 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h14 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h14 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h14 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h14 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h14 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h14 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h14 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h14 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h14 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h14 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h14 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h14 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h14 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h14 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h14 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h14 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h14 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h14 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h14 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h14 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h14 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h14 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h14 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h14 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h14 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h14 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h14 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h14 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h14 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h14 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h14 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h14 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_21 = corresponding_buf_idx_63[5:0] == 6'h15 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h15 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h15 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h15 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h15 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h15 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h15 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h15 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h15 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h15 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h15 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h15 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h15 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h15 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h15 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h15 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h15 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h15 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h15 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h15 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h15 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h15 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h15 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h15 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h15 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h15 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h15 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h15 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h15 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h15 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h15 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h15 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h15 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h15 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h15 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h15 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h15 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h15 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h15 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h15 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h15 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h15 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h15 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h15 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h15 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h15 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h15 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h15 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h15 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h15 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h15 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h15 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h15 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h15 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h15 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h15 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h15 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h15 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h15 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h15 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h15 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h15 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h15 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h15 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_22 = corresponding_buf_idx_63[5:0] == 6'h16 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h16 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h16 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h16 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h16 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h16 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h16 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h16 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h16 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h16 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h16 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h16 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h16 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h16 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h16 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h16 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h16 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h16 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h16 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h16 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h16 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h16 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h16 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h16 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h16 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h16 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h16 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h16 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h16 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h16 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h16 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h16 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h16 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h16 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h16 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h16 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h16 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h16 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h16 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h16 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h16 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h16 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h16 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h16 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h16 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h16 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h16 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h16 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h16 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h16 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h16 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h16 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h16 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h16 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h16 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h16 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h16 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h16 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h16 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h16 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h16 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h16 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h16 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h16 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_23 = corresponding_buf_idx_63[5:0] == 6'h17 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h17 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h17 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h17 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h17 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h17 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h17 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h17 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h17 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h17 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h17 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h17 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h17 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h17 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h17 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h17 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h17 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h17 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h17 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h17 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h17 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h17 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h17 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h17 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h17 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h17 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h17 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h17 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h17 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h17 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h17 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h17 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h17 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h17 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h17 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h17 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h17 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h17 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h17 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h17 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h17 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h17 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h17 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h17 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h17 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h17 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h17 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h17 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h17 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h17 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h17 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h17 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h17 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h17 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h17 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h17 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h17 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h17 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h17 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h17 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h17 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h17 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h17 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h17 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_24 = corresponding_buf_idx_63[5:0] == 6'h18 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h18 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h18 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h18 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h18 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h18 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h18 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h18 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h18 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h18 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h18 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h18 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h18 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h18 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h18 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h18 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h18 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h18 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h18 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h18 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h18 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h18 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h18 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h18 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h18 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h18 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h18 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h18 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h18 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h18 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h18 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h18 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h18 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h18 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h18 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h18 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h18 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h18 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h18 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h18 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h18 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h18 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h18 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h18 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h18 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h18 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h18 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h18 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h18 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h18 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h18 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h18 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h18 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h18 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h18 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h18 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h18 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h18 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h18 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h18 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h18 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h18 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h18 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h18 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_25 = corresponding_buf_idx_63[5:0] == 6'h19 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h19 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h19 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h19 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h19 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h19 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h19 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h19 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h19 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h19 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h19 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h19 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h19 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h19 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h19 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h19 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h19 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h19 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h19 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h19 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h19 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h19 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h19 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h19 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h19 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h19 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h19 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h19 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h19 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h19 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h19 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h19 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h19 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h19 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h19 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h19 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h19 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h19 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h19 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h19 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h19 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h19 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h19 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h19 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h19 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h19 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h19 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h19 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h19 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h19 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h19 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h19 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h19 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h19 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h19 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h19 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h19 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h19 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h19 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h19 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h19 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h19 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h19 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h19 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_26 = corresponding_buf_idx_63[5:0] == 6'h1A ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1A ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1A ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1A ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1A ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1A ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1A ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1A ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1A ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1A ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1A ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1A ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1A ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1A ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1A ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1A ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1A ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1A ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1A ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1A ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1A ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1A ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1A ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1A ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1A ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1A ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1A ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1A ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1A ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1A ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1A ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1A ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1A ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1A ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1A ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1A ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1A ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1A ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1A ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1A ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1A ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1A ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1A ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1A ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1A ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1A ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1A ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1A ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1A ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1A ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1A ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1A ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1A ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1A ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1A ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1A ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1A ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1A ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1A ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1A ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1A ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1A ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1A ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1A & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_27 = corresponding_buf_idx_63[5:0] == 6'h1B ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1B ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1B ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1B ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1B ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1B ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1B ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1B ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1B ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1B ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1B ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1B ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1B ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1B ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1B ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1B ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1B ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1B ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1B ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1B ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1B ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1B ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1B ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1B ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1B ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1B ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1B ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1B ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1B ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1B ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1B ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1B ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1B ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1B ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1B ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1B ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1B ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1B ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1B ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1B ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1B ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1B ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1B ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1B ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1B ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1B ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1B ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1B ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1B ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1B ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1B ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1B ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1B ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1B ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1B ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1B ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1B ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1B ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1B ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1B ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1B ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1B ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1B ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1B & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_28 = corresponding_buf_idx_63[5:0] == 6'h1C ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1C ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1C ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1C ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1C ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1C ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1C ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1C ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1C ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1C ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1C ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1C ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1C ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1C ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1C ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1C ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1C ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1C ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1C ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1C ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1C ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1C ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1C ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1C ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1C ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1C ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1C ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1C ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1C ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1C ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1C ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1C ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1C ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1C ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1C ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1C ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1C ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1C ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1C ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1C ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1C ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1C ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1C ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1C ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1C ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1C ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1C ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1C ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1C ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1C ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1C ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1C ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1C ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1C ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1C ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1C ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1C ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1C ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1C ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1C ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1C ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1C ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1C ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1C & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_29 = corresponding_buf_idx_63[5:0] == 6'h1D ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1D ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1D ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1D ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1D ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1D ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1D ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1D ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1D ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1D ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1D ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1D ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1D ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1D ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1D ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1D ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1D ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1D ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1D ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1D ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1D ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1D ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1D ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1D ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1D ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1D ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1D ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1D ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1D ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1D ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1D ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1D ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1D ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1D ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1D ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1D ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1D ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1D ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1D ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1D ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1D ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1D ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1D ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1D ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1D ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1D ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1D ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1D ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1D ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1D ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1D ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1D ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1D ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1D ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1D ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1D ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1D ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1D ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1D ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1D ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1D ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1D ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1D ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1D & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_30 = corresponding_buf_idx_63[5:0] == 6'h1E ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1E ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1E ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1E ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1E ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1E ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1E ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1E ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1E ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1E ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1E ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1E ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1E ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1E ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1E ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1E ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1E ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1E ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1E ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1E ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1E ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1E ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1E ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1E ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1E ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1E ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1E ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1E ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1E ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1E ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1E ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1E ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1E ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1E ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1E ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1E ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1E ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1E ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1E ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1E ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1E ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1E ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1E ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1E ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1E ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1E ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1E ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1E ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1E ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1E ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1E ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1E ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1E ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1E ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1E ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1E ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1E ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1E ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1E ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1E ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1E ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1E ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1E ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1E & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_31 = corresponding_buf_idx_63[5:0] == 6'h1F ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1F ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1F ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1F ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1F ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1F ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1F ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1F ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1F ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1F ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1F ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1F ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1F ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1F ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1F ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1F ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1F ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1F ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1F ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1F ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1F ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1F ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1F ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1F ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1F ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1F ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1F ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1F ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1F ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1F ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1F ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1F ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1F ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1F ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1F ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1F ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1F ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1F ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1F ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1F ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1F ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1F ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1F ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1F ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1F ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1F ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1F ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1F ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1F ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1F ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1F ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1F ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1F ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1F ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1F ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1F ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1F ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1F ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1F ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1F ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1F ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1F ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1F ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1F & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_32 = corresponding_buf_idx_63[5:0] == 6'h20 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h20 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h20 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h20 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h20 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h20 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h20 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h20 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h20 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h20 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h20 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h20 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h20 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h20 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h20 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h20 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h20 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h20 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h20 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h20 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h20 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h20 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h20 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h20 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h20 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h20 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h20 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h20 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h20 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h20 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h20 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h20 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h20 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h20 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h20 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h20 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h20 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h20 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h20 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h20 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h20 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h20 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h20 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h20 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h20 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h20 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h20 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h20 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h20 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h20 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h20 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h20 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h20 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h20 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h20 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h20 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h20 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h20 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h20 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h20 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h20 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h20 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h20 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h20 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_33 = corresponding_buf_idx_63[5:0] == 6'h21 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h21 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h21 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h21 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h21 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h21 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h21 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h21 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h21 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h21 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h21 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h21 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h21 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h21 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h21 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h21 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h21 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h21 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h21 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h21 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h21 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h21 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h21 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h21 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h21 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h21 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h21 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h21 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h21 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h21 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h21 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h21 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h21 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h21 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h21 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h21 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h21 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h21 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h21 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h21 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h21 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h21 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h21 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h21 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h21 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h21 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h21 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h21 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h21 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h21 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h21 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h21 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h21 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h21 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h21 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h21 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h21 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h21 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h21 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h21 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h21 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h21 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h21 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h21 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_34 = corresponding_buf_idx_63[5:0] == 6'h22 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h22 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h22 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h22 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h22 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h22 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h22 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h22 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h22 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h22 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h22 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h22 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h22 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h22 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h22 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h22 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h22 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h22 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h22 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h22 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h22 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h22 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h22 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h22 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h22 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h22 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h22 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h22 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h22 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h22 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h22 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h22 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h22 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h22 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h22 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h22 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h22 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h22 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h22 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h22 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h22 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h22 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h22 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h22 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h22 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h22 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h22 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h22 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h22 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h22 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h22 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h22 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h22 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h22 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h22 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h22 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h22 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h22 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h22 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h22 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h22 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h22 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h22 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h22 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_35 = corresponding_buf_idx_63[5:0] == 6'h23 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h23 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h23 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h23 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h23 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h23 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h23 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h23 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h23 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h23 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h23 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h23 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h23 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h23 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h23 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h23 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h23 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h23 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h23 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h23 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h23 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h23 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h23 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h23 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h23 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h23 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h23 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h23 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h23 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h23 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h23 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h23 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h23 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h23 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h23 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h23 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h23 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h23 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h23 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h23 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h23 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h23 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h23 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h23 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h23 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h23 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h23 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h23 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h23 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h23 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h23 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h23 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h23 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h23 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h23 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h23 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h23 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h23 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h23 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h23 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h23 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h23 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h23 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h23 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_36 = corresponding_buf_idx_63[5:0] == 6'h24 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h24 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h24 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h24 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h24 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h24 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h24 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h24 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h24 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h24 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h24 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h24 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h24 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h24 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h24 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h24 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h24 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h24 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h24 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h24 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h24 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h24 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h24 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h24 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h24 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h24 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h24 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h24 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h24 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h24 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h24 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h24 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h24 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h24 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h24 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h24 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h24 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h24 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h24 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h24 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h24 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h24 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h24 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h24 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h24 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h24 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h24 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h24 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h24 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h24 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h24 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h24 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h24 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h24 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h24 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h24 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h24 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h24 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h24 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h24 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h24 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h24 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h24 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h24 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_37 = corresponding_buf_idx_63[5:0] == 6'h25 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h25 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h25 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h25 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h25 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h25 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h25 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h25 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h25 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h25 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h25 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h25 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h25 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h25 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h25 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h25 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h25 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h25 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h25 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h25 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h25 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h25 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h25 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h25 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h25 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h25 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h25 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h25 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h25 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h25 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h25 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h25 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h25 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h25 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h25 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h25 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h25 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h25 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h25 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h25 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h25 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h25 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h25 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h25 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h25 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h25 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h25 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h25 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h25 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h25 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h25 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h25 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h25 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h25 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h25 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h25 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h25 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h25 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h25 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h25 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h25 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h25 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h25 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h25 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_38 = corresponding_buf_idx_63[5:0] == 6'h26 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h26 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h26 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h26 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h26 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h26 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h26 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h26 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h26 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h26 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h26 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h26 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h26 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h26 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h26 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h26 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h26 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h26 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h26 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h26 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h26 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h26 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h26 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h26 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h26 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h26 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h26 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h26 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h26 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h26 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h26 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h26 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h26 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h26 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h26 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h26 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h26 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h26 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h26 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h26 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h26 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h26 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h26 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h26 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h26 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h26 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h26 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h26 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h26 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h26 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h26 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h26 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h26 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h26 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h26 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h26 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h26 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h26 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h26 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h26 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h26 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h26 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h26 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h26 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_39 = corresponding_buf_idx_63[5:0] == 6'h27 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h27 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h27 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h27 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h27 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h27 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h27 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h27 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h27 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h27 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h27 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h27 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h27 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h27 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h27 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h27 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h27 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h27 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h27 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h27 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h27 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h27 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h27 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h27 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h27 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h27 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h27 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h27 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h27 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h27 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h27 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h27 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h27 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h27 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h27 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h27 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h27 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h27 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h27 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h27 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h27 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h27 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h27 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h27 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h27 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h27 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h27 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h27 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h27 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h27 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h27 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h27 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h27 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h27 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h27 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h27 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h27 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h27 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h27 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h27 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h27 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h27 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h27 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h27 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_40 = corresponding_buf_idx_63[5:0] == 6'h28 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h28 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h28 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h28 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h28 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h28 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h28 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h28 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h28 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h28 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h28 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h28 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h28 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h28 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h28 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h28 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h28 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h28 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h28 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h28 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h28 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h28 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h28 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h28 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h28 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h28 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h28 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h28 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h28 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h28 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h28 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h28 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h28 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h28 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h28 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h28 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h28 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h28 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h28 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h28 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h28 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h28 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h28 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h28 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h28 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h28 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h28 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h28 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h28 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h28 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h28 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h28 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h28 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h28 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h28 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h28 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h28 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h28 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h28 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h28 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h28 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h28 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h28 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h28 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_41 = corresponding_buf_idx_63[5:0] == 6'h29 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h29 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h29 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h29 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h29 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h29 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h29 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h29 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h29 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h29 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h29 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h29 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h29 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h29 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h29 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h29 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h29 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h29 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h29 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h29 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h29 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h29 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h29 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h29 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h29 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h29 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h29 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h29 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h29 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h29 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h29 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h29 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h29 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h29 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h29 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h29 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h29 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h29 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h29 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h29 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h29 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h29 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h29 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h29 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h29 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h29 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h29 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h29 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h29 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h29 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h29 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h29 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h29 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h29 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h29 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h29 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h29 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h29 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h29 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h29 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h29 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h29 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h29 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h29 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_42 = corresponding_buf_idx_63[5:0] == 6'h2A ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2A ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2A ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2A ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2A ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2A ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2A ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2A ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2A ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2A ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2A ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2A ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2A ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2A ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2A ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2A ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2A ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2A ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2A ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2A ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2A ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2A ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2A ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2A ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2A ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2A ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2A ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2A ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2A ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2A ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2A ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2A ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2A ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2A ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2A ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2A ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2A ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2A ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2A ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2A ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2A ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2A ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2A ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2A ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2A ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2A ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2A ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2A ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2A ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2A ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2A ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2A ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2A ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2A ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2A ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2A ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2A ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2A ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2A ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2A ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2A ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2A ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2A ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2A & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_43 = corresponding_buf_idx_63[5:0] == 6'h2B ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2B ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2B ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2B ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2B ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2B ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2B ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2B ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2B ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2B ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2B ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2B ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2B ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2B ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2B ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2B ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2B ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2B ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2B ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2B ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2B ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2B ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2B ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2B ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2B ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2B ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2B ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2B ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2B ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2B ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2B ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2B ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2B ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2B ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2B ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2B ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2B ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2B ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2B ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2B ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2B ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2B ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2B ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2B ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2B ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2B ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2B ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2B ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2B ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2B ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2B ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2B ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2B ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2B ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2B ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2B ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2B ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2B ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2B ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2B ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2B ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2B ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2B ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2B & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_44 = corresponding_buf_idx_63[5:0] == 6'h2C ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2C ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2C ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2C ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2C ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2C ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2C ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2C ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2C ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2C ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2C ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2C ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2C ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2C ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2C ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2C ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2C ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2C ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2C ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2C ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2C ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2C ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2C ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2C ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2C ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2C ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2C ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2C ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2C ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2C ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2C ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2C ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2C ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2C ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2C ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2C ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2C ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2C ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2C ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2C ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2C ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2C ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2C ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2C ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2C ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2C ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2C ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2C ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2C ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2C ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2C ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2C ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2C ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2C ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2C ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2C ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2C ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2C ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2C ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2C ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2C ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2C ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2C ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2C & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_45 = corresponding_buf_idx_63[5:0] == 6'h2D ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2D ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2D ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2D ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2D ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2D ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2D ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2D ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2D ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2D ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2D ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2D ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2D ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2D ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2D ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2D ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2D ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2D ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2D ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2D ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2D ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2D ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2D ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2D ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2D ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2D ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2D ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2D ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2D ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2D ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2D ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2D ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2D ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2D ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2D ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2D ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2D ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2D ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2D ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2D ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2D ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2D ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2D ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2D ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2D ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2D ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2D ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2D ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2D ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2D ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2D ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2D ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2D ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2D ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2D ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2D ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2D ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2D ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2D ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2D ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2D ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2D ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2D ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2D & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_46 = corresponding_buf_idx_63[5:0] == 6'h2E ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2E ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2E ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2E ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2E ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2E ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2E ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2E ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2E ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2E ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2E ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2E ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2E ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2E ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2E ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2E ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2E ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2E ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2E ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2E ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2E ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2E ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2E ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2E ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2E ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2E ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2E ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2E ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2E ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2E ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2E ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2E ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2E ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2E ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2E ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2E ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2E ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2E ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2E ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2E ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2E ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2E ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2E ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2E ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2E ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2E ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2E ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2E ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2E ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2E ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2E ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2E ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2E ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2E ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2E ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2E ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2E ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2E ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2E ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2E ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2E ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2E ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2E ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2E & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_47 = corresponding_buf_idx_63[5:0] == 6'h2F ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2F ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2F ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2F ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2F ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2F ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2F ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2F ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2F ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2F ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2F ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2F ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2F ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2F ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2F ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2F ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2F ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2F ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2F ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2F ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2F ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2F ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2F ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2F ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2F ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2F ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2F ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2F ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2F ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2F ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2F ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2F ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2F ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2F ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2F ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2F ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2F ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2F ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2F ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2F ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2F ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2F ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2F ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2F ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2F ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2F ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2F ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2F ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2F ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2F ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2F ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2F ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2F ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2F ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2F ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2F ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2F ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2F ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2F ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2F ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2F ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2F ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2F ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2F & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_48 = corresponding_buf_idx_63[5:0] == 6'h30 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h30 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h30 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h30 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h30 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h30 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h30 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h30 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h30 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h30 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h30 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h30 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h30 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h30 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h30 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h30 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h30 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h30 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h30 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h30 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h30 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h30 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h30 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h30 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h30 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h30 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h30 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h30 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h30 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h30 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h30 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h30 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h30 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h30 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h30 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h30 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h30 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h30 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h30 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h30 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h30 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h30 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h30 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h30 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h30 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h30 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h30 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h30 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h30 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h30 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h30 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h30 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h30 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h30 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h30 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h30 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h30 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h30 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h30 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h30 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h30 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h30 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h30 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h30 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_49 = corresponding_buf_idx_63[5:0] == 6'h31 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h31 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h31 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h31 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h31 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h31 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h31 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h31 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h31 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h31 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h31 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h31 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h31 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h31 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h31 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h31 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h31 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h31 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h31 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h31 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h31 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h31 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h31 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h31 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h31 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h31 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h31 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h31 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h31 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h31 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h31 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h31 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h31 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h31 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h31 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h31 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h31 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h31 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h31 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h31 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h31 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h31 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h31 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h31 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h31 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h31 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h31 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h31 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h31 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h31 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h31 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h31 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h31 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h31 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h31 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h31 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h31 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h31 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h31 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h31 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h31 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h31 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h31 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h31 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_50 = corresponding_buf_idx_63[5:0] == 6'h32 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h32 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h32 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h32 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h32 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h32 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h32 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h32 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h32 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h32 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h32 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h32 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h32 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h32 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h32 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h32 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h32 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h32 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h32 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h32 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h32 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h32 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h32 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h32 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h32 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h32 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h32 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h32 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h32 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h32 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h32 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h32 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h32 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h32 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h32 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h32 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h32 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h32 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h32 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h32 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h32 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h32 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h32 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h32 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h32 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h32 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h32 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h32 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h32 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h32 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h32 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h32 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h32 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h32 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h32 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h32 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h32 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h32 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h32 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h32 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h32 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h32 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h32 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h32 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_51 = corresponding_buf_idx_63[5:0] == 6'h33 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h33 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h33 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h33 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h33 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h33 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h33 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h33 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h33 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h33 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h33 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h33 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h33 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h33 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h33 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h33 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h33 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h33 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h33 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h33 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h33 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h33 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h33 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h33 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h33 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h33 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h33 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h33 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h33 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h33 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h33 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h33 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h33 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h33 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h33 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h33 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h33 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h33 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h33 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h33 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h33 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h33 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h33 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h33 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h33 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h33 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h33 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h33 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h33 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h33 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h33 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h33 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h33 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h33 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h33 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h33 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h33 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h33 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h33 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h33 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h33 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h33 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h33 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h33 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_52 = corresponding_buf_idx_63[5:0] == 6'h34 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h34 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h34 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h34 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h34 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h34 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h34 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h34 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h34 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h34 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h34 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h34 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h34 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h34 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h34 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h34 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h34 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h34 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h34 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h34 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h34 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h34 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h34 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h34 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h34 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h34 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h34 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h34 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h34 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h34 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h34 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h34 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h34 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h34 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h34 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h34 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h34 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h34 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h34 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h34 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h34 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h34 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h34 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h34 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h34 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h34 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h34 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h34 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h34 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h34 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h34 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h34 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h34 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h34 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h34 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h34 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h34 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h34 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h34 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h34 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h34 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h34 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h34 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h34 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_53 = corresponding_buf_idx_63[5:0] == 6'h35 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h35 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h35 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h35 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h35 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h35 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h35 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h35 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h35 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h35 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h35 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h35 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h35 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h35 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h35 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h35 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h35 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h35 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h35 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h35 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h35 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h35 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h35 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h35 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h35 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h35 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h35 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h35 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h35 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h35 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h35 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h35 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h35 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h35 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h35 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h35 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h35 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h35 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h35 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h35 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h35 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h35 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h35 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h35 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h35 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h35 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h35 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h35 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h35 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h35 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h35 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h35 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h35 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h35 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h35 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h35 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h35 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h35 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h35 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h35 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h35 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h35 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h35 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h35 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_54 = corresponding_buf_idx_63[5:0] == 6'h36 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h36 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h36 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h36 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h36 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h36 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h36 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h36 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h36 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h36 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h36 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h36 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h36 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h36 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h36 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h36 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h36 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h36 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h36 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h36 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h36 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h36 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h36 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h36 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h36 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h36 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h36 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h36 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h36 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h36 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h36 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h36 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h36 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h36 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h36 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h36 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h36 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h36 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h36 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h36 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h36 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h36 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h36 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h36 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h36 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h36 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h36 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h36 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h36 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h36 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h36 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h36 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h36 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h36 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h36 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h36 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h36 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h36 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h36 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h36 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h36 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h36 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h36 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h36 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_55 = corresponding_buf_idx_63[5:0] == 6'h37 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h37 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h37 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h37 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h37 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h37 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h37 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h37 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h37 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h37 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h37 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h37 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h37 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h37 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h37 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h37 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h37 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h37 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h37 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h37 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h37 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h37 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h37 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h37 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h37 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h37 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h37 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h37 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h37 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h37 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h37 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h37 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h37 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h37 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h37 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h37 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h37 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h37 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h37 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h37 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h37 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h37 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h37 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h37 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h37 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h37 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h37 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h37 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h37 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h37 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h37 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h37 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h37 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h37 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h37 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h37 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h37 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h37 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h37 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h37 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h37 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h37 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h37 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h37 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_56 = corresponding_buf_idx_63[5:0] == 6'h38 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h38 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h38 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h38 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h38 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h38 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h38 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h38 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h38 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h38 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h38 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h38 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h38 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h38 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h38 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h38 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h38 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h38 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h38 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h38 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h38 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h38 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h38 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h38 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h38 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h38 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h38 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h38 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h38 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h38 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h38 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h38 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h38 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h38 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h38 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h38 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h38 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h38 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h38 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h38 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h38 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h38 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h38 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h38 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h38 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h38 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h38 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h38 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h38 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h38 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h38 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h38 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h38 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h38 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h38 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h38 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h38 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h38 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h38 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h38 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h38 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h38 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h38 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h38 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_57 = corresponding_buf_idx_63[5:0] == 6'h39 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h39 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h39 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h39 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h39 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h39 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h39 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h39 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h39 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h39 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h39 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h39 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h39 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h39 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h39 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h39 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h39 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h39 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h39 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h39 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h39 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h39 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h39 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h39 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h39 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h39 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h39 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h39 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h39 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h39 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h39 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h39 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h39 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h39 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h39 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h39 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h39 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h39 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h39 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h39 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h39 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h39 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h39 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h39 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h39 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h39 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h39 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h39 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h39 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h39 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h39 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h39 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h39 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h39 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h39 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h39 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h39 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h39 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h39 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h39 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h39 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h39 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h39 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h39 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_58 = corresponding_buf_idx_63[5:0] == 6'h3A ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3A ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3A ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3A ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3A ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3A ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3A ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3A ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3A ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3A ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3A ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3A ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3A ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3A ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3A ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3A ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3A ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3A ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3A ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3A ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3A ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3A ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3A ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3A ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3A ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3A ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3A ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3A ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3A ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3A ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3A ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3A ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3A ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3A ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3A ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3A ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3A ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3A ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3A ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3A ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3A ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3A ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3A ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3A ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3A ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3A ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3A ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3A ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3A ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3A ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3A ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3A ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3A ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3A ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3A ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3A ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3A ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3A ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3A ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3A ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3A ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3A ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3A ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3A & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_59 = corresponding_buf_idx_63[5:0] == 6'h3B ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3B ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3B ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3B ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3B ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3B ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3B ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3B ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3B ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3B ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3B ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3B ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3B ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3B ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3B ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3B ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3B ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3B ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3B ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3B ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3B ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3B ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3B ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3B ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3B ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3B ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3B ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3B ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3B ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3B ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3B ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3B ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3B ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3B ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3B ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3B ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3B ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3B ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3B ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3B ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3B ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3B ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3B ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3B ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3B ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3B ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3B ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3B ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3B ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3B ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3B ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3B ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3B ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3B ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3B ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3B ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3B ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3B ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3B ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3B ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3B ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3B ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3B ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3B & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_60 = corresponding_buf_idx_63[5:0] == 6'h3C ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3C ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3C ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3C ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3C ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3C ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3C ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3C ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3C ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3C ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3C ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3C ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3C ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3C ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3C ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3C ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3C ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3C ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3C ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3C ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3C ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3C ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3C ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3C ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3C ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3C ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3C ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3C ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3C ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3C ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3C ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3C ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3C ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3C ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3C ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3C ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3C ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3C ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3C ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3C ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3C ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3C ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3C ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3C ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3C ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3C ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3C ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3C ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3C ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3C ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3C ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3C ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3C ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3C ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3C ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3C ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3C ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3C ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3C ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3C ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3C ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3C ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3C ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3C & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_61 = corresponding_buf_idx_63[5:0] == 6'h3D ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3D ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3D ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3D ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3D ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3D ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3D ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3D ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3D ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3D ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3D ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3D ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3D ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3D ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3D ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3D ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3D ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3D ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3D ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3D ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3D ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3D ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3D ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3D ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3D ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3D ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3D ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3D ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3D ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3D ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3D ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3D ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3D ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3D ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3D ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3D ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3D ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3D ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3D ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3D ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3D ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3D ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3D ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3D ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3D ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3D ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3D ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3D ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3D ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3D ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3D ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3D ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3D ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3D ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3D ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3D ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3D ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3D ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3D ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3D ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3D ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3D ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3D ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3D & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_62 = corresponding_buf_idx_63[5:0] == 6'h3E ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3E ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3E ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3E ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3E ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3E ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3E ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3E ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3E ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3E ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3E ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3E ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3E ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3E ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3E ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3E ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3E ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3E ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3E ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3E ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3E ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3E ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3E ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3E ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3E ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3E ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3E ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3E ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3E ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3E ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3E ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3E ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3E ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3E ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3E ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3E ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3E ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3E ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3E ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3E ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3E ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3E ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3E ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3E ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3E ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3E ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3E ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3E ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3E ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3E ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3E ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3E ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3E ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3E ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3E ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3E ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3E ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3E ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3E ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3E ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3E ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3E ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3E ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3E & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_63 = (&(corresponding_buf_idx_63[5:0])) ? _write_data_bit_vec_T_63[0] : (&(corresponding_buf_idx_62[5:0])) ? _write_data_bit_vec_T_62[0] : (&(corresponding_buf_idx_61[5:0])) ? _write_data_bit_vec_T_61[0] : (&(corresponding_buf_idx_60[5:0])) ? _write_data_bit_vec_T_60[0] : (&(corresponding_buf_idx_59[5:0])) ? _write_data_bit_vec_T_59[0] : (&(corresponding_buf_idx_58[5:0])) ? _write_data_bit_vec_T_58[0] : (&(corresponding_buf_idx_57[5:0])) ? _write_data_bit_vec_T_57[0] : (&(corresponding_buf_idx_56[5:0])) ? _write_data_bit_vec_T_56[0] : (&(corresponding_buf_idx_55[5:0])) ? _write_data_bit_vec_T_55[0] : (&(corresponding_buf_idx_54[5:0])) ? _write_data_bit_vec_T_54[0] : (&(corresponding_buf_idx_53[5:0])) ? _write_data_bit_vec_T_53[0] : (&(corresponding_buf_idx_52[5:0])) ? _write_data_bit_vec_T_52[0] : (&(corresponding_buf_idx_51[5:0])) ? _write_data_bit_vec_T_51[0] : (&(corresponding_buf_idx_50[5:0])) ? _write_data_bit_vec_T_50[0] : (&(corresponding_buf_idx_49[5:0])) ? _write_data_bit_vec_T_49[0] : (&(corresponding_buf_idx_48[5:0])) ? _write_data_bit_vec_T_48[0] : (&(corresponding_buf_idx_47[5:0])) ? _write_data_bit_vec_T_47[0] : (&(corresponding_buf_idx_46[5:0])) ? _write_data_bit_vec_T_46[0] : (&(corresponding_buf_idx_45[5:0])) ? _write_data_bit_vec_T_45[0] : (&(corresponding_buf_idx_44[5:0])) ? _write_data_bit_vec_T_44[0] : (&(corresponding_buf_idx_43[5:0])) ? _write_data_bit_vec_T_43[0] : (&(corresponding_buf_idx_42[5:0])) ? _write_data_bit_vec_T_42[0] : (&(corresponding_buf_idx_41[5:0])) ? _write_data_bit_vec_T_41[0] : (&(corresponding_buf_idx_40[5:0])) ? _write_data_bit_vec_T_40[0] : (&(corresponding_buf_idx_39[5:0])) ? _write_data_bit_vec_T_39[0] : (&(corresponding_buf_idx_38[5:0])) ? _write_data_bit_vec_T_38[0] : (&(corresponding_buf_idx_37[5:0])) ? _write_data_bit_vec_T_37[0] : (&(corresponding_buf_idx_36[5:0])) ? _write_data_bit_vec_T_36[0] : (&(corresponding_buf_idx_35[5:0])) ? _write_data_bit_vec_T_35[0] : (&(corresponding_buf_idx_34[5:0])) ? _write_data_bit_vec_T_34[0] : (&(corresponding_buf_idx_33[5:0])) ? _write_data_bit_vec_T_33[0] : (&(corresponding_buf_idx_32[5:0])) ? _write_data_bit_vec_T_32[0] : (&(corresponding_buf_idx_31[5:0])) ? _write_data_bit_vec_T_31[0] : (&(corresponding_buf_idx_30[5:0])) ? _write_data_bit_vec_T_30[0] : (&(corresponding_buf_idx_29[5:0])) ? _write_data_bit_vec_T_29[0] : (&(corresponding_buf_idx_28[5:0])) ? _write_data_bit_vec_T_28[0] : (&(corresponding_buf_idx_27[5:0])) ? _write_data_bit_vec_T_27[0] : (&(corresponding_buf_idx_26[5:0])) ? _write_data_bit_vec_T_26[0] : (&(corresponding_buf_idx_25[5:0])) ? _write_data_bit_vec_T_25[0] : (&(corresponding_buf_idx_24[5:0])) ? _write_data_bit_vec_T_24[0] : (&(corresponding_buf_idx_23[5:0])) ? _write_data_bit_vec_T_23[0] : (&(corresponding_buf_idx_22[5:0])) ? _write_data_bit_vec_T_22[0] : (&(corresponding_buf_idx_21[5:0])) ? _write_data_bit_vec_T_21[0] : (&(corresponding_buf_idx_20[5:0])) ? _write_data_bit_vec_T_20[0] : (&(corresponding_buf_idx_19[5:0])) ? _write_data_bit_vec_T_19[0] : (&(corresponding_buf_idx_18[5:0])) ? _write_data_bit_vec_T_18[0] : (&(corresponding_buf_idx_17[5:0])) ? _write_data_bit_vec_T_17[0] : (&(corresponding_buf_idx_16[5:0])) ? _write_data_bit_vec_T_16[0] : (&(corresponding_buf_idx_15[5:0])) ? _write_data_bit_vec_T_15[0] : (&(corresponding_buf_idx_14[5:0])) ? _write_data_bit_vec_T_14[0] : (&(corresponding_buf_idx_13[5:0])) ? _write_data_bit_vec_T_13[0] : (&(corresponding_buf_idx_12[5:0])) ? _write_data_bit_vec_T_12[0] : (&(corresponding_buf_idx_11[5:0])) ? _write_data_bit_vec_T_11[0] : (&(corresponding_buf_idx_10[5:0])) ? _write_data_bit_vec_T_10[0] : (&(corresponding_buf_idx_9[5:0])) ? _write_data_bit_vec_T_9[0] : (&(corresponding_buf_idx_8[5:0])) ? _write_data_bit_vec_T_8[0] : (&(corresponding_buf_idx_7[5:0])) ? _write_data_bit_vec_T_7[0] : (&(corresponding_buf_idx_6[5:0])) ? _write_data_bit_vec_T_6[0] : (&(corresponding_buf_idx_5[5:0])) ? _write_data_bit_vec_T_5[0] : (&(corresponding_buf_idx_4[5:0])) ? _write_data_bit_vec_T_4[0] : (&(corresponding_buf_idx_3[5:0])) ? _write_data_bit_vec_T_3[0] : (&(corresponding_buf_idx_2[5:0])) ? _write_data_bit_vec_T_2[0] : (&(corresponding_buf_idx_1[5:0])) ? _write_data_bit_vec_T_1[0] : (&(corresponding_buf_idx[5:0])) & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] wire _use_this_queue_T = \|wrap_len_idx_end; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_64 = write_start_idx == 7'h0; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_1; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_1 = _GEN_64; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_3; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_3 = _GEN_64; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_2 = _use_this_queue_T \| _use_this_queue_T_1; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_4 = \|wrap_len_idx_end; // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_6 = \|(wrap_len_idx_end[6:1]); // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_65 = write_start_idx < 7'h2; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_7; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_7 = _GEN_65; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_9; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_9 = _GEN_65; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_8 = _use_this_queue_T_6 \| _use_this_queue_T_7; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_10 = \|(wrap_len_idx_end[6:1]); // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_66 = wrap_len_idx_end > 7'h2; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_12; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_12 = _GEN_66; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_16; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_16 = _GEN_66; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_67 = write_start_idx < 7'h3; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_13; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_13 = _GEN_67; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_15; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_15 = _GEN_67; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_14 = _use_this_queue_T_12 \| _use_this_queue_T_13; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_18 = \|(wrap_len_idx_end[6:2]); // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_68 = write_start_idx < 7'h4; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_19; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_19 = _GEN_68; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_21; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_21 = _GEN_68; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_20 = _use_this_queue_T_18 \| _use_this_queue_T_19; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_22 = \|(wrap_len_idx_end[6:2]); // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_69 = wrap_len_idx_end > 7'h4; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_24; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_24 = _GEN_69; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_28; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_28 = _GEN_69; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_70 = write_start_idx < 7'h5; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_25; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_25 = _GEN_70; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_27; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_27 = _GEN_70; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_26 = _use_this_queue_T_24 \| _use_this_queue_T_25; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_71 = wrap_len_idx_end > 7'h5; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_30; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_30 = _GEN_71; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_34; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_34 = _GEN_71; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_72 = write_start_idx < 7'h6; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_31; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_31 = _GEN_72; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_33; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_33 = _GEN_72; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_32 = _use_this_queue_T_30 \| _use_this_queue_T_31; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_73 = wrap_len_idx_end > 7'h6; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_36; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_36 = _GEN_73; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_40; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_40 = _GEN_73; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_74 = write_start_idx < 7'h7; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_37; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_37 = _GEN_74; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_39; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_39 = _GEN_74; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_38 = _use_this_queue_T_36 \| _use_this_queue_T_37; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_42 = \|(wrap_len_idx_end[6:3]); // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_75 = write_start_idx < 7'h8; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_43; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_43 = _GEN_75; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_45; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_45 = _GEN_75; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_44 = _use_this_queue_T_42 \| _use_this_queue_T_43; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_46 = \|(wrap_len_idx_end[6:3]); // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_76 = wrap_len_idx_end > 7'h8; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_48; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_48 = _GEN_76; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_52; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_52 = _GEN_76; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_77 = write_start_idx < 7'h9; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_49; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_49 = _GEN_77; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_51; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_51 = _GEN_77; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_50 = _use_this_queue_T_48 \| _use_this_queue_T_49; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_78 = wrap_len_idx_end > 7'h9; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_54; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_54 = _GEN_78; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_58; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_58 = _GEN_78; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_79 = write_start_idx < 7'hA; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_55; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_55 = _GEN_79; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_57; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_57 = _GEN_79; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_56 = _use_this_queue_T_54 \| _use_this_queue_T_55; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_80 = wrap_len_idx_end > 7'hA; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_60; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_60 = _GEN_80; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_64; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_64 = _GEN_80; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_81 = write_start_idx < 7'hB; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_61; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_61 = _GEN_81; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_63; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_63 = _GEN_81; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_62 = _use_this_queue_T_60 \| _use_this_queue_T_61; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_82 = wrap_len_idx_end > 7'hB; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_66; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_66 = _GEN_82; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_70; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_70 = _GEN_82; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_83 = write_start_idx < 7'hC; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_67; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_67 = _GEN_83; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_69; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_69 = _GEN_83; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_68 = _use_this_queue_T_66 \| _use_this_queue_T_67; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_84 = wrap_len_idx_end > 7'hC; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_72; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_72 = _GEN_84; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_76; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_76 = _GEN_84; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_85 = write_start_idx < 7'hD; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_73; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_73 = _GEN_85; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_75; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_75 = _GEN_85; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_74 = _use_this_queue_T_72 \| _use_this_queue_T_73; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_86 = wrap_len_idx_end > 7'hD; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_78; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_78 = _GEN_86; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_82; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_82 = _GEN_86; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_87 = write_start_idx < 7'hE; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_79; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_79 = _GEN_87; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_81; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_81 = _GEN_87; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_80 = _use_this_queue_T_78 \| _use_this_queue_T_79; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_88 = wrap_len_idx_end > 7'hE; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_84; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_84 = _GEN_88; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_88; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_88 = _GEN_88; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_89 = write_start_idx < 7'hF; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_85; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_85 = _GEN_89; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_87; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_87 = _GEN_89; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_86 = _use_this_queue_T_84 \| _use_this_queue_T_85; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_90 = \|(wrap_len_idx_end[6:4]); // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_90 = write_start_idx < 7'h10; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_91; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_91 = _GEN_90; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_93; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_93 = _GEN_90; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_92 = _use_this_queue_T_90 \| _use_this_queue_T_91; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_94 = \|(wrap_len_idx_end[6:4]); // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_91 = wrap_len_idx_end > 7'h10; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_96; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_96 = _GEN_91; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_100; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_100 = _GEN_91; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_92 = write_start_idx < 7'h11; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_97; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_97 = _GEN_92; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_99; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_99 = _GEN_92; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_98 = _use_this_queue_T_96 \| _use_this_queue_T_97; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_93 = wrap_len_idx_end > 7'h11; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_102; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_102 = _GEN_93; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_106; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_106 = _GEN_93; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_94 = write_start_idx < 7'h12; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_103; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_103 = _GEN_94; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_105; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_105 = _GEN_94; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_104 = _use_this_queue_T_102 \| _use_this_queue_T_103; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_95 = wrap_len_idx_end > 7'h12; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_108; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_108 = _GEN_95; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_112; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_112 = _GEN_95; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_96 = write_start_idx < 7'h13; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_109; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_109 = _GEN_96; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_111; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_111 = _GEN_96; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_110 = _use_this_queue_T_108 \| _use_this_queue_T_109; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_97 = wrap_len_idx_end > 7'h13; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_114; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_114 = _GEN_97; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_118; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_118 = _GEN_97; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_98 = write_start_idx < 7'h14; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_115; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_115 = _GEN_98; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_117; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_117 = _GEN_98; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_116 = _use_this_queue_T_114 \| _use_this_queue_T_115; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_99 = wrap_len_idx_end > 7'h14; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_120; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_120 = _GEN_99; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_124; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_124 = _GEN_99; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_100 = write_start_idx < 7'h15; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_121; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_121 = _GEN_100; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_123; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_123 = _GEN_100; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_122 = _use_this_queue_T_120 \| _use_this_queue_T_121; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_101 = wrap_len_idx_end > 7'h15; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_126; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_126 = _GEN_101; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_130; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_130 = _GEN_101; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_102 = write_start_idx < 7'h16; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_127; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_127 = _GEN_102; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_129; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_129 = _GEN_102; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_128 = _use_this_queue_T_126 \| _use_this_queue_T_127; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_103 = wrap_len_idx_end > 7'h16; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_132; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_132 = _GEN_103; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_136; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_136 = _GEN_103; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_104 = write_start_idx < 7'h17; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_133; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_133 = _GEN_104; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_135; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_135 = _GEN_104; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_134 = _use_this_queue_T_132 \| _use_this_queue_T_133; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_105 = wrap_len_idx_end > 7'h17; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_138; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_138 = _GEN_105; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_142; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_142 = _GEN_105; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_106 = write_start_idx < 7'h18; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_139; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_139 = _GEN_106; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_141; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_141 = _GEN_106; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_140 = _use_this_queue_T_138 \| _use_this_queue_T_139; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_107 = wrap_len_idx_end > 7'h18; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_144; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_144 = _GEN_107; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_148; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_148 = _GEN_107; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_108 = write_start_idx < 7'h19; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_145; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_145 = _GEN_108; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_147; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_147 = _GEN_108; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_146 = _use_this_queue_T_144 \| _use_this_queue_T_145; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_109 = wrap_len_idx_end > 7'h19; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_150; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_150 = _GEN_109; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_154; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_154 = _GEN_109; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_110 = write_start_idx < 7'h1A; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_151; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_151 = _GEN_110; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_153; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_153 = _GEN_110; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_152 = _use_this_queue_T_150 \| _use_this_queue_T_151; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_111 = wrap_len_idx_end > 7'h1A; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_156; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_156 = _GEN_111; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_160; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_160 = _GEN_111; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_112 = write_start_idx < 7'h1B; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_157; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_157 = _GEN_112; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_159; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_159 = _GEN_112; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_158 = _use_this_queue_T_156 \| _use_this_queue_T_157; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_113 = wrap_len_idx_end > 7'h1B; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_162; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_162 = _GEN_113; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_166; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_166 = _GEN_113; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_114 = write_start_idx < 7'h1C; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_163; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_163 = _GEN_114; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_165; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_165 = _GEN_114; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_164 = _use_this_queue_T_162 \| _use_this_queue_T_163; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_115 = wrap_len_idx_end > 7'h1C; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_168; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_168 = _GEN_115; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_172; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_172 = _GEN_115; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_116 = write_start_idx < 7'h1D; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_169; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_169 = _GEN_116; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_171; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_171 = _GEN_116; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_170 = _use_this_queue_T_168 \| _use_this_queue_T_169; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_117 = wrap_len_idx_end > 7'h1D; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_174; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_174 = _GEN_117; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_178; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_178 = _GEN_117; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_118 = write_start_idx < 7'h1E; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_175; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_175 = _GEN_118; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_177; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_177 = _GEN_118; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_176 = _use_this_queue_T_174 \| _use_this_queue_T_175; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_119 = wrap_len_idx_end > 7'h1E; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_180; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_180 = _GEN_119; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_184; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_184 = _GEN_119; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_120 = write_start_idx < 7'h1F; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_181; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_181 = _GEN_120; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_183; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_183 = _GEN_120; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_182 = _use_this_queue_T_180 \| _use_this_queue_T_181; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_186 = \|(wrap_len_idx_end[6:5]); // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_121 = write_start_idx < 7'h20; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_187; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_187 = _GEN_121; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_189; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_189 = _GEN_121; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_188 = _use_this_queue_T_186 \| _use_this_queue_T_187; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_190 = \|(wrap_len_idx_end[6:5]); // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_122 = wrap_len_idx_end > 7'h20; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_192; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_192 = _GEN_122; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_196; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_196 = _GEN_122; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_123 = write_start_idx < 7'h21; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_193; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_193 = _GEN_123; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_195; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_195 = _GEN_123; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_194 = _use_this_queue_T_192 \| _use_this_queue_T_193; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_197 = _use_this_queue_T_195 & _use_this_queue_T_196; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_32 = wrapped ? _use_this_queue_T_194 : _use_this_queue_T_197; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_124 = wrap_len_idx_end > 7'h21; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_198; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_198 = _GEN_124; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_202; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_202 = _GEN_124; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_125 = write_start_idx < 7'h22; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_199; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_199 = _GEN_125; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_201; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_201 = _GEN_125; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_200 = _use_this_queue_T_198 \| _use_this_queue_T_199; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_203 = _use_this_queue_T_201 & _use_this_queue_T_202; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_33 = wrapped ? _use_this_queue_T_200 : _use_this_queue_T_203; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_126 = wrap_len_idx_end > 7'h22; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_204; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_204 = _GEN_126; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_208; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_208 = _GEN_126; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_127 = write_start_idx < 7'h23; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_205; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_205 = _GEN_127; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_207; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_207 = _GEN_127; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_206 = _use_this_queue_T_204 \| _use_this_queue_T_205; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_209 = _use_this_queue_T_207 & _use_this_queue_T_208; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_34 = wrapped ? _use_this_queue_T_206 : _use_this_queue_T_209; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_128 = wrap_len_idx_end > 7'h23; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_210; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_210 = _GEN_128; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_214; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_214 = _GEN_128; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_129 = write_start_idx < 7'h24; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_211; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_211 = _GEN_129; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_213; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_213 = _GEN_129; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_212 = _use_this_queue_T_210 \| _use_this_queue_T_211; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_215 = _use_this_queue_T_213 & _use_this_queue_T_214; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_35 = wrapped ? _use_this_queue_T_212 : _use_this_queue_T_215; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_130 = wrap_len_idx_end > 7'h24; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_216; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_216 = _GEN_130; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_220; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_220 = _GEN_130; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_131 = write_start_idx < 7'h25; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_217; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_217 = _GEN_131; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_219; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_219 = _GEN_131; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_218 = _use_this_queue_T_216 \| _use_this_queue_T_217; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_221 = _use_this_queue_T_219 & _use_this_queue_T_220; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_36 = wrapped ? _use_this_queue_T_218 : _use_this_queue_T_221; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_132 = wrap_len_idx_end > 7'h25; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_222; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_222 = _GEN_132; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_226; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_226 = _GEN_132; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_133 = write_start_idx < 7'h26; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_223; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_223 = _GEN_133; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_225; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_225 = _GEN_133; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_224 = _use_this_queue_T_222 \| _use_this_queue_T_223; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_227 = _use_this_queue_T_225 & _use_this_queue_T_226; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_37 = wrapped ? _use_this_queue_T_224 : _use_this_queue_T_227; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_134 = wrap_len_idx_end > 7'h26; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_228; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_228 = _GEN_134; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_232; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_232 = _GEN_134; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_135 = write_start_idx < 7'h27; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_229; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_229 = _GEN_135; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_231; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_231 = _GEN_135; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_230 = _use_this_queue_T_228 \| _use_this_queue_T_229; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_233 = _use_this_queue_T_231 & _use_this_queue_T_232; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_38 = wrapped ? _use_this_queue_T_230 : _use_this_queue_T_233; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_136 = wrap_len_idx_end > 7'h27; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_234; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_234 = _GEN_136; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_238; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_238 = _GEN_136; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_137 = write_start_idx < 7'h28; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_235; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_235 = _GEN_137; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_237; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_237 = _GEN_137; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_236 = _use_this_queue_T_234 \| _use_this_queue_T_235; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_239 = _use_this_queue_T_237 & _use_this_queue_T_238; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_39 = wrapped ? _use_this_queue_T_236 : _use_this_queue_T_239; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_138 = wrap_len_idx_end > 7'h28; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_240; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_240 = _GEN_138; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_244; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_244 = _GEN_138; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_139 = write_start_idx < 7'h29; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_241; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_241 = _GEN_139; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_243; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_243 = _GEN_139; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_242 = _use_this_queue_T_240 \| _use_this_queue_T_241; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_245 = _use_this_queue_T_243 & _use_this_queue_T_244; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_40 = wrapped ? _use_this_queue_T_242 : _use_this_queue_T_245; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_140 = wrap_len_idx_end > 7'h29; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_246; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_246 = _GEN_140; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_250; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_250 = _GEN_140; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_141 = write_start_idx < 7'h2A; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_247; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_247 = _GEN_141; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_249; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_249 = _GEN_141; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_248 = _use_this_queue_T_246 \| _use_this_queue_T_247; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_251 = _use_this_queue_T_249 & _use_this_queue_T_250; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_41 = wrapped ? _use_this_queue_T_248 : _use_this_queue_T_251; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_142 = wrap_len_idx_end > 7'h2A; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_252; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_252 = _GEN_142; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_256; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_256 = _GEN_142; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_143 = write_start_idx < 7'h2B; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_253; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_253 = _GEN_143; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_255; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_255 = _GEN_143; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_254 = _use_this_queue_T_252 \| _use_this_queue_T_253; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_257 = _use_this_queue_T_255 & _use_this_queue_T_256; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_42 = wrapped ? _use_this_queue_T_254 : _use_this_queue_T_257; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_144 = wrap_len_idx_end > 7'h2B; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_258; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_258 = _GEN_144; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_262; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_262 = _GEN_144; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_145 = write_start_idx < 7'h2C; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_259; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_259 = _GEN_145; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_261; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_261 = _GEN_145; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_260 = _use_this_queue_T_258 \| _use_this_queue_T_259; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_263 = _use_this_queue_T_261 & _use_this_queue_T_262; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_43 = wrapped ? _use_this_queue_T_260 : _use_this_queue_T_263; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_146 = wrap_len_idx_end > 7'h2C; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_264; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_264 = _GEN_146; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_268; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_268 = _GEN_146; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_147 = write_start_idx < 7'h2D; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_265; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_265 = _GEN_147; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_267; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_267 = _GEN_147; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_266 = _use_this_queue_T_264 \| _use_this_queue_T_265; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_269 = _use_this_queue_T_267 & _use_this_queue_T_268; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_44 = wrapped ? _use_this_queue_T_266 : _use_this_queue_T_269; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_148 = wrap_len_idx_end > 7'h2D; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_270; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_270 = _GEN_148; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_274; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_274 = _GEN_148; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_149 = write_start_idx < 7'h2E; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_271; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_271 = _GEN_149; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_273; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_273 = _GEN_149; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_272 = _use_this_queue_T_270 \| _use_this_queue_T_271; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_275 = _use_this_queue_T_273 & _use_this_queue_T_274; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_45 = wrapped ? _use_this_queue_T_272 : _use_this_queue_T_275; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_150 = wrap_len_idx_end > 7'h2E; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_276; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_276 = _GEN_150; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_280; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_280 = _GEN_150; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_151 = write_start_idx < 7'h2F; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_277; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_277 = _GEN_151; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_279; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_279 = _GEN_151; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_278 = _use_this_queue_T_276 \| _use_this_queue_T_277; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_281 = _use_this_queue_T_279 & _use_this_queue_T_280; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_46 = wrapped ? _use_this_queue_T_278 : _use_this_queue_T_281; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_152 = wrap_len_idx_end > 7'h2F; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_282; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_282 = _GEN_152; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_286; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_286 = _GEN_152; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_153 = write_start_idx < 7'h30; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_283; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_283 = _GEN_153; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_285; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_285 = _GEN_153; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_284 = _use_this_queue_T_282 \| _use_this_queue_T_283; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_287 = _use_this_queue_T_285 & _use_this_queue_T_286; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_47 = wrapped ? _use_this_queue_T_284 : _use_this_queue_T_287; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_154 = wrap_len_idx_end > 7'h30; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_288; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_288 = _GEN_154; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_292; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_292 = _GEN_154; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_155 = write_start_idx < 7'h31; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_289; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_289 = _GEN_155; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_291; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_291 = _GEN_155; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_290 = _use_this_queue_T_288 \| _use_this_queue_T_289; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_293 = _use_this_queue_T_291 & _use_this_queue_T_292; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_48 = wrapped ? _use_this_queue_T_290 : _use_this_queue_T_293; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_156 = wrap_len_idx_end > 7'h31; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_294; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_294 = _GEN_156; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_298; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_298 = _GEN_156; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_157 = write_start_idx < 7'h32; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_295; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_295 = _GEN_157; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_297; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_297 = _GEN_157; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_296 = _use_this_queue_T_294 \| _use_this_queue_T_295; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_299 = _use_this_queue_T_297 & _use_this_queue_T_298; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_49 = wrapped ? _use_this_queue_T_296 : _use_this_queue_T_299; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_158 = wrap_len_idx_end > 7'h32; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_300; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_300 = _GEN_158; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_304; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_304 = _GEN_158; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_159 = write_start_idx < 7'h33; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_301; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_301 = _GEN_159; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_303; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_303 = _GEN_159; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_302 = _use_this_queue_T_300 \| _use_this_queue_T_301; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_305 = _use_this_queue_T_303 & _use_this_queue_T_304; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_50 = wrapped ? _use_this_queue_T_302 : _use_this_queue_T_305; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_160 = wrap_len_idx_end > 7'h33; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_306; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_306 = _GEN_160; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_310; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_310 = _GEN_160; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_161 = write_start_idx < 7'h34; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_307; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_307 = _GEN_161; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_309; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_309 = _GEN_161; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_308 = _use_this_queue_T_306 \| _use_this_queue_T_307; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_311 = _use_this_queue_T_309 & _use_this_queue_T_310; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_51 = wrapped ? _use_this_queue_T_308 : _use_this_queue_T_311; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_162 = wrap_len_idx_end > 7'h34; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_312; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_312 = _GEN_162; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_316; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_316 = _GEN_162; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_163 = write_start_idx < 7'h35; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_313; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_313 = _GEN_163; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_315; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_315 = _GEN_163; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_314 = _use_this_queue_T_312 \| _use_this_queue_T_313; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_317 = _use_this_queue_T_315 & _use_this_queue_T_316; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_52 = wrapped ? _use_this_queue_T_314 : _use_this_queue_T_317; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_164 = wrap_len_idx_end > 7'h35; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_318; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_318 = _GEN_164; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_322; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_322 = _GEN_164; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_165 = write_start_idx < 7'h36; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_319; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_319 = _GEN_165; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_321; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_321 = _GEN_165; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_320 = _use_this_queue_T_318 \| _use_this_queue_T_319; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_323 = _use_this_queue_T_321 & _use_this_queue_T_322; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_53 = wrapped ? _use_this_queue_T_320 : _use_this_queue_T_323; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_166 = wrap_len_idx_end > 7'h36; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_324; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_324 = _GEN_166; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_328; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_328 = _GEN_166; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_167 = write_start_idx < 7'h37; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_325; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_325 = _GEN_167; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_327; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_327 = _GEN_167; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_326 = _use_this_queue_T_324 \| _use_this_queue_T_325; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_329 = _use_this_queue_T_327 & _use_this_queue_T_328; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_54 = wrapped ? _use_this_queue_T_326 : _use_this_queue_T_329; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_168 = wrap_len_idx_end > 7'h37; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_330; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_330 = _GEN_168; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_334; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_334 = _GEN_168; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_169 = write_start_idx < 7'h38; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_331; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_331 = _GEN_169; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_333; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_333 = _GEN_169; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_332 = _use_this_queue_T_330 \| _use_this_queue_T_331; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_335 = _use_this_queue_T_333 & _use_this_queue_T_334; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_55 = wrapped ? _use_this_queue_T_332 : _use_this_queue_T_335; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_170 = wrap_len_idx_end > 7'h38; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_336; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_336 = _GEN_170; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_340; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_340 = _GEN_170; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_171 = write_start_idx < 7'h39; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_337; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_337 = _GEN_171; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_339; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_339 = _GEN_171; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_338 = _use_this_queue_T_336 \| _use_this_queue_T_337; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_341 = _use_this_queue_T_339 & _use_this_queue_T_340; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_56 = wrapped ? _use_this_queue_T_338 : _use_this_queue_T_341; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_172 = wrap_len_idx_end > 7'h39; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_342; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_342 = _GEN_172; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_346; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_346 = _GEN_172; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_173 = write_start_idx < 7'h3A; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_343; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_343 = _GEN_173; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_345; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_345 = _GEN_173; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_344 = _use_this_queue_T_342 \| _use_this_queue_T_343; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_347 = _use_this_queue_T_345 & _use_this_queue_T_346; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_57 = wrapped ? _use_this_queue_T_344 : _use_this_queue_T_347; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_174 = wrap_len_idx_end > 7'h3A; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_348; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_348 = _GEN_174; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_352; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_352 = _GEN_174; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_175 = write_start_idx < 7'h3B; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_349; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_349 = _GEN_175; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_351; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_351 = _GEN_175; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_350 = _use_this_queue_T_348 \| _use_this_queue_T_349; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_353 = _use_this_queue_T_351 & _use_this_queue_T_352; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_58 = wrapped ? _use_this_queue_T_350 : _use_this_queue_T_353; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_176 = wrap_len_idx_end > 7'h3B; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_354; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_354 = _GEN_176; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_358; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_358 = _GEN_176; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_177 = write_start_idx < 7'h3C; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_355; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_355 = _GEN_177; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_357; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_357 = _GEN_177; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_356 = _use_this_queue_T_354 \| _use_this_queue_T_355; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_359 = _use_this_queue_T_357 & _use_this_queue_T_358; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_59 = wrapped ? _use_this_queue_T_356 : _use_this_queue_T_359; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_178 = wrap_len_idx_end > 7'h3C; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_360; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_360 = _GEN_178; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_364; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_364 = _GEN_178; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_179 = write_start_idx < 7'h3D; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_361; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_361 = _GEN_179; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_363; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_363 = _GEN_179; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_362 = _use_this_queue_T_360 \| _use_this_queue_T_361; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_365 = _use_this_queue_T_363 & _use_this_queue_T_364; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_60 = wrapped ? _use_this_queue_T_362 : _use_this_queue_T_365; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_180 = wrap_len_idx_end > 7'h3D; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_366; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_366 = _GEN_180; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_370; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_370 = _GEN_180; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_181 = write_start_idx < 7'h3E; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_367; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_367 = _GEN_181; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_369; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_369 = _GEN_181; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_368 = _use_this_queue_T_366 \| _use_this_queue_T_367; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_371 = _use_this_queue_T_369 & _use_this_queue_T_370; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_61 = wrapped ? _use_this_queue_T_368 : _use_this_queue_T_371; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_182 = wrap_len_idx_end > 7'h3E; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_372; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_372 = _GEN_182; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_376; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_376 = _GEN_182; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_183 = write_start_idx < 7'h3F; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_373; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_373 = _GEN_183; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_375; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_375 = _GEN_183; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_374 = _use_this_queue_T_372 \| _use_this_queue_T_373; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_377 = _use_this_queue_T_375 & _use_this_queue_T_376; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_62 = wrapped ? _use_this_queue_T_374 : _use_this_queue_T_377; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_378 = wrap_len_idx_end[6]; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_382 = wrap_len_idx_end[6]; // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_379 = ~(write_start_idx[6]); // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_380 = _use_this_queue_T_378 \| _use_this_queue_T_379; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_381 = ~(write_start_idx[6]); // @[CompressedBitsBuffer.scala:77:32, :105:65, :106:37] wire _use_this_queue_T_383 = _use_this_queue_T_381 & _use_this_queue_T_382; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_63 = wrapped ? _use_this_queue_T_380 : _use_this_queue_T_383; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _buf_lens_q_io_enq_valid_T = all_queues_ready & _incoming_writes_io_deq_valid; // @[Misc.scala:26:53] wire _buf_lens_q_io_enq_valid_T_1 = _buf_lens_q_io_enq_valid_T & _incoming_writes_io_deq_bits_end_of_message; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _T_263 = _incoming_writes_io_deq_ready_T & _incoming_writes_io_deq_valid; // @[Misc.scala:26:53, :29:18] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [6:0] read_start_idx; // @[CompressedBitsBuffer.scala:126:31] wire bufVecData_0; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_1; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_2; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_3; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_4; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_5; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_6; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_7; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_8; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_9; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_10; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_11; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_12; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_13; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_14; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_15; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_16; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_17; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_18; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_19; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_20; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_21; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_22; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_23; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_24; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_25; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_26; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_27; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_28; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_29; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_30; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_31; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_32; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_33; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_34; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_35; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_36; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_37; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_38; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_39; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_40; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_41; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_42; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_43; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_44; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_45; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_46; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_47; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_48; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_49; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_50; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_51; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_52; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_53; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_54; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_55; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_56; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_57; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_58; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_59; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_60; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_61; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_62; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_63; // @[CompressedBitsBuffer.scala:128:24] wire bufVecReadys_0; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_1; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_2; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_3; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_4; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_5; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_6; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_7; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_8; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_9; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_10; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_11; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_12; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_13; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_14; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_15; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_16; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_17; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_18; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_19; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_20; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_21; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_22; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_23; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_24; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_25; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_26; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_27; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_28; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_29; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_30; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_31; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_32; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_33; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_34; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_35; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_36; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_37; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_38; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_39; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_40; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_41; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_42; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_43; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_44; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_45; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_46; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_47; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_48; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_49; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_50; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_51; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_52; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_53; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_54; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_55; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_56; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_57; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_58; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_59; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_60; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_61; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_62; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_63; // @[CompressedBitsBuffer.scala:129:26] wire bufVecValids_0; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_1; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_2; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_3; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_4; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_5; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_6; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_7; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_8; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_9; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_10; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_11; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_12; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_13; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_14; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_15; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_16; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_17; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_18; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_19; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_20; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_21; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_22; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_23; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_24; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_25; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_26; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_27; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_28; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_29; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_30; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_31; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_32; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_33; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_34; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_35; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_36; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_37; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_38; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_39; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_40; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_41; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_42; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_43; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_44; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_45; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_46; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_47; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_48; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_49; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_50; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_51; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_52; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_53; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_54; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_55; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_56; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_57; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_58; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_59; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_60; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_61; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_62; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_63; // @[CompressedBitsBuffer.scala:130:26] wire remapVecData_0; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_1; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_2; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_3; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_4; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_5; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_6; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_7; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_8; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_9; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_10; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_11; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_12; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_13; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_14; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_15; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_16; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_17; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_18; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_19; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_20; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_21; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_22; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_23; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_24; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_25; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_26; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_27; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_28; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_29; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_30; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_31; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_32; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_33; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_34; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_35; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_36; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_37; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_38; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_39; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_40; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_41; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_42; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_43; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_44; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_45; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_46; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_47; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_48; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_49; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_50; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_51; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_52; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_53; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_54; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_55; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_56; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_57; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_58; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_59; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_60; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_61; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_62; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_63; // @[CompressedBitsBuffer.scala:139:26] wire _remapVecReadys_0_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_1_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_2_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_3_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_4_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_5_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_6_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_7_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_8_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_9_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_10_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_11_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_12_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_13_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_14_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_15_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_16_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_17_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_18_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_19_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_20_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_21_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_22_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_23_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_24_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_25_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_26_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_27_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_28_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_29_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_30_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_31_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_32_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_33_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_34_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_35_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_36_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_37_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_38_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_39_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_40_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_41_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_42_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_43_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_44_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_45_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_46_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_47_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_48_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_49_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_50_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_51_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_52_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_53_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_54_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_55_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_56_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_57_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_58_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_59_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_60_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_61_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_62_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_63_T_2; // @[CompressedBitsBuffer.scala:197:48] wire remapVecReadys_0; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_1; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_2; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_3; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_4; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_5; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_6; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_7; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_8; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_9; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_10; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_11; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_12; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_13; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_14; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_15; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_16; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_17; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_18; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_19; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_20; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_21; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_22; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_23; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_24; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_25; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_26; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_27; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_28; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_29; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_30; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_31; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_32; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_33; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_34; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_35; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_36; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_37; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_38; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_39; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_40; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_41; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_42; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_43; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_44; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_45; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_46; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_47; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_48; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_49; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_50; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_51; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_52; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_53; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_54; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_55; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_56; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_57; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_58; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_59; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_60; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_61; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_62; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_63; // @[CompressedBitsBuffer.scala:140:28] wire remapVecValids_0; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_1; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_2; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_3; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_4; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_5; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_6; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_7; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_8; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_9; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_10; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_11; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_12; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_13; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_14; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_15; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_16; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_17; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_18; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_19; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_20; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_21; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_22; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_23; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_24; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_25; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_26; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_27; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_28; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_29; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_30; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_31; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_32; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_33; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_34; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_35; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_36; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_37; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_38; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_39; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_40; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_41; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_42; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_43; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_44; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_45; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_46; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_47; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_48; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_49; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_50; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_51; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_52; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_53; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_54; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_55; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_56; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_57; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_58; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_59; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_60; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_61; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_62; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_63; // @[CompressedBitsBuffer.scala:141:28] wire [7:0] _remap_idx_T = {1'h0, read_start_idx}; // @[CompressedBitsBuffer.scala:126:31, :144:26] wire [7:0] _GEN_184 = _remap_idx_T % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx = _GEN_184[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_0_T = remap_idx[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_0_T = remap_idx[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [63:0] _GEN_185 = {{bufVecData_63}, {bufVecData_62}, {bufVecData_61}, {bufVecData_60}, {bufVecData_59}, {bufVecData_58}, {bufVecData_57}, {bufVecData_56}, {bufVecData_55}, {bufVecData_54}, {bufVecData_53}, {bufVecData_52}, {bufVecData_51}, {bufVecData_50}, {bufVecData_49}, {bufVecData_48}, {bufVecData_47}, {bufVecData_46}, {bufVecData_45}, {bufVecData_44}, {bufVecData_43}, {bufVecData_42}, {bufVecData_41}, {bufVecData_40}, {bufVecData_39}, {bufVecData_38}, {bufVecData_37}, {bufVecData_36}, {bufVecData_35}, {bufVecData_34}, {bufVecData_33}, {bufVecData_32}, {bufVecData_31}, {bufVecData_30}, {bufVecData_29}, {bufVecData_28}, {bufVecData_27}, {bufVecData_26}, {bufVecData_25}, {bufVecData_24}, {bufVecData_23}, {bufVecData_22}, {bufVecData_21}, {bufVecData_20}, {bufVecData_19}, {bufVecData_18}, {bufVecData_17}, {bufVecData_16}, {bufVecData_15}, {bufVecData_14}, {bufVecData_13}, {bufVecData_12}, {bufVecData_11}, {bufVecData_10}, {bufVecData_9}, {bufVecData_8}, {bufVecData_7}, {bufVecData_6}, {bufVecData_5}, {bufVecData_4}, {bufVecData_3}, {bufVecData_2}, {bufVecData_1}, {bufVecData_0}}; // @[CompressedBitsBuffer.scala:128:24, :145:21] assign remapVecData_0 = _GEN_185[_remapVecData_0_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] wire [63:0] _GEN_186 = {{bufVecValids_63}, {bufVecValids_62}, {bufVecValids_61}, {bufVecValids_60}, {bufVecValids_59}, {bufVecValids_58}, {bufVecValids_57}, {bufVecValids_56}, {bufVecValids_55}, {bufVecValids_54}, {bufVecValids_53}, {bufVecValids_52}, {bufVecValids_51}, {bufVecValids_50}, {bufVecValids_49}, {bufVecValids_48}, {bufVecValids_47}, {bufVecValids_46}, {bufVecValids_45}, {bufVecValids_44}, {bufVecValids_43}, {bufVecValids_42}, {bufVecValids_41}, {bufVecValids_40}, {bufVecValids_39}, {bufVecValids_38}, {bufVecValids_37}, {bufVecValids_36}, {bufVecValids_35}, {bufVecValids_34}, {bufVecValids_33}, {bufVecValids_32}, {bufVecValids_31}, {bufVecValids_30}, {bufVecValids_29}, {bufVecValids_28}, {bufVecValids_27}, {bufVecValids_26}, {bufVecValids_25}, {bufVecValids_24}, {bufVecValids_23}, {bufVecValids_22}, {bufVecValids_21}, {bufVecValids_20}, {bufVecValids_19}, {bufVecValids_18}, {bufVecValids_17}, {bufVecValids_16}, {bufVecValids_15}, {bufVecValids_14}, {bufVecValids_13}, {bufVecValids_12}, {bufVecValids_11}, {bufVecValids_10}, {bufVecValids_9}, {bufVecValids_8}, {bufVecValids_7}, {bufVecValids_6}, {bufVecValids_5}, {bufVecValids_4}, {bufVecValids_3}, {bufVecValids_2}, {bufVecValids_1}, {bufVecValids_0}}; // @[CompressedBitsBuffer.scala:130:26, :146:23] assign remapVecValids_0 = _GEN_186[_remapVecValids_0_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_1 = _remap_idx_T + 8'h1; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_187 = _remap_idx_T_1 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_1 = _GEN_187[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_1_T = remap_idx_1[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_1_T = remap_idx_1[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_1 = _GEN_185[_remapVecData_1_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_1 = _GEN_186[_remapVecValids_1_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_2 = _remap_idx_T + 8'h2; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_188 = _remap_idx_T_2 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_2 = _GEN_188[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_2_T = remap_idx_2[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_2_T = remap_idx_2[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_2 = _GEN_185[_remapVecData_2_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_2 = _GEN_186[_remapVecValids_2_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_3 = _remap_idx_T + 8'h3; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_189 = _remap_idx_T_3 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_3 = _GEN_189[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_3_T = remap_idx_3[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_3_T = remap_idx_3[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_3 = _GEN_185[_remapVecData_3_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_3 = _GEN_186[_remapVecValids_3_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_4 = _remap_idx_T + 8'h4; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_190 = _remap_idx_T_4 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_4 = _GEN_190[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_4_T = remap_idx_4[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_4_T = remap_idx_4[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_4 = _GEN_185[_remapVecData_4_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_4 = _GEN_186[_remapVecValids_4_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_5 = _remap_idx_T + 8'h5; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_191 = _remap_idx_T_5 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_5 = _GEN_191[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_5_T = remap_idx_5[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_5_T = remap_idx_5[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_5 = _GEN_185[_remapVecData_5_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_5 = _GEN_186[_remapVecValids_5_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_6 = _remap_idx_T + 8'h6; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_192 = _remap_idx_T_6 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_6 = _GEN_192[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_6_T = remap_idx_6[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_6_T = remap_idx_6[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_6 = _GEN_185[_remapVecData_6_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_6 = _GEN_186[_remapVecValids_6_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_7 = _remap_idx_T + 8'h7; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_193 = _remap_idx_T_7 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_7 = _GEN_193[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_7_T = remap_idx_7[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_7_T = remap_idx_7[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_7 = _GEN_185[_remapVecData_7_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_7 = _GEN_186[_remapVecValids_7_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_8 = _remap_idx_T + 8'h8; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_194 = _remap_idx_T_8 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_8 = _GEN_194[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_8_T = remap_idx_8[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_8_T = remap_idx_8[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_8 = _GEN_185[_remapVecData_8_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_8 = _GEN_186[_remapVecValids_8_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_9 = _remap_idx_T + 8'h9; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_195 = _remap_idx_T_9 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_9 = _GEN_195[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_9_T = remap_idx_9[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_9_T = remap_idx_9[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_9 = _GEN_185[_remapVecData_9_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_9 = _GEN_186[_remapVecValids_9_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_10 = _remap_idx_T + 8'hA; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_196 = _remap_idx_T_10 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_10 = _GEN_196[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_10_T = remap_idx_10[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_10_T = remap_idx_10[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_10 = _GEN_185[_remapVecData_10_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_10 = _GEN_186[_remapVecValids_10_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_11 = _remap_idx_T + 8'hB; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_197 = _remap_idx_T_11 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_11 = _GEN_197[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_11_T = remap_idx_11[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_11_T = remap_idx_11[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_11 = _GEN_185[_remapVecData_11_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_11 = _GEN_186[_remapVecValids_11_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_12 = _remap_idx_T + 8'hC; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_198 = _remap_idx_T_12 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_12 = _GEN_198[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_12_T = remap_idx_12[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_12_T = remap_idx_12[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_12 = _GEN_185[_remapVecData_12_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_12 = _GEN_186[_remapVecValids_12_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_13 = _remap_idx_T + 8'hD; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_199 = _remap_idx_T_13 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_13 = _GEN_199[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_13_T = remap_idx_13[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_13_T = remap_idx_13[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_13 = _GEN_185[_remapVecData_13_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_13 = _GEN_186[_remapVecValids_13_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_14 = _remap_idx_T + 8'hE; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_200 = _remap_idx_T_14 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_14 = _GEN_200[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_14_T = remap_idx_14[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_14_T = remap_idx_14[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_14 = _GEN_185[_remapVecData_14_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_14 = _GEN_186[_remapVecValids_14_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_15 = _remap_idx_T + 8'hF; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_201 = _remap_idx_T_15 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_15 = _GEN_201[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_15_T = remap_idx_15[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_15_T = remap_idx_15[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_15 = _GEN_185[_remapVecData_15_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_15 = _GEN_186[_remapVecValids_15_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_16 = _remap_idx_T + 8'h10; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_202 = _remap_idx_T_16 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_16 = _GEN_202[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_16_T = remap_idx_16[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_16_T = remap_idx_16[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_16 = _GEN_185[_remapVecData_16_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_16 = _GEN_186[_remapVecValids_16_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_17 = _remap_idx_T + 8'h11; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_203 = _remap_idx_T_17 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_17 = _GEN_203[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_17_T = remap_idx_17[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_17_T = remap_idx_17[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_17 = _GEN_185[_remapVecData_17_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_17 = _GEN_186[_remapVecValids_17_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_18 = _remap_idx_T + 8'h12; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_204 = _remap_idx_T_18 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_18 = _GEN_204[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_18_T = remap_idx_18[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_18_T = remap_idx_18[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_18 = _GEN_185[_remapVecData_18_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_18 = _GEN_186[_remapVecValids_18_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_19 = _remap_idx_T + 8'h13; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_205 = _remap_idx_T_19 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_19 = _GEN_205[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_19_T = remap_idx_19[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_19_T = remap_idx_19[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_19 = _GEN_185[_remapVecData_19_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_19 = _GEN_186[_remapVecValids_19_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_20 = _remap_idx_T + 8'h14; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_206 = _remap_idx_T_20 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_20 = _GEN_206[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_20_T = remap_idx_20[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_20_T = remap_idx_20[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_20 = _GEN_185[_remapVecData_20_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_20 = _GEN_186[_remapVecValids_20_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_21 = _remap_idx_T + 8'h15; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_207 = _remap_idx_T_21 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_21 = _GEN_207[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_21_T = remap_idx_21[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_21_T = remap_idx_21[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_21 = _GEN_185[_remapVecData_21_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_21 = _GEN_186[_remapVecValids_21_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_22 = _remap_idx_T + 8'h16; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_208 = _remap_idx_T_22 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_22 = _GEN_208[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_22_T = remap_idx_22[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_22_T = remap_idx_22[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_22 = _GEN_185[_remapVecData_22_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_22 = _GEN_186[_remapVecValids_22_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_23 = _remap_idx_T + 8'h17; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_209 = _remap_idx_T_23 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_23 = _GEN_209[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_23_T = remap_idx_23[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_23_T = remap_idx_23[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_23 = _GEN_185[_remapVecData_23_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_23 = _GEN_186[_remapVecValids_23_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_24 = _remap_idx_T + 8'h18; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_210 = _remap_idx_T_24 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_24 = _GEN_210[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_24_T = remap_idx_24[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_24_T = remap_idx_24[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_24 = _GEN_185[_remapVecData_24_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_24 = _GEN_186[_remapVecValids_24_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_25 = _remap_idx_T + 8'h19; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_211 = _remap_idx_T_25 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_25 = _GEN_211[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_25_T = remap_idx_25[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_25_T = remap_idx_25[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_25 = _GEN_185[_remapVecData_25_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_25 = _GEN_186[_remapVecValids_25_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_26 = _remap_idx_T + 8'h1A; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_212 = _remap_idx_T_26 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_26 = _GEN_212[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_26_T = remap_idx_26[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_26_T = remap_idx_26[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_26 = _GEN_185[_remapVecData_26_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_26 = _GEN_186[_remapVecValids_26_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_27 = _remap_idx_T + 8'h1B; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_213 = _remap_idx_T_27 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_27 = _GEN_213[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_27_T = remap_idx_27[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_27_T = remap_idx_27[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_27 = _GEN_185[_remapVecData_27_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_27 = _GEN_186[_remapVecValids_27_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_28 = _remap_idx_T + 8'h1C; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_214 = _remap_idx_T_28 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_28 = _GEN_214[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_28_T = remap_idx_28[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_28_T = remap_idx_28[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_28 = _GEN_185[_remapVecData_28_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_28 = _GEN_186[_remapVecValids_28_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_29 = _remap_idx_T + 8'h1D; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_215 = _remap_idx_T_29 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_29 = _GEN_215[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_29_T = remap_idx_29[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_29_T = remap_idx_29[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_29 = _GEN_185[_remapVecData_29_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_29 = _GEN_186[_remapVecValids_29_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_30 = _remap_idx_T + 8'h1E; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_216 = _remap_idx_T_30 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_30 = _GEN_216[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_30_T = remap_idx_30[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_30_T = remap_idx_30[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_30 = _GEN_185[_remapVecData_30_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_30 = _GEN_186[_remapVecValids_30_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_31 = _remap_idx_T + 8'h1F; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_217 = _remap_idx_T_31 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_31 = _GEN_217[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_31_T = remap_idx_31[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_31_T = remap_idx_31[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_31 = _GEN_185[_remapVecData_31_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_31 = _GEN_186[_remapVecValids_31_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_32 = _remap_idx_T + 8'h20; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_218 = _remap_idx_T_32 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_32 = _GEN_218[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_32_T = remap_idx_32[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_32_T = remap_idx_32[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_32 = _GEN_185[_remapVecData_32_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_32 = _GEN_186[_remapVecValids_32_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_33 = _remap_idx_T + 8'h21; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_219 = _remap_idx_T_33 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_33 = _GEN_219[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_33_T = remap_idx_33[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_33_T = remap_idx_33[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_33 = _GEN_185[_remapVecData_33_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_33 = _GEN_186[_remapVecValids_33_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_34 = _remap_idx_T + 8'h22; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_220 = _remap_idx_T_34 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_34 = _GEN_220[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_34_T = remap_idx_34[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_34_T = remap_idx_34[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_34 = _GEN_185[_remapVecData_34_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_34 = _GEN_186[_remapVecValids_34_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_35 = _remap_idx_T + 8'h23; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_221 = _remap_idx_T_35 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_35 = _GEN_221[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_35_T = remap_idx_35[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_35_T = remap_idx_35[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_35 = _GEN_185[_remapVecData_35_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_35 = _GEN_186[_remapVecValids_35_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_36 = _remap_idx_T + 8'h24; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_222 = _remap_idx_T_36 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_36 = _GEN_222[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_36_T = remap_idx_36[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_36_T = remap_idx_36[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_36 = _GEN_185[_remapVecData_36_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_36 = _GEN_186[_remapVecValids_36_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_37 = _remap_idx_T + 8'h25; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_223 = _remap_idx_T_37 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_37 = _GEN_223[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_37_T = remap_idx_37[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_37_T = remap_idx_37[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_37 = _GEN_185[_remapVecData_37_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_37 = _GEN_186[_remapVecValids_37_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_38 = _remap_idx_T + 8'h26; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_224 = _remap_idx_T_38 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_38 = _GEN_224[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_38_T = remap_idx_38[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_38_T = remap_idx_38[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_38 = _GEN_185[_remapVecData_38_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_38 = _GEN_186[_remapVecValids_38_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_39 = _remap_idx_T + 8'h27; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_225 = _remap_idx_T_39 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_39 = _GEN_225[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_39_T = remap_idx_39[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_39_T = remap_idx_39[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_39 = _GEN_185[_remapVecData_39_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_39 = _GEN_186[_remapVecValids_39_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_40 = _remap_idx_T + 8'h28; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_226 = _remap_idx_T_40 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_40 = _GEN_226[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_40_T = remap_idx_40[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_40_T = remap_idx_40[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_40 = _GEN_185[_remapVecData_40_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_40 = _GEN_186[_remapVecValids_40_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_41 = _remap_idx_T + 8'h29; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_227 = _remap_idx_T_41 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_41 = _GEN_227[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_41_T = remap_idx_41[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_41_T = remap_idx_41[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_41 = _GEN_185[_remapVecData_41_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_41 = _GEN_186[_remapVecValids_41_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_42 = _remap_idx_T + 8'h2A; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_228 = _remap_idx_T_42 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_42 = _GEN_228[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_42_T = remap_idx_42[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_42_T = remap_idx_42[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_42 = _GEN_185[_remapVecData_42_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_42 = _GEN_186[_remapVecValids_42_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_43 = _remap_idx_T + 8'h2B; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_229 = _remap_idx_T_43 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_43 = _GEN_229[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_43_T = remap_idx_43[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_43_T = remap_idx_43[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_43 = _GEN_185[_remapVecData_43_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_43 = _GEN_186[_remapVecValids_43_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_44 = _remap_idx_T + 8'h2C; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_230 = _remap_idx_T_44 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_44 = _GEN_230[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_44_T = remap_idx_44[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_44_T = remap_idx_44[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_44 = _GEN_185[_remapVecData_44_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_44 = _GEN_186[_remapVecValids_44_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_45 = _remap_idx_T + 8'h2D; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_231 = _remap_idx_T_45 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_45 = _GEN_231[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_45_T = remap_idx_45[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_45_T = remap_idx_45[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_45 = _GEN_185[_remapVecData_45_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_45 = _GEN_186[_remapVecValids_45_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_46 = _remap_idx_T + 8'h2E; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_232 = _remap_idx_T_46 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_46 = _GEN_232[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_46_T = remap_idx_46[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_46_T = remap_idx_46[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_46 = _GEN_185[_remapVecData_46_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_46 = _GEN_186[_remapVecValids_46_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_47 = _remap_idx_T + 8'h2F; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_233 = _remap_idx_T_47 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_47 = _GEN_233[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_47_T = remap_idx_47[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_47_T = remap_idx_47[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_47 = _GEN_185[_remapVecData_47_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_47 = _GEN_186[_remapVecValids_47_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_48 = _remap_idx_T + 8'h30; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_234 = _remap_idx_T_48 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_48 = _GEN_234[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_48_T = remap_idx_48[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_48_T = remap_idx_48[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_48 = _GEN_185[_remapVecData_48_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_48 = _GEN_186[_remapVecValids_48_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_49 = _remap_idx_T + 8'h31; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_235 = _remap_idx_T_49 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_49 = _GEN_235[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_49_T = remap_idx_49[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_49_T = remap_idx_49[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_49 = _GEN_185[_remapVecData_49_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_49 = _GEN_186[_remapVecValids_49_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_50 = _remap_idx_T + 8'h32; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_236 = _remap_idx_T_50 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_50 = _GEN_236[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_50_T = remap_idx_50[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_50_T = remap_idx_50[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_50 = _GEN_185[_remapVecData_50_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_50 = _GEN_186[_remapVecValids_50_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_51 = _remap_idx_T + 8'h33; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_237 = _remap_idx_T_51 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_51 = _GEN_237[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_51_T = remap_idx_51[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_51_T = remap_idx_51[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_51 = _GEN_185[_remapVecData_51_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_51 = _GEN_186[_remapVecValids_51_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_52 = _remap_idx_T + 8'h34; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_238 = _remap_idx_T_52 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_52 = _GEN_238[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_52_T = remap_idx_52[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_52_T = remap_idx_52[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_52 = _GEN_185[_remapVecData_52_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_52 = _GEN_186[_remapVecValids_52_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_53 = _remap_idx_T + 8'h35; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_239 = _remap_idx_T_53 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_53 = _GEN_239[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_53_T = remap_idx_53[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_53_T = remap_idx_53[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_53 = _GEN_185[_remapVecData_53_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_53 = _GEN_186[_remapVecValids_53_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_54 = _remap_idx_T + 8'h36; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_240 = _remap_idx_T_54 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_54 = _GEN_240[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_54_T = remap_idx_54[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_54_T = remap_idx_54[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_54 = _GEN_185[_remapVecData_54_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_54 = _GEN_186[_remapVecValids_54_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_55 = _remap_idx_T + 8'h37; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_241 = _remap_idx_T_55 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_55 = _GEN_241[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_55_T = remap_idx_55[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_55_T = remap_idx_55[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_55 = _GEN_185[_remapVecData_55_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_55 = _GEN_186[_remapVecValids_55_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_56 = _remap_idx_T + 8'h38; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_242 = _remap_idx_T_56 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_56 = _GEN_242[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_56_T = remap_idx_56[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_56_T = remap_idx_56[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_56 = _GEN_185[_remapVecData_56_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_56 = _GEN_186[_remapVecValids_56_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_57 = _remap_idx_T + 8'h39; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_243 = _remap_idx_T_57 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_57 = _GEN_243[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_57_T = remap_idx_57[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_57_T = remap_idx_57[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_57 = _GEN_185[_remapVecData_57_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_57 = _GEN_186[_remapVecValids_57_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_58 = _remap_idx_T + 8'h3A; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_244 = _remap_idx_T_58 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_58 = _GEN_244[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_58_T = remap_idx_58[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_58_T = remap_idx_58[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_58 = _GEN_185[_remapVecData_58_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_58 = _GEN_186[_remapVecValids_58_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_59 = _remap_idx_T + 8'h3B; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_245 = _remap_idx_T_59 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_59 = _GEN_245[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_59_T = remap_idx_59[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_59_T = remap_idx_59[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_59 = _GEN_185[_remapVecData_59_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_59 = _GEN_186[_remapVecValids_59_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_60 = _remap_idx_T + 8'h3C; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_246 = _remap_idx_T_60 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_60 = _GEN_246[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_60_T = remap_idx_60[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_60_T = remap_idx_60[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_60 = _GEN_185[_remapVecData_60_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_60 = _GEN_186[_remapVecValids_60_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_61 = _remap_idx_T + 8'h3D; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_247 = _remap_idx_T_61 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_61 = _GEN_247[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_61_T = remap_idx_61[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_61_T = remap_idx_61[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_61 = _GEN_185[_remapVecData_61_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_61 = _GEN_186[_remapVecValids_61_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_62 = _remap_idx_T + 8'h3E; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_248 = _remap_idx_T_62 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_62 = _GEN_248[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_62_T = remap_idx_62[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_62_T = remap_idx_62[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_62 = _GEN_185[_remapVecData_62_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_62 = _GEN_186[_remapVecValids_62_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_63 = _remap_idx_T + 8'h3F; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_249 = _remap_idx_T_63 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_63 = _GEN_249[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_63_T = remap_idx_63[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_63_T = remap_idx_63[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_63 = _GEN_185[_remapVecData_63_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_63 = _GEN_186[_remapVecValids_63_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] assign bufVecReadys_0 = remap_idx_63[5:0] == 6'h0 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h0 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h0 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h0 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h0 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h0 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h0 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h0 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h0 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h0 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h0 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h0 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h0 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h0 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h0 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h0 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h0 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h0 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h0 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h0 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h0 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h0 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h0 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h0 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h0 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h0 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h0 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h0 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h0 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h0 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h0 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h0 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h0 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h0 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h0 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h0 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h0 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h0 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h0 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h0 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h0 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h0 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h0 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h0 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h0 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h0 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h0 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h0 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h0 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h0 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h0 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h0 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h0 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h0 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h0 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h0 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h0 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h0 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h0 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h0 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h0 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h0 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h0 ? remapVecReadys_1 : remap_idx[5:0] == 6'h0 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_1 = remap_idx_63[5:0] == 6'h1 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1 ? remapVecReadys_1 : remap_idx[5:0] == 6'h1 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_2 = remap_idx_63[5:0] == 6'h2 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2 ? remapVecReadys_1 : remap_idx[5:0] == 6'h2 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_3 = remap_idx_63[5:0] == 6'h3 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3 ? remapVecReadys_1 : remap_idx[5:0] == 6'h3 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_4 = remap_idx_63[5:0] == 6'h4 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h4 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h4 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h4 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h4 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h4 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h4 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h4 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h4 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h4 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h4 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h4 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h4 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h4 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h4 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h4 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h4 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h4 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h4 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h4 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h4 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h4 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h4 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h4 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h4 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h4 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h4 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h4 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h4 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h4 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h4 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h4 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h4 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h4 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h4 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h4 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h4 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h4 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h4 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h4 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h4 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h4 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h4 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h4 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h4 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h4 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h4 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h4 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h4 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h4 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h4 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h4 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h4 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h4 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h4 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h4 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h4 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h4 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h4 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h4 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h4 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h4 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h4 ? remapVecReadys_1 : remap_idx[5:0] == 6'h4 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_5 = remap_idx_63[5:0] == 6'h5 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h5 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h5 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h5 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h5 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h5 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h5 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h5 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h5 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h5 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h5 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h5 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h5 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h5 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h5 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h5 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h5 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h5 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h5 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h5 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h5 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h5 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h5 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h5 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h5 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h5 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h5 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h5 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h5 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h5 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h5 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h5 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h5 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h5 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h5 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h5 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h5 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h5 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h5 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h5 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h5 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h5 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h5 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h5 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h5 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h5 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h5 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h5 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h5 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h5 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h5 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h5 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h5 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h5 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h5 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h5 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h5 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h5 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h5 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h5 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h5 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h5 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h5 ? remapVecReadys_1 : remap_idx[5:0] == 6'h5 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_6 = remap_idx_63[5:0] == 6'h6 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h6 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h6 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h6 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h6 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h6 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h6 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h6 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h6 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h6 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h6 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h6 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h6 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h6 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h6 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h6 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h6 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h6 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h6 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h6 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h6 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h6 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h6 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h6 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h6 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h6 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h6 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h6 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h6 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h6 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h6 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h6 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h6 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h6 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h6 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h6 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h6 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h6 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h6 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h6 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h6 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h6 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h6 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h6 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h6 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h6 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h6 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h6 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h6 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h6 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h6 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h6 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h6 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h6 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h6 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h6 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h6 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h6 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h6 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h6 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h6 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h6 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h6 ? remapVecReadys_1 : remap_idx[5:0] == 6'h6 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_7 = remap_idx_63[5:0] == 6'h7 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h7 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h7 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h7 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h7 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h7 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h7 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h7 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h7 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h7 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h7 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h7 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h7 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h7 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h7 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h7 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h7 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h7 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h7 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h7 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h7 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h7 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h7 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h7 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h7 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h7 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h7 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h7 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h7 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h7 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h7 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h7 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h7 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h7 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h7 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h7 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h7 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h7 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h7 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h7 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h7 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h7 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h7 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h7 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h7 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h7 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h7 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h7 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h7 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h7 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h7 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h7 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h7 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h7 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h7 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h7 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h7 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h7 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h7 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h7 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h7 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h7 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h7 ? remapVecReadys_1 : remap_idx[5:0] == 6'h7 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_8 = remap_idx_63[5:0] == 6'h8 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h8 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h8 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h8 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h8 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h8 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h8 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h8 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h8 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h8 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h8 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h8 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h8 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h8 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h8 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h8 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h8 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h8 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h8 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h8 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h8 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h8 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h8 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h8 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h8 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h8 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h8 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h8 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h8 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h8 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h8 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h8 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h8 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h8 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h8 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h8 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h8 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h8 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h8 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h8 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h8 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h8 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h8 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h8 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h8 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h8 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h8 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h8 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h8 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h8 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h8 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h8 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h8 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h8 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h8 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h8 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h8 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h8 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h8 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h8 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h8 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h8 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h8 ? remapVecReadys_1 : remap_idx[5:0] == 6'h8 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_9 = remap_idx_63[5:0] == 6'h9 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h9 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h9 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h9 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h9 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h9 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h9 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h9 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h9 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h9 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h9 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h9 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h9 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h9 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h9 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h9 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h9 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h9 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h9 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h9 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h9 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h9 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h9 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h9 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h9 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h9 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h9 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h9 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h9 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h9 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h9 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h9 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h9 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h9 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h9 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h9 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h9 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h9 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h9 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h9 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h9 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h9 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h9 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h9 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h9 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h9 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h9 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h9 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h9 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h9 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h9 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h9 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h9 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h9 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h9 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h9 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h9 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h9 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h9 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h9 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h9 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h9 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h9 ? remapVecReadys_1 : remap_idx[5:0] == 6'h9 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_10 = remap_idx_63[5:0] == 6'hA ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hA ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hA ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hA ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hA ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hA ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hA ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hA ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hA ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hA ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hA ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hA ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hA ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hA ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hA ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hA ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hA ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hA ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hA ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hA ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hA ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hA ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hA ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hA ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hA ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hA ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hA ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hA ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hA ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hA ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hA ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hA ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hA ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hA ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hA ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hA ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hA ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hA ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hA ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hA ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hA ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hA ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hA ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hA ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hA ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hA ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hA ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hA ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hA ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hA ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hA ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hA ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hA ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hA ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hA ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hA ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hA ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hA ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hA ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hA ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hA ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hA ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hA ? remapVecReadys_1 : remap_idx[5:0] == 6'hA & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_11 = remap_idx_63[5:0] == 6'hB ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hB ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hB ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hB ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hB ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hB ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hB ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hB ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hB ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hB ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hB ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hB ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hB ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hB ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hB ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hB ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hB ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hB ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hB ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hB ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hB ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hB ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hB ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hB ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hB ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hB ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hB ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hB ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hB ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hB ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hB ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hB ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hB ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hB ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hB ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hB ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hB ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hB ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hB ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hB ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hB ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hB ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hB ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hB ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hB ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hB ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hB ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hB ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hB ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hB ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hB ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hB ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hB ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hB ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hB ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hB ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hB ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hB ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hB ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hB ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hB ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hB ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hB ? remapVecReadys_1 : remap_idx[5:0] == 6'hB & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_12 = remap_idx_63[5:0] == 6'hC ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hC ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hC ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hC ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hC ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hC ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hC ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hC ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hC ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hC ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hC ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hC ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hC ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hC ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hC ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hC ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hC ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hC ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hC ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hC ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hC ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hC ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hC ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hC ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hC ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hC ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hC ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hC ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hC ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hC ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hC ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hC ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hC ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hC ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hC ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hC ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hC ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hC ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hC ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hC ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hC ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hC ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hC ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hC ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hC ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hC ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hC ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hC ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hC ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hC ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hC ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hC ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hC ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hC ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hC ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hC ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hC ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hC ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hC ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hC ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hC ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hC ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hC ? remapVecReadys_1 : remap_idx[5:0] == 6'hC & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_13 = remap_idx_63[5:0] == 6'hD ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hD ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hD ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hD ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hD ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hD ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hD ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hD ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hD ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hD ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hD ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hD ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hD ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hD ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hD ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hD ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hD ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hD ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hD ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hD ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hD ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hD ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hD ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hD ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hD ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hD ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hD ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hD ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hD ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hD ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hD ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hD ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hD ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hD ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hD ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hD ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hD ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hD ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hD ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hD ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hD ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hD ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hD ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hD ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hD ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hD ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hD ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hD ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hD ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hD ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hD ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hD ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hD ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hD ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hD ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hD ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hD ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hD ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hD ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hD ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hD ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hD ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hD ? remapVecReadys_1 : remap_idx[5:0] == 6'hD & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_14 = remap_idx_63[5:0] == 6'hE ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hE ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hE ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hE ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hE ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hE ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hE ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hE ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hE ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hE ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hE ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hE ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hE ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hE ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hE ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hE ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hE ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hE ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hE ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hE ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hE ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hE ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hE ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hE ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hE ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hE ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hE ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hE ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hE ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hE ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hE ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hE ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hE ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hE ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hE ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hE ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hE ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hE ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hE ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hE ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hE ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hE ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hE ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hE ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hE ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hE ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hE ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hE ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hE ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hE ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hE ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hE ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hE ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hE ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hE ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hE ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hE ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hE ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hE ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hE ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hE ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hE ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hE ? remapVecReadys_1 : remap_idx[5:0] == 6'hE & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_15 = remap_idx_63[5:0] == 6'hF ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hF ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hF ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hF ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hF ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hF ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hF ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hF ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hF ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hF ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hF ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hF ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hF ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hF ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hF ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hF ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hF ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hF ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hF ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hF ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hF ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hF ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hF ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hF ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hF ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hF ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hF ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hF ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hF ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hF ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hF ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hF ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hF ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hF ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hF ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hF ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hF ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hF ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hF ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hF ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hF ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hF ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hF ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hF ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hF ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hF ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hF ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hF ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hF ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hF ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hF ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hF ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hF ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hF ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hF ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hF ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hF ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hF ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hF ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hF ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hF ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hF ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hF ? remapVecReadys_1 : remap_idx[5:0] == 6'hF & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_16 = remap_idx_63[5:0] == 6'h10 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h10 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h10 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h10 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h10 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h10 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h10 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h10 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h10 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h10 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h10 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h10 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h10 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h10 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h10 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h10 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h10 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h10 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h10 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h10 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h10 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h10 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h10 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h10 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h10 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h10 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h10 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h10 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h10 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h10 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h10 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h10 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h10 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h10 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h10 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h10 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h10 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h10 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h10 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h10 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h10 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h10 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h10 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h10 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h10 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h10 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h10 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h10 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h10 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h10 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h10 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h10 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h10 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h10 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h10 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h10 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h10 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h10 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h10 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h10 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h10 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h10 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h10 ? remapVecReadys_1 : remap_idx[5:0] == 6'h10 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_17 = remap_idx_63[5:0] == 6'h11 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h11 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h11 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h11 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h11 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h11 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h11 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h11 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h11 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h11 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h11 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h11 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h11 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h11 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h11 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h11 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h11 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h11 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h11 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h11 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h11 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h11 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h11 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h11 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h11 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h11 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h11 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h11 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h11 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h11 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h11 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h11 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h11 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h11 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h11 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h11 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h11 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h11 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h11 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h11 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h11 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h11 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h11 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h11 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h11 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h11 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h11 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h11 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h11 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h11 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h11 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h11 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h11 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h11 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h11 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h11 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h11 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h11 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h11 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h11 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h11 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h11 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h11 ? remapVecReadys_1 : remap_idx[5:0] == 6'h11 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_18 = remap_idx_63[5:0] == 6'h12 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h12 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h12 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h12 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h12 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h12 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h12 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h12 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h12 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h12 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h12 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h12 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h12 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h12 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h12 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h12 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h12 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h12 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h12 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h12 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h12 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h12 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h12 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h12 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h12 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h12 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h12 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h12 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h12 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h12 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h12 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h12 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h12 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h12 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h12 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h12 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h12 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h12 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h12 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h12 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h12 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h12 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h12 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h12 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h12 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h12 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h12 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h12 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h12 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h12 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h12 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h12 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h12 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h12 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h12 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h12 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h12 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h12 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h12 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h12 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h12 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h12 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h12 ? remapVecReadys_1 : remap_idx[5:0] == 6'h12 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_19 = remap_idx_63[5:0] == 6'h13 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h13 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h13 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h13 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h13 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h13 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h13 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h13 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h13 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h13 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h13 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h13 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h13 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h13 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h13 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h13 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h13 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h13 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h13 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h13 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h13 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h13 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h13 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h13 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h13 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h13 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h13 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h13 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h13 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h13 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h13 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h13 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h13 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h13 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h13 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h13 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h13 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h13 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h13 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h13 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h13 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h13 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h13 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h13 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h13 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h13 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h13 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h13 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h13 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h13 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h13 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h13 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h13 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h13 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h13 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h13 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h13 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h13 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h13 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h13 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h13 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h13 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h13 ? remapVecReadys_1 : remap_idx[5:0] == 6'h13 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_20 = remap_idx_63[5:0] == 6'h14 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h14 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h14 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h14 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h14 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h14 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h14 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h14 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h14 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h14 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h14 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h14 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h14 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h14 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h14 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h14 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h14 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h14 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h14 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h14 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h14 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h14 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h14 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h14 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h14 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h14 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h14 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h14 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h14 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h14 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h14 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h14 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h14 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h14 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h14 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h14 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h14 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h14 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h14 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h14 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h14 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h14 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h14 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h14 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h14 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h14 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h14 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h14 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h14 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h14 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h14 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h14 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h14 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h14 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h14 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h14 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h14 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h14 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h14 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h14 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h14 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h14 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h14 ? remapVecReadys_1 : remap_idx[5:0] == 6'h14 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_21 = remap_idx_63[5:0] == 6'h15 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h15 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h15 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h15 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h15 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h15 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h15 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h15 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h15 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h15 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h15 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h15 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h15 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h15 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h15 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h15 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h15 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h15 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h15 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h15 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h15 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h15 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h15 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h15 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h15 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h15 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h15 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h15 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h15 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h15 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h15 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h15 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h15 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h15 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h15 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h15 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h15 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h15 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h15 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h15 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h15 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h15 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h15 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h15 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h15 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h15 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h15 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h15 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h15 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h15 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h15 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h15 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h15 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h15 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h15 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h15 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h15 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h15 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h15 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h15 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h15 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h15 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h15 ? remapVecReadys_1 : remap_idx[5:0] == 6'h15 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_22 = remap_idx_63[5:0] == 6'h16 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h16 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h16 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h16 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h16 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h16 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h16 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h16 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h16 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h16 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h16 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h16 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h16 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h16 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h16 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h16 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h16 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h16 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h16 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h16 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h16 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h16 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h16 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h16 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h16 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h16 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h16 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h16 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h16 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h16 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h16 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h16 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h16 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h16 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h16 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h16 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h16 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h16 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h16 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h16 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h16 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h16 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h16 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h16 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h16 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h16 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h16 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h16 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h16 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h16 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h16 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h16 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h16 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h16 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h16 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h16 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h16 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h16 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h16 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h16 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h16 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h16 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h16 ? remapVecReadys_1 : remap_idx[5:0] == 6'h16 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_23 = remap_idx_63[5:0] == 6'h17 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h17 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h17 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h17 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h17 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h17 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h17 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h17 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h17 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h17 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h17 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h17 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h17 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h17 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h17 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h17 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h17 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h17 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h17 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h17 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h17 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h17 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h17 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h17 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h17 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h17 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h17 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h17 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h17 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h17 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h17 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h17 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h17 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h17 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h17 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h17 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h17 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h17 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h17 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h17 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h17 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h17 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h17 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h17 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h17 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h17 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h17 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h17 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h17 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h17 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h17 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h17 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h17 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h17 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h17 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h17 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h17 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h17 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h17 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h17 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h17 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h17 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h17 ? remapVecReadys_1 : remap_idx[5:0] == 6'h17 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_24 = remap_idx_63[5:0] == 6'h18 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h18 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h18 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h18 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h18 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h18 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h18 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h18 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h18 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h18 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h18 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h18 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h18 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h18 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h18 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h18 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h18 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h18 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h18 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h18 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h18 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h18 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h18 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h18 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h18 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h18 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h18 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h18 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h18 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h18 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h18 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h18 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h18 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h18 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h18 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h18 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h18 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h18 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h18 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h18 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h18 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h18 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h18 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h18 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h18 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h18 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h18 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h18 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h18 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h18 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h18 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h18 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h18 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h18 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h18 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h18 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h18 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h18 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h18 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h18 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h18 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h18 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h18 ? remapVecReadys_1 : remap_idx[5:0] == 6'h18 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_25 = remap_idx_63[5:0] == 6'h19 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h19 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h19 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h19 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h19 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h19 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h19 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h19 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h19 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h19 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h19 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h19 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h19 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h19 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h19 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h19 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h19 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h19 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h19 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h19 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h19 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h19 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h19 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h19 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h19 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h19 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h19 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h19 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h19 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h19 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h19 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h19 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h19 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h19 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h19 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h19 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h19 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h19 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h19 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h19 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h19 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h19 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h19 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h19 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h19 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h19 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h19 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h19 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h19 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h19 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h19 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h19 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h19 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h19 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h19 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h19 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h19 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h19 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h19 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h19 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h19 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h19 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h19 ? remapVecReadys_1 : remap_idx[5:0] == 6'h19 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_26 = remap_idx_63[5:0] == 6'h1A ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1A ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1A ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1A ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1A ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1A ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1A ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1A ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1A ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1A ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1A ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1A ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1A ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1A ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1A ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1A ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1A ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1A ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1A ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1A ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1A ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1A ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1A ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1A ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1A ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1A ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1A ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1A ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1A ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1A ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1A ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1A ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1A ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1A ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1A ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1A ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1A ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1A ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1A ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1A ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1A ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1A ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1A ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1A ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1A ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1A ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1A ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1A ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1A ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1A ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1A ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1A ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1A ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1A ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1A ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1A ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1A ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1A ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1A ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1A ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1A ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1A ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1A ? remapVecReadys_1 : remap_idx[5:0] == 6'h1A & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_27 = remap_idx_63[5:0] == 6'h1B ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1B ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1B ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1B ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1B ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1B ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1B ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1B ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1B ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1B ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1B ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1B ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1B ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1B ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1B ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1B ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1B ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1B ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1B ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1B ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1B ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1B ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1B ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1B ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1B ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1B ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1B ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1B ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1B ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1B ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1B ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1B ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1B ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1B ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1B ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1B ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1B ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1B ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1B ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1B ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1B ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1B ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1B ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1B ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1B ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1B ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1B ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1B ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1B ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1B ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1B ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1B ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1B ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1B ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1B ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1B ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1B ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1B ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1B ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1B ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1B ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1B ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1B ? remapVecReadys_1 : remap_idx[5:0] == 6'h1B & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_28 = remap_idx_63[5:0] == 6'h1C ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1C ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1C ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1C ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1C ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1C ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1C ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1C ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1C ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1C ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1C ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1C ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1C ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1C ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1C ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1C ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1C ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1C ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1C ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1C ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1C ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1C ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1C ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1C ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1C ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1C ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1C ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1C ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1C ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1C ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1C ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1C ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1C ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1C ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1C ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1C ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1C ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1C ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1C ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1C ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1C ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1C ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1C ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1C ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1C ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1C ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1C ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1C ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1C ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1C ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1C ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1C ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1C ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1C ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1C ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1C ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1C ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1C ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1C ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1C ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1C ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1C ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1C ? remapVecReadys_1 : remap_idx[5:0] == 6'h1C & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_29 = remap_idx_63[5:0] == 6'h1D ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1D ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1D ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1D ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1D ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1D ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1D ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1D ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1D ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1D ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1D ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1D ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1D ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1D ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1D ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1D ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1D ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1D ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1D ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1D ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1D ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1D ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1D ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1D ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1D ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1D ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1D ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1D ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1D ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1D ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1D ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1D ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1D ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1D ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1D ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1D ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1D ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1D ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1D ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1D ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1D ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1D ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1D ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1D ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1D ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1D ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1D ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1D ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1D ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1D ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1D ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1D ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1D ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1D ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1D ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1D ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1D ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1D ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1D ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1D ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1D ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1D ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1D ? remapVecReadys_1 : remap_idx[5:0] == 6'h1D & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_30 = remap_idx_63[5:0] == 6'h1E ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1E ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1E ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1E ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1E ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1E ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1E ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1E ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1E ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1E ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1E ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1E ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1E ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1E ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1E ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1E ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1E ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1E ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1E ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1E ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1E ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1E ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1E ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1E ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1E ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1E ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1E ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1E ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1E ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1E ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1E ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1E ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1E ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1E ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1E ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1E ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1E ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1E ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1E ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1E ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1E ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1E ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1E ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1E ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1E ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1E ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1E ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1E ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1E ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1E ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1E ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1E ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1E ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1E ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1E ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1E ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1E ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1E ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1E ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1E ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1E ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1E ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1E ? remapVecReadys_1 : remap_idx[5:0] == 6'h1E & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_31 = remap_idx_63[5:0] == 6'h1F ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1F ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1F ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1F ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1F ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1F ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1F ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1F ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1F ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1F ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1F ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1F ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1F ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1F ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1F ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1F ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1F ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1F ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1F ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1F ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1F ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1F ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1F ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1F ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1F ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1F ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1F ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1F ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1F ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1F ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1F ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1F ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1F ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1F ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1F ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1F ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1F ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1F ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1F ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1F ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1F ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1F ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1F ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1F ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1F ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1F ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1F ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1F ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1F ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1F ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1F ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1F ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1F ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1F ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1F ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1F ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1F ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1F ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1F ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1F ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1F ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1F ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1F ? remapVecReadys_1 : remap_idx[5:0] == 6'h1F & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_32 = remap_idx_63[5:0] == 6'h20 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h20 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h20 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h20 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h20 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h20 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h20 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h20 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h20 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h20 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h20 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h20 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h20 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h20 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h20 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h20 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h20 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h20 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h20 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h20 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h20 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h20 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h20 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h20 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h20 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h20 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h20 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h20 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h20 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h20 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h20 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h20 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h20 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h20 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h20 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h20 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h20 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h20 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h20 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h20 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h20 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h20 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h20 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h20 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h20 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h20 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h20 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h20 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h20 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h20 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h20 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h20 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h20 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h20 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h20 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h20 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h20 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h20 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h20 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h20 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h20 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h20 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h20 ? remapVecReadys_1 : remap_idx[5:0] == 6'h20 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_33 = remap_idx_63[5:0] == 6'h21 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h21 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h21 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h21 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h21 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h21 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h21 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h21 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h21 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h21 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h21 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h21 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h21 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h21 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h21 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h21 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h21 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h21 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h21 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h21 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h21 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h21 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h21 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h21 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h21 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h21 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h21 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h21 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h21 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h21 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h21 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h21 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h21 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h21 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h21 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h21 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h21 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h21 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h21 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h21 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h21 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h21 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h21 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h21 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h21 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h21 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h21 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h21 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h21 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h21 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h21 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h21 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h21 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h21 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h21 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h21 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h21 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h21 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h21 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h21 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h21 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h21 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h21 ? remapVecReadys_1 : remap_idx[5:0] == 6'h21 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_34 = remap_idx_63[5:0] == 6'h22 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h22 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h22 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h22 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h22 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h22 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h22 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h22 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h22 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h22 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h22 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h22 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h22 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h22 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h22 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h22 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h22 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h22 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h22 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h22 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h22 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h22 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h22 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h22 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h22 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h22 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h22 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h22 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h22 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h22 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h22 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h22 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h22 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h22 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h22 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h22 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h22 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h22 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h22 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h22 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h22 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h22 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h22 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h22 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h22 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h22 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h22 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h22 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h22 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h22 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h22 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h22 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h22 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h22 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h22 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h22 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h22 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h22 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h22 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h22 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h22 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h22 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h22 ? remapVecReadys_1 : remap_idx[5:0] == 6'h22 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_35 = remap_idx_63[5:0] == 6'h23 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h23 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h23 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h23 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h23 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h23 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h23 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h23 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h23 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h23 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h23 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h23 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h23 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h23 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h23 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h23 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h23 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h23 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h23 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h23 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h23 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h23 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h23 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h23 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h23 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h23 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h23 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h23 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h23 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h23 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h23 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h23 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h23 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h23 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h23 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h23 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h23 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h23 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h23 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h23 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h23 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h23 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h23 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h23 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h23 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h23 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h23 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h23 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h23 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h23 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h23 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h23 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h23 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h23 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h23 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h23 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h23 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h23 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h23 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h23 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h23 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h23 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h23 ? remapVecReadys_1 : remap_idx[5:0] == 6'h23 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_36 = remap_idx_63[5:0] == 6'h24 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h24 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h24 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h24 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h24 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h24 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h24 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h24 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h24 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h24 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h24 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h24 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h24 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h24 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h24 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h24 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h24 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h24 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h24 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h24 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h24 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h24 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h24 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h24 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h24 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h24 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h24 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h24 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h24 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h24 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h24 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h24 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h24 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h24 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h24 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h24 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h24 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h24 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h24 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h24 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h24 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h24 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h24 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h24 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h24 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h24 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h24 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h24 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h24 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h24 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h24 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h24 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h24 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h24 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h24 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h24 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h24 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h24 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h24 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h24 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h24 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h24 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h24 ? remapVecReadys_1 : remap_idx[5:0] == 6'h24 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_37 = remap_idx_63[5:0] == 6'h25 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h25 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h25 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h25 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h25 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h25 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h25 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h25 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h25 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h25 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h25 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h25 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h25 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h25 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h25 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h25 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h25 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h25 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h25 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h25 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h25 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h25 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h25 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h25 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h25 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h25 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h25 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h25 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h25 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h25 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h25 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h25 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h25 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h25 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h25 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h25 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h25 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h25 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h25 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h25 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h25 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h25 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h25 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h25 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h25 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h25 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h25 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h25 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h25 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h25 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h25 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h25 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h25 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h25 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h25 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h25 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h25 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h25 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h25 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h25 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h25 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h25 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h25 ? remapVecReadys_1 : remap_idx[5:0] == 6'h25 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_38 = remap_idx_63[5:0] == 6'h26 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h26 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h26 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h26 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h26 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h26 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h26 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h26 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h26 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h26 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h26 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h26 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h26 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h26 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h26 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h26 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h26 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h26 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h26 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h26 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h26 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h26 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h26 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h26 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h26 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h26 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h26 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h26 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h26 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h26 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h26 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h26 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h26 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h26 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h26 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h26 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h26 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h26 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h26 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h26 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h26 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h26 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h26 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h26 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h26 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h26 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h26 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h26 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h26 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h26 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h26 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h26 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h26 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h26 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h26 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h26 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h26 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h26 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h26 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h26 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h26 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h26 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h26 ? remapVecReadys_1 : remap_idx[5:0] == 6'h26 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_39 = remap_idx_63[5:0] == 6'h27 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h27 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h27 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h27 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h27 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h27 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h27 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h27 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h27 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h27 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h27 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h27 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h27 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h27 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h27 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h27 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h27 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h27 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h27 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h27 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h27 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h27 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h27 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h27 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h27 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h27 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h27 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h27 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h27 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h27 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h27 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h27 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h27 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h27 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h27 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h27 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h27 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h27 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h27 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h27 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h27 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h27 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h27 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h27 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h27 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h27 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h27 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h27 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h27 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h27 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h27 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h27 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h27 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h27 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h27 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h27 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h27 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h27 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h27 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h27 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h27 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h27 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h27 ? remapVecReadys_1 : remap_idx[5:0] == 6'h27 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_40 = remap_idx_63[5:0] == 6'h28 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h28 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h28 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h28 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h28 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h28 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h28 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h28 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h28 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h28 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h28 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h28 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h28 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h28 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h28 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h28 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h28 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h28 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h28 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h28 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h28 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h28 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h28 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h28 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h28 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h28 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h28 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h28 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h28 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h28 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h28 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h28 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h28 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h28 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h28 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h28 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h28 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h28 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h28 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h28 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h28 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h28 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h28 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h28 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h28 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h28 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h28 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h28 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h28 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h28 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h28 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h28 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h28 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h28 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h28 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h28 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h28 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h28 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h28 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h28 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h28 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h28 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h28 ? remapVecReadys_1 : remap_idx[5:0] == 6'h28 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_41 = remap_idx_63[5:0] == 6'h29 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h29 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h29 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h29 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h29 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h29 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h29 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h29 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h29 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h29 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h29 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h29 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h29 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h29 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h29 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h29 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h29 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h29 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h29 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h29 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h29 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h29 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h29 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h29 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h29 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h29 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h29 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h29 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h29 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h29 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h29 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h29 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h29 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h29 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h29 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h29 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h29 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h29 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h29 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h29 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h29 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h29 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h29 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h29 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h29 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h29 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h29 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h29 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h29 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h29 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h29 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h29 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h29 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h29 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h29 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h29 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h29 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h29 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h29 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h29 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h29 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h29 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h29 ? remapVecReadys_1 : remap_idx[5:0] == 6'h29 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_42 = remap_idx_63[5:0] == 6'h2A ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2A ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2A ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2A ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2A ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2A ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2A ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2A ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2A ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2A ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2A ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2A ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2A ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2A ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2A ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2A ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2A ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2A ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2A ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2A ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2A ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2A ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2A ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2A ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2A ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2A ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2A ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2A ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2A ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2A ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2A ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2A ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2A ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2A ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2A ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2A ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2A ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2A ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2A ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2A ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2A ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2A ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2A ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2A ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2A ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2A ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2A ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2A ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2A ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2A ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2A ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2A ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2A ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2A ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2A ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2A ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2A ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2A ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2A ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2A ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2A ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2A ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2A ? remapVecReadys_1 : remap_idx[5:0] == 6'h2A & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_43 = remap_idx_63[5:0] == 6'h2B ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2B ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2B ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2B ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2B ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2B ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2B ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2B ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2B ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2B ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2B ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2B ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2B ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2B ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2B ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2B ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2B ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2B ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2B ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2B ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2B ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2B ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2B ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2B ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2B ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2B ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2B ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2B ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2B ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2B ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2B ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2B ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2B ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2B ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2B ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2B ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2B ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2B ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2B ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2B ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2B ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2B ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2B ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2B ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2B ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2B ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2B ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2B ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2B ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2B ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2B ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2B ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2B ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2B ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2B ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2B ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2B ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2B ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2B ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2B ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2B ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2B ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2B ? remapVecReadys_1 : remap_idx[5:0] == 6'h2B & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_44 = remap_idx_63[5:0] == 6'h2C ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2C ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2C ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2C ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2C ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2C ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2C ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2C ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2C ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2C ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2C ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2C ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2C ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2C ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2C ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2C ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2C ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2C ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2C ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2C ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2C ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2C ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2C ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2C ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2C ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2C ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2C ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2C ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2C ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2C ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2C ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2C ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2C ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2C ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2C ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2C ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2C ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2C ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2C ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2C ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2C ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2C ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2C ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2C ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2C ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2C ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2C ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2C ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2C ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2C ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2C ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2C ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2C ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2C ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2C ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2C ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2C ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2C ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2C ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2C ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2C ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2C ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2C ? remapVecReadys_1 : remap_idx[5:0] == 6'h2C & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_45 = remap_idx_63[5:0] == 6'h2D ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2D ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2D ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2D ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2D ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2D ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2D ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2D ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2D ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2D ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2D ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2D ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2D ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2D ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2D ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2D ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2D ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2D ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2D ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2D ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2D ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2D ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2D ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2D ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2D ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2D ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2D ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2D ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2D ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2D ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2D ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2D ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2D ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2D ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2D ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2D ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2D ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2D ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2D ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2D ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2D ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2D ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2D ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2D ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2D ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2D ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2D ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2D ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2D ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2D ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2D ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2D ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2D ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2D ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2D ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2D ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2D ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2D ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2D ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2D ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2D ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2D ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2D ? remapVecReadys_1 : remap_idx[5:0] == 6'h2D & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_46 = remap_idx_63[5:0] == 6'h2E ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2E ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2E ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2E ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2E ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2E ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2E ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2E ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2E ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2E ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2E ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2E ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2E ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2E ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2E ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2E ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2E ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2E ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2E ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2E ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2E ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2E ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2E ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2E ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2E ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2E ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2E ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2E ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2E ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2E ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2E ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2E ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2E ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2E ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2E ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2E ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2E ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2E ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2E ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2E ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2E ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2E ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2E ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2E ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2E ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2E ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2E ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2E ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2E ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2E ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2E ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2E ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2E ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2E ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2E ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2E ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2E ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2E ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2E ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2E ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2E ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2E ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2E ? remapVecReadys_1 : remap_idx[5:0] == 6'h2E & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_47 = remap_idx_63[5:0] == 6'h2F ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2F ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2F ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2F ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2F ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2F ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2F ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2F ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2F ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2F ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2F ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2F ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2F ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2F ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2F ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2F ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2F ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2F ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2F ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2F ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2F ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2F ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2F ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2F ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2F ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2F ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2F ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2F ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2F ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2F ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2F ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2F ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2F ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2F ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2F ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2F ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2F ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2F ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2F ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2F ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2F ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2F ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2F ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2F ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2F ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2F ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2F ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2F ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2F ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2F ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2F ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2F ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2F ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2F ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2F ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2F ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2F ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2F ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2F ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2F ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2F ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2F ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2F ? remapVecReadys_1 : remap_idx[5:0] == 6'h2F & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_48 = remap_idx_63[5:0] == 6'h30 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h30 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h30 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h30 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h30 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h30 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h30 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h30 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h30 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h30 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h30 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h30 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h30 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h30 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h30 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h30 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h30 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h30 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h30 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h30 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h30 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h30 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h30 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h30 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h30 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h30 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h30 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h30 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h30 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h30 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h30 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h30 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h30 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h30 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h30 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h30 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h30 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h30 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h30 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h30 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h30 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h30 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h30 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h30 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h30 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h30 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h30 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h30 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h30 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h30 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h30 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h30 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h30 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h30 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h30 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h30 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h30 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h30 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h30 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h30 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h30 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h30 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h30 ? remapVecReadys_1 : remap_idx[5:0] == 6'h30 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_49 = remap_idx_63[5:0] == 6'h31 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h31 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h31 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h31 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h31 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h31 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h31 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h31 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h31 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h31 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h31 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h31 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h31 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h31 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h31 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h31 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h31 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h31 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h31 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h31 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h31 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h31 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h31 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h31 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h31 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h31 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h31 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h31 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h31 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h31 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h31 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h31 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h31 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h31 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h31 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h31 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h31 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h31 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h31 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h31 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h31 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h31 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h31 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h31 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h31 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h31 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h31 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h31 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h31 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h31 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h31 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h31 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h31 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h31 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h31 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h31 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h31 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h31 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h31 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h31 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h31 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h31 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h31 ? remapVecReadys_1 : remap_idx[5:0] == 6'h31 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_50 = remap_idx_63[5:0] == 6'h32 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h32 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h32 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h32 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h32 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h32 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h32 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h32 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h32 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h32 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h32 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h32 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h32 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h32 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h32 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h32 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h32 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h32 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h32 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h32 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h32 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h32 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h32 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h32 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h32 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h32 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h32 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h32 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h32 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h32 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h32 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h32 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h32 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h32 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h32 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h32 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h32 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h32 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h32 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h32 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h32 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h32 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h32 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h32 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h32 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h32 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h32 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h32 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h32 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h32 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h32 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h32 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h32 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h32 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h32 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h32 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h32 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h32 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h32 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h32 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h32 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h32 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h32 ? remapVecReadys_1 : remap_idx[5:0] == 6'h32 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_51 = remap_idx_63[5:0] == 6'h33 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h33 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h33 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h33 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h33 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h33 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h33 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h33 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h33 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h33 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h33 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h33 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h33 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h33 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h33 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h33 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h33 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h33 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h33 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h33 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h33 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h33 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h33 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h33 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h33 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h33 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h33 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h33 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h33 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h33 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h33 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h33 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h33 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h33 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h33 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h33 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h33 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h33 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h33 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h33 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h33 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h33 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h33 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h33 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h33 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h33 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h33 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h33 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h33 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h33 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h33 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h33 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h33 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h33 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h33 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h33 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h33 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h33 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h33 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h33 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h33 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h33 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h33 ? remapVecReadys_1 : remap_idx[5:0] == 6'h33 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_52 = remap_idx_63[5:0] == 6'h34 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h34 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h34 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h34 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h34 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h34 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h34 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h34 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h34 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h34 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h34 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h34 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h34 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h34 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h34 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h34 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h34 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h34 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h34 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h34 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h34 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h34 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h34 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h34 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h34 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h34 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h34 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h34 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h34 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h34 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h34 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h34 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h34 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h34 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h34 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h34 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h34 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h34 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h34 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h34 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h34 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h34 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h34 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h34 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h34 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h34 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h34 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h34 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h34 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h34 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h34 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h34 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h34 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h34 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h34 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h34 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h34 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h34 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h34 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h34 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h34 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h34 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h34 ? remapVecReadys_1 : remap_idx[5:0] == 6'h34 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_53 = remap_idx_63[5:0] == 6'h35 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h35 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h35 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h35 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h35 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h35 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h35 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h35 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h35 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h35 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h35 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h35 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h35 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h35 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h35 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h35 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h35 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h35 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h35 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h35 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h35 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h35 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h35 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h35 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h35 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h35 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h35 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h35 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h35 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h35 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h35 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h35 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h35 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h35 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h35 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h35 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h35 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h35 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h35 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h35 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h35 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h35 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h35 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h35 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h35 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h35 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h35 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h35 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h35 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h35 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h35 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h35 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h35 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h35 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h35 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h35 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h35 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h35 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h35 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h35 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h35 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h35 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h35 ? remapVecReadys_1 : remap_idx[5:0] == 6'h35 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_54 = remap_idx_63[5:0] == 6'h36 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h36 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h36 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h36 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h36 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h36 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h36 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h36 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h36 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h36 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h36 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h36 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h36 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h36 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h36 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h36 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h36 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h36 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h36 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h36 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h36 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h36 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h36 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h36 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h36 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h36 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h36 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h36 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h36 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h36 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h36 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h36 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h36 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h36 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h36 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h36 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h36 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h36 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h36 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h36 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h36 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h36 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h36 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h36 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h36 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h36 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h36 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h36 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h36 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h36 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h36 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h36 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h36 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h36 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h36 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h36 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h36 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h36 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h36 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h36 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h36 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h36 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h36 ? remapVecReadys_1 : remap_idx[5:0] == 6'h36 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_55 = remap_idx_63[5:0] == 6'h37 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h37 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h37 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h37 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h37 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h37 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h37 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h37 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h37 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h37 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h37 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h37 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h37 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h37 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h37 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h37 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h37 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h37 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h37 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h37 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h37 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h37 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h37 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h37 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h37 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h37 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h37 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h37 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h37 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h37 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h37 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h37 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h37 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h37 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h37 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h37 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h37 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h37 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h37 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h37 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h37 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h37 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h37 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h37 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h37 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h37 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h37 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h37 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h37 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h37 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h37 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h37 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h37 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h37 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h37 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h37 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h37 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h37 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h37 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h37 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h37 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h37 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h37 ? remapVecReadys_1 : remap_idx[5:0] == 6'h37 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_56 = remap_idx_63[5:0] == 6'h38 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h38 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h38 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h38 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h38 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h38 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h38 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h38 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h38 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h38 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h38 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h38 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h38 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h38 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h38 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h38 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h38 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h38 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h38 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h38 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h38 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h38 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h38 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h38 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h38 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h38 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h38 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h38 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h38 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h38 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h38 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h38 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h38 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h38 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h38 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h38 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h38 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h38 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h38 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h38 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h38 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h38 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h38 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h38 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h38 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h38 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h38 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h38 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h38 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h38 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h38 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h38 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h38 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h38 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h38 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h38 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h38 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h38 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h38 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h38 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h38 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h38 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h38 ? remapVecReadys_1 : remap_idx[5:0] == 6'h38 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_57 = remap_idx_63[5:0] == 6'h39 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h39 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h39 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h39 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h39 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h39 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h39 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h39 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h39 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h39 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h39 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h39 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h39 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h39 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h39 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h39 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h39 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h39 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h39 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h39 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h39 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h39 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h39 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h39 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h39 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h39 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h39 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h39 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h39 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h39 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h39 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h39 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h39 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h39 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h39 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h39 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h39 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h39 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h39 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h39 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h39 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h39 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h39 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h39 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h39 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h39 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h39 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h39 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h39 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h39 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h39 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h39 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h39 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h39 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h39 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h39 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h39 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h39 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h39 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h39 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h39 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h39 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h39 ? remapVecReadys_1 : remap_idx[5:0] == 6'h39 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_58 = remap_idx_63[5:0] == 6'h3A ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3A ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3A ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3A ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3A ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3A ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3A ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3A ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3A ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3A ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3A ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3A ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3A ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3A ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3A ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3A ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3A ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3A ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3A ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3A ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3A ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3A ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3A ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3A ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3A ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3A ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3A ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3A ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3A ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3A ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3A ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3A ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3A ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3A ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3A ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3A ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3A ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3A ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3A ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3A ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3A ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3A ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3A ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3A ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3A ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3A ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3A ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3A ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3A ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3A ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3A ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3A ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3A ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3A ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3A ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3A ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3A ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3A ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3A ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3A ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3A ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3A ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3A ? remapVecReadys_1 : remap_idx[5:0] == 6'h3A & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_59 = remap_idx_63[5:0] == 6'h3B ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3B ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3B ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3B ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3B ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3B ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3B ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3B ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3B ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3B ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3B ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3B ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3B ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3B ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3B ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3B ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3B ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3B ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3B ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3B ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3B ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3B ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3B ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3B ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3B ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3B ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3B ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3B ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3B ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3B ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3B ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3B ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3B ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3B ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3B ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3B ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3B ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3B ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3B ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3B ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3B ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3B ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3B ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3B ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3B ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3B ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3B ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3B ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3B ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3B ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3B ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3B ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3B ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3B ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3B ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3B ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3B ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3B ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3B ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3B ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3B ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3B ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3B ? remapVecReadys_1 : remap_idx[5:0] == 6'h3B & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_60 = remap_idx_63[5:0] == 6'h3C ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3C ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3C ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3C ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3C ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3C ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3C ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3C ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3C ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3C ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3C ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3C ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3C ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3C ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3C ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3C ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3C ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3C ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3C ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3C ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3C ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3C ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3C ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3C ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3C ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3C ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3C ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3C ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3C ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3C ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3C ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3C ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3C ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3C ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3C ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3C ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3C ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3C ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3C ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3C ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3C ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3C ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3C ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3C ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3C ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3C ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3C ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3C ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3C ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3C ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3C ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3C ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3C ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3C ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3C ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3C ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3C ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3C ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3C ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3C ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3C ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3C ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3C ? remapVecReadys_1 : remap_idx[5:0] == 6'h3C & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_61 = remap_idx_63[5:0] == 6'h3D ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3D ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3D ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3D ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3D ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3D ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3D ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3D ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3D ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3D ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3D ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3D ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3D ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3D ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3D ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3D ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3D ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3D ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3D ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3D ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3D ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3D ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3D ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3D ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3D ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3D ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3D ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3D ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3D ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3D ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3D ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3D ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3D ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3D ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3D ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3D ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3D ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3D ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3D ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3D ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3D ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3D ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3D ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3D ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3D ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3D ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3D ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3D ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3D ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3D ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3D ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3D ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3D ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3D ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3D ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3D ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3D ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3D ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3D ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3D ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3D ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3D ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3D ? remapVecReadys_1 : remap_idx[5:0] == 6'h3D & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_62 = remap_idx_63[5:0] == 6'h3E ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3E ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3E ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3E ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3E ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3E ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3E ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3E ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3E ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3E ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3E ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3E ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3E ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3E ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3E ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3E ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3E ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3E ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3E ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3E ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3E ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3E ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3E ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3E ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3E ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3E ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3E ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3E ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3E ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3E ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3E ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3E ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3E ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3E ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3E ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3E ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3E ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3E ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3E ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3E ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3E ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3E ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3E ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3E ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3E ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3E ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3E ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3E ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3E ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3E ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3E ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3E ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3E ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3E ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3E ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3E ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3E ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3E ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3E ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3E ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3E ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3E ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3E ? remapVecReadys_1 : remap_idx[5:0] == 6'h3E & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_63 = (&(remap_idx_63[5:0])) ? remapVecReadys_63 : (&(remap_idx_62[5:0])) ? remapVecReadys_62 : (&(remap_idx_61[5:0])) ? remapVecReadys_61 : (&(remap_idx_60[5:0])) ? remapVecReadys_60 : (&(remap_idx_59[5:0])) ? remapVecReadys_59 : (&(remap_idx_58[5:0])) ? remapVecReadys_58 : (&(remap_idx_57[5:0])) ? remapVecReadys_57 : (&(remap_idx_56[5:0])) ? remapVecReadys_56 : (&(remap_idx_55[5:0])) ? remapVecReadys_55 : (&(remap_idx_54[5:0])) ? remapVecReadys_54 : (&(remap_idx_53[5:0])) ? remapVecReadys_53 : (&(remap_idx_52[5:0])) ? remapVecReadys_52 : (&(remap_idx_51[5:0])) ? remapVecReadys_51 : (&(remap_idx_50[5:0])) ? remapVecReadys_50 : (&(remap_idx_49[5:0])) ? remapVecReadys_49 : (&(remap_idx_48[5:0])) ? remapVecReadys_48 : (&(remap_idx_47[5:0])) ? remapVecReadys_47 : (&(remap_idx_46[5:0])) ? remapVecReadys_46 : (&(remap_idx_45[5:0])) ? remapVecReadys_45 : (&(remap_idx_44[5:0])) ? remapVecReadys_44 : (&(remap_idx_43[5:0])) ? remapVecReadys_43 : (&(remap_idx_42[5:0])) ? remapVecReadys_42 : (&(remap_idx_41[5:0])) ? remapVecReadys_41 : (&(remap_idx_40[5:0])) ? remapVecReadys_40 : (&(remap_idx_39[5:0])) ? remapVecReadys_39 : (&(remap_idx_38[5:0])) ? remapVecReadys_38 : (&(remap_idx_37[5:0])) ? remapVecReadys_37 : (&(remap_idx_36[5:0])) ? remapVecReadys_36 : (&(remap_idx_35[5:0])) ? remapVecReadys_35 : (&(remap_idx_34[5:0])) ? remapVecReadys_34 : (&(remap_idx_33[5:0])) ? remapVecReadys_33 : (&(remap_idx_32[5:0])) ? remapVecReadys_32 : (&(remap_idx_31[5:0])) ? remapVecReadys_31 : (&(remap_idx_30[5:0])) ? remapVecReadys_30 : (&(remap_idx_29[5:0])) ? remapVecReadys_29 : (&(remap_idx_28[5:0])) ? remapVecReadys_28 : (&(remap_idx_27[5:0])) ? remapVecReadys_27 : (&(remap_idx_26[5:0])) ? remapVecReadys_26 : (&(remap_idx_25[5:0])) ? remapVecReadys_25 : (&(remap_idx_24[5:0])) ? remapVecReadys_24 : (&(remap_idx_23[5:0])) ? remapVecReadys_23 : (&(remap_idx_22[5:0])) ? remapVecReadys_22 : (&(remap_idx_21[5:0])) ? remapVecReadys_21 : (&(remap_idx_20[5:0])) ? remapVecReadys_20 : (&(remap_idx_19[5:0])) ? remapVecReadys_19 : (&(remap_idx_18[5:0])) ? remapVecReadys_18 : (&(remap_idx_17[5:0])) ? remapVecReadys_17 : (&(remap_idx_16[5:0])) ? remapVecReadys_16 : (&(remap_idx_15[5:0])) ? remapVecReadys_15 : (&(remap_idx_14[5:0])) ? remapVecReadys_14 : (&(remap_idx_13[5:0])) ? remapVecReadys_13 : (&(remap_idx_12[5:0])) ? remapVecReadys_12 : (&(remap_idx_11[5:0])) ? remapVecReadys_11 : (&(remap_idx_10[5:0])) ? remapVecReadys_10 : (&(remap_idx_9[5:0])) ? remapVecReadys_9 : (&(remap_idx_8[5:0])) ? remapVecReadys_8 : (&(remap_idx_7[5:0])) ? remapVecReadys_7 : (&(remap_idx_6[5:0])) ? remapVecReadys_6 : (&(remap_idx_5[5:0])) ? remapVecReadys_5 : (&(remap_idx_4[5:0])) ? remapVecReadys_4 : (&(remap_idx_3[5:0])) ? remapVecReadys_3 : (&(remap_idx_2[5:0])) ? remapVecReadys_2 : (&(remap_idx_1[5:0])) ? remapVecReadys_1 : (&(remap_idx[5:0])) & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] wire [1:0] _count_valid_bits_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [2:0] _count_valid_bits_T_1 = {1'h0, _count_valid_bits_T} + {2'h0, remapVecValids_2}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [3:0] _count_valid_bits_T_2 = {1'h0, _count_valid_bits_T_1} + {3'h0, remapVecValids_3}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [4:0] _count_valid_bits_T_3 = {1'h0, _count_valid_bits_T_2} + {4'h0, remapVecValids_4}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [5:0] _count_valid_bits_T_4 = {1'h0, _count_valid_bits_T_3} + {5'h0, remapVecValids_5}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [6:0] _count_valid_bits_T_5 = {1'h0, _count_valid_bits_T_4} + {6'h0, remapVecValids_6}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [7:0] _count_valid_bits_T_6 = {1'h0, _count_valid_bits_T_5} + {7'h0, remapVecValids_7}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [8:0] _count_valid_bits_T_7 = {1'h0, _count_valid_bits_T_6} + {8'h0, remapVecValids_8}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [9:0] _count_valid_bits_T_8 = {1'h0, _count_valid_bits_T_7} + {9'h0, remapVecValids_9}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [10:0] _count_valid_bits_T_9 = {1'h0, _count_valid_bits_T_8} + {10'h0, remapVecValids_10}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [11:0] _count_valid_bits_T_10 = {1'h0, _count_valid_bits_T_9} + {11'h0, remapVecValids_11}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [12:0] _count_valid_bits_T_11 = {1'h0, _count_valid_bits_T_10} + {12'h0, remapVecValids_12}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [13:0] _count_valid_bits_T_12 = {1'h0, _count_valid_bits_T_11} + {13'h0, remapVecValids_13}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [14:0] _count_valid_bits_T_13 = {1'h0, _count_valid_bits_T_12} + {14'h0, remapVecValids_14}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [15:0] _count_valid_bits_T_14 = {1'h0, _count_valid_bits_T_13} + {15'h0, remapVecValids_15}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [16:0] _count_valid_bits_T_15 = {1'h0, _count_valid_bits_T_14} + {16'h0, remapVecValids_16}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [17:0] _count_valid_bits_T_16 = {1'h0, _count_valid_bits_T_15} + {17'h0, remapVecValids_17}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [18:0] _count_valid_bits_T_17 = {1'h0, _count_valid_bits_T_16} + {18'h0, remapVecValids_18}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [19:0] _count_valid_bits_T_18 = {1'h0, _count_valid_bits_T_17} + {19'h0, remapVecValids_19}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [20:0] _count_valid_bits_T_19 = {1'h0, _count_valid_bits_T_18} + {20'h0, remapVecValids_20}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [21:0] _count_valid_bits_T_20 = {1'h0, _count_valid_bits_T_19} + {21'h0, remapVecValids_21}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [22:0] _count_valid_bits_T_21 = {1'h0, _count_valid_bits_T_20} + {22'h0, remapVecValids_22}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [23:0] _count_valid_bits_T_22 = {1'h0, _count_valid_bits_T_21} + {23'h0, remapVecValids_23}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [24:0] _count_valid_bits_T_23 = {1'h0, _count_valid_bits_T_22} + {24'h0, remapVecValids_24}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [25:0] _count_valid_bits_T_24 = {1'h0, _count_valid_bits_T_23} + {25'h0, remapVecValids_25}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [26:0] _count_valid_bits_T_25 = {1'h0, _count_valid_bits_T_24} + {26'h0, remapVecValids_26}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [27:0] _count_valid_bits_T_26 = {1'h0, _count_valid_bits_T_25} + {27'h0, remapVecValids_27}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [28:0] _count_valid_bits_T_27 = {1'h0, _count_valid_bits_T_26} + {28'h0, remapVecValids_28}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [29:0] _count_valid_bits_T_28 = {1'h0, _count_valid_bits_T_27} + {29'h0, remapVecValids_29}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [30:0] _count_valid_bits_T_29 = {1'h0, _count_valid_bits_T_28} + {30'h0, remapVecValids_30}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [31:0] _count_valid_bits_T_30 = {1'h0, _count_valid_bits_T_29} + {31'h0, remapVecValids_31}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [32:0] _count_valid_bits_T_31 = {1'h0, _count_valid_bits_T_30} + {32'h0, remapVecValids_32}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [33:0] _count_valid_bits_T_32 = {1'h0, _count_valid_bits_T_31} + {33'h0, remapVecValids_33}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [34:0] _count_valid_bits_T_33 = {1'h0, _count_valid_bits_T_32} + {34'h0, remapVecValids_34}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [35:0] _count_valid_bits_T_34 = {1'h0, _count_valid_bits_T_33} + {35'h0, remapVecValids_35}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [36:0] _count_valid_bits_T_35 = {1'h0, _count_valid_bits_T_34} + {36'h0, remapVecValids_36}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [37:0] _count_valid_bits_T_36 = {1'h0, _count_valid_bits_T_35} + {37'h0, remapVecValids_37}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [38:0] _count_valid_bits_T_37 = {1'h0, _count_valid_bits_T_36} + {38'h0, remapVecValids_38}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [39:0] _count_valid_bits_T_38 = {1'h0, _count_valid_bits_T_37} + {39'h0, remapVecValids_39}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [40:0] _count_valid_bits_T_39 = {1'h0, _count_valid_bits_T_38} + {40'h0, remapVecValids_40}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [41:0] _count_valid_bits_T_40 = {1'h0, _count_valid_bits_T_39} + {41'h0, remapVecValids_41}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [42:0] _count_valid_bits_T_41 = {1'h0, _count_valid_bits_T_40} + {42'h0, remapVecValids_42}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [43:0] _count_valid_bits_T_42 = {1'h0, _count_valid_bits_T_41} + {43'h0, remapVecValids_43}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [44:0] _count_valid_bits_T_43 = {1'h0, _count_valid_bits_T_42} + {44'h0, remapVecValids_44}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [45:0] _count_valid_bits_T_44 = {1'h0, _count_valid_bits_T_43} + {45'h0, remapVecValids_45}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [46:0] _count_valid_bits_T_45 = {1'h0, _count_valid_bits_T_44} + {46'h0, remapVecValids_46}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [47:0] _count_valid_bits_T_46 = {1'h0, _count_valid_bits_T_45} + {47'h0, remapVecValids_47}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [48:0] _count_valid_bits_T_47 = {1'h0, _count_valid_bits_T_46} + {48'h0, remapVecValids_48}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [49:0] _count_valid_bits_T_48 = {1'h0, _count_valid_bits_T_47} + {49'h0, remapVecValids_49}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [50:0] _count_valid_bits_T_49 = {1'h0, _count_valid_bits_T_48} + {50'h0, remapVecValids_50}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [51:0] _count_valid_bits_T_50 = {1'h0, _count_valid_bits_T_49} + {51'h0, remapVecValids_51}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [52:0] _count_valid_bits_T_51 = {1'h0, _count_valid_bits_T_50} + {52'h0, remapVecValids_52}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [53:0] _count_valid_bits_T_52 = {1'h0, _count_valid_bits_T_51} + {53'h0, remapVecValids_53}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [54:0] _count_valid_bits_T_53 = {1'h0, _count_valid_bits_T_52} + {54'h0, remapVecValids_54}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [55:0] _count_valid_bits_T_54 = {1'h0, _count_valid_bits_T_53} + {55'h0, remapVecValids_55}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [56:0] _count_valid_bits_T_55 = {1'h0, _count_valid_bits_T_54} + {56'h0, remapVecValids_56}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [57:0] _count_valid_bits_T_56 = {1'h0, _count_valid_bits_T_55} + {57'h0, remapVecValids_57}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [58:0] _count_valid_bits_T_57 = {1'h0, _count_valid_bits_T_56} + {58'h0, remapVecValids_58}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [59:0] _count_valid_bits_T_58 = {1'h0, _count_valid_bits_T_57} + {59'h0, remapVecValids_59}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [60:0] _count_valid_bits_T_59 = {1'h0, _count_valid_bits_T_58} + {60'h0, remapVecValids_60}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [61:0] _count_valid_bits_T_60 = {1'h0, _count_valid_bits_T_59} + {61'h0, remapVecValids_61}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [62:0] _count_valid_bits_T_61 = {1'h0, _count_valid_bits_T_60} + {62'h0, remapVecValids_62}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [63:0] count_valid_bits = {1'h0, _count_valid_bits_T_61} + {63'h0, remapVecValids_63}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [63:0] count_valid_bytes = {3'h0, count_valid_bits[63:3]}; // @[CompressedBitsBuffer.scala:150:64, :151:44] wire [66:0] _remain_valid_bits_T = {count_valid_bytes, 3'h0}; // @[CompressedBitsBuffer.scala:151:44, :152:65] wire [67:0] _remain_valid_bits_T_1 = {4'h0, count_valid_bits} - {1'h0, _remain_valid_bits_T}; // @[CompressedBitsBuffer.scala:150:64, :152:{44,65}] wire [66:0] remain_valid_bits = _remain_valid_bits_T_1[66:0]; // @[CompressedBitsBuffer.scala:152:44] wire byte_aligned = remain_valid_bits == 67'h0; // @[CompressedBitsBuffer.scala:152:44, :153:41] reg [63:0] len_already_consumed; // @[CompressedBitsBuffer.scala:155:37] wire [64:0] _GEN_250 = {1'h0, len_already_consumed}; // @[CompressedBitsBuffer.scala:155:37, :156:55] wire [64:0] _unconsumed_bits_so_far_T = {1'h0, _buf_lens_q_io_deq_bits} - _GEN_250; // @[CompressedBitsBuffer.scala:65:26, :156:55] wire [63:0] unconsumed_bits_so_far = _unconsumed_bits_so_far_T[63:0]; // @[CompressedBitsBuffer.scala:156:55] wire _last_chunk_T = unconsumed_bits_so_far < 64'h41; // @[CompressedBitsBuffer.scala:156:55, :157:71] assign last_chunk = _buf_lens_q_io_deq_valid & _last_chunk_T; // @[CompressedBitsBuffer.scala:65:26, :157:{44,71}] assign io_consumer_last_chunk_0 = last_chunk; // @[CompressedBitsBuffer.scala:38:7, :157:44] wire _avail_bytes_T = ~byte_aligned; // @[CompressedBitsBuffer.scala:153:41, :159:40] wire _avail_bytes_T_1 = last_chunk & _avail_bytes_T; // @[CompressedBitsBuffer.scala:157:44, :159:{37,40}] wire [64:0] _avail_bytes_T_2 = {1'h0, count_valid_bytes} + 65'h1; // @[CompressedBitsBuffer.scala:151:44, :160:51] wire [63:0] _avail_bytes_T_3 = _avail_bytes_T_2[63:0]; // @[CompressedBitsBuffer.scala:160:51] wire [63:0] avail_bytes = _avail_bytes_T_1 ? _avail_bytes_T_3 : count_valid_bytes; // @[CompressedBitsBuffer.scala:151:44, :159:{24,37}, :160:51] assign enough_data = \|avail_bytes; // @[CompressedBitsBuffer.scala:159:24, :162:33] assign io_consumer_valid_0 = enough_data; // @[CompressedBitsBuffer.scala:38:7, :162:33] wire [7:0] count_valid_bits_u8; // @[CompressedBitsBuffer.scala:164:33] assign count_valid_bits_u8 = count_valid_bits[7:0]; // @[CompressedBitsBuffer.scala:150:64, :164:33, :165:23] wire [255:0] _valid_bit_mask_T = 256'h1 << count_valid_bits_u8; // @[CompressedBitsBuffer.scala:164:33, :166:29] wire [256:0] _valid_bit_mask_T_1 = {1'h0, _valid_bit_mask_T} - 257'h1; // @[CompressedBitsBuffer.scala:166:{29,53}] wire [255:0] valid_bit_mask = _valid_bit_mask_T_1[255:0]; // @[CompressedBitsBuffer.scala:166:53] wire [1:0] io_consumer_data_lo_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_lo_lo_lo = {io_consumer_data_lo_lo_lo_lo_hi, io_consumer_data_lo_lo_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_lo_lo_hi = {io_consumer_data_lo_lo_lo_hi_hi, io_consumer_data_lo_lo_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_lo_lo_lo = {io_consumer_data_lo_lo_lo_hi, io_consumer_data_lo_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_lo_hi_lo = {io_consumer_data_lo_lo_hi_lo_hi, io_consumer_data_lo_lo_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_lo_hi_hi = {io_consumer_data_lo_lo_hi_hi_hi, io_consumer_data_lo_lo_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_lo_lo_hi = {io_consumer_data_lo_lo_hi_hi, io_consumer_data_lo_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [15:0] io_consumer_data_lo_lo = {io_consumer_data_lo_lo_hi, io_consumer_data_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_hi_lo_lo = {io_consumer_data_lo_hi_lo_lo_hi, io_consumer_data_lo_hi_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_hi_lo_hi = {io_consumer_data_lo_hi_lo_hi_hi, io_consumer_data_lo_hi_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_lo_hi_lo = {io_consumer_data_lo_hi_lo_hi, io_consumer_data_lo_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_hi_hi_lo = {io_consumer_data_lo_hi_hi_lo_hi, io_consumer_data_lo_hi_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_hi_hi_hi = {io_consumer_data_lo_hi_hi_hi_hi, io_consumer_data_lo_hi_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_lo_hi_hi = {io_consumer_data_lo_hi_hi_hi, io_consumer_data_lo_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [15:0] io_consumer_data_lo_hi = {io_consumer_data_lo_hi_hi, io_consumer_data_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [31:0] io_consumer_data_lo = {io_consumer_data_lo_hi, io_consumer_data_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_lo_lo_lo_lo = {remapVecData_33, remapVecData_32}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_lo_lo_lo_hi = {remapVecData_35, remapVecData_34}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_lo_lo_lo = {io_consumer_data_hi_lo_lo_lo_hi, io_consumer_data_hi_lo_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_lo_lo_hi_lo = {remapVecData_37, remapVecData_36}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_lo_lo_hi_hi = {remapVecData_39, remapVecData_38}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_lo_lo_hi = {io_consumer_data_hi_lo_lo_hi_hi, io_consumer_data_hi_lo_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_hi_lo_lo = {io_consumer_data_hi_lo_lo_hi, io_consumer_data_hi_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_lo_hi_lo_lo = {remapVecData_41, remapVecData_40}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_lo_hi_lo_hi = {remapVecData_43, remapVecData_42}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_lo_hi_lo = {io_consumer_data_hi_lo_hi_lo_hi, io_consumer_data_hi_lo_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_lo_hi_hi_lo = {remapVecData_45, remapVecData_44}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_lo_hi_hi_hi = {remapVecData_47, remapVecData_46}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_lo_hi_hi = {io_consumer_data_hi_lo_hi_hi_hi, io_consumer_data_hi_lo_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_hi_lo_hi = {io_consumer_data_hi_lo_hi_hi, io_consumer_data_hi_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [15:0] io_consumer_data_hi_lo = {io_consumer_data_hi_lo_hi, io_consumer_data_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_hi_lo_lo_lo = {remapVecData_49, remapVecData_48}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_hi_lo_lo_hi = {remapVecData_51, remapVecData_50}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_hi_lo_lo = {io_consumer_data_hi_hi_lo_lo_hi, io_consumer_data_hi_hi_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_hi_lo_hi_lo = {remapVecData_53, remapVecData_52}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_hi_lo_hi_hi = {remapVecData_55, remapVecData_54}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_hi_lo_hi = {io_consumer_data_hi_hi_lo_hi_hi, io_consumer_data_hi_hi_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_hi_hi_lo = {io_consumer_data_hi_hi_lo_hi, io_consumer_data_hi_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_hi_hi_lo_lo = {remapVecData_57, remapVecData_56}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_hi_hi_lo_hi = {remapVecData_59, remapVecData_58}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_hi_hi_lo = {io_consumer_data_hi_hi_hi_lo_hi, io_consumer_data_hi_hi_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_hi_hi_hi_lo = {remapVecData_61, remapVecData_60}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_hi_hi_hi_hi = {remapVecData_63, remapVecData_62}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_hi_hi_hi = {io_consumer_data_hi_hi_hi_hi_hi, io_consumer_data_hi_hi_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_hi_hi_hi = {io_consumer_data_hi_hi_hi_hi, io_consumer_data_hi_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [15:0] io_consumer_data_hi_hi = {io_consumer_data_hi_hi_hi, io_consumer_data_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [31:0] io_consumer_data_hi = {io_consumer_data_hi_hi, io_consumer_data_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [63:0] _io_consumer_data_T = {io_consumer_data_hi, io_consumer_data_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [255:0] _io_consumer_data_T_1 = {192'h0, valid_bit_mask[63:0] & _io_consumer_data_T}; // @[CompressedBitsBuffer.scala:166:53, :168:{26,49}] assign io_consumer_data_0 = _io_consumer_data_T_1[63:0]; // @[CompressedBitsBuffer.scala:38:7, :168:{20,49}] assign io_consumer_avail_bytes_0 = avail_bytes[6:0]; // @[CompressedBitsBuffer.scala:38:7, :159:24, :169:27] wire [9:0] consumed_bits_wide = {io_consumer_consumed_bytes_0, 3'h0}; // @[CompressedBitsBuffer.scala:38:7, :178:55] wire [63:0] _GEN_251 = {54'h0, consumed_bits_wide}; // @[CompressedBitsBuffer.scala:178:55, :179:51] wire consumed_bits_overflow = _GEN_251 > count_valid_bits; // @[CompressedBitsBuffer.scala:150:64, :179:51] wire _consumed_bits_T = ~byte_aligned; // @[CompressedBitsBuffer.scala:153:41, :159:40, :180:41] wire _consumed_bits_T_1 = last_chunk & _consumed_bits_T; // @[CompressedBitsBuffer.scala:157:44, :180:{38,41}] wire _consumed_bits_T_2 = _consumed_bits_T_1 & consumed_bits_overflow; // @[CompressedBitsBuffer.scala:179:51, :180:{38,55}] wire [63:0] consumed_bits = _consumed_bits_T_2 ? count_valid_bits : _GEN_251; // @[CompressedBitsBuffer.scala:150:64, :179:51, :180:{26,55}] wire [64:0] _GEN_252 = {1'h0, consumed_bits}; // @[CompressedBitsBuffer.scala:180:26, :184:95] wire [64:0] _GEN_253 = _GEN_250 + _GEN_252; // @[CompressedBitsBuffer.scala:156:55, :184:95] wire [64:0] _buf_last_T; // @[CompressedBitsBuffer.scala:184:95] assign _buf_last_T = _GEN_253; // @[CompressedBitsBuffer.scala:184:95] wire [64:0] _nxt_len_already_consumed_T; // @[CompressedBitsBuffer.scala:185:74] assign _nxt_len_already_consumed_T = _GEN_253; // @[CompressedBitsBuffer.scala:184:95, :185:74] wire [63:0] _buf_last_T_1 = _buf_last_T[63:0]; // @[CompressedBitsBuffer.scala:184:95] wire _buf_last_T_2 = _buf_lens_q_io_deq_bits == _buf_last_T_1; // @[CompressedBitsBuffer.scala:65:26, :184:{69,95}] wire buf_last = _buf_lens_q_io_deq_valid & _buf_last_T_2; // @[CompressedBitsBuffer.scala:65:26, :184:{42,69}] wire [63:0] _nxt_len_already_consumed_T_1 = _nxt_len_already_consumed_T[63:0]; // @[CompressedBitsBuffer.scala:185:74] wire [63:0] nxt_len_already_consumed = buf_last ? 64'h0 : _nxt_len_already_consumed_T_1; // @[CompressedBitsBuffer.scala:184:42, :185:{37,74}] wire _T_337 = io_consumer_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_32_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_32_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_33_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_33_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_34_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_34_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_35_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_35_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_36_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_36_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_37_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_37_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_38_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_38_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_39_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_39_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_40_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_40_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_41_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_41_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_42_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_42_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_43_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_43_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_44_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_44_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_45_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_45_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_46_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_46_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_47_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_47_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_48_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_48_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_49_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_49_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_50_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_50_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_51_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_51_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_52_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_52_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_53_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_53_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_54_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_54_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_55_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_55_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_56_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_56_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_57_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_57_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_58_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_58_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_59_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_59_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_60_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_60_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_61_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_61_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_62_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_62_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_63_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_63_T_1 = _T_337; // @[Misc.scala:29:18] wire _buf_lens_q_io_deq_ready_T; // @[Misc.scala:29:18] assign _buf_lens_q_io_deq_ready_T = _T_337; // @[Misc.scala:29:18] wire [64:0] _read_start_idx_T = {58'h0, read_start_idx} + _GEN_252; // @[CompressedBitsBuffer.scala:126:31, :184:95, :187:39] wire [64:0] _GEN_254 = _read_start_idx_T % 65'h40; // @[CompressedBitsBuffer.scala:187:{39,57}] wire [6:0] _read_start_idx_T_1 = _GEN_254[6:0]; // @[CompressedBitsBuffer.scala:187:57] wire _remapVecReadys_0_T = \|consumed_bits; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_0_T_2 = _remapVecReadys_0_T & _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign remapVecReadys_0 = _remapVecReadys_0_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_1_T = \|(consumed_bits[63:1]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_1_T_2 = _remapVecReadys_1_T & _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign remapVecReadys_1 = _remapVecReadys_1_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_2_T = consumed_bits > 64'h2; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_2_T_2 = _remapVecReadys_2_T & _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign remapVecReadys_2 = _remapVecReadys_2_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_3_T = \|(consumed_bits[63:2]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_3_T_2 = _remapVecReadys_3_T & _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign remapVecReadys_3 = _remapVecReadys_3_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_4_T = consumed_bits > 64'h4; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_4_T_2 = _remapVecReadys_4_T & _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign remapVecReadys_4 = _remapVecReadys_4_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_5_T = consumed_bits > 64'h5; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_5_T_2 = _remapVecReadys_5_T & _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign remapVecReadys_5 = _remapVecReadys_5_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_6_T = consumed_bits > 64'h6; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_6_T_2 = _remapVecReadys_6_T & _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign remapVecReadys_6 = _remapVecReadys_6_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_7_T = \|(consumed_bits[63:3]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_7_T_2 = _remapVecReadys_7_T & _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign remapVecReadys_7 = _remapVecReadys_7_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_8_T = consumed_bits > 64'h8; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_8_T_2 = _remapVecReadys_8_T & _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign remapVecReadys_8 = _remapVecReadys_8_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_9_T = consumed_bits > 64'h9; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_9_T_2 = _remapVecReadys_9_T & _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign remapVecReadys_9 = _remapVecReadys_9_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_10_T = consumed_bits > 64'hA; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_10_T_2 = _remapVecReadys_10_T & _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign remapVecReadys_10 = _remapVecReadys_10_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_11_T = consumed_bits > 64'hB; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_11_T_2 = _remapVecReadys_11_T & _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign remapVecReadys_11 = _remapVecReadys_11_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_12_T = consumed_bits > 64'hC; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_12_T_2 = _remapVecReadys_12_T & _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign remapVecReadys_12 = _remapVecReadys_12_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_13_T = consumed_bits > 64'hD; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_13_T_2 = _remapVecReadys_13_T & _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign remapVecReadys_13 = _remapVecReadys_13_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_14_T = consumed_bits > 64'hE; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_14_T_2 = _remapVecReadys_14_T & _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign remapVecReadys_14 = _remapVecReadys_14_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_15_T = \|(consumed_bits[63:4]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_15_T_2 = _remapVecReadys_15_T & _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign remapVecReadys_15 = _remapVecReadys_15_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_16_T = consumed_bits > 64'h10; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_16_T_2 = _remapVecReadys_16_T & _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign remapVecReadys_16 = _remapVecReadys_16_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_17_T = consumed_bits > 64'h11; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_17_T_2 = _remapVecReadys_17_T & _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign remapVecReadys_17 = _remapVecReadys_17_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_18_T = consumed_bits > 64'h12; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_18_T_2 = _remapVecReadys_18_T & _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign remapVecReadys_18 = _remapVecReadys_18_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_19_T = consumed_bits > 64'h13; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_19_T_2 = _remapVecReadys_19_T & _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign remapVecReadys_19 = _remapVecReadys_19_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_20_T = consumed_bits > 64'h14; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_20_T_2 = _remapVecReadys_20_T & _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign remapVecReadys_20 = _remapVecReadys_20_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_21_T = consumed_bits > 64'h15; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_21_T_2 = _remapVecReadys_21_T & _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign remapVecReadys_21 = _remapVecReadys_21_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_22_T = consumed_bits > 64'h16; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_22_T_2 = _remapVecReadys_22_T & _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign remapVecReadys_22 = _remapVecReadys_22_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_23_T = consumed_bits > 64'h17; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_23_T_2 = _remapVecReadys_23_T & _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign remapVecReadys_23 = _remapVecReadys_23_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_24_T = consumed_bits > 64'h18; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_24_T_2 = _remapVecReadys_24_T & _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign remapVecReadys_24 = _remapVecReadys_24_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_25_T = consumed_bits > 64'h19; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_25_T_2 = _remapVecReadys_25_T & _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign remapVecReadys_25 = _remapVecReadys_25_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_26_T = consumed_bits > 64'h1A; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_26_T_2 = _remapVecReadys_26_T & _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign remapVecReadys_26 = _remapVecReadys_26_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_27_T = consumed_bits > 64'h1B; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_27_T_2 = _remapVecReadys_27_T & _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign remapVecReadys_27 = _remapVecReadys_27_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_28_T = consumed_bits > 64'h1C; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_28_T_2 = _remapVecReadys_28_T & _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign remapVecReadys_28 = _remapVecReadys_28_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_29_T = consumed_bits > 64'h1D; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_29_T_2 = _remapVecReadys_29_T & _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign remapVecReadys_29 = _remapVecReadys_29_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_30_T = consumed_bits > 64'h1E; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_30_T_2 = _remapVecReadys_30_T & _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign remapVecReadys_30 = _remapVecReadys_30_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_31_T = \|(consumed_bits[63:5]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_31_T_2 = _remapVecReadys_31_T & _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign remapVecReadys_31 = _remapVecReadys_31_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_32_T = consumed_bits > 64'h20; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_32_T_2 = _remapVecReadys_32_T & _remapVecReadys_32_T_1; // @[Misc.scala:29:18] assign remapVecReadys_32 = _remapVecReadys_32_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_33_T = consumed_bits > 64'h21; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_33_T_2 = _remapVecReadys_33_T & _remapVecReadys_33_T_1; // @[Misc.scala:29:18] assign remapVecReadys_33 = _remapVecReadys_33_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_34_T = consumed_bits > 64'h22; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_34_T_2 = _remapVecReadys_34_T & _remapVecReadys_34_T_1; // @[Misc.scala:29:18] assign remapVecReadys_34 = _remapVecReadys_34_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_35_T = consumed_bits > 64'h23; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_35_T_2 = _remapVecReadys_35_T & _remapVecReadys_35_T_1; // @[Misc.scala:29:18] assign remapVecReadys_35 = _remapVecReadys_35_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_36_T = consumed_bits > 64'h24; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_36_T_2 = _remapVecReadys_36_T & _remapVecReadys_36_T_1; // @[Misc.scala:29:18] assign remapVecReadys_36 = _remapVecReadys_36_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_37_T = consumed_bits > 64'h25; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_37_T_2 = _remapVecReadys_37_T & _remapVecReadys_37_T_1; // @[Misc.scala:29:18] assign remapVecReadys_37 = _remapVecReadys_37_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_38_T = consumed_bits > 64'h26; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_38_T_2 = _remapVecReadys_38_T & _remapVecReadys_38_T_1; // @[Misc.scala:29:18] assign remapVecReadys_38 = _remapVecReadys_38_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_39_T = consumed_bits > 64'h27; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_39_T_2 = _remapVecReadys_39_T & _remapVecReadys_39_T_1; // @[Misc.scala:29:18] assign remapVecReadys_39 = _remapVecReadys_39_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_40_T = consumed_bits > 64'h28; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_40_T_2 = _remapVecReadys_40_T & _remapVecReadys_40_T_1; // @[Misc.scala:29:18] assign remapVecReadys_40 = _remapVecReadys_40_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_41_T = consumed_bits > 64'h29; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_41_T_2 = _remapVecReadys_41_T & _remapVecReadys_41_T_1; // @[Misc.scala:29:18] assign remapVecReadys_41 = _remapVecReadys_41_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_42_T = consumed_bits > 64'h2A; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_42_T_2 = _remapVecReadys_42_T & _remapVecReadys_42_T_1; // @[Misc.scala:29:18] assign remapVecReadys_42 = _remapVecReadys_42_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_43_T = consumed_bits > 64'h2B; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_43_T_2 = _remapVecReadys_43_T & _remapVecReadys_43_T_1; // @[Misc.scala:29:18] assign remapVecReadys_43 = _remapVecReadys_43_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_44_T = consumed_bits > 64'h2C; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_44_T_2 = _remapVecReadys_44_T & _remapVecReadys_44_T_1; // @[Misc.scala:29:18] assign remapVecReadys_44 = _remapVecReadys_44_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_45_T = consumed_bits > 64'h2D; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_45_T_2 = _remapVecReadys_45_T & _remapVecReadys_45_T_1; // @[Misc.scala:29:18] assign remapVecReadys_45 = _remapVecReadys_45_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_46_T = consumed_bits > 64'h2E; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_46_T_2 = _remapVecReadys_46_T & _remapVecReadys_46_T_1; // @[Misc.scala:29:18] assign remapVecReadys_46 = _remapVecReadys_46_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_47_T = consumed_bits > 64'h2F; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_47_T_2 = _remapVecReadys_47_T & _remapVecReadys_47_T_1; // @[Misc.scala:29:18] assign remapVecReadys_47 = _remapVecReadys_47_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_48_T = consumed_bits > 64'h30; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_48_T_2 = _remapVecReadys_48_T & _remapVecReadys_48_T_1; // @[Misc.scala:29:18] assign remapVecReadys_48 = _remapVecReadys_48_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_49_T = consumed_bits > 64'h31; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_49_T_2 = _remapVecReadys_49_T & _remapVecReadys_49_T_1; // @[Misc.scala:29:18] assign remapVecReadys_49 = _remapVecReadys_49_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_50_T = consumed_bits > 64'h32; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_50_T_2 = _remapVecReadys_50_T & _remapVecReadys_50_T_1; // @[Misc.scala:29:18] assign remapVecReadys_50 = _remapVecReadys_50_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_51_T = consumed_bits > 64'h33; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_51_T_2 = _remapVecReadys_51_T & _remapVecReadys_51_T_1; // @[Misc.scala:29:18] assign remapVecReadys_51 = _remapVecReadys_51_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_52_T = consumed_bits > 64'h34; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_52_T_2 = _remapVecReadys_52_T & _remapVecReadys_52_T_1; // @[Misc.scala:29:18] assign remapVecReadys_52 = _remapVecReadys_52_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_53_T = consumed_bits > 64'h35; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_53_T_2 = _remapVecReadys_53_T & _remapVecReadys_53_T_1; // @[Misc.scala:29:18] assign remapVecReadys_53 = _remapVecReadys_53_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_54_T = consumed_bits > 64'h36; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_54_T_2 = _remapVecReadys_54_T & _remapVecReadys_54_T_1; // @[Misc.scala:29:18] assign remapVecReadys_54 = _remapVecReadys_54_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_55_T = consumed_bits > 64'h37; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_55_T_2 = _remapVecReadys_55_T & _remapVecReadys_55_T_1; // @[Misc.scala:29:18] assign remapVecReadys_55 = _remapVecReadys_55_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_56_T = consumed_bits > 64'h38; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_56_T_2 = _remapVecReadys_56_T & _remapVecReadys_56_T_1; // @[Misc.scala:29:18] assign remapVecReadys_56 = _remapVecReadys_56_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_57_T = consumed_bits > 64'h39; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_57_T_2 = _remapVecReadys_57_T & _remapVecReadys_57_T_1; // @[Misc.scala:29:18] assign remapVecReadys_57 = _remapVecReadys_57_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_58_T = consumed_bits > 64'h3A; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_58_T_2 = _remapVecReadys_58_T & _remapVecReadys_58_T_1; // @[Misc.scala:29:18] assign remapVecReadys_58 = _remapVecReadys_58_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_59_T = consumed_bits > 64'h3B; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_59_T_2 = _remapVecReadys_59_T & _remapVecReadys_59_T_1; // @[Misc.scala:29:18] assign remapVecReadys_59 = _remapVecReadys_59_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_60_T = consumed_bits > 64'h3C; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_60_T_2 = _remapVecReadys_60_T & _remapVecReadys_60_T_1; // @[Misc.scala:29:18] assign remapVecReadys_60 = _remapVecReadys_60_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_61_T = consumed_bits > 64'h3D; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_61_T_2 = _remapVecReadys_61_T & _remapVecReadys_61_T_1; // @[Misc.scala:29:18] assign remapVecReadys_61 = _remapVecReadys_61_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_62_T = consumed_bits > 64'h3E; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_62_T_2 = _remapVecReadys_62_T & _remapVecReadys_62_T_1; // @[Misc.scala:29:18] assign remapVecReadys_62 = _remapVecReadys_62_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_63_T = \|(consumed_bits[63:6]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_63_T_2 = _remapVecReadys_63_T & _remapVecReadys_63_T_1; // @[Misc.scala:29:18] assign remapVecReadys_63 = _remapVecReadys_63_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _buf_lens_q_io_deq_ready_T_1 = _buf_lens_q_io_deq_ready_T & buf_last; // @[Misc.scala:29:18] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_43; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_86 = {1'h0, loginfo_cycles_43} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_87 = _loginfo_cycles_T_86[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_44; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_88 = {1'h0, loginfo_cycles_44} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_89 = _loginfo_cycles_T_88[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_45; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_90 = {1'h0, loginfo_cycles_45} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_91 = _loginfo_cycles_T_90[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_46; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_92 = {1'h0, loginfo_cycles_46} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_93 = _loginfo_cycles_T_92[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_47; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_94 = {1'h0, loginfo_cycles_47} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_95 = _loginfo_cycles_T_94[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_48; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_96 = {1'h0, loginfo_cycles_48} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_97 = _loginfo_cycles_T_96[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_49; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_98 = {1'h0, loginfo_cycles_49} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_99 = _loginfo_cycles_T_98[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_50; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_100 = {1'h0, loginfo_cycles_50} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_101 = _loginfo_cycles_T_100[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_51; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_102 = {1'h0, loginfo_cycles_51} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_103 = _loginfo_cycles_T_102[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_52; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_104 = {1'h0, loginfo_cycles_52} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_105 = _loginfo_cycles_T_104[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_53; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_106 = {1'h0, loginfo_cycles_53} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_107 = _loginfo_cycles_T_106[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_54; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_108 = {1'h0, loginfo_cycles_54} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_109 = _loginfo_cycles_T_108[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_55; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_110 = {1'h0, loginfo_cycles_55} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_111 = _loginfo_cycles_T_110[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_56; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_112 = {1'h0, loginfo_cycles_56} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_113 = _loginfo_cycles_T_112[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_57; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_114 = {1'h0, loginfo_cycles_57} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_115 = _loginfo_cycles_T_114[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_58; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_116 = {1'h0, loginfo_cycles_58} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_117 = _loginfo_cycles_T_116[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_59; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_118 = {1'h0, loginfo_cycles_59} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_119 = _loginfo_cycles_T_118[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_60; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_120 = {1'h0, loginfo_cycles_60} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_121 = _loginfo_cycles_T_120[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_61; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_122 = {1'h0, loginfo_cycles_61} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_123 = _loginfo_cycles_T_122[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_62; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_124 = {1'h0, loginfo_cycles_62} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_125 = _loginfo_cycles_T_124[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_63; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_126 = {1'h0, loginfo_cycles_63} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_127 = _loginfo_cycles_T_126[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_64; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_128 = {1'h0, loginfo_cycles_64} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_129 = _loginfo_cycles_T_128[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_65; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_130 = {1'h0, loginfo_cycles_65} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_131 = _loginfo_cycles_T_130[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_66; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_132 = {1'h0, loginfo_cycles_66} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_133 = _loginfo_cycles_T_132[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_67; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_134 = {1'h0, loginfo_cycles_67} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_135 = _loginfo_cycles_T_134[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_68; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_136 = {1'h0, loginfo_cycles_68} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_137 = _loginfo_cycles_T_136[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_69; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_138 = {1'h0, loginfo_cycles_69} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_139 = _loginfo_cycles_T_138[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_70; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_140 = {1'h0, loginfo_cycles_70} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_141 = _loginfo_cycles_T_140[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_71; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_142 = {1'h0, loginfo_cycles_71} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_143 = _loginfo_cycles_T_142[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_72; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_144 = {1'h0, loginfo_cycles_72} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_145 = _loginfo_cycles_T_144[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_73; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_146 = {1'h0, loginfo_cycles_73} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_147 = _loginfo_cycles_T_146[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_74; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_148 = {1'h0, loginfo_cycles_74} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_149 = _loginfo_cycles_T_148[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_75; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_150 = {1'h0, loginfo_cycles_75} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_151 = _loginfo_cycles_T_150[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_76; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_152 = {1'h0, loginfo_cycles_76} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_153 = _loginfo_cycles_T_152[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_77; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_154 = {1'h0, loginfo_cycles_77} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_155 = _loginfo_cycles_T_154[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_78; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_156 = {1'h0, loginfo_cycles_78} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_157 = _loginfo_cycles_T_156[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_79; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_158 = {1'h0, loginfo_cycles_79} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_159 = _loginfo_cycles_T_158[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_80; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_160 = {1'h0, loginfo_cycles_80} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_161 = _loginfo_cycles_T_160[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_81; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_162 = {1'h0, loginfo_cycles_81} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_163 = _loginfo_cycles_T_162[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_82; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_164 = {1'h0, loginfo_cycles_82} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_165 = _loginfo_cycles_T_164[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_83; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_166 = {1'h0, loginfo_cycles_83} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_167 = _loginfo_cycles_T_166[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_84; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_168 = {1'h0, loginfo_cycles_84} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_169 = _loginfo_cycles_T_168[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_85; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_170 = {1'h0, loginfo_cycles_85} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_171 = _loginfo_cycles_T_170[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_86; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_172 = {1'h0, loginfo_cycles_86} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_173 = _loginfo_cycles_T_172[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_87; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_174 = {1'h0, loginfo_cycles_87} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_175 = _loginfo_cycles_T_174[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_88; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_176 = {1'h0, loginfo_cycles_88} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_177 = _loginfo_cycles_T_176[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_89; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_178 = {1'h0, loginfo_cycles_89} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_179 = _loginfo_cycles_T_178[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_90; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_180 = {1'h0, loginfo_cycles_90} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_181 = _loginfo_cycles_T_180[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_91; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_182 = {1'h0, loginfo_cycles_91} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_183 = _loginfo_cycles_T_182[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_92; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_184 = {1'h0, loginfo_cycles_92} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_185 = _loginfo_cycles_T_184[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_93; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_186 = {1'h0, loginfo_cycles_93} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_187 = _loginfo_cycles_T_186[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_94; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_188 = {1'h0, loginfo_cycles_94} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_189 = _loginfo_cycles_T_188[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_95; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_190 = {1'h0, loginfo_cycles_95} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_191 = _loginfo_cycles_T_190[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_96; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_192 = {1'h0, loginfo_cycles_96} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_193 = _loginfo_cycles_T_192[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_97; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_194 = {1'h0, loginfo_cycles_97} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_195 = _loginfo_cycles_T_194[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_98; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_196 = {1'h0, loginfo_cycles_98} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_197 = _loginfo_cycles_T_196[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_99; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_198 = {1'h0, loginfo_cycles_99} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_199 = _loginfo_cycles_T_198[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_100; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_200 = {1'h0, loginfo_cycles_100} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_201 = _loginfo_cycles_T_200[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_101; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_202 = {1'h0, loginfo_cycles_101} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_203 = _loginfo_cycles_T_202[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_102; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_204 = {1'h0, loginfo_cycles_102} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_205 = _loginfo_cycles_T_204[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_103; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_206 = {1'h0, loginfo_cycles_103} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_207 = _loginfo_cycles_T_206[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_104; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_208 = {1'h0, loginfo_cycles_104} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_209 = _loginfo_cycles_T_208[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_105; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_210 = {1'h0, loginfo_cycles_105} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_211 = _loginfo_cycles_T_210[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_106; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_212 = {1'h0, loginfo_cycles_106} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_213 = _loginfo_cycles_T_212[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_107; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_214 = {1'h0, loginfo_cycles_107} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_215 = _loginfo_cycles_T_214[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_108; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_216 = {1'h0, loginfo_cycles_108} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_217 = _loginfo_cycles_T_216[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_109; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_218 = {1'h0, loginfo_cycles_109} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_219 = _loginfo_cycles_T_218[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_110; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_220 = {1'h0, loginfo_cycles_110} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_221 = _loginfo_cycles_T_220[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_111; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_222 = {1'h0, loginfo_cycles_111} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_223 = _loginfo_cycles_T_222[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_112; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_224 = {1'h0, loginfo_cycles_112} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_225 = _loginfo_cycles_T_224[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_113; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_226 = {1'h0, loginfo_cycles_113} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_227 = _loginfo_cycles_T_226[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_114; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_228 = {1'h0, loginfo_cycles_114} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_229 = _loginfo_cycles_T_228[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_115; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_230 = {1'h0, loginfo_cycles_115} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_231 = _loginfo_cycles_T_230[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_116; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_232 = {1'h0, loginfo_cycles_116} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_233 = _loginfo_cycles_T_232[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_117; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_234 = {1'h0, loginfo_cycles_117} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_235 = _loginfo_cycles_T_234[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_118; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_236 = {1'h0, loginfo_cycles_118} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_237 = _loginfo_cycles_T_236[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_119; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_238 = {1'h0, loginfo_cycles_119} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_239 = _loginfo_cycles_T_238[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_120; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_240 = {1'h0, loginfo_cycles_120} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_241 = _loginfo_cycles_T_240[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_121; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_242 = {1'h0, loginfo_cycles_121} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_243 = _loginfo_cycles_T_242[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_122; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_244 = {1'h0, loginfo_cycles_122} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_245 = _loginfo_cycles_T_244[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_123; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_246 = {1'h0, loginfo_cycles_123} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_247 = _loginfo_cycles_T_246[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_124; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_248 = {1'h0, loginfo_cycles_124} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_249 = _loginfo_cycles_T_248[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_125; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_250 = {1'h0, loginfo_cycles_125} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_251 = _loginfo_cycles_T_250[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_126; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_252 = {1'h0, loginfo_cycles_126} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_253 = _loginfo_cycles_T_252[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_127; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_254 = {1'h0, loginfo_cycles_127} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_255 = _loginfo_cycles_T_254[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_128; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_256 = {1'h0, loginfo_cycles_128} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_257 = _loginfo_cycles_T_256[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_129; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_258 = {1'h0, loginfo_cycles_129} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_259 = _loginfo_cycles_T_258[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_130; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_260 = {1'h0, loginfo_cycles_130} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_261 = _loginfo_cycles_T_260[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_131; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_262 = {1'h0, loginfo_cycles_131} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_263 = _loginfo_cycles_T_262[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_132; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_264 = {1'h0, loginfo_cycles_132} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_265 = _loginfo_cycles_T_264[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_133; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_266 = {1'h0, loginfo_cycles_133} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_267 = _loginfo_cycles_T_266[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_134; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_268 = {1'h0, loginfo_cycles_134} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_269 = _loginfo_cycles_T_268[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_135; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_270 = {1'h0, loginfo_cycles_135} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_271 = _loginfo_cycles_T_270[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_136; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_272 = {1'h0, loginfo_cycles_136} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_273 = _loginfo_cycles_T_272[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_137; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_274 = {1'h0, loginfo_cycles_137} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_275 = _loginfo_cycles_T_274[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_138; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_276 = {1'h0, loginfo_cycles_138} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_277 = _loginfo_cycles_T_276[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_139; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_278 = {1'h0, loginfo_cycles_139} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_279 = _loginfo_cycles_T_278[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_140; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_280 = {1'h0, loginfo_cycles_140} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_281 = _loginfo_cycles_T_280[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_141; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_282 = {1'h0, loginfo_cycles_141} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_283 = _loginfo_cycles_T_282[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_142; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_284 = {1'h0, loginfo_cycles_142} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_285 = _loginfo_cycles_T_284[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_143; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_286 = {1'h0, loginfo_cycles_143} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_287 = _loginfo_cycles_T_286[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_144; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_288 = {1'h0, loginfo_cycles_144} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_289 = _loginfo_cycles_T_288[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_145; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_290 = {1'h0, loginfo_cycles_145} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_291 = _loginfo_cycles_T_290[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_146; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_292 = {1'h0, loginfo_cycles_146} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_293 = _loginfo_cycles_T_292[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_147; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_294 = {1'h0, loginfo_cycles_147} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_295 = _loginfo_cycles_T_294[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_148; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_296 = {1'h0, loginfo_cycles_148} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_297 = _loginfo_cycles_T_296[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_149; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_298 = {1'h0, loginfo_cycles_149} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_299 = _loginfo_cycles_T_298[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_150; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_300 = {1'h0, loginfo_cycles_150} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_301 = _loginfo_cycles_T_300[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_151; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_302 = {1'h0, loginfo_cycles_151} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_303 = _loginfo_cycles_T_302[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_152; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_304 = {1'h0, loginfo_cycles_152} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_305 = _loginfo_cycles_T_304[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_153; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_306 = {1'h0, loginfo_cycles_153} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_307 = _loginfo_cycles_T_306[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_154; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_308 = {1'h0, loginfo_cycles_154} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_309 = _loginfo_cycles_T_308[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_155; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_310 = {1'h0, loginfo_cycles_155} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_311 = _loginfo_cycles_T_310[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_156; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_312 = {1'h0, loginfo_cycles_156} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_313 = _loginfo_cycles_T_312[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_157; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_314 = {1'h0, loginfo_cycles_157} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_315 = _loginfo_cycles_T_314[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_158; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_316 = {1'h0, loginfo_cycles_158} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_317 = _loginfo_cycles_T_316[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_159; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_318 = {1'h0, loginfo_cycles_159} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_319 = _loginfo_cycles_T_318[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_160; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_320 = {1'h0, loginfo_cycles_160} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_321 = _loginfo_cycles_T_320[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_161; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_322 = {1'h0, loginfo_cycles_161} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_323 = _loginfo_cycles_T_322[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_162; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_324 = {1'h0, loginfo_cycles_162} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_325 = _loginfo_cycles_T_324[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_163; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_326 = {1'h0, loginfo_cycles_163} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_327 = _loginfo_cycles_T_326[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_164; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_328 = {1'h0, loginfo_cycles_164} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_329 = _loginfo_cycles_T_328[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_165; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_330 = {1'h0, loginfo_cycles_165} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_331 = _loginfo_cycles_T_330[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_166; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_332 = {1'h0, loginfo_cycles_166} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_333 = _loginfo_cycles_T_332[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_167; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_334 = {1'h0, loginfo_cycles_167} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_335 = _loginfo_cycles_T_334[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_168; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_336 = {1'h0, loginfo_cycles_168} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_337 = _loginfo_cycles_T_336[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_169; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_338 = {1'h0, loginfo_cycles_169} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_339 = _loginfo_cycles_T_338[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_170; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_340 = {1'h0, loginfo_cycles_170} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_341 = _loginfo_cycles_T_340[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_171; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_342 = {1'h0, loginfo_cycles_171} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_343 = _loginfo_cycles_T_342[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_172; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_344 = {1'h0, loginfo_cycles_172} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_345 = _loginfo_cycles_T_344[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_173; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_346 = {1'h0, loginfo_cycles_173} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_347 = _loginfo_cycles_T_346[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_174; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_348 = {1'h0, loginfo_cycles_174} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_349 = _loginfo_cycles_T_348[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_175; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_350 = {1'h0, loginfo_cycles_175} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_351 = _loginfo_cycles_T_350[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_176; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_352 = {1'h0, loginfo_cycles_176} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_353 = _loginfo_cycles_T_352[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_177; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_354 = {1'h0, loginfo_cycles_177} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_355 = _loginfo_cycles_T_354[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_178; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_356 = {1'h0, loginfo_cycles_178} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_357 = _loginfo_cycles_T_356[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_179; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_358 = {1'h0, loginfo_cycles_179} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_359 = _loginfo_cycles_T_358[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_180; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_360 = {1'h0, loginfo_cycles_180} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_361 = _loginfo_cycles_T_360[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_181; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_362 = {1'h0, loginfo_cycles_181} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_363 = _loginfo_cycles_T_362[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_182; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_364 = {1'h0, loginfo_cycles_182} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_365 = _loginfo_cycles_T_364[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_183; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_366 = {1'h0, loginfo_cycles_183} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_367 = _loginfo_cycles_T_366[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_184; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_368 = {1'h0, loginfo_cycles_184} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_369 = _loginfo_cycles_T_368[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_185; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_370 = {1'h0, loginfo_cycles_185} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_371 = _loginfo_cycles_T_370[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_186; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_372 = {1'h0, loginfo_cycles_186} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_373 = _loginfo_cycles_T_372[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_187; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_374 = {1'h0, loginfo_cycles_187} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_375 = _loginfo_cycles_T_374[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_188; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_376 = {1'h0, loginfo_cycles_188} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_377 = _loginfo_cycles_T_376[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_189; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_378 = {1'h0, loginfo_cycles_189} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_379 = _loginfo_cycles_T_378[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_190; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_380 = {1'h0, loginfo_cycles_190} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_381 = _loginfo_cycles_T_380[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_191; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_382 = {1'h0, loginfo_cycles_191} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_383 = _loginfo_cycles_T_382[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_192; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_384 = {1'h0, loginfo_cycles_192} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_385 = _loginfo_cycles_T_384[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_193; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_386 = {1'h0, loginfo_cycles_193} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_387 = _loginfo_cycles_T_386[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_194; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_388 = {1'h0, loginfo_cycles_194} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_389 = _loginfo_cycles_T_388[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_195; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_390 = {1'h0, loginfo_cycles_195} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_391 = _loginfo_cycles_T_390[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_196; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_392 = {1'h0, loginfo_cycles_196} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_393 = _loginfo_cycles_T_392[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_197; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_394 = {1'h0, loginfo_cycles_197} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_395 = _loginfo_cycles_T_394[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_198; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_396 = {1'h0, loginfo_cycles_198} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_397 = _loginfo_cycles_T_396[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_199; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_398 = {1'h0, loginfo_cycles_199} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_399 = _loginfo_cycles_T_398[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_200; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_400 = {1'h0, loginfo_cycles_200} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_401 = _loginfo_cycles_T_400[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_201; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_402 = {1'h0, loginfo_cycles_201} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_403 = _loginfo_cycles_T_402[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_202; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_404 = {1'h0, loginfo_cycles_202} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_405 = _loginfo_cycles_T_404[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_203; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_406 = {1'h0, loginfo_cycles_203} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_407 = _loginfo_cycles_T_406[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_204; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_408 = {1'h0, loginfo_cycles_204} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_409 = _loginfo_cycles_T_408[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_205; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_410 = {1'h0, loginfo_cycles_205} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_411 = _loginfo_cycles_T_410[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_206; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_412 = {1'h0, loginfo_cycles_206} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_413 = _loginfo_cycles_T_412[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_207; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_414 = {1'h0, loginfo_cycles_207} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_415 = _loginfo_cycles_T_414[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_208; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_416 = {1'h0, loginfo_cycles_208} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_417 = _loginfo_cycles_T_416[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_209; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_418 = {1'h0, loginfo_cycles_209} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_419 = _loginfo_cycles_T_418[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_210; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_420 = {1'h0, loginfo_cycles_210} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_421 = _loginfo_cycles_T_420[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_211; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_422 = {1'h0, loginfo_cycles_211} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_423 = _loginfo_cycles_T_422[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_212; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_424 = {1'h0, loginfo_cycles_212} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_425 = _loginfo_cycles_T_424[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_213; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_426 = {1'h0, loginfo_cycles_213} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_427 = _loginfo_cycles_T_426[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_214; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_428 = {1'h0, loginfo_cycles_214} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_429 = _loginfo_cycles_T_428[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_217( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [15:0] c_sizes_set = 16'h0; // @[Monitor.scala:741:34] wire [7:0] c_opcodes_set = 8'h0; // @[Monitor.scala:740:34] wire [1:0] c_set = 2'h0; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready = 2'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _T_1357 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1357; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1357; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1430 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1430; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1430; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1430; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1357 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1283 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1283 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1283 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1283 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1283 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1329 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1329 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_1298 = _T_1430 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1298 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1298 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1298 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1401 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1401 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_1383 = _T_1430 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1383 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1383 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1383 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels / // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /* Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) \| t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }	module NoCMonitor_3( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth2 - 1)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) \|\| (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf \|\| io.b.isInf val notNaN_isZeroOut = io.a.isZero \|\| io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth2 - 1, 0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.invalidExc := isSigNaNRawFloat(io.a) \|\| isSigNaNRawFloat(io.b) \|\| notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN \|\| io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module MulRecFN_29( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_29 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_96 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_149( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_166 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncQueue( // @[AsyncQueue.scala:226:7] input io_enq_clock, // @[AsyncQueue.scala:227:14] input io_enq_reset, // @[AsyncQueue.scala:227:14] output io_enq_ready, // @[AsyncQueue.scala:227:14] input io_enq_valid, // @[AsyncQueue.scala:227:14] input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:227:14] input io_deq_clock, // @[AsyncQueue.scala:227:14] input io_deq_reset, // @[AsyncQueue.scala:227:14] input io_deq_ready, // @[AsyncQueue.scala:227:14] output io_deq_valid, // @[AsyncQueue.scala:227:14] output [31:0] io_deq_bits_phit // @[AsyncQueue.scala:227:14] ); wire [3:0] _sink_io_async_ridx; // @[AsyncQueue.scala:229:70] wire _sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala:229:70] wire _sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala:229:70] wire [31:0] _source_io_async_mem_0_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_1_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_2_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_3_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_4_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_5_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_6_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_7_phit; // @[AsyncQueue.scala:228:70] wire [3:0] _source_io_async_widx; // @[AsyncQueue.scala:228:70] wire _source_io_async_safe_widx_valid; // @[AsyncQueue.scala:228:70] wire _source_io_async_safe_source_reset_n; // @[AsyncQueue.scala:228:70] AsyncQueueSource_Phit source ( // @[AsyncQueue.scala:228:70] .clock (io_enq_clock), .reset (io_enq_reset), .io_enq_ready (io_enq_ready), .io_enq_valid (io_enq_valid), .io_enq_bits_phit (io_enq_bits_phit), .io_async_mem_0_phit (_source_io_async_mem_0_phit), .io_async_mem_1_phit (_source_io_async_mem_1_phit), .io_async_mem_2_phit (_source_io_async_mem_2_phit), .io_async_mem_3_phit (_source_io_async_mem_3_phit), .io_async_mem_4_phit (_source_io_async_mem_4_phit), .io_async_mem_5_phit (_source_io_async_mem_5_phit), .io_async_mem_6_phit (_source_io_async_mem_6_phit), .io_async_mem_7_phit (_source_io_async_mem_7_phit), .io_async_ridx (_sink_io_async_ridx), // @[AsyncQueue.scala:229:70] .io_async_widx (_source_io_async_widx), .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), // @[AsyncQueue.scala:229:70] .io_async_safe_widx_valid (_source_io_async_safe_widx_valid), .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) // @[AsyncQueue.scala:229:70] ); // @[AsyncQueue.scala:228:70] AsyncQueueSink_Phit sink ( // @[AsyncQueue.scala:229:70] .clock (io_deq_clock), .reset (io_deq_reset), .io_deq_ready (io_deq_ready), .io_deq_valid (io_deq_valid), .io_deq_bits_phit (io_deq_bits_phit), .io_async_mem_0_phit (_source_io_async_mem_0_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_1_phit (_source_io_async_mem_1_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_2_phit (_source_io_async_mem_2_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_3_phit (_source_io_async_mem_3_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_4_phit (_source_io_async_mem_4_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_5_phit (_source_io_async_mem_5_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_6_phit (_source_io_async_mem_6_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_7_phit (_source_io_async_mem_7_phit), // @[AsyncQueue.scala:228:70] .io_async_ridx (_sink_io_async_ridx), .io_async_widx (_source_io_async_widx), // @[AsyncQueue.scala:228:70] .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), .io_async_safe_widx_valid (_source_io_async_safe_widx_valid), // @[AsyncQueue.scala:228:70] .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), // @[AsyncQueue.scala:228:70] .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) ); // @[AsyncQueue.scala:229:70] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_34( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_38 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_93( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. / class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module TLXbar_MasterXbar_BoomTile_i2_o1_a32d64s3k3z4c( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire [2:0] out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [2:0] in_0_c_bits_source; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_ready_0 = auto_anon_in_0_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_valid_0 = auto_anon_in_0_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_opcode_0 = auto_anon_in_0_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_param_0 = auto_anon_in_0_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_c_bits_size_0 = auto_anon_in_0_c_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_c_bits_source_0 = auto_anon_in_0_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_c_bits_address_0 = auto_anon_in_0_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_c_bits_data_0 = auto_anon_in_0_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_valid_0 = auto_anon_in_0_e_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_e_bits_sink_0 = auto_anon_in_0_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_b_valid_0 = auto_anon_out_b_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_b_bits_opcode_0 = auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_b_bits_param_0 = auto_anon_out_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_b_bits_size_0 = auto_anon_out_b_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_b_bits_source_0 = auto_anon_out_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_b_bits_address_0 = auto_anon_out_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_b_bits_mask_0 = auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_b_bits_data_0 = auto_anon_out_b_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_b_bits_corrupt_0 = auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_c_ready_0 = auto_anon_out_c_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_e_ready_0 = auto_anon_out_e_ready; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = 3'h4; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_source = 3'h4; // @[Xbar.scala:159:18] wire [2:0] _in_1_a_bits_source_T = 3'h4; // @[Xbar.scala:166:55] wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h4; // @[Xbar.scala:352:24] wire [2:0] portsAOI_filtered_1_0_bits_source = 3'h4; // @[Xbar.scala:352:24] wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_b_bits_source = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_source = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_e_bits_sink = 3'h0; // @[Xbar.scala:159:18] wire [2:0] _requestEIO_uncommonBits_T_1 = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestEIO_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_source = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_1_0_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_anon_in_1_a_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] in_1_a_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24] wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_valid = 1'h0; // @[Xbar.scala:159:18] wire out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire beatsAI_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _out_0_a_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire [7:0] auto_anon_in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:74:9] wire [7:0] anonIn_1_a_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:159:18] wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24] wire [63:0] auto_anon_in_1_a_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_a_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] in_1_a_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] in_1_b_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] in_1_c_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] portsAOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _out_0_a_bits_T_4 = 64'h0; // @[Mux.scala:30:73] wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire in_1_b_ready = 1'h1; // @[Xbar.scala:159:18] wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _beatsAI_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [8:0] beatsAI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69] wire [31:0] in_1_b_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] in_1_c_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [3:0] in_1_b_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_1_c_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [8:0] beatsAI_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] _beatsAI_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _beatsAI_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [7:0] in_1_b_bits_mask = 8'h0; // @[Xbar.scala:159:18] wire [1:0] in_1_b_bits_param = 2'h0; // @[Xbar.scala:159:18] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_b_ready = auto_anon_in_0_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_c_ready; // @[MixedNode.scala:551:17] wire anonIn_c_valid = auto_anon_in_0_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_opcode = auto_anon_in_0_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_param = auto_anon_in_0_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_c_bits_size = auto_anon_in_0_c_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_c_bits_source = auto_anon_in_0_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_c_bits_address = auto_anon_in_0_c_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_c_bits_data = auto_anon_in_0_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_e_ready; // @[MixedNode.scala:551:17] wire anonIn_e_valid = auto_anon_in_0_e_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_e_bits_sink = auto_anon_in_0_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_b_ready; // @[MixedNode.scala:542:17] wire anonOut_b_valid = auto_anon_out_b_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_b_bits_opcode = auto_anon_out_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_b_bits_param = auto_anon_out_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_b_bits_size = auto_anon_out_b_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_b_bits_source = auto_anon_out_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonOut_b_bits_address = auto_anon_out_b_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonOut_b_bits_mask = auto_anon_out_b_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_b_bits_data = auto_anon_out_b_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_b_bits_corrupt = auto_anon_out_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_c_ready = auto_anon_out_c_ready_0; // @[Xbar.scala:74:9] wire anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_e_ready = auto_anon_out_e_ready_0; // @[Xbar.scala:74:9] wire anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_b_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_b_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_b_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_b_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_b_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_c_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_c_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_c_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_c_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_e_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_out_e_valid_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [1:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_b_ready = anonIn_b_ready; // @[Xbar.scala:159:18] wire in_0_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_valid_0 = anonIn_b_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_b_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_opcode_0 = anonIn_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_param_0 = anonIn_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_b_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_size_0 = anonIn_b_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_b_bits_source_0 = anonIn_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_0_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_address_0 = anonIn_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_0_b_bits_mask; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_mask_0 = anonIn_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_0_b_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_data_0 = anonIn_b_bits_data; // @[Xbar.scala:74:9] wire in_0_b_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_corrupt_0 = anonIn_b_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_c_ready_0 = anonIn_c_ready; // @[Xbar.scala:74:9] wire in_0_c_valid = anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_opcode = anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_param = anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_c_bits_size = anonIn_c_bits_size; // @[Xbar.scala:159:18] wire [1:0] _in_0_c_bits_source_T = anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] in_0_c_bits_address = anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [63:0] in_0_c_bits_data = anonIn_c_bits_data; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_e_ready_0 = anonIn_e_ready; // @[Xbar.scala:74:9] wire in_0_e_valid = anonIn_e_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_e_bits_sink = anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_b_ready; // @[Xbar.scala:216:19] assign auto_anon_out_b_ready_0 = anonOut_b_ready; // @[Xbar.scala:74:9] wire out_0_b_valid = anonOut_b_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_b_bits_opcode = anonOut_b_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_b_bits_param = anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_b_bits_size = anonOut_b_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_0_b_bits_source = anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] out_0_b_bits_address = anonOut_b_bits_address; // @[Xbar.scala:216:19] wire [7:0] out_0_b_bits_mask = anonOut_b_bits_mask; // @[Xbar.scala:216:19] wire [63:0] out_0_b_bits_data = anonOut_b_bits_data; // @[Xbar.scala:216:19] wire out_0_b_bits_corrupt = anonOut_b_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_c_ready = anonOut_c_ready; // @[Xbar.scala:216:19] wire out_0_c_valid; // @[Xbar.scala:216:19] assign auto_anon_out_c_valid_0 = anonOut_c_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_opcode_0 = anonOut_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_param_0 = anonOut_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_c_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_size_0 = anonOut_c_bits_size; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_source_0 = anonOut_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_c_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_address_0 = anonOut_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] out_0_c_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_data_0 = anonOut_c_bits_data; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_e_ready = anonOut_e_ready; // @[Xbar.scala:216:19] wire out_0_e_valid; // @[Xbar.scala:216:19] assign auto_anon_out_e_valid_0 = anonOut_e_valid; // @[Xbar.scala:74:9] wire [2:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign auto_anon_out_e_bits_sink_0 = anonOut_e_bits_sink; // @[Xbar.scala:74:9] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_ready = in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_b_valid = in_0_b_valid; // @[Xbar.scala:159:18] wire [2:0] portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_b_bits_opcode = in_0_b_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_b_bits_param = in_0_b_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_b_bits_size = in_0_b_bits_size; // @[Xbar.scala:159:18] wire [2:0] portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign anonIn_b_bits_address = in_0_b_bits_address; // @[Xbar.scala:159:18] wire [7:0] portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24] assign anonIn_b_bits_mask = in_0_b_bits_mask; // @[Xbar.scala:159:18] wire [63:0] portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_b_bits_data = in_0_b_bits_data; // @[Xbar.scala:159:18] wire portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_b_bits_corrupt = in_0_b_bits_corrupt; // @[Xbar.scala:159:18] wire portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_c_ready = in_0_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_1 = in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_0_bits_opcode = in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_0_bits_param = in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_0_bits_size = in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_0_bits_source = in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T = in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_0_bits_address = in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsCOI_filtered_0_bits_data = in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [2:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsEOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_e_ready = in_0_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_0_valid_T_1 = in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] _requestEIO_uncommonBits_T = in_0_e_bits_sink; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_0_bits_sink = in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire [2:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire [2:0] in_0_b_bits_source; // @[Xbar.scala:159:18] wire [2:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [2:0] in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_b_bits_source_T = in_0_b_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign in_0_c_bits_source = {1'h0, _in_0_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_b_ready = out_0_b_ready; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsBIO_filtered_1_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsBIO_filtered_1_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [2:0] _requestBOI_uncommonBits_T = out_0_b_bits_source; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsBIO_filtered_1_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsBIO_filtered_1_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] wire [7:0] portsBIO_filtered_1_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsBIO_filtered_1_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsBIO_filtered_1_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_ready = out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_c_valid = out_0_c_valid; // @[Xbar.scala:216:19] assign anonOut_c_bits_opcode = out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_c_bits_param = out_0_c_bits_param; // @[Xbar.scala:216:19] assign anonOut_c_bits_size = out_0_c_bits_size; // @[Xbar.scala:216:19] assign anonOut_c_bits_source = out_0_c_bits_source; // @[Xbar.scala:216:19] assign anonOut_c_bits_address = out_0_c_bits_address; // @[Xbar.scala:216:19] assign anonOut_c_bits_data = out_0_c_bits_data; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [2:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_ready = out_0_e_ready; // @[Xbar.scala:216:19, :352:24] wire portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_e_valid = out_0_e_valid; // @[Xbar.scala:216:19] assign _anonOut_e_bits_sink_T = out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_1 = {1'h0, _requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire [1:0] requestBOI_uncommonBits = _requestBOI_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T = out_0_b_bits_source[2]; // @[Xbar.scala:216:19] wire _requestBOI_T_1 = ~_requestBOI_T; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_3 = _requestBOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestBOI_0_0 = _requestBOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_0_valid_T = requestBOI_0_0; // @[Xbar.scala:355:54] wire requestBOI_0_1 = out_0_b_bits_source == 3'h4; // @[Xbar.scala:216:19] wire _portsBIO_filtered_1_valid_T = requestBOI_0_1; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[2]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = out_0_d_bits_source == 3'h4; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73] wire [2:0] requestEIO_uncommonBits = _requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsBO_decode_T = 27'hFFF << out_0_b_bits_size; // @[package.scala:243:71] wire [11:0] _beatsBO_decode_T_1 = _beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsBO_decode_T_2 = ~_beatsBO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsBO_decode = _beatsBO_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsBO_opdata_T = out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19] wire beatsBO_opdata = ~_beatsBO_opdata_T; // @[Edges.scala:97:{28,37}] wire [26:0] _beatsCI_decode_T = 27'hFFF << in_0_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_1 = _beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_2 = ~_beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsCI_decode = _beatsCI_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsCI_opdata = in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [8:0] beatsCI_0 = beatsCI_opdata ? beatsCI_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_b_valid = portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_opcode = portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_param = portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_size = portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_source = portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_address = portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_mask = portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_data = portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_corrupt = portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsBIO_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsBIO_filtered_0_valid_T_1 = out_0_b_valid & _portsBIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_0_valid = _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_1_valid_T_1 = out_0_b_valid & _portsBIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_valid = _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_out_0_b_ready_T = requestBOI_0_0 & portsBIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_2 = _portsBIO_out_0_b_ready_T; // @[Mux.scala:30:73] assign _portsBIO_out_0_b_ready_WIRE = _portsBIO_out_0_b_ready_T_2; // @[Mux.scala:30:73] assign out_0_b_ready = _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign in_0_c_ready = portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_c_valid = portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_opcode = portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_param = portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_size = portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_source = portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_address = portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_data = portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_valid = _portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T \| _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign in_0_e_ready = portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_e_valid = portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_e_bits_sink = portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_valid = _portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid \| portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_451( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_444( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid \|\| io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }	module PriorityQueueStage_66( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops }	module BranchKillableQueue_7( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [39:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [7:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [39:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [7:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:463:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:463:14] input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:463:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:463:14] input io_brupdate_b2_uop_is_rvc, // @[util.scala:463:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_0, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_1, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_2, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_3, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_0, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_1, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_2, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_3, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_4, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_5, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_6, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_7, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_8, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_9, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_issued, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:463:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:463:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:463:14] input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:463:14] input io_brupdate_b2_uop_is_sfb, // @[util.scala:463:14] input io_brupdate_b2_uop_is_fence, // @[util.scala:463:14] input io_brupdate_b2_uop_is_fencei, // @[util.scala:463:14] input io_brupdate_b2_uop_is_sfence, // @[util.scala:463:14] input io_brupdate_b2_uop_is_amo, // @[util.scala:463:14] input io_brupdate_b2_uop_is_eret, // @[util.scala:463:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_brupdate_b2_uop_is_rocc, // @[util.scala:463:14] input io_brupdate_b2_uop_is_mov, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:463:14] input io_brupdate_b2_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:463:14] input io_brupdate_b2_uop_taken, // @[util.scala:463:14] input io_brupdate_b2_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:463:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:463:14] input io_brupdate_b2_uop_prs1_busy, // @[util.scala:463:14] input io_brupdate_b2_uop_prs2_busy, // @[util.scala:463:14] input io_brupdate_b2_uop_prs3_busy, // @[util.scala:463:14] input io_brupdate_b2_uop_ppred_busy, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:463:14] input io_brupdate_b2_uop_exception, // @[util.scala:463:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:463:14] input io_brupdate_b2_uop_mem_signed, // @[util.scala:463:14] input io_brupdate_b2_uop_uses_ldq, // @[util.scala:463:14] input io_brupdate_b2_uop_uses_stq, // @[util.scala:463:14] input io_brupdate_b2_uop_is_unique, // @[util.scala:463:14] input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:463:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:463:14] input io_brupdate_b2_uop_frs3_en, // @[util.scala:463:14] input io_brupdate_b2_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_val, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:463:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:463:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:463:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:463:14] input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:463:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:463:14] input io_brupdate_b2_mispredict, // @[util.scala:463:14] input io_brupdate_b2_taken, // @[util.scala:463:14] input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:463:14] input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:463:14] input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:463:14] input [20:0] io_brupdate_b2_target_offset, // @[util.scala:463:14] input io_flush, // @[util.scala:463:14] output io_empty // @[util.scala:463:14] ); wire _main_io_deq_valid; // @[util.scala:476:22] wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22] wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22] wire [39:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22] wire [15:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22] wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22] wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22] wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22] wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22] wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22] wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22] wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22] wire [39:0] _main_io_deq_bits_addr; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22] wire _main_io_deq_bits_is_hella; // @[util.scala:476:22] wire _main_io_deq_bits_tag_match; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22] wire [19:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22] wire [7:0] _main_io_deq_bits_way_en; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22] wire _main_io_empty; // @[util.scala:476:22] wire [3:0] _main_io_count; // @[util.scala:476:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [7:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:458:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:458:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:458:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:458:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:458:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:458:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:458:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:458:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:458:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:458:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:458:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:458:7] wire io_flush_0 = io_flush; // @[util.scala:458:7] wire _io_empty_T_1; // @[util.scala:484:31] wire [3:0] _io_count_T_1; // @[util.scala:485:31] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [39:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [7:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count; // @[util.scala:458:7] reg [31:0] out_reg_uop_inst; // @[util.scala:477:22] reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22] reg out_reg_uop_is_rvc; // @[util.scala:477:22] reg [39:0] out_reg_uop_debug_pc; // @[util.scala:477:22] reg out_reg_uop_iq_type_0; // @[util.scala:477:22] reg out_reg_uop_iq_type_1; // @[util.scala:477:22] reg out_reg_uop_iq_type_2; // @[util.scala:477:22] reg out_reg_uop_iq_type_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_0; // @[util.scala:477:22] reg out_reg_uop_fu_code_1; // @[util.scala:477:22] reg out_reg_uop_fu_code_2; // @[util.scala:477:22] reg out_reg_uop_fu_code_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_4; // @[util.scala:477:22] reg out_reg_uop_fu_code_5; // @[util.scala:477:22] reg out_reg_uop_fu_code_6; // @[util.scala:477:22] reg out_reg_uop_fu_code_7; // @[util.scala:477:22] reg out_reg_uop_fu_code_8; // @[util.scala:477:22] reg out_reg_uop_fu_code_9; // @[util.scala:477:22] reg out_reg_uop_iw_issued; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22] reg [2:0] out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22] reg [2:0] out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22] reg [2:0] out_reg_uop_dis_col_sel; // @[util.scala:477:22] reg [15:0] out_reg_uop_br_mask; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_tag; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22] reg out_reg_uop_is_sfb; // @[util.scala:477:22] reg out_reg_uop_is_fence; // @[util.scala:477:22] reg out_reg_uop_is_fencei; // @[util.scala:477:22] reg out_reg_uop_is_sfence; // @[util.scala:477:22] reg out_reg_uop_is_amo; // @[util.scala:477:22] reg out_reg_uop_is_eret; // @[util.scala:477:22] reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22] reg out_reg_uop_is_rocc; // @[util.scala:477:22] reg out_reg_uop_is_mov; // @[util.scala:477:22] reg [4:0] out_reg_uop_ftq_idx; // @[util.scala:477:22] reg out_reg_uop_edge_inst; // @[util.scala:477:22] reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22] reg out_reg_uop_taken; // @[util.scala:477:22] reg out_reg_uop_imm_rename; // @[util.scala:477:22] reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22] reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22] reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22] reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22] reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22] reg [6:0] out_reg_uop_rob_idx; // @[util.scala:477:22] reg [4:0] out_reg_uop_ldq_idx; // @[util.scala:477:22] reg [4:0] out_reg_uop_stq_idx; // @[util.scala:477:22] reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22] reg [6:0] out_reg_uop_pdst; // @[util.scala:477:22] reg [6:0] out_reg_uop_prs1; // @[util.scala:477:22] reg [6:0] out_reg_uop_prs2; // @[util.scala:477:22] reg [6:0] out_reg_uop_prs3; // @[util.scala:477:22] reg [4:0] out_reg_uop_ppred; // @[util.scala:477:22] reg out_reg_uop_prs1_busy; // @[util.scala:477:22] reg out_reg_uop_prs2_busy; // @[util.scala:477:22] reg out_reg_uop_prs3_busy; // @[util.scala:477:22] reg out_reg_uop_ppred_busy; // @[util.scala:477:22] reg [6:0] out_reg_uop_stale_pdst; // @[util.scala:477:22] reg out_reg_uop_exception; // @[util.scala:477:22] reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22] reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22] reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22] reg out_reg_uop_mem_signed; // @[util.scala:477:22] reg out_reg_uop_uses_ldq; // @[util.scala:477:22] reg out_reg_uop_uses_stq; // @[util.scala:477:22] reg out_reg_uop_is_unique; // @[util.scala:477:22] reg out_reg_uop_flush_on_commit; // @[util.scala:477:22] reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22] reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22] reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22] reg out_reg_uop_frs3_en; // @[util.scala:477:22] reg out_reg_uop_fcn_dw; // @[util.scala:477:22] reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22] reg out_reg_uop_fp_val; // @[util.scala:477:22] reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22] reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22] reg out_reg_uop_bp_debug_if; // @[util.scala:477:22] reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22] reg [39:0] out_reg_addr; // @[util.scala:477:22] assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22] reg [63:0] out_reg_data; // @[util.scala:477:22] assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22] reg out_reg_is_hella; // @[util.scala:477:22] assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22] reg out_reg_tag_match; // @[util.scala:477:22] assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22] assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22] reg [19:0] out_reg_old_meta_tag; // @[util.scala:477:22] assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22] reg [7:0] out_reg_way_en; // @[util.scala:477:22] assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22] reg [4:0] out_reg_sdq_id; // @[util.scala:477:22] assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22] reg out_valid; // @[util.scala:478:28] assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28] reg [31:0] out_uop_inst; // @[util.scala:479:22] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22] reg [31:0] out_uop_debug_inst; // @[util.scala:479:22] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22] reg out_uop_is_rvc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22] reg [39:0] out_uop_debug_pc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22] wire [39:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_0; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_1; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_2; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_3; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_0; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_1; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_2; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_3; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_4; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_5; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_6; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_7; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_8; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_9; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_iw_p1_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_iw_p2_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_dis_col_sel; // @[util.scala:479:22] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22] reg [15:0] out_uop_br_mask; // @[util.scala:479:22] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22] reg [3:0] out_uop_br_tag; // @[util.scala:479:22] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_type; // @[util.scala:479:22] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22] reg out_uop_is_sfb; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22] reg out_uop_is_fence; // @[util.scala:479:22] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22] reg out_uop_is_fencei; // @[util.scala:479:22] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22] reg out_uop_is_sfence; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22] reg out_uop_is_amo; // @[util.scala:479:22] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22] wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22] reg out_uop_is_eret; // @[util.scala:479:22] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22] wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22] reg out_uop_is_sys_pc2epc; // @[util.scala:479:22] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22] reg out_uop_is_rocc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22] reg out_uop_is_mov; // @[util.scala:479:22] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22] wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_ftq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22] reg out_uop_edge_inst; // @[util.scala:479:22] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22] wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pc_lob; // @[util.scala:479:22] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22] reg out_uop_taken; // @[util.scala:479:22] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22] wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22] reg out_uop_imm_rename; // @[util.scala:479:22] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22] wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_imm_sel; // @[util.scala:479:22] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_pimm; // @[util.scala:479:22] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22] reg [19:0] out_uop_imm_packed; // @[util.scala:479:22] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22] wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_op1_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_op2_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wen; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_toint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fma; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_div; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_vec; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_rob_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_ldq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_stq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_prs1; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_prs2; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_prs3; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_ppred; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22] reg out_uop_prs1_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs2_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs3_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22] reg out_uop_ppred_busy; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_stale_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22] reg out_uop_exception; // @[util.scala:479:22] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22] wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22] reg [63:0] out_uop_exc_cause; // @[util.scala:479:22] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22] wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_mem_size; // @[util.scala:479:22] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22] reg out_uop_mem_signed; // @[util.scala:479:22] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22] wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22] reg out_uop_uses_ldq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22] reg out_uop_uses_stq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22] reg out_uop_is_unique; // @[util.scala:479:22] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22] wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22] reg out_uop_flush_on_commit; // @[util.scala:479:22] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22] wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22] reg out_uop_ldst_is_rs1; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22] wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs1; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs2; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs3; // @[util.scala:479:22] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22] reg out_uop_frs3_en; // @[util.scala:479:22] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22] wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22] reg out_uop_fcn_dw; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22] wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_fcn_op; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22] reg out_uop_fp_val; // @[util.scala:479:22] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_fp_rm; // @[util.scala:479:22] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_typ; // @[util.scala:479:22] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_pf_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ae_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ma_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_debug_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_xcpt_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22] wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34] assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31] wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:476:22, :478:28, :485:31] assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31] assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31] wire [15:0] _out_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [15:0] out_uop_out_br_mask; // @[util.scala:104:23] wire [15:0] _out_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :458:7] assign _out_uop_out_br_mask_T_1 = out_uop_br_mask & _out_uop_out_br_mask_T; // @[util.scala:93:{25,27}, :479:22] assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire [15:0] _out_valid_T = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:126:51, :458:7, :479:22] wire _out_valid_T_1 = \|_out_valid_T; // @[util.scala:126:{51,59}] wire _out_valid_T_2 = _out_valid_T_1; // @[util.scala:61:61, :126:59] wire _out_valid_T_3 = ~_out_valid_T_2; // @[util.scala:61:61, :492:31] wire _out_valid_T_4 = out_valid & _out_valid_T_3; // @[util.scala:478:28, :492:{28,31}] wire _out_valid_T_5 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:458:7, :479:22, :492:94] wire _out_valid_T_6 = ~_out_valid_T_5; // @[util.scala:492:{83,94}] wire _out_valid_T_7 = _out_valid_T_4 & _out_valid_T_6; // @[util.scala:492:{28,80,83}] wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 \| ~out_valid; // @[Decoupled.scala:51:35] wire [15:0] _out_valid_T_8 = io_brupdate_b1_mispredict_mask_0 & _main_io_deq_bits_uop_br_mask; // @[util.scala:126:51, :458:7, :476:22] wire _out_valid_T_9 = \|_out_valid_T_8; // @[util.scala:126:{51,59}] wire _out_valid_T_10 = _out_valid_T_9; // @[util.scala:61:61, :126:59] wire _out_valid_T_11 = ~_out_valid_T_10; // @[util.scala:61:61, :496:41] wire _out_valid_T_12 = _main_io_deq_valid & _out_valid_T_11; // @[util.scala:476:22, :496:{38,41}] wire _out_valid_T_13 = io_flush_0 & _main_io_deq_bits_uop_uses_ldq; // @[util.scala:458:7, :476:22, :496:117] wire _out_valid_T_14 = ~_out_valid_T_13; // @[util.scala:496:{106,117}] wire _out_valid_T_15 = _out_valid_T_12 & _out_valid_T_14; // @[util.scala:496:{38,103,106}] wire [15:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25] wire out_uop_out_1_iq_type_0; // @[util.scala:104:23] wire out_uop_out_1_iq_type_1; // @[util.scala:104:23] wire out_uop_out_1_iq_type_2; // @[util.scala:104:23] wire out_uop_out_1_iq_type_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_0; // @[util.scala:104:23] wire out_uop_out_1_fu_code_1; // @[util.scala:104:23] wire out_uop_out_1_fu_code_2; // @[util.scala:104:23] wire out_uop_out_1_fu_code_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_4; // @[util.scala:104:23] wire out_uop_out_1_fu_code_5; // @[util.scala:104:23] wire out_uop_out_1_fu_code_6; // @[util.scala:104:23] wire out_uop_out_1_fu_code_7; // @[util.scala:104:23] wire out_uop_out_1_fu_code_8; // @[util.scala:104:23] wire out_uop_out_1_fu_code_9; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23] wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23] wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23] wire out_uop_out_1_is_rvc; // @[util.scala:104:23] wire [39:0] out_uop_out_1_debug_pc; // @[util.scala:104:23] wire out_uop_out_1_iw_issued; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23] wire [2:0] out_uop_out_1_dis_col_sel; // @[util.scala:104:23] wire [15:0] out_uop_out_1_br_mask; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_tag; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23] wire out_uop_out_1_is_sfb; // @[util.scala:104:23] wire out_uop_out_1_is_fence; // @[util.scala:104:23] wire out_uop_out_1_is_fencei; // @[util.scala:104:23] wire out_uop_out_1_is_sfence; // @[util.scala:104:23] wire out_uop_out_1_is_amo; // @[util.scala:104:23] wire out_uop_out_1_is_eret; // @[util.scala:104:23] wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23] wire out_uop_out_1_is_rocc; // @[util.scala:104:23] wire out_uop_out_1_is_mov; // @[util.scala:104:23] wire [4:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23] wire out_uop_out_1_edge_inst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23] wire out_uop_out_1_taken; // @[util.scala:104:23] wire out_uop_out_1_imm_rename; // @[util.scala:104:23] wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23] wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23] wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23] wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23] wire [6:0] out_uop_out_1_rob_idx; // @[util.scala:104:23] wire [4:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23] wire [4:0] out_uop_out_1_stq_idx; // @[util.scala:104:23] wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23] wire [6:0] out_uop_out_1_pdst; // @[util.scala:104:23] wire [6:0] out_uop_out_1_prs1; // @[util.scala:104:23] wire [6:0] out_uop_out_1_prs2; // @[util.scala:104:23] wire [6:0] out_uop_out_1_prs3; // @[util.scala:104:23] wire [4:0] out_uop_out_1_ppred; // @[util.scala:104:23] wire out_uop_out_1_prs1_busy; // @[util.scala:104:23] wire out_uop_out_1_prs2_busy; // @[util.scala:104:23] wire out_uop_out_1_prs3_busy; // @[util.scala:104:23] wire out_uop_out_1_ppred_busy; // @[util.scala:104:23] wire [6:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23] wire out_uop_out_1_exception; // @[util.scala:104:23] wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23] wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23] wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23] wire out_uop_out_1_mem_signed; // @[util.scala:104:23] wire out_uop_out_1_uses_ldq; // @[util.scala:104:23] wire out_uop_out_1_uses_stq; // @[util.scala:104:23] wire out_uop_out_1_is_unique; // @[util.scala:104:23] wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23] wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23] wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23] wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23] wire out_uop_out_1_frs3_en; // @[util.scala:104:23] wire out_uop_out_1_fcn_dw; // @[util.scala:104:23] wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23] wire out_uop_out_1_fp_val; // @[util.scala:104:23] wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23] wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23] wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23] wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23] wire [15:0] _out_uop_out_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :458:7] assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask & _out_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}, :476:22] assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] always @(posedge clock) begin // @[util.scala:458:7] if (main_io_deq_ready) begin // @[util.scala:495:23] out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22] out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22] out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22] out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22] out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22] out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22] out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22] out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22] out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22] out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22] out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22] out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22] out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22] out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22] out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22] out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22] out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22] out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22] out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22] out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22] out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22] out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22] out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22] out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22] out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22] out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22] out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22] out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22] out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22] out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22] out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22] out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22] out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22] out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22] out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22] out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22] out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22] out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22] out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22] out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22] out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22] out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22] out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22] out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22] out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22] out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22] out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22] out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22] out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22] out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22] out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22] out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22] out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22] end out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] if (reset) // @[util.scala:458:7] out_valid <= 1'h0; // @[util.scala:478:28] else // @[util.scala:458:7] out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}] always @(posedge) BranchKillableQueue_6 main ( // @[util.scala:476:22] .clock (clock), .reset (reset), .io_enq_ready (io_enq_ready_0), .io_enq_valid (io_enq_valid_0), // @[util.scala:458:7] .io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7] .io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7] .io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7] .io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7] .io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7] .io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7] .io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7] .io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7] .io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7] .io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7] .io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7] .io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7] .io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7] .io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7] .io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7] .io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7] .io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7] .io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7] .io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7] .io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7] .io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7] .io_deq_ready (main_io_deq_ready), // @[util.scala:495:23] .io_deq_valid (_main_io_deq_valid), .io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst), .io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst), .io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc), .io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc), .io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0), .io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1), .io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2), .io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3), .io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0), .io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1), .io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2), .io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3), .io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4), .io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5), .io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6), .io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7), .io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8), .io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9), .io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued), .io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen), .io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen), .io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child), .io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child), .io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint), .io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint), .io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint), .io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel), .io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask), .io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag), .io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type), .io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb), .io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence), .io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei), .io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence), .io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo), .io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret), .io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc), .io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc), .io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov), .io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx), .io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst), .io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob), .io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken), .io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename), .io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel), .io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm), .io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed), .io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel), .io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel), .io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst), .io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen), .io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1), .io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2), .io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3), .io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12), .io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23), .io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn), .io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut), .io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint), .io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint), .io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe), .io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma), .io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div), .io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt), .io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags), .io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec), .io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx), .io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx), .io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx), .io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx), .io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst), .io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1), .io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2), .io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3), .io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred), .io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy), .io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy), .io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy), .io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy), .io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst), .io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception), .io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause), .io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd), .io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size), .io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed), .io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq), .io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq), .io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique), .io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit), .io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd), .io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1), .io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst), .io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1), .io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2), .io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3), .io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype), .io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype), .io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype), .io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en), .io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw), .io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op), .io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val), .io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm), .io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ), .io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if), .io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if), .io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if), .io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if), .io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if), .io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc), .io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc), .io_deq_bits_addr (_main_io_deq_bits_addr), .io_deq_bits_data (_main_io_deq_bits_data), .io_deq_bits_is_hella (_main_io_deq_bits_is_hella), .io_deq_bits_tag_match (_main_io_deq_bits_tag_match), .io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state), .io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag), .io_deq_bits_way_en (_main_io_deq_bits_way_en), .io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id), .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask_0), // @[util.scala:458:7] .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask_0), // @[util.scala:458:7] .io_brupdate_b2_uop_inst (io_brupdate_b2_uop_inst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_debug_inst (io_brupdate_b2_uop_debug_inst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_rvc (io_brupdate_b2_uop_is_rvc_0), // @[util.scala:458:7] .io_brupdate_b2_uop_debug_pc (io_brupdate_b2_uop_debug_pc_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iq_type_0 (io_brupdate_b2_uop_iq_type_0_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iq_type_1 (io_brupdate_b2_uop_iq_type_1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iq_type_2 (io_brupdate_b2_uop_iq_type_2_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iq_type_3 (io_brupdate_b2_uop_iq_type_3_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_0 (io_brupdate_b2_uop_fu_code_0_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_1 (io_brupdate_b2_uop_fu_code_1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_2 (io_brupdate_b2_uop_fu_code_2_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_3 (io_brupdate_b2_uop_fu_code_3_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_4 (io_brupdate_b2_uop_fu_code_4_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_5 (io_brupdate_b2_uop_fu_code_5_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_6 (io_brupdate_b2_uop_fu_code_6_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_7 (io_brupdate_b2_uop_fu_code_7_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_8 (io_brupdate_b2_uop_fu_code_8_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_9 (io_brupdate_b2_uop_fu_code_9_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_issued (io_brupdate_b2_uop_iw_issued_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_issued_partial_agen (io_brupdate_b2_uop_iw_issued_partial_agen_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_issued_partial_dgen (io_brupdate_b2_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_p1_speculative_child (io_brupdate_b2_uop_iw_p1_speculative_child_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_p2_speculative_child (io_brupdate_b2_uop_iw_p2_speculative_child_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_p1_bypass_hint (io_brupdate_b2_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_p2_bypass_hint (io_brupdate_b2_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_p3_bypass_hint (io_brupdate_b2_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7] .io_brupdate_b2_uop_dis_col_sel (io_brupdate_b2_uop_dis_col_sel_0), // @[util.scala:458:7] .io_brupdate_b2_uop_br_mask (io_brupdate_b2_uop_br_mask_0), // @[util.scala:458:7] .io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag_0), // @[util.scala:458:7] .io_brupdate_b2_uop_br_type (io_brupdate_b2_uop_br_type_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_sfb (io_brupdate_b2_uop_is_sfb_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_fence (io_brupdate_b2_uop_is_fence_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_fencei (io_brupdate_b2_uop_is_fencei_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_sfence (io_brupdate_b2_uop_is_sfence_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_amo (io_brupdate_b2_uop_is_amo_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_eret (io_brupdate_b2_uop_is_eret_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_sys_pc2epc (io_brupdate_b2_uop_is_sys_pc2epc_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_rocc (io_brupdate_b2_uop_is_rocc_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_mov (io_brupdate_b2_uop_is_mov_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ftq_idx (io_brupdate_b2_uop_ftq_idx_0), // @[util.scala:458:7] .io_brupdate_b2_uop_edge_inst (io_brupdate_b2_uop_edge_inst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_pc_lob (io_brupdate_b2_uop_pc_lob_0), // @[util.scala:458:7] .io_brupdate_b2_uop_taken (io_brupdate_b2_uop_taken_0), // @[util.scala:458:7] .io_brupdate_b2_uop_imm_rename (io_brupdate_b2_uop_imm_rename_0), // @[util.scala:458:7] .io_brupdate_b2_uop_imm_sel (io_brupdate_b2_uop_imm_sel_0), // @[util.scala:458:7] .io_brupdate_b2_uop_pimm (io_brupdate_b2_uop_pimm_0), // @[util.scala:458:7] .io_brupdate_b2_uop_imm_packed (io_brupdate_b2_uop_imm_packed_0), // @[util.scala:458:7] .io_brupdate_b2_uop_op1_sel (io_brupdate_b2_uop_op1_sel_0), // @[util.scala:458:7] .io_brupdate_b2_uop_op2_sel (io_brupdate_b2_uop_op2_sel_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_ldst (io_brupdate_b2_uop_fp_ctrl_ldst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_wen (io_brupdate_b2_uop_fp_ctrl_wen_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_ren1 (io_brupdate_b2_uop_fp_ctrl_ren1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_ren2 (io_brupdate_b2_uop_fp_ctrl_ren2_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_ren3 (io_brupdate_b2_uop_fp_ctrl_ren3_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_swap12 (io_brupdate_b2_uop_fp_ctrl_swap12_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_swap23 (io_brupdate_b2_uop_fp_ctrl_swap23_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_typeTagIn (io_brupdate_b2_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_typeTagOut (io_brupdate_b2_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_fromint (io_brupdate_b2_uop_fp_ctrl_fromint_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_toint (io_brupdate_b2_uop_fp_ctrl_toint_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_fastpipe (io_brupdate_b2_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_fma (io_brupdate_b2_uop_fp_ctrl_fma_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_div (io_brupdate_b2_uop_fp_ctrl_div_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_sqrt (io_brupdate_b2_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_wflags (io_brupdate_b2_uop_fp_ctrl_wflags_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_vec (io_brupdate_b2_uop_fp_ctrl_vec_0), // @[util.scala:458:7] .io_brupdate_b2_uop_rob_idx (io_brupdate_b2_uop_rob_idx_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ldq_idx (io_brupdate_b2_uop_ldq_idx_0), // @[util.scala:458:7] .io_brupdate_b2_uop_stq_idx (io_brupdate_b2_uop_stq_idx_0), // @[util.scala:458:7] .io_brupdate_b2_uop_rxq_idx (io_brupdate_b2_uop_rxq_idx_0), // @[util.scala:458:7] .io_brupdate_b2_uop_pdst (io_brupdate_b2_uop_pdst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs1 (io_brupdate_b2_uop_prs1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs2 (io_brupdate_b2_uop_prs2_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs3 (io_brupdate_b2_uop_prs3_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ppred (io_brupdate_b2_uop_ppred_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs1_busy (io_brupdate_b2_uop_prs1_busy_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs2_busy (io_brupdate_b2_uop_prs2_busy_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs3_busy (io_brupdate_b2_uop_prs3_busy_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ppred_busy (io_brupdate_b2_uop_ppred_busy_0), // @[util.scala:458:7] .io_brupdate_b2_uop_stale_pdst (io_brupdate_b2_uop_stale_pdst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_exception (io_brupdate_b2_uop_exception_0), // @[util.scala:458:7] .io_brupdate_b2_uop_exc_cause (io_brupdate_b2_uop_exc_cause_0), // @[util.scala:458:7] .io_brupdate_b2_uop_mem_cmd (io_brupdate_b2_uop_mem_cmd_0), // @[util.scala:458:7] .io_brupdate_b2_uop_mem_size (io_brupdate_b2_uop_mem_size_0), // @[util.scala:458:7] .io_brupdate_b2_uop_mem_signed (io_brupdate_b2_uop_mem_signed_0), // @[util.scala:458:7] .io_brupdate_b2_uop_uses_ldq (io_brupdate_b2_uop_uses_ldq_0), // @[util.scala:458:7] .io_brupdate_b2_uop_uses_stq (io_brupdate_b2_uop_uses_stq_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_unique (io_brupdate_b2_uop_is_unique_0), // @[util.scala:458:7] .io_brupdate_b2_uop_flush_on_commit (io_brupdate_b2_uop_flush_on_commit_0), // @[util.scala:458:7] .io_brupdate_b2_uop_csr_cmd (io_brupdate_b2_uop_csr_cmd_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ldst_is_rs1 (io_brupdate_b2_uop_ldst_is_rs1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ldst (io_brupdate_b2_uop_ldst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_lrs1 (io_brupdate_b2_uop_lrs1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_lrs2 (io_brupdate_b2_uop_lrs2_0), // @[util.scala:458:7] .io_brupdate_b2_uop_lrs3 (io_brupdate_b2_uop_lrs3_0), // @[util.scala:458:7] .io_brupdate_b2_uop_dst_rtype (io_brupdate_b2_uop_dst_rtype_0), // @[util.scala:458:7] .io_brupdate_b2_uop_lrs1_rtype (io_brupdate_b2_uop_lrs1_rtype_0), // @[util.scala:458:7] .io_brupdate_b2_uop_lrs2_rtype (io_brupdate_b2_uop_lrs2_rtype_0), // @[util.scala:458:7] .io_brupdate_b2_uop_frs3_en (io_brupdate_b2_uop_frs3_en_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fcn_dw (io_brupdate_b2_uop_fcn_dw_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fcn_op (io_brupdate_b2_uop_fcn_op_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_val (io_brupdate_b2_uop_fp_val_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_rm (io_brupdate_b2_uop_fp_rm_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_typ (io_brupdate_b2_uop_fp_typ_0), // @[util.scala:458:7] .io_brupdate_b2_uop_xcpt_pf_if (io_brupdate_b2_uop_xcpt_pf_if_0), // @[util.scala:458:7] .io_brupdate_b2_uop_xcpt_ae_if (io_brupdate_b2_uop_xcpt_ae_if_0), // @[util.scala:458:7] .io_brupdate_b2_uop_xcpt_ma_if (io_brupdate_b2_uop_xcpt_ma_if_0), // @[util.scala:458:7] .io_brupdate_b2_uop_bp_debug_if (io_brupdate_b2_uop_bp_debug_if_0), // @[util.scala:458:7] .io_brupdate_b2_uop_bp_xcpt_if (io_brupdate_b2_uop_bp_xcpt_if_0), // @[util.scala:458:7] .io_brupdate_b2_uop_debug_fsrc (io_brupdate_b2_uop_debug_fsrc_0), // @[util.scala:458:7] .io_brupdate_b2_uop_debug_tsrc (io_brupdate_b2_uop_debug_tsrc_0), // @[util.scala:458:7] .io_brupdate_b2_mispredict (io_brupdate_b2_mispredict_0), // @[util.scala:458:7] .io_brupdate_b2_taken (io_brupdate_b2_taken_0), // @[util.scala:458:7] .io_brupdate_b2_cfi_type (io_brupdate_b2_cfi_type_0), // @[util.scala:458:7] .io_brupdate_b2_pc_sel (io_brupdate_b2_pc_sel_0), // @[util.scala:458:7] .io_brupdate_b2_jalr_target (io_brupdate_b2_jalr_target_0), // @[util.scala:458:7] .io_brupdate_b2_target_offset (io_brupdate_b2_target_offset_0), // @[util.scala:458:7] .io_flush (io_flush_0), // @[util.scala:458:7] .io_empty (_main_io_empty), .io_count (_main_io_count) ); // @[util.scala:476:22] assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22] assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22] assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22] assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_144( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_248 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels / // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /* Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) \| t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }	module NoCMonitor_52( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero \| flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File rawFloatFromIN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }	module INToRecFN_i64_e5_s11( // @[INToRecFN.scala:43:7] input io_signedIn, // @[INToRecFN.scala:46:16] input [63:0] io_in, // @[INToRecFN.scala:46:16] input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16] output [16:0] io_out, // @[INToRecFN.scala:46:16] output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16] ); wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7] wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7] wire [16:0] io_out_0; // @[INToRecFN.scala:43:7] wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7] wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34] wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}] wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23] wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31] wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31] wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44] wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}] wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53] wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70] wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}] wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23] wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72] wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23] wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23] wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28] assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}] assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23] wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}] wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}] assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}] assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72] assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20] RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23] .io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23] .io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23] .io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23] .io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[INToRecFN.scala:60:15] assign io_out = io_out_0; // @[INToRecFN.scala:43:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_20 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_21 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_22 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_27 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_28 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire _source_ok_T_49 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_29 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 \| _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 \| _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 \| _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 \| _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_72 = _source_ok_T_71 \| _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 \| _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 \| _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 \| _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_77 \| _source_ok_WIRE_29; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_79 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire _source_ok_T_103 = io_in_d_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_103; // @[Parameters.scala:1138:31] wire _source_ok_T_104 = io_in_d_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire _source_ok_T_105 = io_in_d_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_105; // @[Parameters.scala:1138:31] wire _source_ok_T_106 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_106; // @[Parameters.scala:1138:31] wire _source_ok_T_107 = io_in_d_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_107; // @[Parameters.scala:1138:31] wire _source_ok_T_108 = io_in_d_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_112; // @[Parameters.scala:1138:31] wire _source_ok_T_113 = io_in_d_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_113; // @[Parameters.scala:1138:31] wire _source_ok_T_114 = io_in_d_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire _source_ok_T_115 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_115; // @[Parameters.scala:1138:31] wire _source_ok_T_116 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire _source_ok_T_118 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_20 = _source_ok_T_118; // @[Parameters.scala:1138:31] wire _source_ok_T_119 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_21 = _source_ok_T_119; // @[Parameters.scala:1138:31] wire _source_ok_T_120 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_22 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire _source_ok_T_121 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_121; // @[Parameters.scala:1138:31] wire _source_ok_T_122 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_122; // @[Parameters.scala:1138:31] wire _source_ok_T_123 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_123; // @[Parameters.scala:1138:31] wire _source_ok_T_124 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_124; // @[Parameters.scala:1138:31] wire _source_ok_T_125 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_27 = _source_ok_T_125; // @[Parameters.scala:1138:31] wire _source_ok_T_126 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_28 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire _source_ok_T_127 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_29 = _source_ok_T_127; // @[Parameters.scala:1138:31] wire _source_ok_T_128 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_129 = _source_ok_T_128 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_130 = _source_ok_T_129 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_131 = _source_ok_T_130 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_132 = _source_ok_T_131 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_133 = _source_ok_T_132 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_134 = _source_ok_T_133 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_135 = _source_ok_T_134 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 \| _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 \| _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 \| _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 \| _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 \| _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 \| _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 \| _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 \| _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 \| _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 \| _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 \| _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 \| _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 \| _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 \| _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 \| _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 \| _source_ok_WIRE_1_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 \| _source_ok_WIRE_1_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_155 \| _source_ok_WIRE_1_29; // @[Parameters.scala:1138:31, :1139:46] wire _T_1766 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1766; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1766; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_1839 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1839; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1839; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1839; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1692 = _T_1766 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1692 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1692 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1692 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1692 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1692 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1738 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1738 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1707 = _T_1839 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1707 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1707 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1707 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1810 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1810 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1792 = _T_1839 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1792 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1792 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1792 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_35( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire excluded_client = 1'h0; // @[MSHR.scala:279:28] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53] wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_52( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn \|\| noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }	module test_router_32ClockSinkDomain( // @[ClockDomain.scala:14:9] output [4:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_27 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid), .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head), .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail), .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload), .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id), .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return), .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid), .auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head), .auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail), .auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload), .auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return), .auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundRawFNToRecFN_e8_s24_13( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_13 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_421( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops }	module BranchKillableQueue_32( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty, // @[util.scala:463:14] output [3:0] io_count // @[util.scala:463:14] ); wire [130:0] _ram_ext_R0_data; // @[util.scala:503:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _do_enq_T_4 = 1'h1; // @[util.scala:514:42] wire _do_enq_T_7 = 1'h1; // @[util.scala:514:102] wire _valids_0_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_0_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_1_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_1_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_2_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_2_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_3_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_3_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_4_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_4_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_5_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_5_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_6_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_6_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_7_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_7_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_8_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_8_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_9_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_9_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_10_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_10_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_11_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_11_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_12_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_12_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_13_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_13_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_14_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_14_T_6 = 1'h1; // @[util.scala:520:83] wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_8 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_9 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_10 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_11 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_12 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_13 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_14 = 1'h0; // @[util.scala:504:34] wire _do_enq_T_2 = 1'h0; // @[util.scala:126:59] wire _do_enq_T_3 = 1'h0; // @[util.scala:61:61] wire _do_enq_T_6 = 1'h0; // @[util.scala:514:113] wire _valids_0_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_0_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_0_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_1_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_1_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_1_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_2_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_2_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_2_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_3_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_3_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_3_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_4_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_4_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_4_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_5_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_5_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_5_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_6_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_6_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_6_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_7_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_7_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_7_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_8_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_8_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_8_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_9_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_9_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_9_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_10_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_10_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_10_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_11_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_11_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_11_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_12_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_12_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_12_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_13_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_13_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_13_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_14_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_14_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_14_T_5 = 1'h0; // @[util.scala:520:94] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:458:7] wire [3:0] _do_enq_T_1 = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_0_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_1_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_2_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_3_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_4_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_5_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_6_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_7_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_8_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_9_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_10_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_11_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_12_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_13_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_14_T = 4'h0; // @[util.scala:126:51] wire _io_enq_ready_T; // @[util.scala:543:21] wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:93:25, :458:7] wire _io_deq_valid_T_1; // @[util.scala:548:42] wire [31:0] out_uop_inst; // @[util.scala:545:19] wire [31:0] out_uop_debug_inst; // @[util.scala:545:19] wire out_uop_is_rvc; // @[util.scala:545:19] wire [33:0] out_uop_debug_pc; // @[util.scala:545:19] wire out_uop_iq_type_0; // @[util.scala:545:19] wire out_uop_iq_type_1; // @[util.scala:545:19] wire out_uop_iq_type_2; // @[util.scala:545:19] wire out_uop_iq_type_3; // @[util.scala:545:19] wire out_uop_fu_code_0; // @[util.scala:545:19] wire out_uop_fu_code_1; // @[util.scala:545:19] wire out_uop_fu_code_2; // @[util.scala:545:19] wire out_uop_fu_code_3; // @[util.scala:545:19] wire out_uop_fu_code_4; // @[util.scala:545:19] wire out_uop_fu_code_5; // @[util.scala:545:19] wire out_uop_fu_code_6; // @[util.scala:545:19] wire out_uop_fu_code_7; // @[util.scala:545:19] wire out_uop_fu_code_8; // @[util.scala:545:19] wire out_uop_fu_code_9; // @[util.scala:545:19] wire out_uop_iw_issued; // @[util.scala:545:19] wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19] wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19] wire out_uop_iw_p1_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p2_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19] wire out_uop_dis_col_sel; // @[util.scala:545:19] wire [3:0] out_uop_br_mask; // @[util.scala:545:19] wire [1:0] out_uop_br_tag; // @[util.scala:545:19] wire [3:0] out_uop_br_type; // @[util.scala:545:19] wire out_uop_is_sfb; // @[util.scala:545:19] wire out_uop_is_fence; // @[util.scala:545:19] wire out_uop_is_fencei; // @[util.scala:545:19] wire out_uop_is_sfence; // @[util.scala:545:19] wire out_uop_is_amo; // @[util.scala:545:19] wire out_uop_is_eret; // @[util.scala:545:19] wire out_uop_is_sys_pc2epc; // @[util.scala:545:19] wire out_uop_is_rocc; // @[util.scala:545:19] wire out_uop_is_mov; // @[util.scala:545:19] wire [3:0] out_uop_ftq_idx; // @[util.scala:545:19] wire out_uop_edge_inst; // @[util.scala:545:19] wire [5:0] out_uop_pc_lob; // @[util.scala:545:19] wire out_uop_taken; // @[util.scala:545:19] wire out_uop_imm_rename; // @[util.scala:545:19] wire [2:0] out_uop_imm_sel; // @[util.scala:545:19] wire [4:0] out_uop_pimm; // @[util.scala:545:19] wire [19:0] out_uop_imm_packed; // @[util.scala:545:19] wire [1:0] out_uop_op1_sel; // @[util.scala:545:19] wire [2:0] out_uop_op2_sel; // @[util.scala:545:19] wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19] wire out_uop_fp_ctrl_wen; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19] wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19] wire out_uop_fp_ctrl_toint; // @[util.scala:545:19] wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19] wire out_uop_fp_ctrl_fma; // @[util.scala:545:19] wire out_uop_fp_ctrl_div; // @[util.scala:545:19] wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19] wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19] wire out_uop_fp_ctrl_vec; // @[util.scala:545:19] wire [4:0] out_uop_rob_idx; // @[util.scala:545:19] wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19] wire [3:0] out_uop_stq_idx; // @[util.scala:545:19] wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19] wire [5:0] out_uop_pdst; // @[util.scala:545:19] wire [5:0] out_uop_prs1; // @[util.scala:545:19] wire [5:0] out_uop_prs2; // @[util.scala:545:19] wire [5:0] out_uop_prs3; // @[util.scala:545:19] wire [3:0] out_uop_ppred; // @[util.scala:545:19] wire out_uop_prs1_busy; // @[util.scala:545:19] wire out_uop_prs2_busy; // @[util.scala:545:19] wire out_uop_prs3_busy; // @[util.scala:545:19] wire out_uop_ppred_busy; // @[util.scala:545:19] wire [5:0] out_uop_stale_pdst; // @[util.scala:545:19] wire out_uop_exception; // @[util.scala:545:19] wire [63:0] out_uop_exc_cause; // @[util.scala:545:19] wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19] wire [1:0] out_uop_mem_size; // @[util.scala:545:19] wire out_uop_mem_signed; // @[util.scala:545:19] wire out_uop_uses_ldq; // @[util.scala:545:19] wire out_uop_uses_stq; // @[util.scala:545:19] wire out_uop_is_unique; // @[util.scala:545:19] wire out_uop_flush_on_commit; // @[util.scala:545:19] wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19] wire out_uop_ldst_is_rs1; // @[util.scala:545:19] wire [5:0] out_uop_ldst; // @[util.scala:545:19] wire [5:0] out_uop_lrs1; // @[util.scala:545:19] wire [5:0] out_uop_lrs2; // @[util.scala:545:19] wire [5:0] out_uop_lrs3; // @[util.scala:545:19] wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19] wire out_uop_frs3_en; // @[util.scala:545:19] wire out_uop_fcn_dw; // @[util.scala:545:19] wire [4:0] out_uop_fcn_op; // @[util.scala:545:19] wire out_uop_fp_val; // @[util.scala:545:19] wire [2:0] out_uop_fp_rm; // @[util.scala:545:19] wire [1:0] out_uop_fp_typ; // @[util.scala:545:19] wire out_uop_xcpt_pf_if; // @[util.scala:545:19] wire out_uop_xcpt_ae_if; // @[util.scala:545:19] wire out_uop_xcpt_ma_if; // @[util.scala:545:19] wire out_uop_bp_debug_if; // @[util.scala:545:19] wire out_uop_bp_xcpt_if; // @[util.scala:545:19] wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19] wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19] wire [33:0] out_addr; // @[util.scala:545:19] wire [63:0] out_data; // @[util.scala:545:19] wire out_is_hella; // @[util.scala:545:19] wire out_tag_match; // @[util.scala:545:19] wire [1:0] out_old_meta_coh_state; // @[util.scala:545:19] wire [21:0] out_old_meta_tag; // @[util.scala:545:19] wire [1:0] out_way_en; // @[util.scala:545:19] wire [4:0] out_sdq_id; // @[util.scala:545:19] wire _io_empty_T_1; // @[util.scala:512:27] wire [3:0] _io_count_T_5; // @[util.scala:556:22] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count_0; // @[util.scala:458:7] assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:503:22, :545:19] assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:503:22, :545:19] assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:503:22, :545:19] assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:503:22, :545:19] assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:503:22, :545:19] assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:503:22, :545:19] assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:503:22, :545:19] assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:503:22, :545:19] reg valids_0; // @[util.scala:504:26] wire _valids_0_T_4 = valids_0; // @[util.scala:504:26, :520:31] reg valids_1; // @[util.scala:504:26] wire _valids_1_T_4 = valids_1; // @[util.scala:504:26, :520:31] reg valids_2; // @[util.scala:504:26] wire _valids_2_T_4 = valids_2; // @[util.scala:504:26, :520:31] reg valids_3; // @[util.scala:504:26] wire _valids_3_T_4 = valids_3; // @[util.scala:504:26, :520:31] reg valids_4; // @[util.scala:504:26] wire _valids_4_T_4 = valids_4; // @[util.scala:504:26, :520:31] reg valids_5; // @[util.scala:504:26] wire _valids_5_T_4 = valids_5; // @[util.scala:504:26, :520:31] reg valids_6; // @[util.scala:504:26] wire _valids_6_T_4 = valids_6; // @[util.scala:504:26, :520:31] reg valids_7; // @[util.scala:504:26] wire _valids_7_T_4 = valids_7; // @[util.scala:504:26, :520:31] reg valids_8; // @[util.scala:504:26] wire _valids_8_T_4 = valids_8; // @[util.scala:504:26, :520:31] reg valids_9; // @[util.scala:504:26] wire _valids_9_T_4 = valids_9; // @[util.scala:504:26, :520:31] reg valids_10; // @[util.scala:504:26] wire _valids_10_T_4 = valids_10; // @[util.scala:504:26, :520:31] reg valids_11; // @[util.scala:504:26] wire _valids_11_T_4 = valids_11; // @[util.scala:504:26, :520:31] reg valids_12; // @[util.scala:504:26] wire _valids_12_T_4 = valids_12; // @[util.scala:504:26, :520:31] reg valids_13; // @[util.scala:504:26] wire _valids_13_T_4 = valids_13; // @[util.scala:504:26, :520:31] reg valids_14; // @[util.scala:504:26] wire _valids_14_T_4 = valids_14; // @[util.scala:504:26, :520:31] reg [31:0] uops_0_inst; // @[util.scala:505:22] reg [31:0] uops_0_debug_inst; // @[util.scala:505:22] reg uops_0_is_rvc; // @[util.scala:505:22] reg [33:0] uops_0_debug_pc; // @[util.scala:505:22] reg uops_0_iq_type_0; // @[util.scala:505:22] reg uops_0_iq_type_1; // @[util.scala:505:22] reg uops_0_iq_type_2; // @[util.scala:505:22] reg uops_0_iq_type_3; // @[util.scala:505:22] reg uops_0_fu_code_0; // @[util.scala:505:22] reg uops_0_fu_code_1; // @[util.scala:505:22] reg uops_0_fu_code_2; // @[util.scala:505:22] reg uops_0_fu_code_3; // @[util.scala:505:22] reg uops_0_fu_code_4; // @[util.scala:505:22] reg uops_0_fu_code_5; // @[util.scala:505:22] reg uops_0_fu_code_6; // @[util.scala:505:22] reg uops_0_fu_code_7; // @[util.scala:505:22] reg uops_0_fu_code_8; // @[util.scala:505:22] reg uops_0_fu_code_9; // @[util.scala:505:22] reg uops_0_iw_issued; // @[util.scala:505:22] reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_0_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_0_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_0_br_mask; // @[util.scala:505:22] wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_0_br_tag; // @[util.scala:505:22] reg [3:0] uops_0_br_type; // @[util.scala:505:22] reg uops_0_is_sfb; // @[util.scala:505:22] reg uops_0_is_fence; // @[util.scala:505:22] reg uops_0_is_fencei; // @[util.scala:505:22] reg uops_0_is_sfence; // @[util.scala:505:22] reg uops_0_is_amo; // @[util.scala:505:22] reg uops_0_is_eret; // @[util.scala:505:22] reg uops_0_is_sys_pc2epc; // @[util.scala:505:22] reg uops_0_is_rocc; // @[util.scala:505:22] reg uops_0_is_mov; // @[util.scala:505:22] reg [3:0] uops_0_ftq_idx; // @[util.scala:505:22] reg uops_0_edge_inst; // @[util.scala:505:22] reg [5:0] uops_0_pc_lob; // @[util.scala:505:22] reg uops_0_taken; // @[util.scala:505:22] reg uops_0_imm_rename; // @[util.scala:505:22] reg [2:0] uops_0_imm_sel; // @[util.scala:505:22] reg [4:0] uops_0_pimm; // @[util.scala:505:22] reg [19:0] uops_0_imm_packed; // @[util.scala:505:22] reg [1:0] uops_0_op1_sel; // @[util.scala:505:22] reg [2:0] uops_0_op2_sel; // @[util.scala:505:22] reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_0_fp_ctrl_wen; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_0_fp_ctrl_toint; // @[util.scala:505:22] reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_0_fp_ctrl_fma; // @[util.scala:505:22] reg uops_0_fp_ctrl_div; // @[util.scala:505:22] reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_0_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_0_rob_idx; // @[util.scala:505:22] reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_0_stq_idx; // @[util.scala:505:22] reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_0_pdst; // @[util.scala:505:22] reg [5:0] uops_0_prs1; // @[util.scala:505:22] reg [5:0] uops_0_prs2; // @[util.scala:505:22] reg [5:0] uops_0_prs3; // @[util.scala:505:22] reg [3:0] uops_0_ppred; // @[util.scala:505:22] reg uops_0_prs1_busy; // @[util.scala:505:22] reg uops_0_prs2_busy; // @[util.scala:505:22] reg uops_0_prs3_busy; // @[util.scala:505:22] reg uops_0_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_0_stale_pdst; // @[util.scala:505:22] reg uops_0_exception; // @[util.scala:505:22] reg [63:0] uops_0_exc_cause; // @[util.scala:505:22] reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_0_mem_size; // @[util.scala:505:22] reg uops_0_mem_signed; // @[util.scala:505:22] reg uops_0_uses_ldq; // @[util.scala:505:22] reg uops_0_uses_stq; // @[util.scala:505:22] reg uops_0_is_unique; // @[util.scala:505:22] reg uops_0_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22] reg uops_0_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_0_ldst; // @[util.scala:505:22] reg [5:0] uops_0_lrs1; // @[util.scala:505:22] reg [5:0] uops_0_lrs2; // @[util.scala:505:22] reg [5:0] uops_0_lrs3; // @[util.scala:505:22] reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22] reg uops_0_frs3_en; // @[util.scala:505:22] reg uops_0_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_0_fcn_op; // @[util.scala:505:22] reg uops_0_fp_val; // @[util.scala:505:22] reg [2:0] uops_0_fp_rm; // @[util.scala:505:22] reg [1:0] uops_0_fp_typ; // @[util.scala:505:22] reg uops_0_xcpt_pf_if; // @[util.scala:505:22] reg uops_0_xcpt_ae_if; // @[util.scala:505:22] reg uops_0_xcpt_ma_if; // @[util.scala:505:22] reg uops_0_bp_debug_if; // @[util.scala:505:22] reg uops_0_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_1_inst; // @[util.scala:505:22] reg [31:0] uops_1_debug_inst; // @[util.scala:505:22] reg uops_1_is_rvc; // @[util.scala:505:22] reg [33:0] uops_1_debug_pc; // @[util.scala:505:22] reg uops_1_iq_type_0; // @[util.scala:505:22] reg uops_1_iq_type_1; // @[util.scala:505:22] reg uops_1_iq_type_2; // @[util.scala:505:22] reg uops_1_iq_type_3; // @[util.scala:505:22] reg uops_1_fu_code_0; // @[util.scala:505:22] reg uops_1_fu_code_1; // @[util.scala:505:22] reg uops_1_fu_code_2; // @[util.scala:505:22] reg uops_1_fu_code_3; // @[util.scala:505:22] reg uops_1_fu_code_4; // @[util.scala:505:22] reg uops_1_fu_code_5; // @[util.scala:505:22] reg uops_1_fu_code_6; // @[util.scala:505:22] reg uops_1_fu_code_7; // @[util.scala:505:22] reg uops_1_fu_code_8; // @[util.scala:505:22] reg uops_1_fu_code_9; // @[util.scala:505:22] reg uops_1_iw_issued; // @[util.scala:505:22] reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_1_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_1_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_1_br_mask; // @[util.scala:505:22] wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_1_br_tag; // @[util.scala:505:22] reg [3:0] uops_1_br_type; // @[util.scala:505:22] reg uops_1_is_sfb; // @[util.scala:505:22] reg uops_1_is_fence; // @[util.scala:505:22] reg uops_1_is_fencei; // @[util.scala:505:22] reg uops_1_is_sfence; // @[util.scala:505:22] reg uops_1_is_amo; // @[util.scala:505:22] reg uops_1_is_eret; // @[util.scala:505:22] reg uops_1_is_sys_pc2epc; // @[util.scala:505:22] reg uops_1_is_rocc; // @[util.scala:505:22] reg uops_1_is_mov; // @[util.scala:505:22] reg [3:0] uops_1_ftq_idx; // @[util.scala:505:22] reg uops_1_edge_inst; // @[util.scala:505:22] reg [5:0] uops_1_pc_lob; // @[util.scala:505:22] reg uops_1_taken; // @[util.scala:505:22] reg uops_1_imm_rename; // @[util.scala:505:22] reg [2:0] uops_1_imm_sel; // @[util.scala:505:22] reg [4:0] uops_1_pimm; // @[util.scala:505:22] reg [19:0] uops_1_imm_packed; // @[util.scala:505:22] reg [1:0] uops_1_op1_sel; // @[util.scala:505:22] reg [2:0] uops_1_op2_sel; // @[util.scala:505:22] reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_1_fp_ctrl_wen; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_1_fp_ctrl_toint; // @[util.scala:505:22] reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_1_fp_ctrl_fma; // @[util.scala:505:22] reg uops_1_fp_ctrl_div; // @[util.scala:505:22] reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_1_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_1_rob_idx; // @[util.scala:505:22] reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_1_stq_idx; // @[util.scala:505:22] reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_1_pdst; // @[util.scala:505:22] reg [5:0] uops_1_prs1; // @[util.scala:505:22] reg [5:0] uops_1_prs2; // @[util.scala:505:22] reg [5:0] uops_1_prs3; // @[util.scala:505:22] reg [3:0] uops_1_ppred; // @[util.scala:505:22] reg uops_1_prs1_busy; // @[util.scala:505:22] reg uops_1_prs2_busy; // @[util.scala:505:22] reg uops_1_prs3_busy; // @[util.scala:505:22] reg uops_1_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_1_stale_pdst; // @[util.scala:505:22] reg uops_1_exception; // @[util.scala:505:22] reg [63:0] uops_1_exc_cause; // @[util.scala:505:22] reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_1_mem_size; // @[util.scala:505:22] reg uops_1_mem_signed; // @[util.scala:505:22] reg uops_1_uses_ldq; // @[util.scala:505:22] reg uops_1_uses_stq; // @[util.scala:505:22] reg uops_1_is_unique; // @[util.scala:505:22] reg uops_1_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22] reg uops_1_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_1_ldst; // @[util.scala:505:22] reg [5:0] uops_1_lrs1; // @[util.scala:505:22] reg [5:0] uops_1_lrs2; // @[util.scala:505:22] reg [5:0] uops_1_lrs3; // @[util.scala:505:22] reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22] reg uops_1_frs3_en; // @[util.scala:505:22] reg uops_1_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_1_fcn_op; // @[util.scala:505:22] reg uops_1_fp_val; // @[util.scala:505:22] reg [2:0] uops_1_fp_rm; // @[util.scala:505:22] reg [1:0] uops_1_fp_typ; // @[util.scala:505:22] reg uops_1_xcpt_pf_if; // @[util.scala:505:22] reg uops_1_xcpt_ae_if; // @[util.scala:505:22] reg uops_1_xcpt_ma_if; // @[util.scala:505:22] reg uops_1_bp_debug_if; // @[util.scala:505:22] reg uops_1_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_2_inst; // @[util.scala:505:22] reg [31:0] uops_2_debug_inst; // @[util.scala:505:22] reg uops_2_is_rvc; // @[util.scala:505:22] reg [33:0] uops_2_debug_pc; // @[util.scala:505:22] reg uops_2_iq_type_0; // @[util.scala:505:22] reg uops_2_iq_type_1; // @[util.scala:505:22] reg uops_2_iq_type_2; // @[util.scala:505:22] reg uops_2_iq_type_3; // @[util.scala:505:22] reg uops_2_fu_code_0; // @[util.scala:505:22] reg uops_2_fu_code_1; // @[util.scala:505:22] reg uops_2_fu_code_2; // @[util.scala:505:22] reg uops_2_fu_code_3; // @[util.scala:505:22] reg uops_2_fu_code_4; // @[util.scala:505:22] reg uops_2_fu_code_5; // @[util.scala:505:22] reg uops_2_fu_code_6; // @[util.scala:505:22] reg uops_2_fu_code_7; // @[util.scala:505:22] reg uops_2_fu_code_8; // @[util.scala:505:22] reg uops_2_fu_code_9; // @[util.scala:505:22] reg uops_2_iw_issued; // @[util.scala:505:22] reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_2_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_2_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_2_br_mask; // @[util.scala:505:22] wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_2_br_tag; // @[util.scala:505:22] reg [3:0] uops_2_br_type; // @[util.scala:505:22] reg uops_2_is_sfb; // @[util.scala:505:22] reg uops_2_is_fence; // @[util.scala:505:22] reg uops_2_is_fencei; // @[util.scala:505:22] reg uops_2_is_sfence; // @[util.scala:505:22] reg uops_2_is_amo; // @[util.scala:505:22] reg uops_2_is_eret; // @[util.scala:505:22] reg uops_2_is_sys_pc2epc; // @[util.scala:505:22] reg uops_2_is_rocc; // @[util.scala:505:22] reg uops_2_is_mov; // @[util.scala:505:22] reg [3:0] uops_2_ftq_idx; // @[util.scala:505:22] reg uops_2_edge_inst; // @[util.scala:505:22] reg [5:0] uops_2_pc_lob; // @[util.scala:505:22] reg uops_2_taken; // @[util.scala:505:22] reg uops_2_imm_rename; // @[util.scala:505:22] reg [2:0] uops_2_imm_sel; // @[util.scala:505:22] reg [4:0] uops_2_pimm; // @[util.scala:505:22] reg [19:0] uops_2_imm_packed; // @[util.scala:505:22] reg [1:0] uops_2_op1_sel; // @[util.scala:505:22] reg [2:0] uops_2_op2_sel; // @[util.scala:505:22] reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_2_fp_ctrl_wen; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_2_fp_ctrl_toint; // @[util.scala:505:22] reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_2_fp_ctrl_fma; // @[util.scala:505:22] reg uops_2_fp_ctrl_div; // @[util.scala:505:22] reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_2_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_2_rob_idx; // @[util.scala:505:22] reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_2_stq_idx; // @[util.scala:505:22] reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_2_pdst; // @[util.scala:505:22] reg [5:0] uops_2_prs1; // @[util.scala:505:22] reg [5:0] uops_2_prs2; // @[util.scala:505:22] reg [5:0] uops_2_prs3; // @[util.scala:505:22] reg [3:0] uops_2_ppred; // @[util.scala:505:22] reg uops_2_prs1_busy; // @[util.scala:505:22] reg uops_2_prs2_busy; // @[util.scala:505:22] reg uops_2_prs3_busy; // @[util.scala:505:22] reg uops_2_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_2_stale_pdst; // @[util.scala:505:22] reg uops_2_exception; // @[util.scala:505:22] reg [63:0] uops_2_exc_cause; // @[util.scala:505:22] reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_2_mem_size; // @[util.scala:505:22] reg uops_2_mem_signed; // @[util.scala:505:22] reg uops_2_uses_ldq; // @[util.scala:505:22] reg uops_2_uses_stq; // @[util.scala:505:22] reg uops_2_is_unique; // @[util.scala:505:22] reg uops_2_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22] reg uops_2_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_2_ldst; // @[util.scala:505:22] reg [5:0] uops_2_lrs1; // @[util.scala:505:22] reg [5:0] uops_2_lrs2; // @[util.scala:505:22] reg [5:0] uops_2_lrs3; // @[util.scala:505:22] reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22] reg uops_2_frs3_en; // @[util.scala:505:22] reg uops_2_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_2_fcn_op; // @[util.scala:505:22] reg uops_2_fp_val; // @[util.scala:505:22] reg [2:0] uops_2_fp_rm; // @[util.scala:505:22] reg [1:0] uops_2_fp_typ; // @[util.scala:505:22] reg uops_2_xcpt_pf_if; // @[util.scala:505:22] reg uops_2_xcpt_ae_if; // @[util.scala:505:22] reg uops_2_xcpt_ma_if; // @[util.scala:505:22] reg uops_2_bp_debug_if; // @[util.scala:505:22] reg uops_2_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_3_inst; // @[util.scala:505:22] reg [31:0] uops_3_debug_inst; // @[util.scala:505:22] reg uops_3_is_rvc; // @[util.scala:505:22] reg [33:0] uops_3_debug_pc; // @[util.scala:505:22] reg uops_3_iq_type_0; // @[util.scala:505:22] reg uops_3_iq_type_1; // @[util.scala:505:22] reg uops_3_iq_type_2; // @[util.scala:505:22] reg uops_3_iq_type_3; // @[util.scala:505:22] reg uops_3_fu_code_0; // @[util.scala:505:22] reg uops_3_fu_code_1; // @[util.scala:505:22] reg uops_3_fu_code_2; // @[util.scala:505:22] reg uops_3_fu_code_3; // @[util.scala:505:22] reg uops_3_fu_code_4; // @[util.scala:505:22] reg uops_3_fu_code_5; // @[util.scala:505:22] reg uops_3_fu_code_6; // @[util.scala:505:22] reg uops_3_fu_code_7; // @[util.scala:505:22] reg uops_3_fu_code_8; // @[util.scala:505:22] reg uops_3_fu_code_9; // @[util.scala:505:22] reg uops_3_iw_issued; // @[util.scala:505:22] reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_3_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_3_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_3_br_mask; // @[util.scala:505:22] wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_3_br_tag; // @[util.scala:505:22] reg [3:0] uops_3_br_type; // @[util.scala:505:22] reg uops_3_is_sfb; // @[util.scala:505:22] reg uops_3_is_fence; // @[util.scala:505:22] reg uops_3_is_fencei; // @[util.scala:505:22] reg uops_3_is_sfence; // @[util.scala:505:22] reg uops_3_is_amo; // @[util.scala:505:22] reg uops_3_is_eret; // @[util.scala:505:22] reg uops_3_is_sys_pc2epc; // @[util.scala:505:22] reg uops_3_is_rocc; // @[util.scala:505:22] reg uops_3_is_mov; // @[util.scala:505:22] reg [3:0] uops_3_ftq_idx; // @[util.scala:505:22] reg uops_3_edge_inst; // @[util.scala:505:22] reg [5:0] uops_3_pc_lob; // @[util.scala:505:22] reg uops_3_taken; // @[util.scala:505:22] reg uops_3_imm_rename; // @[util.scala:505:22] reg [2:0] uops_3_imm_sel; // @[util.scala:505:22] reg [4:0] uops_3_pimm; // @[util.scala:505:22] reg [19:0] uops_3_imm_packed; // @[util.scala:505:22] reg [1:0] uops_3_op1_sel; // @[util.scala:505:22] reg [2:0] uops_3_op2_sel; // @[util.scala:505:22] reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_3_fp_ctrl_wen; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_3_fp_ctrl_toint; // @[util.scala:505:22] reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_3_fp_ctrl_fma; // @[util.scala:505:22] reg uops_3_fp_ctrl_div; // @[util.scala:505:22] reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_3_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_3_rob_idx; // @[util.scala:505:22] reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_3_stq_idx; // @[util.scala:505:22] reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_3_pdst; // @[util.scala:505:22] reg [5:0] uops_3_prs1; // @[util.scala:505:22] reg [5:0] uops_3_prs2; // @[util.scala:505:22] reg [5:0] uops_3_prs3; // @[util.scala:505:22] reg [3:0] uops_3_ppred; // @[util.scala:505:22] reg uops_3_prs1_busy; // @[util.scala:505:22] reg uops_3_prs2_busy; // @[util.scala:505:22] reg uops_3_prs3_busy; // @[util.scala:505:22] reg uops_3_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_3_stale_pdst; // @[util.scala:505:22] reg uops_3_exception; // @[util.scala:505:22] reg [63:0] uops_3_exc_cause; // @[util.scala:505:22] reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_3_mem_size; // @[util.scala:505:22] reg uops_3_mem_signed; // @[util.scala:505:22] reg uops_3_uses_ldq; // @[util.scala:505:22] reg uops_3_uses_stq; // @[util.scala:505:22] reg uops_3_is_unique; // @[util.scala:505:22] reg uops_3_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22] reg uops_3_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_3_ldst; // @[util.scala:505:22] reg [5:0] uops_3_lrs1; // @[util.scala:505:22] reg [5:0] uops_3_lrs2; // @[util.scala:505:22] reg [5:0] uops_3_lrs3; // @[util.scala:505:22] reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22] reg uops_3_frs3_en; // @[util.scala:505:22] reg uops_3_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_3_fcn_op; // @[util.scala:505:22] reg uops_3_fp_val; // @[util.scala:505:22] reg [2:0] uops_3_fp_rm; // @[util.scala:505:22] reg [1:0] uops_3_fp_typ; // @[util.scala:505:22] reg uops_3_xcpt_pf_if; // @[util.scala:505:22] reg uops_3_xcpt_ae_if; // @[util.scala:505:22] reg uops_3_xcpt_ma_if; // @[util.scala:505:22] reg uops_3_bp_debug_if; // @[util.scala:505:22] reg uops_3_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_4_inst; // @[util.scala:505:22] reg [31:0] uops_4_debug_inst; // @[util.scala:505:22] reg uops_4_is_rvc; // @[util.scala:505:22] reg [33:0] uops_4_debug_pc; // @[util.scala:505:22] reg uops_4_iq_type_0; // @[util.scala:505:22] reg uops_4_iq_type_1; // @[util.scala:505:22] reg uops_4_iq_type_2; // @[util.scala:505:22] reg uops_4_iq_type_3; // @[util.scala:505:22] reg uops_4_fu_code_0; // @[util.scala:505:22] reg uops_4_fu_code_1; // @[util.scala:505:22] reg uops_4_fu_code_2; // @[util.scala:505:22] reg uops_4_fu_code_3; // @[util.scala:505:22] reg uops_4_fu_code_4; // @[util.scala:505:22] reg uops_4_fu_code_5; // @[util.scala:505:22] reg uops_4_fu_code_6; // @[util.scala:505:22] reg uops_4_fu_code_7; // @[util.scala:505:22] reg uops_4_fu_code_8; // @[util.scala:505:22] reg uops_4_fu_code_9; // @[util.scala:505:22] reg uops_4_iw_issued; // @[util.scala:505:22] reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_4_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_4_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_4_br_mask; // @[util.scala:505:22] wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_4_br_tag; // @[util.scala:505:22] reg [3:0] uops_4_br_type; // @[util.scala:505:22] reg uops_4_is_sfb; // @[util.scala:505:22] reg uops_4_is_fence; // @[util.scala:505:22] reg uops_4_is_fencei; // @[util.scala:505:22] reg uops_4_is_sfence; // @[util.scala:505:22] reg uops_4_is_amo; // @[util.scala:505:22] reg uops_4_is_eret; // @[util.scala:505:22] reg uops_4_is_sys_pc2epc; // @[util.scala:505:22] reg uops_4_is_rocc; // @[util.scala:505:22] reg uops_4_is_mov; // @[util.scala:505:22] reg [3:0] uops_4_ftq_idx; // @[util.scala:505:22] reg uops_4_edge_inst; // @[util.scala:505:22] reg [5:0] uops_4_pc_lob; // @[util.scala:505:22] reg uops_4_taken; // @[util.scala:505:22] reg uops_4_imm_rename; // @[util.scala:505:22] reg [2:0] uops_4_imm_sel; // @[util.scala:505:22] reg [4:0] uops_4_pimm; // @[util.scala:505:22] reg [19:0] uops_4_imm_packed; // @[util.scala:505:22] reg [1:0] uops_4_op1_sel; // @[util.scala:505:22] reg [2:0] uops_4_op2_sel; // @[util.scala:505:22] reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_4_fp_ctrl_wen; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_4_fp_ctrl_toint; // @[util.scala:505:22] reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_4_fp_ctrl_fma; // @[util.scala:505:22] reg uops_4_fp_ctrl_div; // @[util.scala:505:22] reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_4_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_4_rob_idx; // @[util.scala:505:22] reg [3:0] uops_4_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_4_stq_idx; // @[util.scala:505:22] reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_4_pdst; // @[util.scala:505:22] reg [5:0] uops_4_prs1; // @[util.scala:505:22] reg [5:0] uops_4_prs2; // @[util.scala:505:22] reg [5:0] uops_4_prs3; // @[util.scala:505:22] reg [3:0] uops_4_ppred; // @[util.scala:505:22] reg uops_4_prs1_busy; // @[util.scala:505:22] reg uops_4_prs2_busy; // @[util.scala:505:22] reg uops_4_prs3_busy; // @[util.scala:505:22] reg uops_4_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_4_stale_pdst; // @[util.scala:505:22] reg uops_4_exception; // @[util.scala:505:22] reg [63:0] uops_4_exc_cause; // @[util.scala:505:22] reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_4_mem_size; // @[util.scala:505:22] reg uops_4_mem_signed; // @[util.scala:505:22] reg uops_4_uses_ldq; // @[util.scala:505:22] reg uops_4_uses_stq; // @[util.scala:505:22] reg uops_4_is_unique; // @[util.scala:505:22] reg uops_4_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22] reg uops_4_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_4_ldst; // @[util.scala:505:22] reg [5:0] uops_4_lrs1; // @[util.scala:505:22] reg [5:0] uops_4_lrs2; // @[util.scala:505:22] reg [5:0] uops_4_lrs3; // @[util.scala:505:22] reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22] reg uops_4_frs3_en; // @[util.scala:505:22] reg uops_4_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_4_fcn_op; // @[util.scala:505:22] reg uops_4_fp_val; // @[util.scala:505:22] reg [2:0] uops_4_fp_rm; // @[util.scala:505:22] reg [1:0] uops_4_fp_typ; // @[util.scala:505:22] reg uops_4_xcpt_pf_if; // @[util.scala:505:22] reg uops_4_xcpt_ae_if; // @[util.scala:505:22] reg uops_4_xcpt_ma_if; // @[util.scala:505:22] reg uops_4_bp_debug_if; // @[util.scala:505:22] reg uops_4_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_5_inst; // @[util.scala:505:22] reg [31:0] uops_5_debug_inst; // @[util.scala:505:22] reg uops_5_is_rvc; // @[util.scala:505:22] reg [33:0] uops_5_debug_pc; // @[util.scala:505:22] reg uops_5_iq_type_0; // @[util.scala:505:22] reg uops_5_iq_type_1; // @[util.scala:505:22] reg uops_5_iq_type_2; // @[util.scala:505:22] reg uops_5_iq_type_3; // @[util.scala:505:22] reg uops_5_fu_code_0; // @[util.scala:505:22] reg uops_5_fu_code_1; // @[util.scala:505:22] reg uops_5_fu_code_2; // @[util.scala:505:22] reg uops_5_fu_code_3; // @[util.scala:505:22] reg uops_5_fu_code_4; // @[util.scala:505:22] reg uops_5_fu_code_5; // @[util.scala:505:22] reg uops_5_fu_code_6; // @[util.scala:505:22] reg uops_5_fu_code_7; // @[util.scala:505:22] reg uops_5_fu_code_8; // @[util.scala:505:22] reg uops_5_fu_code_9; // @[util.scala:505:22] reg uops_5_iw_issued; // @[util.scala:505:22] reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_5_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_5_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_5_br_mask; // @[util.scala:505:22] wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_5_br_tag; // @[util.scala:505:22] reg [3:0] uops_5_br_type; // @[util.scala:505:22] reg uops_5_is_sfb; // @[util.scala:505:22] reg uops_5_is_fence; // @[util.scala:505:22] reg uops_5_is_fencei; // @[util.scala:505:22] reg uops_5_is_sfence; // @[util.scala:505:22] reg uops_5_is_amo; // @[util.scala:505:22] reg uops_5_is_eret; // @[util.scala:505:22] reg uops_5_is_sys_pc2epc; // @[util.scala:505:22] reg uops_5_is_rocc; // @[util.scala:505:22] reg uops_5_is_mov; // @[util.scala:505:22] reg [3:0] uops_5_ftq_idx; // @[util.scala:505:22] reg uops_5_edge_inst; // @[util.scala:505:22] reg [5:0] uops_5_pc_lob; // @[util.scala:505:22] reg uops_5_taken; // @[util.scala:505:22] reg uops_5_imm_rename; // @[util.scala:505:22] reg [2:0] uops_5_imm_sel; // @[util.scala:505:22] reg [4:0] uops_5_pimm; // @[util.scala:505:22] reg [19:0] uops_5_imm_packed; // @[util.scala:505:22] reg [1:0] uops_5_op1_sel; // @[util.scala:505:22] reg [2:0] uops_5_op2_sel; // @[util.scala:505:22] reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_5_fp_ctrl_wen; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_5_fp_ctrl_toint; // @[util.scala:505:22] reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_5_fp_ctrl_fma; // @[util.scala:505:22] reg uops_5_fp_ctrl_div; // @[util.scala:505:22] reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_5_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_5_rob_idx; // @[util.scala:505:22] reg [3:0] uops_5_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_5_stq_idx; // @[util.scala:505:22] reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_5_pdst; // @[util.scala:505:22] reg [5:0] uops_5_prs1; // @[util.scala:505:22] reg [5:0] uops_5_prs2; // @[util.scala:505:22] reg [5:0] uops_5_prs3; // @[util.scala:505:22] reg [3:0] uops_5_ppred; // @[util.scala:505:22] reg uops_5_prs1_busy; // @[util.scala:505:22] reg uops_5_prs2_busy; // @[util.scala:505:22] reg uops_5_prs3_busy; // @[util.scala:505:22] reg uops_5_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_5_stale_pdst; // @[util.scala:505:22] reg uops_5_exception; // @[util.scala:505:22] reg [63:0] uops_5_exc_cause; // @[util.scala:505:22] reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_5_mem_size; // @[util.scala:505:22] reg uops_5_mem_signed; // @[util.scala:505:22] reg uops_5_uses_ldq; // @[util.scala:505:22] reg uops_5_uses_stq; // @[util.scala:505:22] reg uops_5_is_unique; // @[util.scala:505:22] reg uops_5_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22] reg uops_5_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_5_ldst; // @[util.scala:505:22] reg [5:0] uops_5_lrs1; // @[util.scala:505:22] reg [5:0] uops_5_lrs2; // @[util.scala:505:22] reg [5:0] uops_5_lrs3; // @[util.scala:505:22] reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22] reg uops_5_frs3_en; // @[util.scala:505:22] reg uops_5_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_5_fcn_op; // @[util.scala:505:22] reg uops_5_fp_val; // @[util.scala:505:22] reg [2:0] uops_5_fp_rm; // @[util.scala:505:22] reg [1:0] uops_5_fp_typ; // @[util.scala:505:22] reg uops_5_xcpt_pf_if; // @[util.scala:505:22] reg uops_5_xcpt_ae_if; // @[util.scala:505:22] reg uops_5_xcpt_ma_if; // @[util.scala:505:22] reg uops_5_bp_debug_if; // @[util.scala:505:22] reg uops_5_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_6_inst; // @[util.scala:505:22] reg [31:0] uops_6_debug_inst; // @[util.scala:505:22] reg uops_6_is_rvc; // @[util.scala:505:22] reg [33:0] uops_6_debug_pc; // @[util.scala:505:22] reg uops_6_iq_type_0; // @[util.scala:505:22] reg uops_6_iq_type_1; // @[util.scala:505:22] reg uops_6_iq_type_2; // @[util.scala:505:22] reg uops_6_iq_type_3; // @[util.scala:505:22] reg uops_6_fu_code_0; // @[util.scala:505:22] reg uops_6_fu_code_1; // @[util.scala:505:22] reg uops_6_fu_code_2; // @[util.scala:505:22] reg uops_6_fu_code_3; // @[util.scala:505:22] reg uops_6_fu_code_4; // @[util.scala:505:22] reg uops_6_fu_code_5; // @[util.scala:505:22] reg uops_6_fu_code_6; // @[util.scala:505:22] reg uops_6_fu_code_7; // @[util.scala:505:22] reg uops_6_fu_code_8; // @[util.scala:505:22] reg uops_6_fu_code_9; // @[util.scala:505:22] reg uops_6_iw_issued; // @[util.scala:505:22] reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_6_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_6_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_6_br_mask; // @[util.scala:505:22] wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_6_br_tag; // @[util.scala:505:22] reg [3:0] uops_6_br_type; // @[util.scala:505:22] reg uops_6_is_sfb; // @[util.scala:505:22] reg uops_6_is_fence; // @[util.scala:505:22] reg uops_6_is_fencei; // @[util.scala:505:22] reg uops_6_is_sfence; // @[util.scala:505:22] reg uops_6_is_amo; // @[util.scala:505:22] reg uops_6_is_eret; // @[util.scala:505:22] reg uops_6_is_sys_pc2epc; // @[util.scala:505:22] reg uops_6_is_rocc; // @[util.scala:505:22] reg uops_6_is_mov; // @[util.scala:505:22] reg [3:0] uops_6_ftq_idx; // @[util.scala:505:22] reg uops_6_edge_inst; // @[util.scala:505:22] reg [5:0] uops_6_pc_lob; // @[util.scala:505:22] reg uops_6_taken; // @[util.scala:505:22] reg uops_6_imm_rename; // @[util.scala:505:22] reg [2:0] uops_6_imm_sel; // @[util.scala:505:22] reg [4:0] uops_6_pimm; // @[util.scala:505:22] reg [19:0] uops_6_imm_packed; // @[util.scala:505:22] reg [1:0] uops_6_op1_sel; // @[util.scala:505:22] reg [2:0] uops_6_op2_sel; // @[util.scala:505:22] reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_6_fp_ctrl_wen; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_6_fp_ctrl_toint; // @[util.scala:505:22] reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_6_fp_ctrl_fma; // @[util.scala:505:22] reg uops_6_fp_ctrl_div; // @[util.scala:505:22] reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_6_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_6_rob_idx; // @[util.scala:505:22] reg [3:0] uops_6_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_6_stq_idx; // @[util.scala:505:22] reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_6_pdst; // @[util.scala:505:22] reg [5:0] uops_6_prs1; // @[util.scala:505:22] reg [5:0] uops_6_prs2; // @[util.scala:505:22] reg [5:0] uops_6_prs3; // @[util.scala:505:22] reg [3:0] uops_6_ppred; // @[util.scala:505:22] reg uops_6_prs1_busy; // @[util.scala:505:22] reg uops_6_prs2_busy; // @[util.scala:505:22] reg uops_6_prs3_busy; // @[util.scala:505:22] reg uops_6_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_6_stale_pdst; // @[util.scala:505:22] reg uops_6_exception; // @[util.scala:505:22] reg [63:0] uops_6_exc_cause; // @[util.scala:505:22] reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_6_mem_size; // @[util.scala:505:22] reg uops_6_mem_signed; // @[util.scala:505:22] reg uops_6_uses_ldq; // @[util.scala:505:22] reg uops_6_uses_stq; // @[util.scala:505:22] reg uops_6_is_unique; // @[util.scala:505:22] reg uops_6_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22] reg uops_6_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_6_ldst; // @[util.scala:505:22] reg [5:0] uops_6_lrs1; // @[util.scala:505:22] reg [5:0] uops_6_lrs2; // @[util.scala:505:22] reg [5:0] uops_6_lrs3; // @[util.scala:505:22] reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22] reg uops_6_frs3_en; // @[util.scala:505:22] reg uops_6_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_6_fcn_op; // @[util.scala:505:22] reg uops_6_fp_val; // @[util.scala:505:22] reg [2:0] uops_6_fp_rm; // @[util.scala:505:22] reg [1:0] uops_6_fp_typ; // @[util.scala:505:22] reg uops_6_xcpt_pf_if; // @[util.scala:505:22] reg uops_6_xcpt_ae_if; // @[util.scala:505:22] reg uops_6_xcpt_ma_if; // @[util.scala:505:22] reg uops_6_bp_debug_if; // @[util.scala:505:22] reg uops_6_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_7_inst; // @[util.scala:505:22] reg [31:0] uops_7_debug_inst; // @[util.scala:505:22] reg uops_7_is_rvc; // @[util.scala:505:22] reg [33:0] uops_7_debug_pc; // @[util.scala:505:22] reg uops_7_iq_type_0; // @[util.scala:505:22] reg uops_7_iq_type_1; // @[util.scala:505:22] reg uops_7_iq_type_2; // @[util.scala:505:22] reg uops_7_iq_type_3; // @[util.scala:505:22] reg uops_7_fu_code_0; // @[util.scala:505:22] reg uops_7_fu_code_1; // @[util.scala:505:22] reg uops_7_fu_code_2; // @[util.scala:505:22] reg uops_7_fu_code_3; // @[util.scala:505:22] reg uops_7_fu_code_4; // @[util.scala:505:22] reg uops_7_fu_code_5; // @[util.scala:505:22] reg uops_7_fu_code_6; // @[util.scala:505:22] reg uops_7_fu_code_7; // @[util.scala:505:22] reg uops_7_fu_code_8; // @[util.scala:505:22] reg uops_7_fu_code_9; // @[util.scala:505:22] reg uops_7_iw_issued; // @[util.scala:505:22] reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_7_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_7_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_7_br_mask; // @[util.scala:505:22] wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_7_br_tag; // @[util.scala:505:22] reg [3:0] uops_7_br_type; // @[util.scala:505:22] reg uops_7_is_sfb; // @[util.scala:505:22] reg uops_7_is_fence; // @[util.scala:505:22] reg uops_7_is_fencei; // @[util.scala:505:22] reg uops_7_is_sfence; // @[util.scala:505:22] reg uops_7_is_amo; // @[util.scala:505:22] reg uops_7_is_eret; // @[util.scala:505:22] reg uops_7_is_sys_pc2epc; // @[util.scala:505:22] reg uops_7_is_rocc; // @[util.scala:505:22] reg uops_7_is_mov; // @[util.scala:505:22] reg [3:0] uops_7_ftq_idx; // @[util.scala:505:22] reg uops_7_edge_inst; // @[util.scala:505:22] reg [5:0] uops_7_pc_lob; // @[util.scala:505:22] reg uops_7_taken; // @[util.scala:505:22] reg uops_7_imm_rename; // @[util.scala:505:22] reg [2:0] uops_7_imm_sel; // @[util.scala:505:22] reg [4:0] uops_7_pimm; // @[util.scala:505:22] reg [19:0] uops_7_imm_packed; // @[util.scala:505:22] reg [1:0] uops_7_op1_sel; // @[util.scala:505:22] reg [2:0] uops_7_op2_sel; // @[util.scala:505:22] reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_7_fp_ctrl_wen; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_7_fp_ctrl_toint; // @[util.scala:505:22] reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_7_fp_ctrl_fma; // @[util.scala:505:22] reg uops_7_fp_ctrl_div; // @[util.scala:505:22] reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_7_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_7_rob_idx; // @[util.scala:505:22] reg [3:0] uops_7_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_7_stq_idx; // @[util.scala:505:22] reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_7_pdst; // @[util.scala:505:22] reg [5:0] uops_7_prs1; // @[util.scala:505:22] reg [5:0] uops_7_prs2; // @[util.scala:505:22] reg [5:0] uops_7_prs3; // @[util.scala:505:22] reg [3:0] uops_7_ppred; // @[util.scala:505:22] reg uops_7_prs1_busy; // @[util.scala:505:22] reg uops_7_prs2_busy; // @[util.scala:505:22] reg uops_7_prs3_busy; // @[util.scala:505:22] reg uops_7_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_7_stale_pdst; // @[util.scala:505:22] reg uops_7_exception; // @[util.scala:505:22] reg [63:0] uops_7_exc_cause; // @[util.scala:505:22] reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_7_mem_size; // @[util.scala:505:22] reg uops_7_mem_signed; // @[util.scala:505:22] reg uops_7_uses_ldq; // @[util.scala:505:22] reg uops_7_uses_stq; // @[util.scala:505:22] reg uops_7_is_unique; // @[util.scala:505:22] reg uops_7_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22] reg uops_7_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_7_ldst; // @[util.scala:505:22] reg [5:0] uops_7_lrs1; // @[util.scala:505:22] reg [5:0] uops_7_lrs2; // @[util.scala:505:22] reg [5:0] uops_7_lrs3; // @[util.scala:505:22] reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22] reg uops_7_frs3_en; // @[util.scala:505:22] reg uops_7_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_7_fcn_op; // @[util.scala:505:22] reg uops_7_fp_val; // @[util.scala:505:22] reg [2:0] uops_7_fp_rm; // @[util.scala:505:22] reg [1:0] uops_7_fp_typ; // @[util.scala:505:22] reg uops_7_xcpt_pf_if; // @[util.scala:505:22] reg uops_7_xcpt_ae_if; // @[util.scala:505:22] reg uops_7_xcpt_ma_if; // @[util.scala:505:22] reg uops_7_bp_debug_if; // @[util.scala:505:22] reg uops_7_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_8_inst; // @[util.scala:505:22] reg [31:0] uops_8_debug_inst; // @[util.scala:505:22] reg uops_8_is_rvc; // @[util.scala:505:22] reg [33:0] uops_8_debug_pc; // @[util.scala:505:22] reg uops_8_iq_type_0; // @[util.scala:505:22] reg uops_8_iq_type_1; // @[util.scala:505:22] reg uops_8_iq_type_2; // @[util.scala:505:22] reg uops_8_iq_type_3; // @[util.scala:505:22] reg uops_8_fu_code_0; // @[util.scala:505:22] reg uops_8_fu_code_1; // @[util.scala:505:22] reg uops_8_fu_code_2; // @[util.scala:505:22] reg uops_8_fu_code_3; // @[util.scala:505:22] reg uops_8_fu_code_4; // @[util.scala:505:22] reg uops_8_fu_code_5; // @[util.scala:505:22] reg uops_8_fu_code_6; // @[util.scala:505:22] reg uops_8_fu_code_7; // @[util.scala:505:22] reg uops_8_fu_code_8; // @[util.scala:505:22] reg uops_8_fu_code_9; // @[util.scala:505:22] reg uops_8_iw_issued; // @[util.scala:505:22] reg uops_8_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_8_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_8_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_8_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_8_br_mask; // @[util.scala:505:22] wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_8_br_tag; // @[util.scala:505:22] reg [3:0] uops_8_br_type; // @[util.scala:505:22] reg uops_8_is_sfb; // @[util.scala:505:22] reg uops_8_is_fence; // @[util.scala:505:22] reg uops_8_is_fencei; // @[util.scala:505:22] reg uops_8_is_sfence; // @[util.scala:505:22] reg uops_8_is_amo; // @[util.scala:505:22] reg uops_8_is_eret; // @[util.scala:505:22] reg uops_8_is_sys_pc2epc; // @[util.scala:505:22] reg uops_8_is_rocc; // @[util.scala:505:22] reg uops_8_is_mov; // @[util.scala:505:22] reg [3:0] uops_8_ftq_idx; // @[util.scala:505:22] reg uops_8_edge_inst; // @[util.scala:505:22] reg [5:0] uops_8_pc_lob; // @[util.scala:505:22] reg uops_8_taken; // @[util.scala:505:22] reg uops_8_imm_rename; // @[util.scala:505:22] reg [2:0] uops_8_imm_sel; // @[util.scala:505:22] reg [4:0] uops_8_pimm; // @[util.scala:505:22] reg [19:0] uops_8_imm_packed; // @[util.scala:505:22] reg [1:0] uops_8_op1_sel; // @[util.scala:505:22] reg [2:0] uops_8_op2_sel; // @[util.scala:505:22] reg uops_8_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_8_fp_ctrl_wen; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_8_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_8_fp_ctrl_toint; // @[util.scala:505:22] reg uops_8_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_8_fp_ctrl_fma; // @[util.scala:505:22] reg uops_8_fp_ctrl_div; // @[util.scala:505:22] reg uops_8_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_8_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_8_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_8_rob_idx; // @[util.scala:505:22] reg [3:0] uops_8_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_8_stq_idx; // @[util.scala:505:22] reg [1:0] uops_8_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_8_pdst; // @[util.scala:505:22] reg [5:0] uops_8_prs1; // @[util.scala:505:22] reg [5:0] uops_8_prs2; // @[util.scala:505:22] reg [5:0] uops_8_prs3; // @[util.scala:505:22] reg [3:0] uops_8_ppred; // @[util.scala:505:22] reg uops_8_prs1_busy; // @[util.scala:505:22] reg uops_8_prs2_busy; // @[util.scala:505:22] reg uops_8_prs3_busy; // @[util.scala:505:22] reg uops_8_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_8_stale_pdst; // @[util.scala:505:22] reg uops_8_exception; // @[util.scala:505:22] reg [63:0] uops_8_exc_cause; // @[util.scala:505:22] reg [4:0] uops_8_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_8_mem_size; // @[util.scala:505:22] reg uops_8_mem_signed; // @[util.scala:505:22] reg uops_8_uses_ldq; // @[util.scala:505:22] reg uops_8_uses_stq; // @[util.scala:505:22] reg uops_8_is_unique; // @[util.scala:505:22] reg uops_8_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_8_csr_cmd; // @[util.scala:505:22] reg uops_8_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_8_ldst; // @[util.scala:505:22] reg [5:0] uops_8_lrs1; // @[util.scala:505:22] reg [5:0] uops_8_lrs2; // @[util.scala:505:22] reg [5:0] uops_8_lrs3; // @[util.scala:505:22] reg [1:0] uops_8_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:505:22] reg uops_8_frs3_en; // @[util.scala:505:22] reg uops_8_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_8_fcn_op; // @[util.scala:505:22] reg uops_8_fp_val; // @[util.scala:505:22] reg [2:0] uops_8_fp_rm; // @[util.scala:505:22] reg [1:0] uops_8_fp_typ; // @[util.scala:505:22] reg uops_8_xcpt_pf_if; // @[util.scala:505:22] reg uops_8_xcpt_ae_if; // @[util.scala:505:22] reg uops_8_xcpt_ma_if; // @[util.scala:505:22] reg uops_8_bp_debug_if; // @[util.scala:505:22] reg uops_8_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_8_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_8_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_9_inst; // @[util.scala:505:22] reg [31:0] uops_9_debug_inst; // @[util.scala:505:22] reg uops_9_is_rvc; // @[util.scala:505:22] reg [33:0] uops_9_debug_pc; // @[util.scala:505:22] reg uops_9_iq_type_0; // @[util.scala:505:22] reg uops_9_iq_type_1; // @[util.scala:505:22] reg uops_9_iq_type_2; // @[util.scala:505:22] reg uops_9_iq_type_3; // @[util.scala:505:22] reg uops_9_fu_code_0; // @[util.scala:505:22] reg uops_9_fu_code_1; // @[util.scala:505:22] reg uops_9_fu_code_2; // @[util.scala:505:22] reg uops_9_fu_code_3; // @[util.scala:505:22] reg uops_9_fu_code_4; // @[util.scala:505:22] reg uops_9_fu_code_5; // @[util.scala:505:22] reg uops_9_fu_code_6; // @[util.scala:505:22] reg uops_9_fu_code_7; // @[util.scala:505:22] reg uops_9_fu_code_8; // @[util.scala:505:22] reg uops_9_fu_code_9; // @[util.scala:505:22] reg uops_9_iw_issued; // @[util.scala:505:22] reg uops_9_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_9_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_9_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_9_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_9_br_mask; // @[util.scala:505:22] wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_9_br_tag; // @[util.scala:505:22] reg [3:0] uops_9_br_type; // @[util.scala:505:22] reg uops_9_is_sfb; // @[util.scala:505:22] reg uops_9_is_fence; // @[util.scala:505:22] reg uops_9_is_fencei; // @[util.scala:505:22] reg uops_9_is_sfence; // @[util.scala:505:22] reg uops_9_is_amo; // @[util.scala:505:22] reg uops_9_is_eret; // @[util.scala:505:22] reg uops_9_is_sys_pc2epc; // @[util.scala:505:22] reg uops_9_is_rocc; // @[util.scala:505:22] reg uops_9_is_mov; // @[util.scala:505:22] reg [3:0] uops_9_ftq_idx; // @[util.scala:505:22] reg uops_9_edge_inst; // @[util.scala:505:22] reg [5:0] uops_9_pc_lob; // @[util.scala:505:22] reg uops_9_taken; // @[util.scala:505:22] reg uops_9_imm_rename; // @[util.scala:505:22] reg [2:0] uops_9_imm_sel; // @[util.scala:505:22] reg [4:0] uops_9_pimm; // @[util.scala:505:22] reg [19:0] uops_9_imm_packed; // @[util.scala:505:22] reg [1:0] uops_9_op1_sel; // @[util.scala:505:22] reg [2:0] uops_9_op2_sel; // @[util.scala:505:22] reg uops_9_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_9_fp_ctrl_wen; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_9_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_9_fp_ctrl_toint; // @[util.scala:505:22] reg uops_9_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_9_fp_ctrl_fma; // @[util.scala:505:22] reg uops_9_fp_ctrl_div; // @[util.scala:505:22] reg uops_9_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_9_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_9_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_9_rob_idx; // @[util.scala:505:22] reg [3:0] uops_9_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_9_stq_idx; // @[util.scala:505:22] reg [1:0] uops_9_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_9_pdst; // @[util.scala:505:22] reg [5:0] uops_9_prs1; // @[util.scala:505:22] reg [5:0] uops_9_prs2; // @[util.scala:505:22] reg [5:0] uops_9_prs3; // @[util.scala:505:22] reg [3:0] uops_9_ppred; // @[util.scala:505:22] reg uops_9_prs1_busy; // @[util.scala:505:22] reg uops_9_prs2_busy; // @[util.scala:505:22] reg uops_9_prs3_busy; // @[util.scala:505:22] reg uops_9_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_9_stale_pdst; // @[util.scala:505:22] reg uops_9_exception; // @[util.scala:505:22] reg [63:0] uops_9_exc_cause; // @[util.scala:505:22] reg [4:0] uops_9_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_9_mem_size; // @[util.scala:505:22] reg uops_9_mem_signed; // @[util.scala:505:22] reg uops_9_uses_ldq; // @[util.scala:505:22] reg uops_9_uses_stq; // @[util.scala:505:22] reg uops_9_is_unique; // @[util.scala:505:22] reg uops_9_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_9_csr_cmd; // @[util.scala:505:22] reg uops_9_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_9_ldst; // @[util.scala:505:22] reg [5:0] uops_9_lrs1; // @[util.scala:505:22] reg [5:0] uops_9_lrs2; // @[util.scala:505:22] reg [5:0] uops_9_lrs3; // @[util.scala:505:22] reg [1:0] uops_9_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:505:22] reg uops_9_frs3_en; // @[util.scala:505:22] reg uops_9_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_9_fcn_op; // @[util.scala:505:22] reg uops_9_fp_val; // @[util.scala:505:22] reg [2:0] uops_9_fp_rm; // @[util.scala:505:22] reg [1:0] uops_9_fp_typ; // @[util.scala:505:22] reg uops_9_xcpt_pf_if; // @[util.scala:505:22] reg uops_9_xcpt_ae_if; // @[util.scala:505:22] reg uops_9_xcpt_ma_if; // @[util.scala:505:22] reg uops_9_bp_debug_if; // @[util.scala:505:22] reg uops_9_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_9_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_9_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_10_inst; // @[util.scala:505:22] reg [31:0] uops_10_debug_inst; // @[util.scala:505:22] reg uops_10_is_rvc; // @[util.scala:505:22] reg [33:0] uops_10_debug_pc; // @[util.scala:505:22] reg uops_10_iq_type_0; // @[util.scala:505:22] reg uops_10_iq_type_1; // @[util.scala:505:22] reg uops_10_iq_type_2; // @[util.scala:505:22] reg uops_10_iq_type_3; // @[util.scala:505:22] reg uops_10_fu_code_0; // @[util.scala:505:22] reg uops_10_fu_code_1; // @[util.scala:505:22] reg uops_10_fu_code_2; // @[util.scala:505:22] reg uops_10_fu_code_3; // @[util.scala:505:22] reg uops_10_fu_code_4; // @[util.scala:505:22] reg uops_10_fu_code_5; // @[util.scala:505:22] reg uops_10_fu_code_6; // @[util.scala:505:22] reg uops_10_fu_code_7; // @[util.scala:505:22] reg uops_10_fu_code_8; // @[util.scala:505:22] reg uops_10_fu_code_9; // @[util.scala:505:22] reg uops_10_iw_issued; // @[util.scala:505:22] reg uops_10_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_10_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_10_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_10_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_10_br_mask; // @[util.scala:505:22] wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_10_br_tag; // @[util.scala:505:22] reg [3:0] uops_10_br_type; // @[util.scala:505:22] reg uops_10_is_sfb; // @[util.scala:505:22] reg uops_10_is_fence; // @[util.scala:505:22] reg uops_10_is_fencei; // @[util.scala:505:22] reg uops_10_is_sfence; // @[util.scala:505:22] reg uops_10_is_amo; // @[util.scala:505:22] reg uops_10_is_eret; // @[util.scala:505:22] reg uops_10_is_sys_pc2epc; // @[util.scala:505:22] reg uops_10_is_rocc; // @[util.scala:505:22] reg uops_10_is_mov; // @[util.scala:505:22] reg [3:0] uops_10_ftq_idx; // @[util.scala:505:22] reg uops_10_edge_inst; // @[util.scala:505:22] reg [5:0] uops_10_pc_lob; // @[util.scala:505:22] reg uops_10_taken; // @[util.scala:505:22] reg uops_10_imm_rename; // @[util.scala:505:22] reg [2:0] uops_10_imm_sel; // @[util.scala:505:22] reg [4:0] uops_10_pimm; // @[util.scala:505:22] reg [19:0] uops_10_imm_packed; // @[util.scala:505:22] reg [1:0] uops_10_op1_sel; // @[util.scala:505:22] reg [2:0] uops_10_op2_sel; // @[util.scala:505:22] reg uops_10_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_10_fp_ctrl_wen; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_10_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_10_fp_ctrl_toint; // @[util.scala:505:22] reg uops_10_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_10_fp_ctrl_fma; // @[util.scala:505:22] reg uops_10_fp_ctrl_div; // @[util.scala:505:22] reg uops_10_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_10_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_10_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_10_rob_idx; // @[util.scala:505:22] reg [3:0] uops_10_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_10_stq_idx; // @[util.scala:505:22] reg [1:0] uops_10_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_10_pdst; // @[util.scala:505:22] reg [5:0] uops_10_prs1; // @[util.scala:505:22] reg [5:0] uops_10_prs2; // @[util.scala:505:22] reg [5:0] uops_10_prs3; // @[util.scala:505:22] reg [3:0] uops_10_ppred; // @[util.scala:505:22] reg uops_10_prs1_busy; // @[util.scala:505:22] reg uops_10_prs2_busy; // @[util.scala:505:22] reg uops_10_prs3_busy; // @[util.scala:505:22] reg uops_10_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_10_stale_pdst; // @[util.scala:505:22] reg uops_10_exception; // @[util.scala:505:22] reg [63:0] uops_10_exc_cause; // @[util.scala:505:22] reg [4:0] uops_10_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_10_mem_size; // @[util.scala:505:22] reg uops_10_mem_signed; // @[util.scala:505:22] reg uops_10_uses_ldq; // @[util.scala:505:22] reg uops_10_uses_stq; // @[util.scala:505:22] reg uops_10_is_unique; // @[util.scala:505:22] reg uops_10_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_10_csr_cmd; // @[util.scala:505:22] reg uops_10_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_10_ldst; // @[util.scala:505:22] reg [5:0] uops_10_lrs1; // @[util.scala:505:22] reg [5:0] uops_10_lrs2; // @[util.scala:505:22] reg [5:0] uops_10_lrs3; // @[util.scala:505:22] reg [1:0] uops_10_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:505:22] reg uops_10_frs3_en; // @[util.scala:505:22] reg uops_10_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_10_fcn_op; // @[util.scala:505:22] reg uops_10_fp_val; // @[util.scala:505:22] reg [2:0] uops_10_fp_rm; // @[util.scala:505:22] reg [1:0] uops_10_fp_typ; // @[util.scala:505:22] reg uops_10_xcpt_pf_if; // @[util.scala:505:22] reg uops_10_xcpt_ae_if; // @[util.scala:505:22] reg uops_10_xcpt_ma_if; // @[util.scala:505:22] reg uops_10_bp_debug_if; // @[util.scala:505:22] reg uops_10_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_10_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_10_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_11_inst; // @[util.scala:505:22] reg [31:0] uops_11_debug_inst; // @[util.scala:505:22] reg uops_11_is_rvc; // @[util.scala:505:22] reg [33:0] uops_11_debug_pc; // @[util.scala:505:22] reg uops_11_iq_type_0; // @[util.scala:505:22] reg uops_11_iq_type_1; // @[util.scala:505:22] reg uops_11_iq_type_2; // @[util.scala:505:22] reg uops_11_iq_type_3; // @[util.scala:505:22] reg uops_11_fu_code_0; // @[util.scala:505:22] reg uops_11_fu_code_1; // @[util.scala:505:22] reg uops_11_fu_code_2; // @[util.scala:505:22] reg uops_11_fu_code_3; // @[util.scala:505:22] reg uops_11_fu_code_4; // @[util.scala:505:22] reg uops_11_fu_code_5; // @[util.scala:505:22] reg uops_11_fu_code_6; // @[util.scala:505:22] reg uops_11_fu_code_7; // @[util.scala:505:22] reg uops_11_fu_code_8; // @[util.scala:505:22] reg uops_11_fu_code_9; // @[util.scala:505:22] reg uops_11_iw_issued; // @[util.scala:505:22] reg uops_11_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_11_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_11_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_11_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_11_br_mask; // @[util.scala:505:22] wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_11_br_tag; // @[util.scala:505:22] reg [3:0] uops_11_br_type; // @[util.scala:505:22] reg uops_11_is_sfb; // @[util.scala:505:22] reg uops_11_is_fence; // @[util.scala:505:22] reg uops_11_is_fencei; // @[util.scala:505:22] reg uops_11_is_sfence; // @[util.scala:505:22] reg uops_11_is_amo; // @[util.scala:505:22] reg uops_11_is_eret; // @[util.scala:505:22] reg uops_11_is_sys_pc2epc; // @[util.scala:505:22] reg uops_11_is_rocc; // @[util.scala:505:22] reg uops_11_is_mov; // @[util.scala:505:22] reg [3:0] uops_11_ftq_idx; // @[util.scala:505:22] reg uops_11_edge_inst; // @[util.scala:505:22] reg [5:0] uops_11_pc_lob; // @[util.scala:505:22] reg uops_11_taken; // @[util.scala:505:22] reg uops_11_imm_rename; // @[util.scala:505:22] reg [2:0] uops_11_imm_sel; // @[util.scala:505:22] reg [4:0] uops_11_pimm; // @[util.scala:505:22] reg [19:0] uops_11_imm_packed; // @[util.scala:505:22] reg [1:0] uops_11_op1_sel; // @[util.scala:505:22] reg [2:0] uops_11_op2_sel; // @[util.scala:505:22] reg uops_11_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_11_fp_ctrl_wen; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_11_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_11_fp_ctrl_toint; // @[util.scala:505:22] reg uops_11_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_11_fp_ctrl_fma; // @[util.scala:505:22] reg uops_11_fp_ctrl_div; // @[util.scala:505:22] reg uops_11_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_11_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_11_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_11_rob_idx; // @[util.scala:505:22] reg [3:0] uops_11_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_11_stq_idx; // @[util.scala:505:22] reg [1:0] uops_11_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_11_pdst; // @[util.scala:505:22] reg [5:0] uops_11_prs1; // @[util.scala:505:22] reg [5:0] uops_11_prs2; // @[util.scala:505:22] reg [5:0] uops_11_prs3; // @[util.scala:505:22] reg [3:0] uops_11_ppred; // @[util.scala:505:22] reg uops_11_prs1_busy; // @[util.scala:505:22] reg uops_11_prs2_busy; // @[util.scala:505:22] reg uops_11_prs3_busy; // @[util.scala:505:22] reg uops_11_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_11_stale_pdst; // @[util.scala:505:22] reg uops_11_exception; // @[util.scala:505:22] reg [63:0] uops_11_exc_cause; // @[util.scala:505:22] reg [4:0] uops_11_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_11_mem_size; // @[util.scala:505:22] reg uops_11_mem_signed; // @[util.scala:505:22] reg uops_11_uses_ldq; // @[util.scala:505:22] reg uops_11_uses_stq; // @[util.scala:505:22] reg uops_11_is_unique; // @[util.scala:505:22] reg uops_11_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_11_csr_cmd; // @[util.scala:505:22] reg uops_11_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_11_ldst; // @[util.scala:505:22] reg [5:0] uops_11_lrs1; // @[util.scala:505:22] reg [5:0] uops_11_lrs2; // @[util.scala:505:22] reg [5:0] uops_11_lrs3; // @[util.scala:505:22] reg [1:0] uops_11_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:505:22] reg uops_11_frs3_en; // @[util.scala:505:22] reg uops_11_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_11_fcn_op; // @[util.scala:505:22] reg uops_11_fp_val; // @[util.scala:505:22] reg [2:0] uops_11_fp_rm; // @[util.scala:505:22] reg [1:0] uops_11_fp_typ; // @[util.scala:505:22] reg uops_11_xcpt_pf_if; // @[util.scala:505:22] reg uops_11_xcpt_ae_if; // @[util.scala:505:22] reg uops_11_xcpt_ma_if; // @[util.scala:505:22] reg uops_11_bp_debug_if; // @[util.scala:505:22] reg uops_11_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_11_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_11_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_12_inst; // @[util.scala:505:22] reg [31:0] uops_12_debug_inst; // @[util.scala:505:22] reg uops_12_is_rvc; // @[util.scala:505:22] reg [33:0] uops_12_debug_pc; // @[util.scala:505:22] reg uops_12_iq_type_0; // @[util.scala:505:22] reg uops_12_iq_type_1; // @[util.scala:505:22] reg uops_12_iq_type_2; // @[util.scala:505:22] reg uops_12_iq_type_3; // @[util.scala:505:22] reg uops_12_fu_code_0; // @[util.scala:505:22] reg uops_12_fu_code_1; // @[util.scala:505:22] reg uops_12_fu_code_2; // @[util.scala:505:22] reg uops_12_fu_code_3; // @[util.scala:505:22] reg uops_12_fu_code_4; // @[util.scala:505:22] reg uops_12_fu_code_5; // @[util.scala:505:22] reg uops_12_fu_code_6; // @[util.scala:505:22] reg uops_12_fu_code_7; // @[util.scala:505:22] reg uops_12_fu_code_8; // @[util.scala:505:22] reg uops_12_fu_code_9; // @[util.scala:505:22] reg uops_12_iw_issued; // @[util.scala:505:22] reg uops_12_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_12_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_12_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_12_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_12_br_mask; // @[util.scala:505:22] wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_12_br_tag; // @[util.scala:505:22] reg [3:0] uops_12_br_type; // @[util.scala:505:22] reg uops_12_is_sfb; // @[util.scala:505:22] reg uops_12_is_fence; // @[util.scala:505:22] reg uops_12_is_fencei; // @[util.scala:505:22] reg uops_12_is_sfence; // @[util.scala:505:22] reg uops_12_is_amo; // @[util.scala:505:22] reg uops_12_is_eret; // @[util.scala:505:22] reg uops_12_is_sys_pc2epc; // @[util.scala:505:22] reg uops_12_is_rocc; // @[util.scala:505:22] reg uops_12_is_mov; // @[util.scala:505:22] reg [3:0] uops_12_ftq_idx; // @[util.scala:505:22] reg uops_12_edge_inst; // @[util.scala:505:22] reg [5:0] uops_12_pc_lob; // @[util.scala:505:22] reg uops_12_taken; // @[util.scala:505:22] reg uops_12_imm_rename; // @[util.scala:505:22] reg [2:0] uops_12_imm_sel; // @[util.scala:505:22] reg [4:0] uops_12_pimm; // @[util.scala:505:22] reg [19:0] uops_12_imm_packed; // @[util.scala:505:22] reg [1:0] uops_12_op1_sel; // @[util.scala:505:22] reg [2:0] uops_12_op2_sel; // @[util.scala:505:22] reg uops_12_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_12_fp_ctrl_wen; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_12_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_12_fp_ctrl_toint; // @[util.scala:505:22] reg uops_12_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_12_fp_ctrl_fma; // @[util.scala:505:22] reg uops_12_fp_ctrl_div; // @[util.scala:505:22] reg uops_12_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_12_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_12_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_12_rob_idx; // @[util.scala:505:22] reg [3:0] uops_12_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_12_stq_idx; // @[util.scala:505:22] reg [1:0] uops_12_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_12_pdst; // @[util.scala:505:22] reg [5:0] uops_12_prs1; // @[util.scala:505:22] reg [5:0] uops_12_prs2; // @[util.scala:505:22] reg [5:0] uops_12_prs3; // @[util.scala:505:22] reg [3:0] uops_12_ppred; // @[util.scala:505:22] reg uops_12_prs1_busy; // @[util.scala:505:22] reg uops_12_prs2_busy; // @[util.scala:505:22] reg uops_12_prs3_busy; // @[util.scala:505:22] reg uops_12_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_12_stale_pdst; // @[util.scala:505:22] reg uops_12_exception; // @[util.scala:505:22] reg [63:0] uops_12_exc_cause; // @[util.scala:505:22] reg [4:0] uops_12_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_12_mem_size; // @[util.scala:505:22] reg uops_12_mem_signed; // @[util.scala:505:22] reg uops_12_uses_ldq; // @[util.scala:505:22] reg uops_12_uses_stq; // @[util.scala:505:22] reg uops_12_is_unique; // @[util.scala:505:22] reg uops_12_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_12_csr_cmd; // @[util.scala:505:22] reg uops_12_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_12_ldst; // @[util.scala:505:22] reg [5:0] uops_12_lrs1; // @[util.scala:505:22] reg [5:0] uops_12_lrs2; // @[util.scala:505:22] reg [5:0] uops_12_lrs3; // @[util.scala:505:22] reg [1:0] uops_12_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:505:22] reg uops_12_frs3_en; // @[util.scala:505:22] reg uops_12_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_12_fcn_op; // @[util.scala:505:22] reg uops_12_fp_val; // @[util.scala:505:22] reg [2:0] uops_12_fp_rm; // @[util.scala:505:22] reg [1:0] uops_12_fp_typ; // @[util.scala:505:22] reg uops_12_xcpt_pf_if; // @[util.scala:505:22] reg uops_12_xcpt_ae_if; // @[util.scala:505:22] reg uops_12_xcpt_ma_if; // @[util.scala:505:22] reg uops_12_bp_debug_if; // @[util.scala:505:22] reg uops_12_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_12_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_12_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_13_inst; // @[util.scala:505:22] reg [31:0] uops_13_debug_inst; // @[util.scala:505:22] reg uops_13_is_rvc; // @[util.scala:505:22] reg [33:0] uops_13_debug_pc; // @[util.scala:505:22] reg uops_13_iq_type_0; // @[util.scala:505:22] reg uops_13_iq_type_1; // @[util.scala:505:22] reg uops_13_iq_type_2; // @[util.scala:505:22] reg uops_13_iq_type_3; // @[util.scala:505:22] reg uops_13_fu_code_0; // @[util.scala:505:22] reg uops_13_fu_code_1; // @[util.scala:505:22] reg uops_13_fu_code_2; // @[util.scala:505:22] reg uops_13_fu_code_3; // @[util.scala:505:22] reg uops_13_fu_code_4; // @[util.scala:505:22] reg uops_13_fu_code_5; // @[util.scala:505:22] reg uops_13_fu_code_6; // @[util.scala:505:22] reg uops_13_fu_code_7; // @[util.scala:505:22] reg uops_13_fu_code_8; // @[util.scala:505:22] reg uops_13_fu_code_9; // @[util.scala:505:22] reg uops_13_iw_issued; // @[util.scala:505:22] reg uops_13_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_13_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_13_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_13_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_13_br_mask; // @[util.scala:505:22] wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_13_br_tag; // @[util.scala:505:22] reg [3:0] uops_13_br_type; // @[util.scala:505:22] reg uops_13_is_sfb; // @[util.scala:505:22] reg uops_13_is_fence; // @[util.scala:505:22] reg uops_13_is_fencei; // @[util.scala:505:22] reg uops_13_is_sfence; // @[util.scala:505:22] reg uops_13_is_amo; // @[util.scala:505:22] reg uops_13_is_eret; // @[util.scala:505:22] reg uops_13_is_sys_pc2epc; // @[util.scala:505:22] reg uops_13_is_rocc; // @[util.scala:505:22] reg uops_13_is_mov; // @[util.scala:505:22] reg [3:0] uops_13_ftq_idx; // @[util.scala:505:22] reg uops_13_edge_inst; // @[util.scala:505:22] reg [5:0] uops_13_pc_lob; // @[util.scala:505:22] reg uops_13_taken; // @[util.scala:505:22] reg uops_13_imm_rename; // @[util.scala:505:22] reg [2:0] uops_13_imm_sel; // @[util.scala:505:22] reg [4:0] uops_13_pimm; // @[util.scala:505:22] reg [19:0] uops_13_imm_packed; // @[util.scala:505:22] reg [1:0] uops_13_op1_sel; // @[util.scala:505:22] reg [2:0] uops_13_op2_sel; // @[util.scala:505:22] reg uops_13_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_13_fp_ctrl_wen; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_13_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_13_fp_ctrl_toint; // @[util.scala:505:22] reg uops_13_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_13_fp_ctrl_fma; // @[util.scala:505:22] reg uops_13_fp_ctrl_div; // @[util.scala:505:22] reg uops_13_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_13_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_13_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_13_rob_idx; // @[util.scala:505:22] reg [3:0] uops_13_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_13_stq_idx; // @[util.scala:505:22] reg [1:0] uops_13_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_13_pdst; // @[util.scala:505:22] reg [5:0] uops_13_prs1; // @[util.scala:505:22] reg [5:0] uops_13_prs2; // @[util.scala:505:22] reg [5:0] uops_13_prs3; // @[util.scala:505:22] reg [3:0] uops_13_ppred; // @[util.scala:505:22] reg uops_13_prs1_busy; // @[util.scala:505:22] reg uops_13_prs2_busy; // @[util.scala:505:22] reg uops_13_prs3_busy; // @[util.scala:505:22] reg uops_13_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_13_stale_pdst; // @[util.scala:505:22] reg uops_13_exception; // @[util.scala:505:22] reg [63:0] uops_13_exc_cause; // @[util.scala:505:22] reg [4:0] uops_13_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_13_mem_size; // @[util.scala:505:22] reg uops_13_mem_signed; // @[util.scala:505:22] reg uops_13_uses_ldq; // @[util.scala:505:22] reg uops_13_uses_stq; // @[util.scala:505:22] reg uops_13_is_unique; // @[util.scala:505:22] reg uops_13_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_13_csr_cmd; // @[util.scala:505:22] reg uops_13_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_13_ldst; // @[util.scala:505:22] reg [5:0] uops_13_lrs1; // @[util.scala:505:22] reg [5:0] uops_13_lrs2; // @[util.scala:505:22] reg [5:0] uops_13_lrs3; // @[util.scala:505:22] reg [1:0] uops_13_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:505:22] reg uops_13_frs3_en; // @[util.scala:505:22] reg uops_13_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_13_fcn_op; // @[util.scala:505:22] reg uops_13_fp_val; // @[util.scala:505:22] reg [2:0] uops_13_fp_rm; // @[util.scala:505:22] reg [1:0] uops_13_fp_typ; // @[util.scala:505:22] reg uops_13_xcpt_pf_if; // @[util.scala:505:22] reg uops_13_xcpt_ae_if; // @[util.scala:505:22] reg uops_13_xcpt_ma_if; // @[util.scala:505:22] reg uops_13_bp_debug_if; // @[util.scala:505:22] reg uops_13_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_13_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_13_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_14_inst; // @[util.scala:505:22] reg [31:0] uops_14_debug_inst; // @[util.scala:505:22] reg uops_14_is_rvc; // @[util.scala:505:22] reg [33:0] uops_14_debug_pc; // @[util.scala:505:22] reg uops_14_iq_type_0; // @[util.scala:505:22] reg uops_14_iq_type_1; // @[util.scala:505:22] reg uops_14_iq_type_2; // @[util.scala:505:22] reg uops_14_iq_type_3; // @[util.scala:505:22] reg uops_14_fu_code_0; // @[util.scala:505:22] reg uops_14_fu_code_1; // @[util.scala:505:22] reg uops_14_fu_code_2; // @[util.scala:505:22] reg uops_14_fu_code_3; // @[util.scala:505:22] reg uops_14_fu_code_4; // @[util.scala:505:22] reg uops_14_fu_code_5; // @[util.scala:505:22] reg uops_14_fu_code_6; // @[util.scala:505:22] reg uops_14_fu_code_7; // @[util.scala:505:22] reg uops_14_fu_code_8; // @[util.scala:505:22] reg uops_14_fu_code_9; // @[util.scala:505:22] reg uops_14_iw_issued; // @[util.scala:505:22] reg uops_14_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_14_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_14_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_14_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_14_br_mask; // @[util.scala:505:22] wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_14_br_tag; // @[util.scala:505:22] reg [3:0] uops_14_br_type; // @[util.scala:505:22] reg uops_14_is_sfb; // @[util.scala:505:22] reg uops_14_is_fence; // @[util.scala:505:22] reg uops_14_is_fencei; // @[util.scala:505:22] reg uops_14_is_sfence; // @[util.scala:505:22] reg uops_14_is_amo; // @[util.scala:505:22] reg uops_14_is_eret; // @[util.scala:505:22] reg uops_14_is_sys_pc2epc; // @[util.scala:505:22] reg uops_14_is_rocc; // @[util.scala:505:22] reg uops_14_is_mov; // @[util.scala:505:22] reg [3:0] uops_14_ftq_idx; // @[util.scala:505:22] reg uops_14_edge_inst; // @[util.scala:505:22] reg [5:0] uops_14_pc_lob; // @[util.scala:505:22] reg uops_14_taken; // @[util.scala:505:22] reg uops_14_imm_rename; // @[util.scala:505:22] reg [2:0] uops_14_imm_sel; // @[util.scala:505:22] reg [4:0] uops_14_pimm; // @[util.scala:505:22] reg [19:0] uops_14_imm_packed; // @[util.scala:505:22] reg [1:0] uops_14_op1_sel; // @[util.scala:505:22] reg [2:0] uops_14_op2_sel; // @[util.scala:505:22] reg uops_14_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_14_fp_ctrl_wen; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_14_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_14_fp_ctrl_toint; // @[util.scala:505:22] reg uops_14_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_14_fp_ctrl_fma; // @[util.scala:505:22] reg uops_14_fp_ctrl_div; // @[util.scala:505:22] reg uops_14_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_14_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_14_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_14_rob_idx; // @[util.scala:505:22] reg [3:0] uops_14_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_14_stq_idx; // @[util.scala:505:22] reg [1:0] uops_14_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_14_pdst; // @[util.scala:505:22] reg [5:0] uops_14_prs1; // @[util.scala:505:22] reg [5:0] uops_14_prs2; // @[util.scala:505:22] reg [5:0] uops_14_prs3; // @[util.scala:505:22] reg [3:0] uops_14_ppred; // @[util.scala:505:22] reg uops_14_prs1_busy; // @[util.scala:505:22] reg uops_14_prs2_busy; // @[util.scala:505:22] reg uops_14_prs3_busy; // @[util.scala:505:22] reg uops_14_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_14_stale_pdst; // @[util.scala:505:22] reg uops_14_exception; // @[util.scala:505:22] reg [63:0] uops_14_exc_cause; // @[util.scala:505:22] reg [4:0] uops_14_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_14_mem_size; // @[util.scala:505:22] reg uops_14_mem_signed; // @[util.scala:505:22] reg uops_14_uses_ldq; // @[util.scala:505:22] reg uops_14_uses_stq; // @[util.scala:505:22] reg uops_14_is_unique; // @[util.scala:505:22] reg uops_14_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_14_csr_cmd; // @[util.scala:505:22] reg uops_14_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_14_ldst; // @[util.scala:505:22] reg [5:0] uops_14_lrs1; // @[util.scala:505:22] reg [5:0] uops_14_lrs2; // @[util.scala:505:22] reg [5:0] uops_14_lrs3; // @[util.scala:505:22] reg [1:0] uops_14_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:505:22] reg uops_14_frs3_en; // @[util.scala:505:22] reg uops_14_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_14_fcn_op; // @[util.scala:505:22] reg uops_14_fp_val; // @[util.scala:505:22] reg [2:0] uops_14_fp_rm; // @[util.scala:505:22] reg [1:0] uops_14_fp_typ; // @[util.scala:505:22] reg uops_14_xcpt_pf_if; // @[util.scala:505:22] reg uops_14_xcpt_ae_if; // @[util.scala:505:22] reg uops_14_xcpt_ma_if; // @[util.scala:505:22] reg uops_14_bp_debug_if; // @[util.scala:505:22] reg uops_14_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_14_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_14_debug_tsrc; // @[util.scala:505:22] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:509:29] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :512:27] wire full = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _do_enq_T_5 = _do_enq_T; // @[Decoupled.scala:51:35] wire _do_enq_T_8 = _do_enq_T_5; // @[util.scala:514:{39,99}] wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}] wire [15:0] _GEN = {{valids_0}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44] wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_0; // @[util.scala:515:44] wire _do_deq_T_1 = io_deq_ready_0 \| _do_deq_T; // @[util.scala:458:7, :515:{41,44}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:458:7, :515:71] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}] wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}] wire _valids_0_T_7 = _valids_0_T_4; // @[util.scala:520:{31,80}] wire _valids_1_T_7 = _valids_1_T_4; // @[util.scala:520:{31,80}] wire _valids_2_T_7 = _valids_2_T_4; // @[util.scala:520:{31,80}] wire _valids_3_T_7 = _valids_3_T_4; // @[util.scala:520:{31,80}] wire _valids_4_T_7 = _valids_4_T_4; // @[util.scala:520:{31,80}] wire _valids_5_T_7 = _valids_5_T_4; // @[util.scala:520:{31,80}] wire _valids_6_T_7 = _valids_6_T_4; // @[util.scala:520:{31,80}] wire _valids_7_T_7 = _valids_7_T_4; // @[util.scala:520:{31,80}] wire _valids_8_T_7 = _valids_8_T_4; // @[util.scala:520:{31,80}] wire _valids_9_T_7 = _valids_9_T_4; // @[util.scala:520:{31,80}] wire _valids_10_T_7 = _valids_10_T_4; // @[util.scala:520:{31,80}] wire _valids_11_T_7 = _valids_11_T_4; // @[util.scala:520:{31,80}] wire _valids_12_T_7 = _valids_12_T_4; // @[util.scala:520:{31,80}] wire _valids_13_T_7 = _valids_13_T_4; // @[util.scala:520:{31,80}] wire _valids_14_T_7 = _valids_14_T_4; // @[util.scala:520:{31,80}] wire wrap = enq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_1 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = deq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:458:7, :545:19] assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:458:7, :545:19] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_way_en_0 = out_way_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:458:7, :545:19] wire [15:0][31:0] _GEN_3 = {{uops_0_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_inst = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_4 = {{uops_0_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_5 = {{uops_0_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rvc = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][33:0] _GEN_6 = {{uops_0_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_pc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_0_iq_type_0}, {uops_14_iq_type_0}, {uops_13_iq_type_0}, {uops_12_iq_type_0}, {uops_11_iq_type_0}, {uops_10_iq_type_0}, {uops_9_iq_type_0}, {uops_8_iq_type_0}, {uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_0 = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_8 = {{uops_0_iq_type_1}, {uops_14_iq_type_1}, {uops_13_iq_type_1}, {uops_12_iq_type_1}, {uops_11_iq_type_1}, {uops_10_iq_type_1}, {uops_9_iq_type_1}, {uops_8_iq_type_1}, {uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_1 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_9 = {{uops_0_iq_type_2}, {uops_14_iq_type_2}, {uops_13_iq_type_2}, {uops_12_iq_type_2}, {uops_11_iq_type_2}, {uops_10_iq_type_2}, {uops_9_iq_type_2}, {uops_8_iq_type_2}, {uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_2 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_10 = {{uops_0_iq_type_3}, {uops_14_iq_type_3}, {uops_13_iq_type_3}, {uops_12_iq_type_3}, {uops_11_iq_type_3}, {uops_10_iq_type_3}, {uops_9_iq_type_3}, {uops_8_iq_type_3}, {uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_3 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_11 = {{uops_0_fu_code_0}, {uops_14_fu_code_0}, {uops_13_fu_code_0}, {uops_12_fu_code_0}, {uops_11_fu_code_0}, {uops_10_fu_code_0}, {uops_9_fu_code_0}, {uops_8_fu_code_0}, {uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_0 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_12 = {{uops_0_fu_code_1}, {uops_14_fu_code_1}, {uops_13_fu_code_1}, {uops_12_fu_code_1}, {uops_11_fu_code_1}, {uops_10_fu_code_1}, {uops_9_fu_code_1}, {uops_8_fu_code_1}, {uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_1 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_13 = {{uops_0_fu_code_2}, {uops_14_fu_code_2}, {uops_13_fu_code_2}, {uops_12_fu_code_2}, {uops_11_fu_code_2}, {uops_10_fu_code_2}, {uops_9_fu_code_2}, {uops_8_fu_code_2}, {uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_2 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_14 = {{uops_0_fu_code_3}, {uops_14_fu_code_3}, {uops_13_fu_code_3}, {uops_12_fu_code_3}, {uops_11_fu_code_3}, {uops_10_fu_code_3}, {uops_9_fu_code_3}, {uops_8_fu_code_3}, {uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_3 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_15 = {{uops_0_fu_code_4}, {uops_14_fu_code_4}, {uops_13_fu_code_4}, {uops_12_fu_code_4}, {uops_11_fu_code_4}, {uops_10_fu_code_4}, {uops_9_fu_code_4}, {uops_8_fu_code_4}, {uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_4 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_0_fu_code_5}, {uops_14_fu_code_5}, {uops_13_fu_code_5}, {uops_12_fu_code_5}, {uops_11_fu_code_5}, {uops_10_fu_code_5}, {uops_9_fu_code_5}, {uops_8_fu_code_5}, {uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_5 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_17 = {{uops_0_fu_code_6}, {uops_14_fu_code_6}, {uops_13_fu_code_6}, {uops_12_fu_code_6}, {uops_11_fu_code_6}, {uops_10_fu_code_6}, {uops_9_fu_code_6}, {uops_8_fu_code_6}, {uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_6 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_0_fu_code_7}, {uops_14_fu_code_7}, {uops_13_fu_code_7}, {uops_12_fu_code_7}, {uops_11_fu_code_7}, {uops_10_fu_code_7}, {uops_9_fu_code_7}, {uops_8_fu_code_7}, {uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_7 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_0_fu_code_8}, {uops_14_fu_code_8}, {uops_13_fu_code_8}, {uops_12_fu_code_8}, {uops_11_fu_code_8}, {uops_10_fu_code_8}, {uops_9_fu_code_8}, {uops_8_fu_code_8}, {uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_8 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_0_fu_code_9}, {uops_14_fu_code_9}, {uops_13_fu_code_9}, {uops_12_fu_code_9}, {uops_11_fu_code_9}, {uops_10_fu_code_9}, {uops_9_fu_code_9}, {uops_8_fu_code_9}, {uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_9 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_21 = {{uops_0_iw_issued}, {uops_14_iw_issued}, {uops_13_iw_issued}, {uops_12_iw_issued}, {uops_11_iw_issued}, {uops_10_iw_issued}, {uops_9_iw_issued}, {uops_8_iw_issued}, {uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_0_iw_issued_partial_agen}, {uops_14_iw_issued_partial_agen}, {uops_13_iw_issued_partial_agen}, {uops_12_iw_issued_partial_agen}, {uops_11_iw_issued_partial_agen}, {uops_10_iw_issued_partial_agen}, {uops_9_iw_issued_partial_agen}, {uops_8_iw_issued_partial_agen}, {uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_agen = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_0_iw_issued_partial_dgen}, {uops_14_iw_issued_partial_dgen}, {uops_13_iw_issued_partial_dgen}, {uops_12_iw_issued_partial_dgen}, {uops_11_iw_issued_partial_dgen}, {uops_10_iw_issued_partial_dgen}, {uops_9_iw_issued_partial_dgen}, {uops_8_iw_issued_partial_dgen}, {uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_dgen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_0_iw_p1_speculative_child}, {uops_14_iw_p1_speculative_child}, {uops_13_iw_p1_speculative_child}, {uops_12_iw_p1_speculative_child}, {uops_11_iw_p1_speculative_child}, {uops_10_iw_p1_speculative_child}, {uops_9_iw_p1_speculative_child}, {uops_8_iw_p1_speculative_child}, {uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_speculative_child = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_0_iw_p2_speculative_child}, {uops_14_iw_p2_speculative_child}, {uops_13_iw_p2_speculative_child}, {uops_12_iw_p2_speculative_child}, {uops_11_iw_p2_speculative_child}, {uops_10_iw_p2_speculative_child}, {uops_9_iw_p2_speculative_child}, {uops_8_iw_p2_speculative_child}, {uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_0_iw_p1_bypass_hint}, {uops_14_iw_p1_bypass_hint}, {uops_13_iw_p1_bypass_hint}, {uops_12_iw_p1_bypass_hint}, {uops_11_iw_p1_bypass_hint}, {uops_10_iw_p1_bypass_hint}, {uops_9_iw_p1_bypass_hint}, {uops_8_iw_p1_bypass_hint}, {uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_bypass_hint = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_0_iw_p2_bypass_hint}, {uops_14_iw_p2_bypass_hint}, {uops_13_iw_p2_bypass_hint}, {uops_12_iw_p2_bypass_hint}, {uops_11_iw_p2_bypass_hint}, {uops_10_iw_p2_bypass_hint}, {uops_9_iw_p2_bypass_hint}, {uops_8_iw_p2_bypass_hint}, {uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_28 = {{uops_0_iw_p3_bypass_hint}, {uops_14_iw_p3_bypass_hint}, {uops_13_iw_p3_bypass_hint}, {uops_12_iw_p3_bypass_hint}, {uops_11_iw_p3_bypass_hint}, {uops_10_iw_p3_bypass_hint}, {uops_9_iw_p3_bypass_hint}, {uops_8_iw_p3_bypass_hint}, {uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p3_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_29 = {{uops_0_dis_col_sel}, {uops_14_dis_col_sel}, {uops_13_dis_col_sel}, {uops_12_dis_col_sel}, {uops_11_dis_col_sel}, {uops_10_dis_col_sel}, {uops_9_dis_col_sel}, {uops_8_dis_col_sel}, {uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_dis_col_sel = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_30 = {{uops_0_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21] assign out_uop_br_mask = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_31 = {{uops_0_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21] assign out_uop_br_tag = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_32 = {{uops_0_br_type}, {uops_14_br_type}, {uops_13_br_type}, {uops_12_br_type}, {uops_11_br_type}, {uops_10_br_type}, {uops_9_br_type}, {uops_8_br_type}, {uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21] assign out_uop_br_type = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_0_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfb = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_34 = {{uops_0_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fence = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_35 = {{uops_0_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fencei = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_36 = {{uops_0_is_sfence}, {uops_14_is_sfence}, {uops_13_is_sfence}, {uops_12_is_sfence}, {uops_11_is_sfence}, {uops_10_is_sfence}, {uops_9_is_sfence}, {uops_8_is_sfence}, {uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfence = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_37 = {{uops_0_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21] assign out_uop_is_amo = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_38 = {{uops_0_is_eret}, {uops_14_is_eret}, {uops_13_is_eret}, {uops_12_is_eret}, {uops_11_is_eret}, {uops_10_is_eret}, {uops_9_is_eret}, {uops_8_is_eret}, {uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21] assign out_uop_is_eret = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_39 = {{uops_0_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sys_pc2epc = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_40 = {{uops_0_is_rocc}, {uops_14_is_rocc}, {uops_13_is_rocc}, {uops_12_is_rocc}, {uops_11_is_rocc}, {uops_10_is_rocc}, {uops_9_is_rocc}, {uops_8_is_rocc}, {uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rocc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_41 = {{uops_0_is_mov}, {uops_14_is_mov}, {uops_13_is_mov}, {uops_12_is_mov}, {uops_11_is_mov}, {uops_10_is_mov}, {uops_9_is_mov}, {uops_8_is_mov}, {uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21] assign out_uop_is_mov = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_42 = {{uops_0_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ftq_idx = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_43 = {{uops_0_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_edge_inst = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_44 = {{uops_0_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21] assign out_uop_pc_lob = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_0_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21] assign out_uop_taken = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_0_imm_rename}, {uops_14_imm_rename}, {uops_13_imm_rename}, {uops_12_imm_rename}, {uops_11_imm_rename}, {uops_10_imm_rename}, {uops_9_imm_rename}, {uops_8_imm_rename}, {uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_rename = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_47 = {{uops_0_imm_sel}, {uops_14_imm_sel}, {uops_13_imm_sel}, {uops_12_imm_sel}, {uops_11_imm_sel}, {uops_10_imm_sel}, {uops_9_imm_sel}, {uops_8_imm_sel}, {uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_sel = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_48 = {{uops_0_pimm}, {uops_14_pimm}, {uops_13_pimm}, {uops_12_pimm}, {uops_11_pimm}, {uops_10_pimm}, {uops_9_pimm}, {uops_8_pimm}, {uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21] assign out_uop_pimm = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_49 = {{uops_0_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_packed = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_50 = {{uops_0_op1_sel}, {uops_14_op1_sel}, {uops_13_op1_sel}, {uops_12_op1_sel}, {uops_11_op1_sel}, {uops_10_op1_sel}, {uops_9_op1_sel}, {uops_8_op1_sel}, {uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op1_sel = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_51 = {{uops_0_op2_sel}, {uops_14_op2_sel}, {uops_13_op2_sel}, {uops_12_op2_sel}, {uops_11_op2_sel}, {uops_10_op2_sel}, {uops_9_op2_sel}, {uops_8_op2_sel}, {uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op2_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_0_fp_ctrl_ldst}, {uops_14_fp_ctrl_ldst}, {uops_13_fp_ctrl_ldst}, {uops_12_fp_ctrl_ldst}, {uops_11_fp_ctrl_ldst}, {uops_10_fp_ctrl_ldst}, {uops_9_fp_ctrl_ldst}, {uops_8_fp_ctrl_ldst}, {uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ldst = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_53 = {{uops_0_fp_ctrl_wen}, {uops_14_fp_ctrl_wen}, {uops_13_fp_ctrl_wen}, {uops_12_fp_ctrl_wen}, {uops_11_fp_ctrl_wen}, {uops_10_fp_ctrl_wen}, {uops_9_fp_ctrl_wen}, {uops_8_fp_ctrl_wen}, {uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wen = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_54 = {{uops_0_fp_ctrl_ren1}, {uops_14_fp_ctrl_ren1}, {uops_13_fp_ctrl_ren1}, {uops_12_fp_ctrl_ren1}, {uops_11_fp_ctrl_ren1}, {uops_10_fp_ctrl_ren1}, {uops_9_fp_ctrl_ren1}, {uops_8_fp_ctrl_ren1}, {uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren1 = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_0_fp_ctrl_ren2}, {uops_14_fp_ctrl_ren2}, {uops_13_fp_ctrl_ren2}, {uops_12_fp_ctrl_ren2}, {uops_11_fp_ctrl_ren2}, {uops_10_fp_ctrl_ren2}, {uops_9_fp_ctrl_ren2}, {uops_8_fp_ctrl_ren2}, {uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren2 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_0_fp_ctrl_ren3}, {uops_14_fp_ctrl_ren3}, {uops_13_fp_ctrl_ren3}, {uops_12_fp_ctrl_ren3}, {uops_11_fp_ctrl_ren3}, {uops_10_fp_ctrl_ren3}, {uops_9_fp_ctrl_ren3}, {uops_8_fp_ctrl_ren3}, {uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren3 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_0_fp_ctrl_swap12}, {uops_14_fp_ctrl_swap12}, {uops_13_fp_ctrl_swap12}, {uops_12_fp_ctrl_swap12}, {uops_11_fp_ctrl_swap12}, {uops_10_fp_ctrl_swap12}, {uops_9_fp_ctrl_swap12}, {uops_8_fp_ctrl_swap12}, {uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap12 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_0_fp_ctrl_swap23}, {uops_14_fp_ctrl_swap23}, {uops_13_fp_ctrl_swap23}, {uops_12_fp_ctrl_swap23}, {uops_11_fp_ctrl_swap23}, {uops_10_fp_ctrl_swap23}, {uops_9_fp_ctrl_swap23}, {uops_8_fp_ctrl_swap23}, {uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap23 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_59 = {{uops_0_fp_ctrl_typeTagIn}, {uops_14_fp_ctrl_typeTagIn}, {uops_13_fp_ctrl_typeTagIn}, {uops_12_fp_ctrl_typeTagIn}, {uops_11_fp_ctrl_typeTagIn}, {uops_10_fp_ctrl_typeTagIn}, {uops_9_fp_ctrl_typeTagIn}, {uops_8_fp_ctrl_typeTagIn}, {uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagIn = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_60 = {{uops_0_fp_ctrl_typeTagOut}, {uops_14_fp_ctrl_typeTagOut}, {uops_13_fp_ctrl_typeTagOut}, {uops_12_fp_ctrl_typeTagOut}, {uops_11_fp_ctrl_typeTagOut}, {uops_10_fp_ctrl_typeTagOut}, {uops_9_fp_ctrl_typeTagOut}, {uops_8_fp_ctrl_typeTagOut}, {uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagOut = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_0_fp_ctrl_fromint}, {uops_14_fp_ctrl_fromint}, {uops_13_fp_ctrl_fromint}, {uops_12_fp_ctrl_fromint}, {uops_11_fp_ctrl_fromint}, {uops_10_fp_ctrl_fromint}, {uops_9_fp_ctrl_fromint}, {uops_8_fp_ctrl_fromint}, {uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fromint = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_0_fp_ctrl_toint}, {uops_14_fp_ctrl_toint}, {uops_13_fp_ctrl_toint}, {uops_12_fp_ctrl_toint}, {uops_11_fp_ctrl_toint}, {uops_10_fp_ctrl_toint}, {uops_9_fp_ctrl_toint}, {uops_8_fp_ctrl_toint}, {uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_toint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_0_fp_ctrl_fastpipe}, {uops_14_fp_ctrl_fastpipe}, {uops_13_fp_ctrl_fastpipe}, {uops_12_fp_ctrl_fastpipe}, {uops_11_fp_ctrl_fastpipe}, {uops_10_fp_ctrl_fastpipe}, {uops_9_fp_ctrl_fastpipe}, {uops_8_fp_ctrl_fastpipe}, {uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fastpipe = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_0_fp_ctrl_fma}, {uops_14_fp_ctrl_fma}, {uops_13_fp_ctrl_fma}, {uops_12_fp_ctrl_fma}, {uops_11_fp_ctrl_fma}, {uops_10_fp_ctrl_fma}, {uops_9_fp_ctrl_fma}, {uops_8_fp_ctrl_fma}, {uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fma = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_65 = {{uops_0_fp_ctrl_div}, {uops_14_fp_ctrl_div}, {uops_13_fp_ctrl_div}, {uops_12_fp_ctrl_div}, {uops_11_fp_ctrl_div}, {uops_10_fp_ctrl_div}, {uops_9_fp_ctrl_div}, {uops_8_fp_ctrl_div}, {uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_div = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_66 = {{uops_0_fp_ctrl_sqrt}, {uops_14_fp_ctrl_sqrt}, {uops_13_fp_ctrl_sqrt}, {uops_12_fp_ctrl_sqrt}, {uops_11_fp_ctrl_sqrt}, {uops_10_fp_ctrl_sqrt}, {uops_9_fp_ctrl_sqrt}, {uops_8_fp_ctrl_sqrt}, {uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_sqrt = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_67 = {{uops_0_fp_ctrl_wflags}, {uops_14_fp_ctrl_wflags}, {uops_13_fp_ctrl_wflags}, {uops_12_fp_ctrl_wflags}, {uops_11_fp_ctrl_wflags}, {uops_10_fp_ctrl_wflags}, {uops_9_fp_ctrl_wflags}, {uops_8_fp_ctrl_wflags}, {uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wflags = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_68 = {{uops_0_fp_ctrl_vec}, {uops_14_fp_ctrl_vec}, {uops_13_fp_ctrl_vec}, {uops_12_fp_ctrl_vec}, {uops_11_fp_ctrl_vec}, {uops_10_fp_ctrl_vec}, {uops_9_fp_ctrl_vec}, {uops_8_fp_ctrl_vec}, {uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_vec = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_69 = {{uops_0_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rob_idx = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_70 = {{uops_0_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ldq_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_71 = {{uops_0_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_stq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_0_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rxq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_73 = {{uops_0_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_pdst = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_74 = {{uops_0_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1 = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_75 = {{uops_0_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_76 = {{uops_0_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_77 = {{uops_0_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_0_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1_busy = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_0_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_0_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_81 = {{uops_0_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_82 = {{uops_0_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_stale_pdst = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_83 = {{uops_0_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21] assign out_uop_exception = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_84 = {{uops_0_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21] assign out_uop_exc_cause = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_85 = {{uops_0_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_cmd = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_86 = {{uops_0_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_size = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_87 = {{uops_0_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_signed = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_88 = {{uops_0_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_ldq = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_89 = {{uops_0_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_stq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_90 = {{uops_0_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21] assign out_uop_is_unique = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_91 = {{uops_0_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21] assign out_uop_flush_on_commit = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_92 = {{uops_0_csr_cmd}, {uops_14_csr_cmd}, {uops_13_csr_cmd}, {uops_12_csr_cmd}, {uops_11_csr_cmd}, {uops_10_csr_cmd}, {uops_9_csr_cmd}, {uops_8_csr_cmd}, {uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_csr_cmd = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_93 = {{uops_0_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst_is_rs1 = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_94 = {{uops_0_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_95 = {{uops_0_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1 = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_96 = {{uops_0_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_97 = {{uops_0_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs3 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_98 = {{uops_0_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_dst_rtype = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_99 = {{uops_0_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_100 = {{uops_0_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_101 = {{uops_0_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21] assign out_uop_frs3_en = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_102 = {{uops_0_fcn_dw}, {uops_14_fcn_dw}, {uops_13_fcn_dw}, {uops_12_fcn_dw}, {uops_11_fcn_dw}, {uops_10_fcn_dw}, {uops_9_fcn_dw}, {uops_8_fcn_dw}, {uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_dw = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_103 = {{uops_0_fcn_op}, {uops_14_fcn_op}, {uops_13_fcn_op}, {uops_12_fcn_op}, {uops_11_fcn_op}, {uops_10_fcn_op}, {uops_9_fcn_op}, {uops_8_fcn_op}, {uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_op = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_104 = {{uops_0_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_val = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_105 = {{uops_0_fp_rm}, {uops_14_fp_rm}, {uops_13_fp_rm}, {uops_12_fp_rm}, {uops_11_fp_rm}, {uops_10_fp_rm}, {uops_9_fp_rm}, {uops_8_fp_rm}, {uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_rm = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_106 = {{uops_0_fp_typ}, {uops_14_fp_typ}, {uops_13_fp_typ}, {uops_12_fp_typ}, {uops_11_fp_typ}, {uops_10_fp_typ}, {uops_9_fp_typ}, {uops_8_fp_typ}, {uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_typ = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_107 = {{uops_0_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_pf_if = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_108 = {{uops_0_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ae_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_109 = {{uops_0_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ma_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_110 = {{uops_0_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_debug_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_111 = {{uops_0_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_xcpt_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_112 = {{uops_0_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_fsrc = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_113 = {{uops_0_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_tsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:458:7, :515:71, :548:32] assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:515:44, :548:{32,42}] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42] wire [4:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:551:34] wire [3:0] _io_count_T = {4{maybe_full}}; // @[util.scala:509:29, :557:12] wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40] wire [4:0] _io_count_T_2 = {1'h0, ptr_diff} + 5'hF; // @[util.scala:551:34, :560:26] wire [3:0] _io_count_T_3 = _io_count_T_2[3:0]; // @[util.scala:560:26] wire [3:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:551:34, :559:{12,27}, :560:26] assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:511:35, :556:22, :557:12, :559:12] assign io_count_0 = _io_count_T_5; // @[util.scala:458:7, :556:22] wire _GEN_114 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_115 = do_enq & _GEN_114; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_116 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_117 = do_enq & _GEN_116; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_118 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_119 = do_enq & _GEN_118; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_120 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_121 = do_enq & _GEN_120; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_122 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_123 = do_enq & _GEN_122; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_124 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_125 = do_enq & _GEN_124; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_126 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_127 = do_enq & _GEN_126; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_128 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_129 = do_enq & _GEN_128; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_130 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_131 = do_enq & _GEN_130; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_132 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_133 = do_enq & _GEN_132; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_134 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_135 = do_enq & _GEN_134; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_136 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_137 = do_enq & _GEN_136; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_138 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_139 = do_enq & _GEN_138; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_140 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_141 = do_enq & _GEN_140; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_142 = do_enq & wrap; // @[Counter.scala:73:24] always @(posedge clock) begin // @[util.scala:458:7] if (reset) begin // @[util.scala:458:7] valids_0 <= 1'h0; // @[util.scala:504:26] valids_1 <= 1'h0; // @[util.scala:504:26] valids_2 <= 1'h0; // @[util.scala:504:26] valids_3 <= 1'h0; // @[util.scala:504:26] valids_4 <= 1'h0; // @[util.scala:504:26] valids_5 <= 1'h0; // @[util.scala:504:26] valids_6 <= 1'h0; // @[util.scala:504:26] valids_7 <= 1'h0; // @[util.scala:504:26] valids_8 <= 1'h0; // @[util.scala:504:26] valids_9 <= 1'h0; // @[util.scala:504:26] valids_10 <= 1'h0; // @[util.scala:504:26] valids_11 <= 1'h0; // @[util.scala:504:26] valids_12 <= 1'h0; // @[util.scala:504:26] valids_13 <= 1'h0; // @[util.scala:504:26] valids_14 <= 1'h0; // @[util.scala:504:26] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:509:29] end else begin // @[util.scala:458:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_115 \| _valids_0_T_7); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_117 \| _valids_1_T_7); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_119 \| _valids_2_T_7); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_121 \| _valids_3_T_7); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_123 \| _valids_4_T_7); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_125 \| _valids_5_T_7); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_127 \| _valids_6_T_7); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_129 \| _valids_7_T_7); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_131 \| _valids_8_T_7); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_133 \| _valids_9_T_7); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_135 \| _valids_10_T_7); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_137 \| _valids_11_T_7); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_139 \| _valids_12_T_7); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_141 \| _valids_13_T_7); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & wrap_1) & (_GEN_142 \| _valids_14_T_7); // @[Counter.scala:73:24] if (do_enq) // @[util.scala:514:26] enq_ptr_value <= wrap ? 4'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (do_deq) // @[util.scala:515:26] deq_ptr_value <= wrap_1 ? 4'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18] maybe_full <= do_enq; // @[util.scala:509:29, :514:26] end if (_GEN_115) begin // @[util.scala:520:18, :526:19, :528:35] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_114) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_0) // @[util.scala:504:26] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_117) begin // @[util.scala:520:18, :526:19, :528:35] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_116) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_1) // @[util.scala:504:26] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_119) begin // @[util.scala:520:18, :526:19, :528:35] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_118) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_2) // @[util.scala:504:26] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_120) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_3) // @[util.scala:504:26] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_123) begin // @[util.scala:520:18, :526:19, :528:35] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_122) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_4) // @[util.scala:504:26] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_125) begin // @[util.scala:520:18, :526:19, :528:35] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_124) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_5) // @[util.scala:504:26] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_127) begin // @[util.scala:520:18, :526:19, :528:35] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_126) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_6) // @[util.scala:504:26] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_128) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_7) // @[util.scala:504:26] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_131) begin // @[util.scala:520:18, :526:19, :528:35] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_8_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_8_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_8_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_8_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_8_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_8_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_8_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_8_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_8_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_8_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_8_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_8_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_8_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_8_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_8_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_130) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_8) // @[util.scala:504:26] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_133) begin // @[util.scala:520:18, :526:19, :528:35] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_9_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_9_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_9_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_9_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_9_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_9_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_9_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_9_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_9_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_9_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_9_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_9_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_9_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_9_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_9_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_132) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_9) // @[util.scala:504:26] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_135) begin // @[util.scala:520:18, :526:19, :528:35] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_10_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_10_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_10_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_10_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_10_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_10_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_10_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_10_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_10_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_10_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_10_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_10_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_10_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_10_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_10_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_134) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_10) // @[util.scala:504:26] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_137) begin // @[util.scala:520:18, :526:19, :528:35] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_11_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_11_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_11_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_11_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_11_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_11_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_11_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_11_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_11_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_11_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_11_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_11_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_11_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_11_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_11_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_136) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_11) // @[util.scala:504:26] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_139) begin // @[util.scala:520:18, :526:19, :528:35] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_12_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_12_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_12_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_12_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_12_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_12_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_12_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_12_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_12_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_12_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_12_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_12_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_12_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_12_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_12_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_138) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_12) // @[util.scala:504:26] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_141) begin // @[util.scala:520:18, :526:19, :528:35] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_13_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_13_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_13_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_13_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_13_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_13_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_13_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_13_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_13_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_13_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_13_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_13_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_13_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_13_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_13_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_140) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_13) // @[util.scala:504:26] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_142) begin // @[util.scala:520:18, :526:19, :528:35] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_14_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_14_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_14_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_14_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_14_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_14_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_14_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_14_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_14_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_14_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_14_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_14_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_14_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_14_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_14_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & wrap) // @[Counter.scala:73:24] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_14) // @[util.scala:504:26] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:97:21, :505:22] always @(posedge) ram_15x131 ram_ext ( // @[util.scala:503:22] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:514:26] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:458:7, :503:22] ); // @[util.scala:503:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] assign io_count = io_count_0; // @[util.scala:458:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [19:0] inflight; // @[Monitor.scala:614:27] reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [31:0] _GEN_0 = {27'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [31:0] _GEN_3 = {27'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [19:0] inflight_1; // @[Monitor.scala:726:35] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File ToAXI4.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField} import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp} import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1} import freechips.rocketchip.util.DataToAugmentedData class AXI4TLStateBundle(val sourceBits: Int) extends Bundle { val size = UInt(4.W) val source = UInt((sourceBits max 1).W) } case object AXI4TLState extends ControlKey[AXI4TLStateBundle]("tl_state") case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBundle](AXI4TLState, Output(new AXI4TLStateBundle(sourceBits)), x => { x.size := 0.U x.source := 0.U }) /* TLtoAXI4IdMap serves as a record for the translation performed between id spaces. * * Its member [axi4Masters] is used as the new AXI4MasterParameters in diplomacy. * Its member [mapping] is used as the template for the circuit generated in TLToAXI4Node.module. / class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapEntry] { val tlMasters = tlPort.masters.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType) private val axi4IdSize = tlMasters.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size } private val axi4IdStart = axi4IdSize.scanLeft(0)(_+_).init val axi4Masters = axi4IdStart.zip(axi4IdSize).zip(tlMasters).map { case ((start, size), tl) => AXI4MasterParameters( name = tl.name, id = IdRange(start, start+size), aligned = true, maxFlight = Some(if (tl.requestFifo) tl.sourceId.size else 1), nodePath = tl.nodePath) } private val axi4IdEnd = axi4Masters.map(_.id.end).max private val axiDigits = String.valueOf(axi4IdEnd-1).length() private val tlDigits = String.valueOf(tlPort.endSourceId-1).length() protected val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s" val mapping: Seq[TLToAXI4IdMapEntry] = tlMasters.zip(axi4Masters).map { case (tl, axi) => TLToAXI4IdMapEntry(axi.id, tl.sourceId, tl.name, tl.supports.probe, tl.requestFifo) } } case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = axi4Id val maxTransactionsInFlight = Some(tlId.size) } case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)( dFn = { p => AXI4MasterPortParameters( masters = (new TLtoAXI4IdMap(p)).axi4Masters, requestFields = (if (wcorrupt) Seq(AMBACorruptField()) else Seq()) ++ p.requestFields.filter(!_.isInstanceOf[AMBAProtField]), echoFields = AXI4TLStateField(log2Ceil(p.endSourceId)) +: p.echoFields, responseKeys = p.responseKeys) }, uFn = { p => TLSlavePortParameters.v1( managers = p.slaves.map { case s => TLSlaveParameters.v1( address = s.address, resources = s.resources, regionType = s.regionType, executable = s.executable, nodePath = s.nodePath, supportsGet = s.supportsRead, supportsPutFull = s.supportsWrite, supportsPutPartial = s.supportsWrite, fifoId = Some(0), mayDenyPut = true, mayDenyGet = true)}, beatBytes = p.beatBytes, minLatency = p.minLatency, responseFields = p.responseFields, requestKeys = AMBAProt +: p.requestKeys) }) // wcorrupt alone is not enough; a slave must include AMBACorrupt in the slave port's requestKeys class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0, val wcorrupt: Boolean = true)(implicit p: Parameters) extends LazyModule { require(stripBits == 0, "stripBits > 0 is no longer supported on TLToAXI4") val node = TLToAXI4Node(wcorrupt) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val slaves = edgeOut.slave.slaves // All pairs of slaves must promise that they will never interleave data require (slaves(0).interleavedId.isDefined) slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) } // Construct the source=>ID mapping table val map = new TLtoAXI4IdMap(edgeIn.client) val sourceStall = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(false.B)) val sourceTable = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(0.U.asTypeOf(out.aw.bits.id))) val idStall = WireDefault(VecInit.fill(edgeOut.master.endId)(false.B)) var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] } map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) => for (i <- 0 until tlId.size) { val id = axi4Id.start + (if (fifo) 0 else i) sourceStall(tlId.start + i) := idStall(id) sourceTable(tlId.start + i) := id.U } if (fifo) { idCount(axi4Id.start) = Some(tlId.size) } } adapterName.foreach { n => println(s"$n AXI4-ID <= TL-Source mapping:\n${map.pretty}\n") ElaborationArtefacts.add(s"$n.axi4.json", s"""{"mapping":[${map.mapping.mkString(",")}]}""") } // We need to keep the following state from A => D: (size, source) // All of those fields could potentially require 0 bits (argh. Chisel.) // We will pack all of that extra information into the echo bits. require (log2Ceil(edgeIn.maxLgSize+1) <= 4) val a_address = edgeIn.address(in.a.bits) val a_source = in.a.bits.source val a_size = edgeIn.size(in.a.bits) val a_isPut = edgeIn.hasData(in.a.bits) val (a_first, a_last, _) = edgeIn.firstlast(in.a) val r_state = out.r.bits.echo(AXI4TLState) val r_source = r_state.source val r_size = r_state.size val b_state = out.b.bits.echo(AXI4TLState) val b_source = b_state.source val b_size = b_state.size // We need these Queues because AXI4 queues are irrevocable val depth = if (combinational) 1 else 2 val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params))) val out_w = Wire(chiselTypeOf(out.w)) out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational) val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational) // Fan out the ARW channel to AR and AW out.ar.bits := queue_arw.bits out.aw.bits := queue_arw.bits out.ar.valid := queue_arw.valid && !queue_arw.bits.wen out.aw.valid := queue_arw.valid && queue_arw.bits.wen queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready) val beatBytes = edgeIn.manager.beatBytes val maxSize = log2Ceil(beatBytes).U val doneAW = RegInit(false.B) when (in.a.fire) { doneAW := !a_last } val arw = out_arw.bits arw.wen := a_isPut arw.id := sourceTable(a_source) arw.addr := a_address arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes) arw.size := Mux(a_size >= maxSize, maxSize, a_size) arw.burst := AXI4Parameters.BURST_INCR arw.lock := 0.U // not exclusive (LR/SC unsupported b/c no forward progress guarantee) arw.cache := 0.U // do not allow AXI to modify our transactions arw.prot := AXI4Parameters.PROT_PRIVILEGED arw.qos := 0.U // no QoS Connectable.waiveUnmatched(arw.user, in.a.bits.user) match { case (lhs, rhs) => lhs :<= rhs } Connectable.waiveUnmatched(arw.echo, in.a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = arw.echo(AXI4TLState) a_extra.source := a_source a_extra.size := a_size in.a.bits.user.lift(AMBAProt).foreach { x => val prot = Wire(Vec(3, Bool())) val cache = Wire(Vec(4, Bool())) prot(0) := x.privileged prot(1) := !x.secure prot(2) := x.fetch cache(0) := x.bufferable cache(1) := x.modifiable cache(2) := x.readalloc cache(3) := x.writealloc arw.prot := Cat(prot.reverse) arw.cache := Cat(cache.reverse) } val stall = sourceStall(in.a.bits.source) && a_first in.a.ready := !stall && Mux(a_isPut, (doneAW \|\| out_arw.ready) && out_w.ready, out_arw.ready) out_arw.valid := !stall && in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, true.B) out_w.valid := !stall && in.a.valid && a_isPut && (doneAW \|\| out_arw.ready) out_w.bits.data := in.a.bits.data out_w.bits.strb := in.a.bits.mask out_w.bits.last := a_last out_w.bits.user.lift(AMBACorrupt).foreach { _ := in.a.bits.corrupt } // R and B => D arbitration val r_holds_d = RegInit(false.B) when (out.r.fire) { r_holds_d := !out.r.bits.last } // Give R higher priority than B, unless B has been delayed for 8 cycles val b_delay = Reg(UInt(3.W)) when (out.b.valid && !out.b.ready) { b_delay := b_delay + 1.U } .otherwise { b_delay := 0.U } val r_wins = (out.r.valid && b_delay =/= 7.U) \|\| r_holds_d out.r.ready := in.d.ready && r_wins out.b.ready := in.d.ready && !r_wins in.d.valid := Mux(r_wins, out.r.valid, out.b.valid) // If the first beat of the AXI RRESP is RESP_DECERR, treat this as a denied // request. We must pulse extend this value as AXI is allowed to change the // value of RRESP on every beat, and ChipLink may not. val r_first = RegInit(true.B) when (out.r.fire) { r_first := out.r.bits.last } val r_denied = out.r.bits.resp === AXI4Parameters.RESP_DECERR holdUnless r_first val r_corrupt = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY val b_denied = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY val r_d = edgeIn.AccessAck(r_source, r_size, 0.U, denied = r_denied, corrupt = r_corrupt \|\| r_denied) val b_d = edgeIn.AccessAck(b_source, b_size, denied = b_denied) Connectable.waiveUnmatched(r_d.user, out.r.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(r_d.echo, out.r.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.user, out.b.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.echo, out.b.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } in.d.bits := Mux(r_wins, r_d, b_d) in.d.bits.data := out.r.bits.data // avoid a costly Mux // We need to track if any reads or writes are inflight for a given ID. // If the opposite type arrives, we must stall until it completes. val a_sel = UIntToOH(arw.id, edgeOut.master.endId).asBools val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).asBools val d_last = Mux(r_wins, out.r.bits.last, true.B) // If FIFO was requested, ensure that R+W ordering is preserved (a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) => // AXI does not guarantee read vs. write ordering. In particular, if we // are in the middle of receiving a read burst and then issue a write, // the write might affect the read burst. This violates FIFO behaviour. // To solve this, we must wait until the last beat of a burst, but this // means that a TileLink master which performs early source reuse can // have one more transaction inflight than we promised AXI; stall it too. val maxCount = n.getOrElse(1) val count = RegInit(0.U(log2Ceil(maxCount + 1).W)) val write = Reg(Bool()) val idle = count === 0.U val inc = as && out_arw.fire val dec = ds && d_last && in.d.fire count := count + inc.asUInt - dec.asUInt assert (!dec \|\| count =/= 0.U) // underflow assert (!inc \|\| count =/= maxCount.U) // overflow when (inc) { write := arw.wen } // If only one transaction can be inflight, it can't mismatch val mismatch = if (maxCount > 1) { write =/= arw.wen } else { false.B } s := (!idle && mismatch) \|\| (count === maxCount.U) } // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B } } } object TLToAXI4 { def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0, wcorrupt: Boolean = true)(implicit p: Parameters) = { val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits, wcorrupt)) tl2axi4.node } def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = { if ( a.supports.probe && !b.supports.probe) return false if (!a.supports.probe && b.supports.probe) return true if ( a.requestFifo && !b.requestFifo ) return false if (!a.requestFifo && b.requestFifo ) return true return false } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLToAXI4( // @[ToAXI4.scala:103:9] input clock, // @[ToAXI4.scala:103:9] input reset, // @[ToAXI4.scala:103:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire [5:0] out_arw_bits_id; // @[ToAXI4.scala:153:25] wire auto_in_a_valid_0 = auto_in_a_valid; // @[ToAXI4.scala:103:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[ToAXI4.scala:103:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[ToAXI4.scala:103:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[ToAXI4.scala:103:9] wire [5:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[ToAXI4.scala:103:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[ToAXI4.scala:103:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[ToAXI4.scala:103:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[ToAXI4.scala:103:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[ToAXI4.scala:103:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[ToAXI4.scala:103:9] wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[ToAXI4.scala:103:9] wire auto_out_w_ready_0 = auto_out_w_ready; // @[ToAXI4.scala:103:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[ToAXI4.scala:103:9] wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_b_bits_echo_tl_state_size_0 = auto_out_b_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_b_bits_echo_tl_state_source_0 = auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9] wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[ToAXI4.scala:103:9] wire auto_out_r_valid_0 = auto_out_r_valid; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[ToAXI4.scala:103:9] wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[ToAXI4.scala:103:9] wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_r_bits_echo_tl_state_size_0 = auto_out_r_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_r_bits_echo_tl_state_source_0 = auto_out_r_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9] wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[ToAXI4.scala:103:9] wire [63:0][5:0] _GEN = '{6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h27, 6'h26, 6'h25, 6'h24, 6'h23, 6'h22, 6'h21, 6'h20, 6'h1F, 6'h1E, 6'h1D, 6'h1C, 6'h1B, 6'h1A, 6'h19, 6'h18, 6'h17, 6'h16, 6'h15, 6'h14, 6'h13, 6'h12, 6'h11, 6'h10, 6'hF, 6'hE, 6'hD, 6'hC, 6'hB, 6'hA, 6'h9, 6'h8, 6'h7, 6'h6, 6'h5, 6'h4, 6'h3, 6'h2, 6'h1, 6'h0}; wire [1:0] auto_in_d_bits_param = 2'h0; // @[ToAXI4.scala:103:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] r_d_param = 2'h0; // @[Edges.scala:810:17] wire [1:0] b_d_param = 2'h0; // @[Edges.scala:792:17] wire [1:0] _nodeIn_d_bits_T_param = 2'h0; // @[ToAXI4.scala:255:23] wire auto_in_d_bits_sink = 1'h0; // @[ToAXI4.scala:103:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire _sourceStall_WIRE_0 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_1 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_2 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_3 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_4 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_5 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_6 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_7 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_8 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_9 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_10 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_11 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_12 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_13 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_14 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_15 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_16 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_17 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_18 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_19 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_20 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_21 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_22 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_23 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_24 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_25 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_26 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_27 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_28 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_29 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_30 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_31 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_32 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_33 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_34 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_35 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_36 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_37 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_38 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_39 = 1'h0; // @[ToAXI4.scala:113:76] wire _idStall_WIRE_0 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_1 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_2 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_3 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_4 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_5 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_6 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_7 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_8 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_9 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_10 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_11 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_12 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_13 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_14 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_15 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_16 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_17 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_18 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_19 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_20 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_21 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_22 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_23 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_24 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_25 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_26 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_27 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_28 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_29 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_30 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_31 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_32 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_33 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_34 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_35 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_36 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_37 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_38 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_39 = 1'h0; // @[ToAXI4.scala:115:67] wire out_arw_bits_lock = 1'h0; // @[ToAXI4.scala:153:25] wire r_d_sink = 1'h0; // @[Edges.scala:810:17] wire b_d_sink = 1'h0; // @[Edges.scala:792:17] wire b_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire _nodeIn_d_bits_T_sink = 1'h0; // @[ToAXI4.scala:255:23] wire _idStall_0_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_1_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_2_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_3_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_4_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_5_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_6_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_7_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_8_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_9_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_10_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_11_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_12_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_13_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_14_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_15_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_16_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_17_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_18_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_19_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_20_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_21_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_22_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_23_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_24_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_25_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_26_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_27_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_28_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_29_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_30_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_31_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_32_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_33_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_34_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_35_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_36_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_37_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_38_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_39_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire [63:0] r_d_data = 64'h0; // @[Edges.scala:810:17] wire [63:0] b_d_data = 64'h0; // @[Edges.scala:792:17] wire [63:0] _nodeIn_d_bits_T_data = 64'h0; // @[ToAXI4.scala:255:23] wire [2:0] b_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [2:0] out_arw_bits_prot = 3'h1; // @[ToAXI4.scala:153:25] wire [2:0] r_d_opcode = 3'h1; // @[Edges.scala:810:17] wire [3:0] out_arw_bits_cache = 4'h0; // @[ToAXI4.scala:153:25] wire [3:0] out_arw_bits_qos = 4'h0; // @[ToAXI4.scala:153:25] wire [1:0] out_arw_bits_burst = 2'h1; // @[ToAXI4.scala:153:25] wire [5:0] sourceTable_39 = 6'h27; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_38 = 6'h26; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_37 = 6'h25; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_36 = 6'h24; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_35 = 6'h23; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_34 = 6'h22; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_33 = 6'h21; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_32 = 6'h20; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_31 = 6'h1F; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_30 = 6'h1E; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_29 = 6'h1D; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_28 = 6'h1C; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_27 = 6'h1B; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_26 = 6'h1A; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_25 = 6'h19; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_24 = 6'h18; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_23 = 6'h17; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_22 = 6'h16; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_21 = 6'h15; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_20 = 6'h14; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_19 = 6'h13; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_18 = 6'h12; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_17 = 6'h11; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_16 = 6'h10; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_15 = 6'hF; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_14 = 6'hE; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_13 = 6'hD; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_12 = 6'hC; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_11 = 6'hB; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_10 = 6'hA; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_9 = 6'h9; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_8 = 6'h8; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_7 = 6'h7; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_6 = 6'h6; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_5 = 6'h5; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_4 = 6'h4; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_3 = 6'h3; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_2 = 6'h2; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_1 = 6'h1; // @[ToAXI4.scala:114:36] wire [5:0] _sourceTable_WIRE = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_1 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_2 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_3 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_4 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_5 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_6 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_7 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_8 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_9 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_10 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_11 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_12 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_13 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_14 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_15 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_16 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_17 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_18 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_19 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_20 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_21 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_22 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_23 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_24 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_25 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_26 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_27 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_28 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_29 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_30 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_31 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_32 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_33 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_34 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_35 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_36 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_37 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_38 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_39 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_40_0 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_1 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_2 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_3 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_4 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_5 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_6 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_7 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_8 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_9 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_10 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_11 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_12 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_13 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_14 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_15 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_16 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_17 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_18 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_19 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_20 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_21 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_22 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_23 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_24 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_25 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_26 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_27 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_28 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_29 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_30 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_31 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_32 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_33 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_34 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_35 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_36 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_37 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_38 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_39 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] sourceTable_0 = 6'h0; // @[ToAXI4.scala:114:36] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[ToAXI4.scala:103:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[ToAXI4.scala:103:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[ToAXI4.scala:103:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[ToAXI4.scala:103:9] wire [5:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[ToAXI4.scala:103:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[ToAXI4.scala:103:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[ToAXI4.scala:103:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[ToAXI4.scala:103:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[ToAXI4.scala:103:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[ToAXI4.scala:103:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[ToAXI4.scala:103:9] wire nodeOut_aw_valid; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_aw_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_w_ready = auto_out_w_ready_0; // @[ToAXI4.scala:103:9] wire nodeOut_w_valid; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17] wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[ToAXI4.scala:103:9] wire [5:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[ToAXI4.scala:103:9] wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[ToAXI4.scala:103:9] wire [3:0] nodeOut_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9] wire [5:0] nodeOut_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9] wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[ToAXI4.scala:103:9] wire nodeOut_ar_valid; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_ar_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_r_ready; // @[MixedNode.scala:542:17] wire nodeOut_r_valid = auto_out_r_valid_0; // @[ToAXI4.scala:103:9] wire [5:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[ToAXI4.scala:103:9] wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[ToAXI4.scala:103:9] wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[ToAXI4.scala:103:9] wire [3:0] nodeOut_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9] wire [5:0] nodeOut_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9] wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[ToAXI4.scala:103:9] wire auto_in_a_ready_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_in_d_bits_opcode_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_in_d_bits_size_0; // @[ToAXI4.scala:103:9] wire [5:0] auto_in_d_bits_source_0; // @[ToAXI4.scala:103:9] wire auto_in_d_bits_denied_0; // @[ToAXI4.scala:103:9] wire [63:0] auto_in_d_bits_data_0; // @[ToAXI4.scala:103:9] wire auto_in_d_bits_corrupt_0; // @[ToAXI4.scala:103:9] wire auto_in_d_valid_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_aw_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_aw_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_aw_bits_id_0; // @[ToAXI4.scala:103:9] wire [31:0] auto_out_aw_bits_addr_0; // @[ToAXI4.scala:103:9] wire [7:0] auto_out_aw_bits_len_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_out_aw_bits_size_0; // @[ToAXI4.scala:103:9] wire [1:0] auto_out_aw_bits_burst_0; // @[ToAXI4.scala:103:9] wire auto_out_aw_bits_lock_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_aw_bits_cache_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_out_aw_bits_prot_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_aw_bits_qos_0; // @[ToAXI4.scala:103:9] wire auto_out_aw_valid_0; // @[ToAXI4.scala:103:9] wire [63:0] auto_out_w_bits_data_0; // @[ToAXI4.scala:103:9] wire [7:0] auto_out_w_bits_strb_0; // @[ToAXI4.scala:103:9] wire auto_out_w_bits_last_0; // @[ToAXI4.scala:103:9] wire auto_out_w_valid_0; // @[ToAXI4.scala:103:9] wire auto_out_b_ready_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_ar_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_ar_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_ar_bits_id_0; // @[ToAXI4.scala:103:9] wire [31:0] auto_out_ar_bits_addr_0; // @[ToAXI4.scala:103:9] wire [7:0] auto_out_ar_bits_len_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_out_ar_bits_size_0; // @[ToAXI4.scala:103:9] wire [1:0] auto_out_ar_bits_burst_0; // @[ToAXI4.scala:103:9] wire auto_out_ar_bits_lock_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_ar_bits_cache_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_out_ar_bits_prot_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_ar_bits_qos_0; // @[ToAXI4.scala:103:9] wire auto_out_ar_valid_0; // @[ToAXI4.scala:103:9] wire auto_out_r_ready_0; // @[ToAXI4.scala:103:9] wire _nodeIn_a_ready_T_4; // @[ToAXI4.scala:206:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[ToAXI4.scala:103:9] wire [5:0] out_arw_bits_echo_tl_state_source = nodeIn_a_bits_source; // @[ToAXI4.scala:153:25] wire [31:0] out_arw_bits_addr = nodeIn_a_bits_address; // @[ToAXI4.scala:153:25] wire [7:0] out_w_bits_strb = nodeIn_a_bits_mask; // @[ToAXI4.scala:154:23] wire [63:0] out_w_bits_data = nodeIn_a_bits_data; // @[ToAXI4.scala:154:23] wire _nodeIn_d_valid_T; // @[ToAXI4.scala:229:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[ToAXI4.scala:103:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[ToAXI4.scala:255:23] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[ToAXI4.scala:103:9] wire [2:0] _nodeIn_d_bits_T_size; // @[ToAXI4.scala:255:23] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[ToAXI4.scala:103:9] wire [5:0] _nodeIn_d_bits_T_source; // @[ToAXI4.scala:255:23] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[ToAXI4.scala:103:9] wire _nodeIn_d_bits_T_denied; // @[ToAXI4.scala:255:23] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[ToAXI4.scala:103:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[ToAXI4.scala:103:9] wire _nodeIn_d_bits_T_corrupt; // @[ToAXI4.scala:255:23] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[ToAXI4.scala:103:9] wire _nodeOut_aw_valid_T; // @[ToAXI4.scala:162:39] assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[ToAXI4.scala:103:9] wire [5:0] queue_arw_bits_id; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[ToAXI4.scala:103:9] wire [31:0] queue_arw_bits_addr; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[ToAXI4.scala:103:9] wire [7:0] queue_arw_bits_len; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[ToAXI4.scala:103:9] wire [2:0] queue_arw_bits_size; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[ToAXI4.scala:103:9] wire [1:0] queue_arw_bits_burst; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[ToAXI4.scala:103:9] wire queue_arw_bits_lock; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[ToAXI4.scala:103:9] wire [3:0] queue_arw_bits_cache; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[ToAXI4.scala:103:9] wire [2:0] queue_arw_bits_prot; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[ToAXI4.scala:103:9] wire [3:0] queue_arw_bits_qos; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[ToAXI4.scala:103:9] wire [3:0] queue_arw_bits_echo_tl_state_size; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_echo_tl_state_size_0 = nodeOut_aw_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9] wire [5:0] queue_arw_bits_echo_tl_state_source; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_echo_tl_state_source_0 = nodeOut_aw_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9] wire nodeOut_w_irr_ready = nodeOut_w_ready; // @[Decoupled.scala:401:19] wire nodeOut_w_irr_valid; // @[Decoupled.scala:401:19] assign auto_out_w_valid_0 = nodeOut_w_valid; // @[ToAXI4.scala:103:9] wire [63:0] nodeOut_w_irr_bits_data; // @[Decoupled.scala:401:19] assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[ToAXI4.scala:103:9] wire [7:0] nodeOut_w_irr_bits_strb; // @[Decoupled.scala:401:19] assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[ToAXI4.scala:103:9] wire nodeOut_w_irr_bits_last; // @[Decoupled.scala:401:19] assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[ToAXI4.scala:103:9] wire _nodeOut_b_ready_T_1; // @[ToAXI4.scala:228:33] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[ToAXI4.scala:103:9] wire [5:0] b_d_source = nodeOut_b_bits_echo_tl_state_source; // @[Edges.scala:792:17] wire _nodeOut_ar_valid_T_1; // @[ToAXI4.scala:161:39] assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_echo_tl_state_size_0 = nodeOut_ar_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_echo_tl_state_source_0 = nodeOut_ar_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9] wire _nodeOut_r_ready_T; // @[ToAXI4.scala:227:33] assign auto_out_r_ready_0 = nodeOut_r_ready; // @[ToAXI4.scala:103:9] assign nodeIn_d_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [5:0] r_d_source = nodeOut_r_bits_echo_tl_state_source; // @[Edges.scala:810:17] wire idStall_0; // @[ToAXI4.scala:115:32] wire idStall_1; // @[ToAXI4.scala:115:32] wire idStall_2; // @[ToAXI4.scala:115:32] wire idStall_3; // @[ToAXI4.scala:115:32] wire idStall_4; // @[ToAXI4.scala:115:32] wire idStall_5; // @[ToAXI4.scala:115:32] wire idStall_6; // @[ToAXI4.scala:115:32] wire idStall_7; // @[ToAXI4.scala:115:32] wire idStall_8; // @[ToAXI4.scala:115:32] wire idStall_9; // @[ToAXI4.scala:115:32] wire idStall_10; // @[ToAXI4.scala:115:32] wire idStall_11; // @[ToAXI4.scala:115:32] wire idStall_12; // @[ToAXI4.scala:115:32] wire idStall_13; // @[ToAXI4.scala:115:32] wire idStall_14; // @[ToAXI4.scala:115:32] wire idStall_15; // @[ToAXI4.scala:115:32] wire idStall_16; // @[ToAXI4.scala:115:32] wire idStall_17; // @[ToAXI4.scala:115:32] wire idStall_18; // @[ToAXI4.scala:115:32] wire idStall_19; // @[ToAXI4.scala:115:32] wire idStall_20; // @[ToAXI4.scala:115:32] wire idStall_21; // @[ToAXI4.scala:115:32] wire idStall_22; // @[ToAXI4.scala:115:32] wire idStall_23; // @[ToAXI4.scala:115:32] wire idStall_24; // @[ToAXI4.scala:115:32] wire idStall_25; // @[ToAXI4.scala:115:32] wire idStall_26; // @[ToAXI4.scala:115:32] wire idStall_27; // @[ToAXI4.scala:115:32] wire idStall_28; // @[ToAXI4.scala:115:32] wire idStall_29; // @[ToAXI4.scala:115:32] wire idStall_30; // @[ToAXI4.scala:115:32] wire idStall_31; // @[ToAXI4.scala:115:32] wire idStall_32; // @[ToAXI4.scala:115:32] wire idStall_33; // @[ToAXI4.scala:115:32] wire idStall_34; // @[ToAXI4.scala:115:32] wire idStall_35; // @[ToAXI4.scala:115:32] wire idStall_36; // @[ToAXI4.scala:115:32] wire idStall_37; // @[ToAXI4.scala:115:32] wire idStall_38; // @[ToAXI4.scala:115:32] wire idStall_39; // @[ToAXI4.scala:115:32] wire sourceStall_0; // @[ToAXI4.scala:113:36] wire sourceStall_1; // @[ToAXI4.scala:113:36] wire sourceStall_2; // @[ToAXI4.scala:113:36] wire sourceStall_3; // @[ToAXI4.scala:113:36] wire sourceStall_4; // @[ToAXI4.scala:113:36] wire sourceStall_5; // @[ToAXI4.scala:113:36] wire sourceStall_6; // @[ToAXI4.scala:113:36] wire sourceStall_7; // @[ToAXI4.scala:113:36] wire sourceStall_8; // @[ToAXI4.scala:113:36] wire sourceStall_9; // @[ToAXI4.scala:113:36] wire sourceStall_10; // @[ToAXI4.scala:113:36] wire sourceStall_11; // @[ToAXI4.scala:113:36] wire sourceStall_12; // @[ToAXI4.scala:113:36] wire sourceStall_13; // @[ToAXI4.scala:113:36] wire sourceStall_14; // @[ToAXI4.scala:113:36] wire sourceStall_15; // @[ToAXI4.scala:113:36] wire sourceStall_16; // @[ToAXI4.scala:113:36] wire sourceStall_17; // @[ToAXI4.scala:113:36] wire sourceStall_18; // @[ToAXI4.scala:113:36] wire sourceStall_19; // @[ToAXI4.scala:113:36] wire sourceStall_20; // @[ToAXI4.scala:113:36] wire sourceStall_21; // @[ToAXI4.scala:113:36] wire sourceStall_22; // @[ToAXI4.scala:113:36] wire sourceStall_23; // @[ToAXI4.scala:113:36] wire sourceStall_24; // @[ToAXI4.scala:113:36] wire sourceStall_25; // @[ToAXI4.scala:113:36] wire sourceStall_26; // @[ToAXI4.scala:113:36] wire sourceStall_27; // @[ToAXI4.scala:113:36] wire sourceStall_28; // @[ToAXI4.scala:113:36] wire sourceStall_29; // @[ToAXI4.scala:113:36] wire sourceStall_30; // @[ToAXI4.scala:113:36] wire sourceStall_31; // @[ToAXI4.scala:113:36] wire sourceStall_32; // @[ToAXI4.scala:113:36] wire sourceStall_33; // @[ToAXI4.scala:113:36] wire sourceStall_34; // @[ToAXI4.scala:113:36] wire sourceStall_35; // @[ToAXI4.scala:113:36] wire sourceStall_36; // @[ToAXI4.scala:113:36] wire sourceStall_37; // @[ToAXI4.scala:113:36] wire sourceStall_38; // @[ToAXI4.scala:113:36] wire sourceStall_39; // @[ToAXI4.scala:113:36] wire _idStall_0_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_0 = idStall_0; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_1_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_1 = idStall_1; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_2_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_2 = idStall_2; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_3_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_3 = idStall_3; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_4_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_4 = idStall_4; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_5_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_5 = idStall_5; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_6_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_6 = idStall_6; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_7_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_7 = idStall_7; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_8_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_8 = idStall_8; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_9_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_9 = idStall_9; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_10_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_10 = idStall_10; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_11_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_11 = idStall_11; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_12_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_12 = idStall_12; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_13_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_13 = idStall_13; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_14_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_14 = idStall_14; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_15_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_15 = idStall_15; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_16_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_16 = idStall_16; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_17_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_17 = idStall_17; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_18_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_18 = idStall_18; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_19_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_19 = idStall_19; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_20_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_20 = idStall_20; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_21_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_21 = idStall_21; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_22_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_22 = idStall_22; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_23_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_23 = idStall_23; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_24_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_24 = idStall_24; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_25_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_25 = idStall_25; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_26_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_26 = idStall_26; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_27_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_27 = idStall_27; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_28_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_28 = idStall_28; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_29_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_29 = idStall_29; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_30_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_30 = idStall_30; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_31_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_31 = idStall_31; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_32_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_32 = idStall_32; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_33_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_33 = idStall_33; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_34_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_34 = idStall_34; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_35_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_35 = idStall_35; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_36_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_36 = idStall_36; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_37_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_37 = idStall_37; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_38_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_38 = idStall_38; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_39_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_39 = idStall_39; // @[ToAXI4.scala:113:36, :115:32] wire _a_isPut_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire a_isPut = ~_a_isPut_opdata_T; // @[Edges.scala:92:{28,37}] wire out_arw_bits_wen = a_isPut; // @[ToAXI4.scala:153:25] wire _T_1 = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire [12:0] _r_beats1_decode_T = 13'h3F << nodeIn_a_bits_size; // @[package.scala:243:71] wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] r_beats1_decode = _r_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] r_counter; // @[Edges.scala:229:27] wire [3:0] _r_counter1_T = {1'h0, r_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] r_counter1 = _r_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = r_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_last = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire out_w_bits_last = a_last; // @[ToAXI4.scala:154:23] wire r_3 = a_last & _T_1; // @[Decoupled.scala:51:35] wire [2:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _r_counter_T = a_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _out_arw_valid_T_5; // @[ToAXI4.scala:207:45] wire [5:0] a_sel_shiftAmount = out_arw_bits_id; // @[OneHot.scala:64:49] wire [7:0] _out_arw_bits_len_T_3; // @[ToAXI4.scala:174:84] wire [2:0] _out_arw_bits_size_T_1; // @[ToAXI4.scala:175:23] wire [3:0] out_arw_bits_echo_tl_state_size; // @[ToAXI4.scala:153:25] wire [7:0] out_arw_bits_len; // @[ToAXI4.scala:153:25] wire [2:0] out_arw_bits_size; // @[ToAXI4.scala:153:25] wire out_arw_ready; // @[ToAXI4.scala:153:25] wire out_arw_valid; // @[ToAXI4.scala:153:25] wire _out_w_valid_T_4; // @[ToAXI4.scala:209:54] wire out_w_ready; // @[ToAXI4.scala:154:23] wire out_w_valid; // @[ToAXI4.scala:154:23] assign nodeOut_w_valid = nodeOut_w_irr_valid; // @[Decoupled.scala:401:19] assign nodeOut_w_bits_data = nodeOut_w_irr_bits_data; // @[Decoupled.scala:401:19] assign nodeOut_w_bits_strb = nodeOut_w_irr_bits_strb; // @[Decoupled.scala:401:19] assign nodeOut_w_bits_last = nodeOut_w_irr_bits_last; // @[Decoupled.scala:401:19] wire _queue_arw_ready_T; // @[ToAXI4.scala:163:29] assign nodeOut_aw_bits_id = queue_arw_bits_id; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_id = queue_arw_bits_id; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_addr = queue_arw_bits_addr; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_addr = queue_arw_bits_addr; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_len = queue_arw_bits_len; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_len = queue_arw_bits_len; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_size = queue_arw_bits_size; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_size = queue_arw_bits_size; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_burst = queue_arw_bits_burst; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_burst = queue_arw_bits_burst; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_lock = queue_arw_bits_lock; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_lock = queue_arw_bits_lock; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_cache = queue_arw_bits_cache; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_cache = queue_arw_bits_cache; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_prot = queue_arw_bits_prot; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_prot = queue_arw_bits_prot; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_qos = queue_arw_bits_qos; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_qos = queue_arw_bits_qos; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_echo_tl_state_size = queue_arw_bits_echo_tl_state_size; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_echo_tl_state_size = queue_arw_bits_echo_tl_state_size; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_echo_tl_state_source = queue_arw_bits_echo_tl_state_source; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_echo_tl_state_source = queue_arw_bits_echo_tl_state_source; // @[Decoupled.scala:401:19] wire queue_arw_bits_wen; // @[Decoupled.scala:401:19] wire queue_arw_ready; // @[Decoupled.scala:401:19] wire queue_arw_valid; // @[Decoupled.scala:401:19] wire _nodeOut_ar_valid_T = ~queue_arw_bits_wen; // @[Decoupled.scala:401:19] assign _nodeOut_ar_valid_T_1 = queue_arw_valid & _nodeOut_ar_valid_T; // @[Decoupled.scala:401:19] assign nodeOut_ar_valid = _nodeOut_ar_valid_T_1; // @[ToAXI4.scala:161:39] assign _nodeOut_aw_valid_T = queue_arw_valid & queue_arw_bits_wen; // @[Decoupled.scala:401:19] assign nodeOut_aw_valid = _nodeOut_aw_valid_T; // @[ToAXI4.scala:162:39] assign _queue_arw_ready_T = queue_arw_bits_wen ? nodeOut_aw_ready : nodeOut_ar_ready; // @[Decoupled.scala:401:19] assign queue_arw_ready = _queue_arw_ready_T; // @[Decoupled.scala:401:19] reg doneAW; // @[ToAXI4.scala:167:30] wire _doneAW_T = ~a_last; // @[ToAXI4.scala:168:36] assign out_arw_bits_id = _GEN[nodeIn_a_bits_source]; // @[ToAXI4.scala:153:25, :172:17] wire [17:0] _out_arw_bits_len_T = 18'h7FF << nodeIn_a_bits_size; // @[package.scala:243:71] wire [10:0] _out_arw_bits_len_T_1 = _out_arw_bits_len_T[10:0]; // @[package.scala:243:{71,76}] wire [10:0] _out_arw_bits_len_T_2 = ~_out_arw_bits_len_T_1; // @[package.scala:243:{46,76}] assign _out_arw_bits_len_T_3 = _out_arw_bits_len_T_2[10:3]; // @[package.scala:243:46] assign out_arw_bits_len = _out_arw_bits_len_T_3; // @[ToAXI4.scala:153:25, :174:84] wire _out_arw_bits_size_T = nodeIn_a_bits_size > 3'h2; // @[ToAXI4.scala:175:31] assign _out_arw_bits_size_T_1 = _out_arw_bits_size_T ? 3'h3 : nodeIn_a_bits_size; // @[ToAXI4.scala:175:{23,31}] assign out_arw_bits_size = _out_arw_bits_size_T_1; // @[ToAXI4.scala:153:25, :175:23] assign out_arw_bits_echo_tl_state_size = {1'h0, nodeIn_a_bits_size}; // @[ToAXI4.scala:153:25, :189:22] wire [63:0] _GEN_0 = {{sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_39}, {sourceStall_38}, {sourceStall_37}, {sourceStall_36}, {sourceStall_35}, {sourceStall_34}, {sourceStall_33}, {sourceStall_32}, {sourceStall_31}, {sourceStall_30}, {sourceStall_29}, {sourceStall_28}, {sourceStall_27}, {sourceStall_26}, {sourceStall_25}, {sourceStall_24}, {sourceStall_23}, {sourceStall_22}, {sourceStall_21}, {sourceStall_20}, {sourceStall_19}, {sourceStall_18}, {sourceStall_17}, {sourceStall_16}, {sourceStall_15}, {sourceStall_14}, {sourceStall_13}, {sourceStall_12}, {sourceStall_11}, {sourceStall_10}, {sourceStall_9}, {sourceStall_8}, {sourceStall_7}, {sourceStall_6}, {sourceStall_5}, {sourceStall_4}, {sourceStall_3}, {sourceStall_2}, {sourceStall_1}, {sourceStall_0}}; // @[ToAXI4.scala:113:36, :205:49] wire stall = _GEN_0[nodeIn_a_bits_source] & a_first; // @[ToAXI4.scala:205:49] wire _nodeIn_a_ready_T = ~stall; // @[ToAXI4.scala:205:49, :206:21] wire _GEN_1 = doneAW \| out_arw_ready; // @[ToAXI4.scala:153:25, :167:30, :206:52] wire _nodeIn_a_ready_T_1; // @[ToAXI4.scala:206:52] assign _nodeIn_a_ready_T_1 = _GEN_1; // @[ToAXI4.scala:206:52] wire _out_w_valid_T_3; // @[ToAXI4.scala:209:65] assign _out_w_valid_T_3 = _GEN_1; // @[ToAXI4.scala:206:52, :209:65] wire _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T_1 & out_w_ready; // @[ToAXI4.scala:154:23, :206:{52,70}] wire _nodeIn_a_ready_T_3 = a_isPut ? _nodeIn_a_ready_T_2 : out_arw_ready; // @[ToAXI4.scala:153:25, :206:{34,70}] assign _nodeIn_a_ready_T_4 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_3; // @[ToAXI4.scala:206:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_4; // @[ToAXI4.scala:206:28] wire _out_arw_valid_T = ~stall; // @[ToAXI4.scala:205:49, :206:21, :207:24] wire _out_arw_valid_T_1 = _out_arw_valid_T & nodeIn_a_valid; // @[ToAXI4.scala:207:{24,31}] wire _out_arw_valid_T_2 = ~doneAW; // @[ToAXI4.scala:167:30, :207:61] wire _out_arw_valid_T_3 = _out_arw_valid_T_2 & out_w_ready; // @[ToAXI4.scala:154:23, :207:{61,69}] wire _out_arw_valid_T_4 = ~a_isPut \| _out_arw_valid_T_3; // @[ToAXI4.scala:207:{51,69}] assign _out_arw_valid_T_5 = _out_arw_valid_T_1 & _out_arw_valid_T_4; // @[ToAXI4.scala:207:{31,45,51}] assign out_arw_valid = _out_arw_valid_T_5; // @[ToAXI4.scala:153:25, :207:45] wire _out_w_valid_T = ~stall; // @[ToAXI4.scala:205:49, :206:21, :209:22] wire _out_w_valid_T_1 = _out_w_valid_T & nodeIn_a_valid; // @[ToAXI4.scala:209:{22,29}] wire _out_w_valid_T_2 = _out_w_valid_T_1 & a_isPut; // @[ToAXI4.scala:209:{29,43}] assign _out_w_valid_T_4 = _out_w_valid_T_2 & _out_w_valid_T_3; // @[ToAXI4.scala:209:{43,54,65}] assign out_w_valid = _out_w_valid_T_4; // @[ToAXI4.scala:154:23, :209:54] reg r_holds_d; // @[ToAXI4.scala:216:30] wire _r_holds_d_T = ~nodeOut_r_bits_last; // @[ToAXI4.scala:217:40] reg [2:0] b_delay; // @[ToAXI4.scala:219:24] wire [3:0] _b_delay_T = {1'h0, b_delay} + 4'h1; // @[ToAXI4.scala:219:24, :221:28] wire [2:0] _b_delay_T_1 = _b_delay_T[2:0]; // @[ToAXI4.scala:221:28] wire _r_wins_T = b_delay != 3'h7; // @[ToAXI4.scala:219:24, :225:44] wire _r_wins_T_1 = nodeOut_r_valid & _r_wins_T; // @[ToAXI4.scala:225:{33,44}] wire r_wins = _r_wins_T_1 \| r_holds_d; // @[ToAXI4.scala:216:30, :225:{33,53}] assign _nodeOut_r_ready_T = nodeIn_d_ready & r_wins; // @[ToAXI4.scala:225:53, :227:33] assign nodeOut_r_ready = _nodeOut_r_ready_T; // @[ToAXI4.scala:227:33] wire _nodeOut_b_ready_T = ~r_wins; // @[ToAXI4.scala:225:53, :228:36] assign _nodeOut_b_ready_T_1 = nodeIn_d_ready & _nodeOut_b_ready_T; // @[ToAXI4.scala:228:{33,36}] assign nodeOut_b_ready = _nodeOut_b_ready_T_1; // @[ToAXI4.scala:228:33] assign _nodeIn_d_valid_T = r_wins ? nodeOut_r_valid : nodeOut_b_valid; // @[ToAXI4.scala:225:53, :229:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[ToAXI4.scala:229:24] reg r_first; // @[ToAXI4.scala:234:28] wire _r_denied_T = &nodeOut_r_bits_resp; // @[ToAXI4.scala:236:39] reg r_denied_r; // @[package.scala:88:63] wire r_denied = r_first ? _r_denied_T : r_denied_r; // @[package.scala:88:{42,63}] wire r_d_denied = r_denied; // @[package.scala:88:42] wire r_corrupt = \|nodeOut_r_bits_resp; // @[ToAXI4.scala:237:39] wire b_denied = \|nodeOut_b_bits_resp; // @[ToAXI4.scala:238:39] wire b_d_denied = b_denied; // @[ToAXI4.scala:238:39] wire _r_d_T = r_corrupt \| r_denied; // @[package.scala:88:42] wire r_d_corrupt = _r_d_T; // @[ToAXI4.scala:240:96] wire [2:0] r_d_size; // @[Edges.scala:810:17] assign r_d_size = nodeOut_r_bits_echo_tl_state_size[2:0]; // @[Edges.scala:810:17, :813:15] wire [2:0] b_d_size; // @[Edges.scala:792:17] assign b_d_size = nodeOut_b_bits_echo_tl_state_size[2:0]; // @[Edges.scala:792:17, :795:15] assign _nodeIn_d_bits_T_opcode = {2'h0, r_wins}; // @[ToAXI4.scala:225:53, :255:23] assign _nodeIn_d_bits_T_size = r_wins ? r_d_size : b_d_size; // @[ToAXI4.scala:225:53, :255:23] assign _nodeIn_d_bits_T_source = r_wins ? r_d_source : b_d_source; // @[ToAXI4.scala:225:53, :255:23] assign _nodeIn_d_bits_T_denied = r_wins ? r_d_denied : b_d_denied; // @[ToAXI4.scala:225:53, :255:23] assign _nodeIn_d_bits_T_corrupt = r_wins & r_d_corrupt; // @[ToAXI4.scala:225:53, :255:23] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[ToAXI4.scala:255:23] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[ToAXI4.scala:255:23] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[ToAXI4.scala:255:23] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[ToAXI4.scala:255:23] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[ToAXI4.scala:255:23] wire [63:0] _a_sel_T = 64'h1 << a_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _a_sel_T_1 = _a_sel_T[39:0]; // @[OneHot.scala:65:{12,27}] wire a_sel_0 = _a_sel_T_1[0]; // @[OneHot.scala:65:27] wire a_sel_1 = _a_sel_T_1[1]; // @[OneHot.scala:65:27] wire a_sel_2 = _a_sel_T_1[2]; // @[OneHot.scala:65:27] wire a_sel_3 = _a_sel_T_1[3]; // @[OneHot.scala:65:27] wire a_sel_4 = _a_sel_T_1[4]; // @[OneHot.scala:65:27] wire a_sel_5 = _a_sel_T_1[5]; // @[OneHot.scala:65:27] wire a_sel_6 = _a_sel_T_1[6]; // @[OneHot.scala:65:27] wire a_sel_7 = _a_sel_T_1[7]; // @[OneHot.scala:65:27] wire a_sel_8 = _a_sel_T_1[8]; // @[OneHot.scala:65:27] wire a_sel_9 = _a_sel_T_1[9]; // @[OneHot.scala:65:27] wire a_sel_10 = _a_sel_T_1[10]; // @[OneHot.scala:65:27] wire a_sel_11 = _a_sel_T_1[11]; // @[OneHot.scala:65:27] wire a_sel_12 = _a_sel_T_1[12]; // @[OneHot.scala:65:27] wire a_sel_13 = _a_sel_T_1[13]; // @[OneHot.scala:65:27] wire a_sel_14 = _a_sel_T_1[14]; // @[OneHot.scala:65:27] wire a_sel_15 = _a_sel_T_1[15]; // @[OneHot.scala:65:27] wire a_sel_16 = _a_sel_T_1[16]; // @[OneHot.scala:65:27] wire a_sel_17 = _a_sel_T_1[17]; // @[OneHot.scala:65:27] wire a_sel_18 = _a_sel_T_1[18]; // @[OneHot.scala:65:27] wire a_sel_19 = _a_sel_T_1[19]; // @[OneHot.scala:65:27] wire a_sel_20 = _a_sel_T_1[20]; // @[OneHot.scala:65:27] wire a_sel_21 = _a_sel_T_1[21]; // @[OneHot.scala:65:27] wire a_sel_22 = _a_sel_T_1[22]; // @[OneHot.scala:65:27] wire a_sel_23 = _a_sel_T_1[23]; // @[OneHot.scala:65:27] wire a_sel_24 = _a_sel_T_1[24]; // @[OneHot.scala:65:27] wire a_sel_25 = _a_sel_T_1[25]; // @[OneHot.scala:65:27] wire a_sel_26 = _a_sel_T_1[26]; // @[OneHot.scala:65:27] wire a_sel_27 = _a_sel_T_1[27]; // @[OneHot.scala:65:27] wire a_sel_28 = _a_sel_T_1[28]; // @[OneHot.scala:65:27] wire a_sel_29 = _a_sel_T_1[29]; // @[OneHot.scala:65:27] wire a_sel_30 = _a_sel_T_1[30]; // @[OneHot.scala:65:27] wire a_sel_31 = _a_sel_T_1[31]; // @[OneHot.scala:65:27] wire a_sel_32 = _a_sel_T_1[32]; // @[OneHot.scala:65:27] wire a_sel_33 = _a_sel_T_1[33]; // @[OneHot.scala:65:27] wire a_sel_34 = _a_sel_T_1[34]; // @[OneHot.scala:65:27] wire a_sel_35 = _a_sel_T_1[35]; // @[OneHot.scala:65:27] wire a_sel_36 = _a_sel_T_1[36]; // @[OneHot.scala:65:27] wire a_sel_37 = _a_sel_T_1[37]; // @[OneHot.scala:65:27] wire a_sel_38 = _a_sel_T_1[38]; // @[OneHot.scala:65:27] wire a_sel_39 = _a_sel_T_1[39]; // @[OneHot.scala:65:27] wire [5:0] _d_sel_T = r_wins ? nodeOut_r_bits_id : nodeOut_b_bits_id; // @[ToAXI4.scala:225:53, :261:31] wire [5:0] d_sel_shiftAmount = _d_sel_T; // @[OneHot.scala:64:49] wire [63:0] _d_sel_T_1 = 64'h1 << d_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _d_sel_T_2 = _d_sel_T_1[39:0]; // @[OneHot.scala:65:{12,27}] wire d_sel_0 = _d_sel_T_2[0]; // @[OneHot.scala:65:27] wire d_sel_1 = _d_sel_T_2[1]; // @[OneHot.scala:65:27] wire d_sel_2 = _d_sel_T_2[2]; // @[OneHot.scala:65:27] wire d_sel_3 = _d_sel_T_2[3]; // @[OneHot.scala:65:27] wire d_sel_4 = _d_sel_T_2[4]; // @[OneHot.scala:65:27] wire d_sel_5 = _d_sel_T_2[5]; // @[OneHot.scala:65:27] wire d_sel_6 = _d_sel_T_2[6]; // @[OneHot.scala:65:27] wire d_sel_7 = _d_sel_T_2[7]; // @[OneHot.scala:65:27] wire d_sel_8 = _d_sel_T_2[8]; // @[OneHot.scala:65:27] wire d_sel_9 = _d_sel_T_2[9]; // @[OneHot.scala:65:27] wire d_sel_10 = _d_sel_T_2[10]; // @[OneHot.scala:65:27] wire d_sel_11 = _d_sel_T_2[11]; // @[OneHot.scala:65:27] wire d_sel_12 = _d_sel_T_2[12]; // @[OneHot.scala:65:27] wire d_sel_13 = _d_sel_T_2[13]; // @[OneHot.scala:65:27] wire d_sel_14 = _d_sel_T_2[14]; // @[OneHot.scala:65:27] wire d_sel_15 = _d_sel_T_2[15]; // @[OneHot.scala:65:27] wire d_sel_16 = _d_sel_T_2[16]; // @[OneHot.scala:65:27] wire d_sel_17 = _d_sel_T_2[17]; // @[OneHot.scala:65:27] wire d_sel_18 = _d_sel_T_2[18]; // @[OneHot.scala:65:27] wire d_sel_19 = _d_sel_T_2[19]; // @[OneHot.scala:65:27] wire d_sel_20 = _d_sel_T_2[20]; // @[OneHot.scala:65:27] wire d_sel_21 = _d_sel_T_2[21]; // @[OneHot.scala:65:27] wire d_sel_22 = _d_sel_T_2[22]; // @[OneHot.scala:65:27] wire d_sel_23 = _d_sel_T_2[23]; // @[OneHot.scala:65:27] wire d_sel_24 = _d_sel_T_2[24]; // @[OneHot.scala:65:27] wire d_sel_25 = _d_sel_T_2[25]; // @[OneHot.scala:65:27] wire d_sel_26 = _d_sel_T_2[26]; // @[OneHot.scala:65:27] wire d_sel_27 = _d_sel_T_2[27]; // @[OneHot.scala:65:27] wire d_sel_28 = _d_sel_T_2[28]; // @[OneHot.scala:65:27] wire d_sel_29 = _d_sel_T_2[29]; // @[OneHot.scala:65:27] wire d_sel_30 = _d_sel_T_2[30]; // @[OneHot.scala:65:27] wire d_sel_31 = _d_sel_T_2[31]; // @[OneHot.scala:65:27] wire d_sel_32 = _d_sel_T_2[32]; // @[OneHot.scala:65:27] wire d_sel_33 = _d_sel_T_2[33]; // @[OneHot.scala:65:27] wire d_sel_34 = _d_sel_T_2[34]; // @[OneHot.scala:65:27] wire d_sel_35 = _d_sel_T_2[35]; // @[OneHot.scala:65:27] wire d_sel_36 = _d_sel_T_2[36]; // @[OneHot.scala:65:27] wire d_sel_37 = _d_sel_T_2[37]; // @[OneHot.scala:65:27] wire d_sel_38 = _d_sel_T_2[38]; // @[OneHot.scala:65:27] wire d_sel_39 = _d_sel_T_2[39]; // @[OneHot.scala:65:27] wire d_last = ~r_wins \| nodeOut_r_bits_last; // @[ToAXI4.scala:225:53, :262:23] reg count; // @[ToAXI4.scala:272:28] wire _idStall_0_T_2 = count; // @[ToAXI4.scala:272:28, :286:44] reg write; // @[ToAXI4.scala:273:24] wire idle = ~count; // @[ToAXI4.scala:272:28, :274:26] wire _GEN_2 = out_arw_ready & out_arw_valid; // @[Decoupled.scala:51:35] wire _inc_T; // @[Decoupled.scala:51:35] assign _inc_T = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_1; // @[Decoupled.scala:51:35] assign _inc_T_1 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_2; // @[Decoupled.scala:51:35] assign _inc_T_2 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_3; // @[Decoupled.scala:51:35] assign _inc_T_3 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_4; // @[Decoupled.scala:51:35] assign _inc_T_4 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_5; // @[Decoupled.scala:51:35] assign _inc_T_5 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_6; // @[Decoupled.scala:51:35] assign _inc_T_6 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_7; // @[Decoupled.scala:51:35] assign _inc_T_7 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_8; // @[Decoupled.scala:51:35] assign _inc_T_8 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_9; // @[Decoupled.scala:51:35] assign _inc_T_9 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_10; // @[Decoupled.scala:51:35] assign _inc_T_10 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_11; // @[Decoupled.scala:51:35] assign _inc_T_11 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_12; // @[Decoupled.scala:51:35] assign _inc_T_12 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_13; // @[Decoupled.scala:51:35] assign _inc_T_13 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_14; // @[Decoupled.scala:51:35] assign _inc_T_14 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_15; // @[Decoupled.scala:51:35] assign _inc_T_15 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_16; // @[Decoupled.scala:51:35] assign _inc_T_16 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_17; // @[Decoupled.scala:51:35] assign _inc_T_17 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_18; // @[Decoupled.scala:51:35] assign _inc_T_18 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_19; // @[Decoupled.scala:51:35] assign _inc_T_19 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_20; // @[Decoupled.scala:51:35] assign _inc_T_20 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_21; // @[Decoupled.scala:51:35] assign _inc_T_21 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_22; // @[Decoupled.scala:51:35] assign _inc_T_22 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_23; // @[Decoupled.scala:51:35] assign _inc_T_23 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_24; // @[Decoupled.scala:51:35] assign _inc_T_24 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_25; // @[Decoupled.scala:51:35] assign _inc_T_25 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_26; // @[Decoupled.scala:51:35] assign _inc_T_26 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_27; // @[Decoupled.scala:51:35] assign _inc_T_27 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_28; // @[Decoupled.scala:51:35] assign _inc_T_28 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_29; // @[Decoupled.scala:51:35] assign _inc_T_29 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_30; // @[Decoupled.scala:51:35] assign _inc_T_30 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_31; // @[Decoupled.scala:51:35] assign _inc_T_31 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_32; // @[Decoupled.scala:51:35] assign _inc_T_32 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_33; // @[Decoupled.scala:51:35] assign _inc_T_33 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_34; // @[Decoupled.scala:51:35] assign _inc_T_34 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_35; // @[Decoupled.scala:51:35] assign _inc_T_35 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_36; // @[Decoupled.scala:51:35] assign _inc_T_36 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_37; // @[Decoupled.scala:51:35] assign _inc_T_37 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_38; // @[Decoupled.scala:51:35] assign _inc_T_38 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_39; // @[Decoupled.scala:51:35] assign _inc_T_39 = _GEN_2; // @[Decoupled.scala:51:35] wire inc = a_sel_0 & _inc_T; // @[Decoupled.scala:51:35] wire _dec_T = d_sel_0 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire _GEN_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire _dec_T_1; // @[Decoupled.scala:51:35] assign _dec_T_1 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_3; // @[Decoupled.scala:51:35] assign _dec_T_3 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_5; // @[Decoupled.scala:51:35] assign _dec_T_5 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_7; // @[Decoupled.scala:51:35] assign _dec_T_7 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_9; // @[Decoupled.scala:51:35] assign _dec_T_9 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_11; // @[Decoupled.scala:51:35] assign _dec_T_11 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_13; // @[Decoupled.scala:51:35] assign _dec_T_13 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_15; // @[Decoupled.scala:51:35] assign _dec_T_15 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_17; // @[Decoupled.scala:51:35] assign _dec_T_17 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_19; // @[Decoupled.scala:51:35] assign _dec_T_19 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_21; // @[Decoupled.scala:51:35] assign _dec_T_21 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_23; // @[Decoupled.scala:51:35] assign _dec_T_23 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_25; // @[Decoupled.scala:51:35] assign _dec_T_25 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_27; // @[Decoupled.scala:51:35] assign _dec_T_27 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_29; // @[Decoupled.scala:51:35] assign _dec_T_29 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_31; // @[Decoupled.scala:51:35] assign _dec_T_31 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_33; // @[Decoupled.scala:51:35] assign _dec_T_33 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_35; // @[Decoupled.scala:51:35] assign _dec_T_35 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_37; // @[Decoupled.scala:51:35] assign _dec_T_37 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_39; // @[Decoupled.scala:51:35] assign _dec_T_39 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_41; // @[Decoupled.scala:51:35] assign _dec_T_41 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_43; // @[Decoupled.scala:51:35] assign _dec_T_43 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_45; // @[Decoupled.scala:51:35] assign _dec_T_45 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_47; // @[Decoupled.scala:51:35] assign _dec_T_47 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_49; // @[Decoupled.scala:51:35] assign _dec_T_49 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_51; // @[Decoupled.scala:51:35] assign _dec_T_51 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_53; // @[Decoupled.scala:51:35] assign _dec_T_53 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_55; // @[Decoupled.scala:51:35] assign _dec_T_55 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_57; // @[Decoupled.scala:51:35] assign _dec_T_57 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_59; // @[Decoupled.scala:51:35] assign _dec_T_59 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_61; // @[Decoupled.scala:51:35] assign _dec_T_61 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_63; // @[Decoupled.scala:51:35] assign _dec_T_63 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_65; // @[Decoupled.scala:51:35] assign _dec_T_65 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_67; // @[Decoupled.scala:51:35] assign _dec_T_67 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_69; // @[Decoupled.scala:51:35] assign _dec_T_69 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_71; // @[Decoupled.scala:51:35] assign _dec_T_71 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_73; // @[Decoupled.scala:51:35] assign _dec_T_73 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_75; // @[Decoupled.scala:51:35] assign _dec_T_75 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_77; // @[Decoupled.scala:51:35] assign _dec_T_77 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_79; // @[Decoupled.scala:51:35] assign _dec_T_79 = _GEN_3; // @[Decoupled.scala:51:35] wire dec = _dec_T & _dec_T_1; // @[Decoupled.scala:51:35] wire [1:0] _count_T = {1'h0, count} + {1'h0, inc}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_1 = _count_T[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_2 = {1'h0, _count_T_1} - {1'h0, dec}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_3 = _count_T_2[0]; // @[ToAXI4.scala:278:37] wire _idStall_0_T = ~idle; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_0_T_3 = _idStall_0_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_0 = _idStall_0_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_1; // @[ToAXI4.scala:272:28] wire _idStall_1_T_2 = count_1; // @[ToAXI4.scala:272:28, :286:44] reg write_1; // @[ToAXI4.scala:273:24] wire idle_1 = ~count_1; // @[ToAXI4.scala:272:28, :274:26] wire inc_1 = a_sel_1 & _inc_T_1; // @[Decoupled.scala:51:35] wire _dec_T_2 = d_sel_1 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_1 = _dec_T_2 & _dec_T_3; // @[Decoupled.scala:51:35] wire [1:0] _count_T_4 = {1'h0, count_1} + {1'h0, inc_1}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_5 = _count_T_4[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_6 = {1'h0, _count_T_5} - {1'h0, dec_1}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_7 = _count_T_6[0]; // @[ToAXI4.scala:278:37] wire _idStall_1_T = ~idle_1; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_1_T_3 = _idStall_1_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_1 = _idStall_1_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_2; // @[ToAXI4.scala:272:28] wire _idStall_2_T_2 = count_2; // @[ToAXI4.scala:272:28, :286:44] reg write_2; // @[ToAXI4.scala:273:24] wire idle_2 = ~count_2; // @[ToAXI4.scala:272:28, :274:26] wire inc_2 = a_sel_2 & _inc_T_2; // @[Decoupled.scala:51:35] wire _dec_T_4 = d_sel_2 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_2 = _dec_T_4 & _dec_T_5; // @[Decoupled.scala:51:35] wire [1:0] _count_T_8 = {1'h0, count_2} + {1'h0, inc_2}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_9 = _count_T_8[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_10 = {1'h0, _count_T_9} - {1'h0, dec_2}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_11 = _count_T_10[0]; // @[ToAXI4.scala:278:37] wire _idStall_2_T = ~idle_2; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_2_T_3 = _idStall_2_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_2 = _idStall_2_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_3; // @[ToAXI4.scala:272:28] wire _idStall_3_T_2 = count_3; // @[ToAXI4.scala:272:28, :286:44] reg write_3; // @[ToAXI4.scala:273:24] wire idle_3 = ~count_3; // @[ToAXI4.scala:272:28, :274:26] wire inc_3 = a_sel_3 & _inc_T_3; // @[Decoupled.scala:51:35] wire _dec_T_6 = d_sel_3 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_3 = _dec_T_6 & _dec_T_7; // @[Decoupled.scala:51:35] wire [1:0] _count_T_12 = {1'h0, count_3} + {1'h0, inc_3}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_13 = _count_T_12[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_14 = {1'h0, _count_T_13} - {1'h0, dec_3}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_15 = _count_T_14[0]; // @[ToAXI4.scala:278:37] wire _idStall_3_T = ~idle_3; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_3_T_3 = _idStall_3_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_3 = _idStall_3_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_4; // @[ToAXI4.scala:272:28] wire _idStall_4_T_2 = count_4; // @[ToAXI4.scala:272:28, :286:44] reg write_4; // @[ToAXI4.scala:273:24] wire idle_4 = ~count_4; // @[ToAXI4.scala:272:28, :274:26] wire inc_4 = a_sel_4 & _inc_T_4; // @[Decoupled.scala:51:35] wire _dec_T_8 = d_sel_4 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_4 = _dec_T_8 & _dec_T_9; // @[Decoupled.scala:51:35] wire [1:0] _count_T_16 = {1'h0, count_4} + {1'h0, inc_4}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_17 = _count_T_16[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_18 = {1'h0, _count_T_17} - {1'h0, dec_4}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_19 = _count_T_18[0]; // @[ToAXI4.scala:278:37] wire _idStall_4_T = ~idle_4; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_4_T_3 = _idStall_4_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_4 = _idStall_4_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_5; // @[ToAXI4.scala:272:28] wire _idStall_5_T_2 = count_5; // @[ToAXI4.scala:272:28, :286:44] reg write_5; // @[ToAXI4.scala:273:24] wire idle_5 = ~count_5; // @[ToAXI4.scala:272:28, :274:26] wire inc_5 = a_sel_5 & _inc_T_5; // @[Decoupled.scala:51:35] wire _dec_T_10 = d_sel_5 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_5 = _dec_T_10 & _dec_T_11; // @[Decoupled.scala:51:35] wire [1:0] _count_T_20 = {1'h0, count_5} + {1'h0, inc_5}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_21 = _count_T_20[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_22 = {1'h0, _count_T_21} - {1'h0, dec_5}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_23 = _count_T_22[0]; // @[ToAXI4.scala:278:37] wire _idStall_5_T = ~idle_5; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_5_T_3 = _idStall_5_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_5 = _idStall_5_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_6; // @[ToAXI4.scala:272:28] wire _idStall_6_T_2 = count_6; // @[ToAXI4.scala:272:28, :286:44] reg write_6; // @[ToAXI4.scala:273:24] wire idle_6 = ~count_6; // @[ToAXI4.scala:272:28, :274:26] wire inc_6 = a_sel_6 & _inc_T_6; // @[Decoupled.scala:51:35] wire _dec_T_12 = d_sel_6 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_6 = _dec_T_12 & _dec_T_13; // @[Decoupled.scala:51:35] wire [1:0] _count_T_24 = {1'h0, count_6} + {1'h0, inc_6}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_25 = _count_T_24[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_26 = {1'h0, _count_T_25} - {1'h0, dec_6}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_27 = _count_T_26[0]; // @[ToAXI4.scala:278:37] wire _idStall_6_T = ~idle_6; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_6_T_3 = _idStall_6_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_6 = _idStall_6_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_7; // @[ToAXI4.scala:272:28] wire _idStall_7_T_2 = count_7; // @[ToAXI4.scala:272:28, :286:44] reg write_7; // @[ToAXI4.scala:273:24] wire idle_7 = ~count_7; // @[ToAXI4.scala:272:28, :274:26] wire inc_7 = a_sel_7 & _inc_T_7; // @[Decoupled.scala:51:35] wire _dec_T_14 = d_sel_7 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_7 = _dec_T_14 & _dec_T_15; // @[Decoupled.scala:51:35] wire [1:0] _count_T_28 = {1'h0, count_7} + {1'h0, inc_7}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_29 = _count_T_28[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_30 = {1'h0, _count_T_29} - {1'h0, dec_7}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_31 = _count_T_30[0]; // @[ToAXI4.scala:278:37] wire _idStall_7_T = ~idle_7; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_7_T_3 = _idStall_7_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_7 = _idStall_7_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_8; // @[ToAXI4.scala:272:28] wire _idStall_8_T_2 = count_8; // @[ToAXI4.scala:272:28, :286:44] reg write_8; // @[ToAXI4.scala:273:24] wire idle_8 = ~count_8; // @[ToAXI4.scala:272:28, :274:26] wire inc_8 = a_sel_8 & _inc_T_8; // @[Decoupled.scala:51:35] wire _dec_T_16 = d_sel_8 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_8 = _dec_T_16 & _dec_T_17; // @[Decoupled.scala:51:35] wire [1:0] _count_T_32 = {1'h0, count_8} + {1'h0, inc_8}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_33 = _count_T_32[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_34 = {1'h0, _count_T_33} - {1'h0, dec_8}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_35 = _count_T_34[0]; // @[ToAXI4.scala:278:37] wire _idStall_8_T = ~idle_8; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_8_T_3 = _idStall_8_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_8 = _idStall_8_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_9; // @[ToAXI4.scala:272:28] wire _idStall_9_T_2 = count_9; // @[ToAXI4.scala:272:28, :286:44] reg write_9; // @[ToAXI4.scala:273:24] wire idle_9 = ~count_9; // @[ToAXI4.scala:272:28, :274:26] wire inc_9 = a_sel_9 & _inc_T_9; // @[Decoupled.scala:51:35] wire _dec_T_18 = d_sel_9 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_9 = _dec_T_18 & _dec_T_19; // @[Decoupled.scala:51:35] wire [1:0] _count_T_36 = {1'h0, count_9} + {1'h0, inc_9}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_37 = _count_T_36[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_38 = {1'h0, _count_T_37} - {1'h0, dec_9}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_39 = _count_T_38[0]; // @[ToAXI4.scala:278:37] wire _idStall_9_T = ~idle_9; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_9_T_3 = _idStall_9_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_9 = _idStall_9_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_10; // @[ToAXI4.scala:272:28] wire _idStall_10_T_2 = count_10; // @[ToAXI4.scala:272:28, :286:44] reg write_10; // @[ToAXI4.scala:273:24] wire idle_10 = ~count_10; // @[ToAXI4.scala:272:28, :274:26] wire inc_10 = a_sel_10 & _inc_T_10; // @[Decoupled.scala:51:35] wire _dec_T_20 = d_sel_10 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_10 = _dec_T_20 & _dec_T_21; // @[Decoupled.scala:51:35] wire [1:0] _count_T_40 = {1'h0, count_10} + {1'h0, inc_10}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_41 = _count_T_40[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_42 = {1'h0, _count_T_41} - {1'h0, dec_10}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_43 = _count_T_42[0]; // @[ToAXI4.scala:278:37] wire _idStall_10_T = ~idle_10; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_10_T_3 = _idStall_10_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_10 = _idStall_10_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_11; // @[ToAXI4.scala:272:28] wire _idStall_11_T_2 = count_11; // @[ToAXI4.scala:272:28, :286:44] reg write_11; // @[ToAXI4.scala:273:24] wire idle_11 = ~count_11; // @[ToAXI4.scala:272:28, :274:26] wire inc_11 = a_sel_11 & _inc_T_11; // @[Decoupled.scala:51:35] wire _dec_T_22 = d_sel_11 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_11 = _dec_T_22 & _dec_T_23; // @[Decoupled.scala:51:35] wire [1:0] _count_T_44 = {1'h0, count_11} + {1'h0, inc_11}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_45 = _count_T_44[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_46 = {1'h0, _count_T_45} - {1'h0, dec_11}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_47 = _count_T_46[0]; // @[ToAXI4.scala:278:37] wire _idStall_11_T = ~idle_11; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_11_T_3 = _idStall_11_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_11 = _idStall_11_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_12; // @[ToAXI4.scala:272:28] wire _idStall_12_T_2 = count_12; // @[ToAXI4.scala:272:28, :286:44] reg write_12; // @[ToAXI4.scala:273:24] wire idle_12 = ~count_12; // @[ToAXI4.scala:272:28, :274:26] wire inc_12 = a_sel_12 & _inc_T_12; // @[Decoupled.scala:51:35] wire _dec_T_24 = d_sel_12 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_12 = _dec_T_24 & _dec_T_25; // @[Decoupled.scala:51:35] wire [1:0] _count_T_48 = {1'h0, count_12} + {1'h0, inc_12}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_49 = _count_T_48[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_50 = {1'h0, _count_T_49} - {1'h0, dec_12}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_51 = _count_T_50[0]; // @[ToAXI4.scala:278:37] wire _idStall_12_T = ~idle_12; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_12_T_3 = _idStall_12_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_12 = _idStall_12_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_13; // @[ToAXI4.scala:272:28] wire _idStall_13_T_2 = count_13; // @[ToAXI4.scala:272:28, :286:44] reg write_13; // @[ToAXI4.scala:273:24] wire idle_13 = ~count_13; // @[ToAXI4.scala:272:28, :274:26] wire inc_13 = a_sel_13 & _inc_T_13; // @[Decoupled.scala:51:35] wire _dec_T_26 = d_sel_13 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_13 = _dec_T_26 & _dec_T_27; // @[Decoupled.scala:51:35] wire [1:0] _count_T_52 = {1'h0, count_13} + {1'h0, inc_13}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_53 = _count_T_52[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_54 = {1'h0, _count_T_53} - {1'h0, dec_13}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_55 = _count_T_54[0]; // @[ToAXI4.scala:278:37] wire _idStall_13_T = ~idle_13; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_13_T_3 = _idStall_13_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_13 = _idStall_13_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_14; // @[ToAXI4.scala:272:28] wire _idStall_14_T_2 = count_14; // @[ToAXI4.scala:272:28, :286:44] reg write_14; // @[ToAXI4.scala:273:24] wire idle_14 = ~count_14; // @[ToAXI4.scala:272:28, :274:26] wire inc_14 = a_sel_14 & _inc_T_14; // @[Decoupled.scala:51:35] wire _dec_T_28 = d_sel_14 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_14 = _dec_T_28 & _dec_T_29; // @[Decoupled.scala:51:35] wire [1:0] _count_T_56 = {1'h0, count_14} + {1'h0, inc_14}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_57 = _count_T_56[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_58 = {1'h0, _count_T_57} - {1'h0, dec_14}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_59 = _count_T_58[0]; // @[ToAXI4.scala:278:37] wire _idStall_14_T = ~idle_14; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_14_T_3 = _idStall_14_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_14 = _idStall_14_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_15; // @[ToAXI4.scala:272:28] wire _idStall_15_T_2 = count_15; // @[ToAXI4.scala:272:28, :286:44] reg write_15; // @[ToAXI4.scala:273:24] wire idle_15 = ~count_15; // @[ToAXI4.scala:272:28, :274:26] wire inc_15 = a_sel_15 & _inc_T_15; // @[Decoupled.scala:51:35] wire _dec_T_30 = d_sel_15 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_15 = _dec_T_30 & _dec_T_31; // @[Decoupled.scala:51:35] wire [1:0] _count_T_60 = {1'h0, count_15} + {1'h0, inc_15}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_61 = _count_T_60[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_62 = {1'h0, _count_T_61} - {1'h0, dec_15}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_63 = _count_T_62[0]; // @[ToAXI4.scala:278:37] wire _idStall_15_T = ~idle_15; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_15_T_3 = _idStall_15_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_15 = _idStall_15_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_16; // @[ToAXI4.scala:272:28] wire _idStall_16_T_2 = count_16; // @[ToAXI4.scala:272:28, :286:44] reg write_16; // @[ToAXI4.scala:273:24] wire idle_16 = ~count_16; // @[ToAXI4.scala:272:28, :274:26] wire inc_16 = a_sel_16 & _inc_T_16; // @[Decoupled.scala:51:35] wire _dec_T_32 = d_sel_16 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_16 = _dec_T_32 & _dec_T_33; // @[Decoupled.scala:51:35] wire [1:0] _count_T_64 = {1'h0, count_16} + {1'h0, inc_16}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_65 = _count_T_64[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_66 = {1'h0, _count_T_65} - {1'h0, dec_16}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_67 = _count_T_66[0]; // @[ToAXI4.scala:278:37] wire _idStall_16_T = ~idle_16; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_16_T_3 = _idStall_16_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_16 = _idStall_16_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_17; // @[ToAXI4.scala:272:28] wire _idStall_17_T_2 = count_17; // @[ToAXI4.scala:272:28, :286:44] reg write_17; // @[ToAXI4.scala:273:24] wire idle_17 = ~count_17; // @[ToAXI4.scala:272:28, :274:26] wire inc_17 = a_sel_17 & _inc_T_17; // @[Decoupled.scala:51:35] wire _dec_T_34 = d_sel_17 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_17 = _dec_T_34 & _dec_T_35; // @[Decoupled.scala:51:35] wire [1:0] _count_T_68 = {1'h0, count_17} + {1'h0, inc_17}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_69 = _count_T_68[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_70 = {1'h0, _count_T_69} - {1'h0, dec_17}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_71 = _count_T_70[0]; // @[ToAXI4.scala:278:37] wire _idStall_17_T = ~idle_17; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_17_T_3 = _idStall_17_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_17 = _idStall_17_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_18; // @[ToAXI4.scala:272:28] wire _idStall_18_T_2 = count_18; // @[ToAXI4.scala:272:28, :286:44] reg write_18; // @[ToAXI4.scala:273:24] wire idle_18 = ~count_18; // @[ToAXI4.scala:272:28, :274:26] wire inc_18 = a_sel_18 & _inc_T_18; // @[Decoupled.scala:51:35] wire _dec_T_36 = d_sel_18 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_18 = _dec_T_36 & _dec_T_37; // @[Decoupled.scala:51:35] wire [1:0] _count_T_72 = {1'h0, count_18} + {1'h0, inc_18}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_73 = _count_T_72[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_74 = {1'h0, _count_T_73} - {1'h0, dec_18}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_75 = _count_T_74[0]; // @[ToAXI4.scala:278:37] wire _idStall_18_T = ~idle_18; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_18_T_3 = _idStall_18_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_18 = _idStall_18_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_19; // @[ToAXI4.scala:272:28] wire _idStall_19_T_2 = count_19; // @[ToAXI4.scala:272:28, :286:44] reg write_19; // @[ToAXI4.scala:273:24] wire idle_19 = ~count_19; // @[ToAXI4.scala:272:28, :274:26] wire inc_19 = a_sel_19 & _inc_T_19; // @[Decoupled.scala:51:35] wire _dec_T_38 = d_sel_19 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_19 = _dec_T_38 & _dec_T_39; // @[Decoupled.scala:51:35] wire [1:0] _count_T_76 = {1'h0, count_19} + {1'h0, inc_19}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_77 = _count_T_76[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_78 = {1'h0, _count_T_77} - {1'h0, dec_19}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_79 = _count_T_78[0]; // @[ToAXI4.scala:278:37] wire _idStall_19_T = ~idle_19; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_19_T_3 = _idStall_19_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_19 = _idStall_19_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_20; // @[ToAXI4.scala:272:28] wire _idStall_20_T_2 = count_20; // @[ToAXI4.scala:272:28, :286:44] reg write_20; // @[ToAXI4.scala:273:24] wire idle_20 = ~count_20; // @[ToAXI4.scala:272:28, :274:26] wire inc_20 = a_sel_20 & _inc_T_20; // @[Decoupled.scala:51:35] wire _dec_T_40 = d_sel_20 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_20 = _dec_T_40 & _dec_T_41; // @[Decoupled.scala:51:35] wire [1:0] _count_T_80 = {1'h0, count_20} + {1'h0, inc_20}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_81 = _count_T_80[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_82 = {1'h0, _count_T_81} - {1'h0, dec_20}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_83 = _count_T_82[0]; // @[ToAXI4.scala:278:37] wire _idStall_20_T = ~idle_20; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_20_T_3 = _idStall_20_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_20 = _idStall_20_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_21; // @[ToAXI4.scala:272:28] wire _idStall_21_T_2 = count_21; // @[ToAXI4.scala:272:28, :286:44] reg write_21; // @[ToAXI4.scala:273:24] wire idle_21 = ~count_21; // @[ToAXI4.scala:272:28, :274:26] wire inc_21 = a_sel_21 & _inc_T_21; // @[Decoupled.scala:51:35] wire _dec_T_42 = d_sel_21 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_21 = _dec_T_42 & _dec_T_43; // @[Decoupled.scala:51:35] wire [1:0] _count_T_84 = {1'h0, count_21} + {1'h0, inc_21}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_85 = _count_T_84[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_86 = {1'h0, _count_T_85} - {1'h0, dec_21}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_87 = _count_T_86[0]; // @[ToAXI4.scala:278:37] wire _idStall_21_T = ~idle_21; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_21_T_3 = _idStall_21_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_21 = _idStall_21_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_22; // @[ToAXI4.scala:272:28] wire _idStall_22_T_2 = count_22; // @[ToAXI4.scala:272:28, :286:44] reg write_22; // @[ToAXI4.scala:273:24] wire idle_22 = ~count_22; // @[ToAXI4.scala:272:28, :274:26] wire inc_22 = a_sel_22 & _inc_T_22; // @[Decoupled.scala:51:35] wire _dec_T_44 = d_sel_22 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_22 = _dec_T_44 & _dec_T_45; // @[Decoupled.scala:51:35] wire [1:0] _count_T_88 = {1'h0, count_22} + {1'h0, inc_22}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_89 = _count_T_88[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_90 = {1'h0, _count_T_89} - {1'h0, dec_22}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_91 = _count_T_90[0]; // @[ToAXI4.scala:278:37] wire _idStall_22_T = ~idle_22; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_22_T_3 = _idStall_22_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_22 = _idStall_22_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_23; // @[ToAXI4.scala:272:28] wire _idStall_23_T_2 = count_23; // @[ToAXI4.scala:272:28, :286:44] reg write_23; // @[ToAXI4.scala:273:24] wire idle_23 = ~count_23; // @[ToAXI4.scala:272:28, :274:26] wire inc_23 = a_sel_23 & _inc_T_23; // @[Decoupled.scala:51:35] wire _dec_T_46 = d_sel_23 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_23 = _dec_T_46 & _dec_T_47; // @[Decoupled.scala:51:35] wire [1:0] _count_T_92 = {1'h0, count_23} + {1'h0, inc_23}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_93 = _count_T_92[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_94 = {1'h0, _count_T_93} - {1'h0, dec_23}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_95 = _count_T_94[0]; // @[ToAXI4.scala:278:37] wire _idStall_23_T = ~idle_23; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_23_T_3 = _idStall_23_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_23 = _idStall_23_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_24; // @[ToAXI4.scala:272:28] wire _idStall_24_T_2 = count_24; // @[ToAXI4.scala:272:28, :286:44] reg write_24; // @[ToAXI4.scala:273:24] wire idle_24 = ~count_24; // @[ToAXI4.scala:272:28, :274:26] wire inc_24 = a_sel_24 & _inc_T_24; // @[Decoupled.scala:51:35] wire _dec_T_48 = d_sel_24 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_24 = _dec_T_48 & _dec_T_49; // @[Decoupled.scala:51:35] wire [1:0] _count_T_96 = {1'h0, count_24} + {1'h0, inc_24}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_97 = _count_T_96[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_98 = {1'h0, _count_T_97} - {1'h0, dec_24}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_99 = _count_T_98[0]; // @[ToAXI4.scala:278:37] wire _idStall_24_T = ~idle_24; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_24_T_3 = _idStall_24_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_24 = _idStall_24_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_25; // @[ToAXI4.scala:272:28] wire _idStall_25_T_2 = count_25; // @[ToAXI4.scala:272:28, :286:44] reg write_25; // @[ToAXI4.scala:273:24] wire idle_25 = ~count_25; // @[ToAXI4.scala:272:28, :274:26] wire inc_25 = a_sel_25 & _inc_T_25; // @[Decoupled.scala:51:35] wire _dec_T_50 = d_sel_25 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_25 = _dec_T_50 & _dec_T_51; // @[Decoupled.scala:51:35] wire [1:0] _count_T_100 = {1'h0, count_25} + {1'h0, inc_25}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_101 = _count_T_100[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_102 = {1'h0, _count_T_101} - {1'h0, dec_25}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_103 = _count_T_102[0]; // @[ToAXI4.scala:278:37] wire _idStall_25_T = ~idle_25; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_25_T_3 = _idStall_25_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_25 = _idStall_25_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_26; // @[ToAXI4.scala:272:28] wire _idStall_26_T_2 = count_26; // @[ToAXI4.scala:272:28, :286:44] reg write_26; // @[ToAXI4.scala:273:24] wire idle_26 = ~count_26; // @[ToAXI4.scala:272:28, :274:26] wire inc_26 = a_sel_26 & _inc_T_26; // @[Decoupled.scala:51:35] wire _dec_T_52 = d_sel_26 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_26 = _dec_T_52 & _dec_T_53; // @[Decoupled.scala:51:35] wire [1:0] _count_T_104 = {1'h0, count_26} + {1'h0, inc_26}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_105 = _count_T_104[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_106 = {1'h0, _count_T_105} - {1'h0, dec_26}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_107 = _count_T_106[0]; // @[ToAXI4.scala:278:37] wire _idStall_26_T = ~idle_26; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_26_T_3 = _idStall_26_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_26 = _idStall_26_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_27; // @[ToAXI4.scala:272:28] wire _idStall_27_T_2 = count_27; // @[ToAXI4.scala:272:28, :286:44] reg write_27; // @[ToAXI4.scala:273:24] wire idle_27 = ~count_27; // @[ToAXI4.scala:272:28, :274:26] wire inc_27 = a_sel_27 & _inc_T_27; // @[Decoupled.scala:51:35] wire _dec_T_54 = d_sel_27 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_27 = _dec_T_54 & _dec_T_55; // @[Decoupled.scala:51:35] wire [1:0] _count_T_108 = {1'h0, count_27} + {1'h0, inc_27}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_109 = _count_T_108[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_110 = {1'h0, _count_T_109} - {1'h0, dec_27}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_111 = _count_T_110[0]; // @[ToAXI4.scala:278:37] wire _idStall_27_T = ~idle_27; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_27_T_3 = _idStall_27_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_27 = _idStall_27_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_28; // @[ToAXI4.scala:272:28] wire _idStall_28_T_2 = count_28; // @[ToAXI4.scala:272:28, :286:44] reg write_28; // @[ToAXI4.scala:273:24] wire idle_28 = ~count_28; // @[ToAXI4.scala:272:28, :274:26] wire inc_28 = a_sel_28 & _inc_T_28; // @[Decoupled.scala:51:35] wire _dec_T_56 = d_sel_28 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_28 = _dec_T_56 & _dec_T_57; // @[Decoupled.scala:51:35] wire [1:0] _count_T_112 = {1'h0, count_28} + {1'h0, inc_28}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_113 = _count_T_112[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_114 = {1'h0, _count_T_113} - {1'h0, dec_28}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_115 = _count_T_114[0]; // @[ToAXI4.scala:278:37] wire _idStall_28_T = ~idle_28; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_28_T_3 = _idStall_28_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_28 = _idStall_28_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_29; // @[ToAXI4.scala:272:28] wire _idStall_29_T_2 = count_29; // @[ToAXI4.scala:272:28, :286:44] reg write_29; // @[ToAXI4.scala:273:24] wire idle_29 = ~count_29; // @[ToAXI4.scala:272:28, :274:26] wire inc_29 = a_sel_29 & _inc_T_29; // @[Decoupled.scala:51:35] wire _dec_T_58 = d_sel_29 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_29 = _dec_T_58 & _dec_T_59; // @[Decoupled.scala:51:35] wire [1:0] _count_T_116 = {1'h0, count_29} + {1'h0, inc_29}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_117 = _count_T_116[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_118 = {1'h0, _count_T_117} - {1'h0, dec_29}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_119 = _count_T_118[0]; // @[ToAXI4.scala:278:37] wire _idStall_29_T = ~idle_29; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_29_T_3 = _idStall_29_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_29 = _idStall_29_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_30; // @[ToAXI4.scala:272:28] wire _idStall_30_T_2 = count_30; // @[ToAXI4.scala:272:28, :286:44] reg write_30; // @[ToAXI4.scala:273:24] wire idle_30 = ~count_30; // @[ToAXI4.scala:272:28, :274:26] wire inc_30 = a_sel_30 & _inc_T_30; // @[Decoupled.scala:51:35] wire _dec_T_60 = d_sel_30 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_30 = _dec_T_60 & _dec_T_61; // @[Decoupled.scala:51:35] wire [1:0] _count_T_120 = {1'h0, count_30} + {1'h0, inc_30}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_121 = _count_T_120[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_122 = {1'h0, _count_T_121} - {1'h0, dec_30}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_123 = _count_T_122[0]; // @[ToAXI4.scala:278:37] wire _idStall_30_T = ~idle_30; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_30_T_3 = _idStall_30_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_30 = _idStall_30_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_31; // @[ToAXI4.scala:272:28] wire _idStall_31_T_2 = count_31; // @[ToAXI4.scala:272:28, :286:44] reg write_31; // @[ToAXI4.scala:273:24] wire idle_31 = ~count_31; // @[ToAXI4.scala:272:28, :274:26] wire inc_31 = a_sel_31 & _inc_T_31; // @[Decoupled.scala:51:35] wire _dec_T_62 = d_sel_31 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_31 = _dec_T_62 & _dec_T_63; // @[Decoupled.scala:51:35] wire [1:0] _count_T_124 = {1'h0, count_31} + {1'h0, inc_31}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_125 = _count_T_124[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_126 = {1'h0, _count_T_125} - {1'h0, dec_31}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_127 = _count_T_126[0]; // @[ToAXI4.scala:278:37] wire _idStall_31_T = ~idle_31; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_31_T_3 = _idStall_31_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_31 = _idStall_31_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_32; // @[ToAXI4.scala:272:28] wire _idStall_32_T_2 = count_32; // @[ToAXI4.scala:272:28, :286:44] reg write_32; // @[ToAXI4.scala:273:24] wire idle_32 = ~count_32; // @[ToAXI4.scala:272:28, :274:26] wire inc_32 = a_sel_32 & _inc_T_32; // @[Decoupled.scala:51:35] wire _dec_T_64 = d_sel_32 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_32 = _dec_T_64 & _dec_T_65; // @[Decoupled.scala:51:35] wire [1:0] _count_T_128 = {1'h0, count_32} + {1'h0, inc_32}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_129 = _count_T_128[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_130 = {1'h0, _count_T_129} - {1'h0, dec_32}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_131 = _count_T_130[0]; // @[ToAXI4.scala:278:37] wire _idStall_32_T = ~idle_32; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_32_T_3 = _idStall_32_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_32 = _idStall_32_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_33; // @[ToAXI4.scala:272:28] wire _idStall_33_T_2 = count_33; // @[ToAXI4.scala:272:28, :286:44] reg write_33; // @[ToAXI4.scala:273:24] wire idle_33 = ~count_33; // @[ToAXI4.scala:272:28, :274:26] wire inc_33 = a_sel_33 & _inc_T_33; // @[Decoupled.scala:51:35] wire _dec_T_66 = d_sel_33 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_33 = _dec_T_66 & _dec_T_67; // @[Decoupled.scala:51:35] wire [1:0] _count_T_132 = {1'h0, count_33} + {1'h0, inc_33}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_133 = _count_T_132[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_134 = {1'h0, _count_T_133} - {1'h0, dec_33}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_135 = _count_T_134[0]; // @[ToAXI4.scala:278:37] wire _idStall_33_T = ~idle_33; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_33_T_3 = _idStall_33_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_33 = _idStall_33_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_34; // @[ToAXI4.scala:272:28] wire _idStall_34_T_2 = count_34; // @[ToAXI4.scala:272:28, :286:44] reg write_34; // @[ToAXI4.scala:273:24] wire idle_34 = ~count_34; // @[ToAXI4.scala:272:28, :274:26] wire inc_34 = a_sel_34 & _inc_T_34; // @[Decoupled.scala:51:35] wire _dec_T_68 = d_sel_34 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_34 = _dec_T_68 & _dec_T_69; // @[Decoupled.scala:51:35] wire [1:0] _count_T_136 = {1'h0, count_34} + {1'h0, inc_34}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_137 = _count_T_136[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_138 = {1'h0, _count_T_137} - {1'h0, dec_34}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_139 = _count_T_138[0]; // @[ToAXI4.scala:278:37] wire _idStall_34_T = ~idle_34; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_34_T_3 = _idStall_34_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_34 = _idStall_34_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_35; // @[ToAXI4.scala:272:28] wire _idStall_35_T_2 = count_35; // @[ToAXI4.scala:272:28, :286:44] reg write_35; // @[ToAXI4.scala:273:24] wire idle_35 = ~count_35; // @[ToAXI4.scala:272:28, :274:26] wire inc_35 = a_sel_35 & _inc_T_35; // @[Decoupled.scala:51:35] wire _dec_T_70 = d_sel_35 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_35 = _dec_T_70 & _dec_T_71; // @[Decoupled.scala:51:35] wire [1:0] _count_T_140 = {1'h0, count_35} + {1'h0, inc_35}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_141 = _count_T_140[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_142 = {1'h0, _count_T_141} - {1'h0, dec_35}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_143 = _count_T_142[0]; // @[ToAXI4.scala:278:37] wire _idStall_35_T = ~idle_35; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_35_T_3 = _idStall_35_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_35 = _idStall_35_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_36; // @[ToAXI4.scala:272:28] wire _idStall_36_T_2 = count_36; // @[ToAXI4.scala:272:28, :286:44] reg write_36; // @[ToAXI4.scala:273:24] wire idle_36 = ~count_36; // @[ToAXI4.scala:272:28, :274:26] wire inc_36 = a_sel_36 & _inc_T_36; // @[Decoupled.scala:51:35] wire _dec_T_72 = d_sel_36 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_36 = _dec_T_72 & _dec_T_73; // @[Decoupled.scala:51:35] wire [1:0] _count_T_144 = {1'h0, count_36} + {1'h0, inc_36}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_145 = _count_T_144[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_146 = {1'h0, _count_T_145} - {1'h0, dec_36}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_147 = _count_T_146[0]; // @[ToAXI4.scala:278:37] wire _idStall_36_T = ~idle_36; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_36_T_3 = _idStall_36_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_36 = _idStall_36_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_37; // @[ToAXI4.scala:272:28] wire _idStall_37_T_2 = count_37; // @[ToAXI4.scala:272:28, :286:44] reg write_37; // @[ToAXI4.scala:273:24] wire idle_37 = ~count_37; // @[ToAXI4.scala:272:28, :274:26] wire inc_37 = a_sel_37 & _inc_T_37; // @[Decoupled.scala:51:35] wire _dec_T_74 = d_sel_37 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_37 = _dec_T_74 & _dec_T_75; // @[Decoupled.scala:51:35] wire [1:0] _count_T_148 = {1'h0, count_37} + {1'h0, inc_37}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_149 = _count_T_148[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_150 = {1'h0, _count_T_149} - {1'h0, dec_37}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_151 = _count_T_150[0]; // @[ToAXI4.scala:278:37] wire _idStall_37_T = ~idle_37; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_37_T_3 = _idStall_37_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_37 = _idStall_37_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_38; // @[ToAXI4.scala:272:28] wire _idStall_38_T_2 = count_38; // @[ToAXI4.scala:272:28, :286:44] reg write_38; // @[ToAXI4.scala:273:24] wire idle_38 = ~count_38; // @[ToAXI4.scala:272:28, :274:26] wire inc_38 = a_sel_38 & _inc_T_38; // @[Decoupled.scala:51:35] wire _dec_T_76 = d_sel_38 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_38 = _dec_T_76 & _dec_T_77; // @[Decoupled.scala:51:35] wire [1:0] _count_T_152 = {1'h0, count_38} + {1'h0, inc_38}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_153 = _count_T_152[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_154 = {1'h0, _count_T_153} - {1'h0, dec_38}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_155 = _count_T_154[0]; // @[ToAXI4.scala:278:37] wire _idStall_38_T = ~idle_38; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_38_T_3 = _idStall_38_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_38 = _idStall_38_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_39; // @[ToAXI4.scala:272:28] wire _idStall_39_T_2 = count_39; // @[ToAXI4.scala:272:28, :286:44] reg write_39; // @[ToAXI4.scala:273:24] wire idle_39 = ~count_39; // @[ToAXI4.scala:272:28, :274:26] wire inc_39 = a_sel_39 & _inc_T_39; // @[Decoupled.scala:51:35] wire _dec_T_78 = d_sel_39 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_39 = _dec_T_78 & _dec_T_79; // @[Decoupled.scala:51:35] wire [1:0] _count_T_156 = {1'h0, count_39} + {1'h0, inc_39}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_157 = _count_T_156[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_158 = {1'h0, _count_T_157} - {1'h0, dec_39}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_159 = _count_T_158[0]; // @[ToAXI4.scala:278:37]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFNToRaw_postMul_e8_s24_6( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = \|_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = \|_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = \|_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = \|_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 \| io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd \| io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 \| io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 \| _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 \| _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 \| _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 \| io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T \| _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29] wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 \| _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_184( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_194 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_110( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131073:0] _c_sizes_set_T_1 = 131074'h0; // @[Monitor.scala:768:52] wire [16:0] _c_opcodes_set_T = 17'h0; // @[Monitor.scala:767:79] wire [16:0] _c_sizes_set_T = 17'h0; // @[Monitor.scala:768:77] wire [131074:0] _c_opcodes_set_T_1 = 131075'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [16383:0] _c_set_wo_ready_T = 16384'h1; // @[OneHot.scala:58:35] wire [16383:0] _c_set_T = 16384'h1; // @[OneHot.scala:58:35] wire [32831:0] c_opcodes_set = 32832'h0; // @[Monitor.scala:740:34] wire [32831:0] c_sizes_set = 32832'h0; // @[Monitor.scala:741:34] wire [8207:0] c_set = 8208'h0; // @[Monitor.scala:738:34] wire [8207:0] c_set_wo_ready = 8208'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [13:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [13:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [13:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [13:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [13:0] source_1; // @[Monitor.scala:541:22] reg [8207:0] inflight; // @[Monitor.scala:614:27] reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [8207:0] a_set; // @[Monitor.scala:626:34] wire [8207:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [32831:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [32831:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [16:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [16:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [16:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [16:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [16:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [16:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [16:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [16:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [16:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [32831:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [32831:0] _a_opcode_lookup_T_6 = {32828'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [32831:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [32831:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [32831:0] _a_size_lookup_T_6 = {32828'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [32831:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[32831:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [16383:0] _GEN_2 = 16384'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [16383:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [16:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [16:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [16:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [131074:0] _a_opcodes_set_T_1 = {131071'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [131073:0] _a_sizes_set_T_1 = {131071'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8207:0] d_clr; // @[Monitor.scala:664:34] wire [8207:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [32831:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [32831:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [16383:0] _GEN_5 = 16384'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_5 = 131087'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [131086:0] _d_sizes_clr_T_5 = 131087'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8207:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8207:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8207:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [32831:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [32831:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [32831:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [32831:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [32831:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [32831:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8207:0] inflight_1; // @[Monitor.scala:726:35] wire [8207:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [32831:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [32831:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [32831:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [32831:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [32831:0] _c_opcode_lookup_T_6 = {32828'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [32831:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [32831:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [32831:0] _c_size_lookup_T_6 = {32828'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [32831:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[32831:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [8207:0] d_clr_1; // @[Monitor.scala:774:34] wire [8207:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [32831:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [32831:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_11 = 131087'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [131086:0] _d_sizes_clr_T_11 = 131087'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 14'h0; // @[Monitor.scala:36:7, :795:113] wire [8207:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8207:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [32831:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [32831:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [32831:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [32831:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_10( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_sizes_set = 32'h0; // @[Monitor.scala:741:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_set = 4'h0; // @[Monitor.scala:738:34] wire [3:0] c_set_wo_ready = 4'h0; // @[Monitor.scala:739:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [35:0] _c_sizes_set_T_1 = 36'h0; // @[Monitor.scala:768:52] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_T = 5'h0; // @[Monitor.scala:767:79] wire [4:0] _c_sizes_set_T = 5'h0; // @[Monitor.scala:768:77] wire [34:0] _c_opcodes_set_T_1 = 35'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_set_wo_ready_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_set_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] c_opcodes_set = 16'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [3:0] inflight; // @[Monitor.scala:614:27] reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [31:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] a_set; // @[Monitor.scala:626:34] wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [31:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_3 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_4 = 4'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [3:0] d_clr; // @[Monitor.scala:664:34] wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_6 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_7 = 4'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [3:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [15:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [31:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [3:0] inflight_1; // @[Monitor.scala:726:35] wire [3:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] d_clr_1; // @[Monitor.scala:774:34] wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7, :795:113] wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_259( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_21( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_209 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_210 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_211 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_212 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired \|\| fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module Router_20( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_3_to_5_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_3_to_5_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_3_to_5_io_out_valid; // @[Router.scala:125:13] wire _output_unit_2_to_8_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_2_to_8_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_5_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_1_to_5_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _ingress_unit_2_from_5_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_2_from_5_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_in_ready; // @[Router.scala:116:13] wire _input_unit_1_from_8_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_1_from_8_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_5_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_8_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_5_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_56( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_76 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //**************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander / * Mixin for issue queue types / trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /* * Mixin for scalar operation constants / trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //********************************* // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //******************************** // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } / * Mixin for RISCV constants / trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /* * Mixin for exception cause constants / trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //*************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ / * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot / class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /* * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports / class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) \|\| (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid \|\| io.clear \|\| io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br \|\| slot_uop.is_jal \|\| slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 \|\| p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) \|\| (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned \|\| p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }	module IssueSlot_45( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } }	module NoCMonitor_121( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h1; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File PMA.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters} class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val paddr = Input(UInt()) val resp = Output(new Bundle { val cacheable = Bool() val r = Bool() val w = Bool() val pp = Bool() val al = Bool() val aa = Bool() val x = Bool() val eff = Bool() }) }) // PMA // check exist a slave can consume this address. val legal_address = manager.findSafe(io.paddr).reduce(_\|\|_) // check utility to help check SoC property. def fastCheck(member: TLManagerParameters => Boolean) = legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B) io.resp.cacheable := fastCheck(_.supportsAcquireB) io.resp.r := fastCheck(_.supportsGet) io.resp.w := fastCheck(_.supportsPutFull) io.resp.pp := fastCheck(_.supportsPutPartial) io.resp.al := fastCheck(_.supportsLogical) io.resp.aa := fastCheck(_.supportsArithmetic) io.resp.x := fastCheck(_.executable) io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }	module PMAChecker_2( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_65 = 1'h0; // @[Mux.scala:30:73] wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_37; // @[PMA.scala:39:19] wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_55; // @[PMA.scala:39:19] wire _io_resp_pp_T_55; // @[PMA.scala:39:19] wire _io_resp_al_T_55; // @[PMA.scala:39:19] wire _io_resp_aa_T_55; // @[PMA.scala:39:19] wire _io_resp_x_T_79; // @[PMA.scala:39:19] wire _io_resp_eff_T_67; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_41; // @[Parameters.scala:137:31] assign _io_resp_eff_T_41 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_47; // @[Parameters.scala:137:31] assign _io_resp_w_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_47; // @[Parameters.scala:137:31] assign _io_resp_pp_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_47; // @[Parameters.scala:137:31] assign _io_resp_al_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_47; // @[Parameters.scala:137:31] assign _io_resp_aa_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_46; // @[Parameters.scala:137:31] assign _io_resp_eff_T_46 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h20000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h21000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_30 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h22000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_35 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h23000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h24000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_50 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_60; // @[Parameters.scala:137:31] assign _legal_address_T_60 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_61 = {1'h0, _legal_address_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_62 = _legal_address_T_61 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_63 = _legal_address_T_62; // @[Parameters.scala:137:46] wire _legal_address_T_64 = _legal_address_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_12 = _legal_address_T_64; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_65; // @[Parameters.scala:137:31] assign _legal_address_T_65 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_23; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_23 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_51; // @[Parameters.scala:137:31] assign _io_resp_eff_T_51 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_66 = {1'h0, _legal_address_T_65}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_67 = _legal_address_T_66 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_68 = _legal_address_T_67; // @[Parameters.scala:137:46] wire _legal_address_T_69 = _legal_address_T_68 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_13 = _legal_address_T_69; // @[Parameters.scala:612:40] wire [39:0] _GEN_8 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_70; // @[Parameters.scala:137:31] assign _legal_address_T_70 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_15; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_15 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_59; // @[Parameters.scala:137:31] assign _io_resp_x_T_59 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_71 = {1'h0, _legal_address_T_70}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_72 = _legal_address_T_71 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_73 = _legal_address_T_72; // @[Parameters.scala:137:46] wire _legal_address_T_74 = _legal_address_T_73 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_14 = _legal_address_T_74; // @[Parameters.scala:612:40] wire [39:0] _GEN_9 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_75; // @[Parameters.scala:137:31] assign _legal_address_T_75 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_64; // @[Parameters.scala:137:31] assign _io_resp_x_T_64 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_30; // @[Parameters.scala:137:31] assign _io_resp_eff_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_76 = {1'h0, _legal_address_T_75}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_77 = _legal_address_T_76 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_78 = _legal_address_T_77; // @[Parameters.scala:137:46] wire _legal_address_T_79 = _legal_address_T_78 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_15 = _legal_address_T_79; // @[Parameters.scala:612:40] wire [39:0] _GEN_10 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_80; // @[Parameters.scala:137:31] assign _legal_address_T_80 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_28; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_28 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_35; // @[Parameters.scala:137:31] assign _io_resp_w_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_35; // @[Parameters.scala:137:31] assign _io_resp_pp_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_35; // @[Parameters.scala:137:31] assign _io_resp_al_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_35; // @[Parameters.scala:137:31] assign _io_resp_aa_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_56; // @[Parameters.scala:137:31] assign _io_resp_eff_T_56 = _GEN_10; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_81 = {1'h0, _legal_address_T_80}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_82 = _legal_address_T_81 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_83 = _legal_address_T_82; // @[Parameters.scala:137:46] wire _legal_address_T_84 = _legal_address_T_83 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_16 = _legal_address_T_84; // @[Parameters.scala:612:40] wire _legal_address_T_85 = _legal_address_WIRE_0 \| _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_86 = _legal_address_T_85 \| _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_87 = _legal_address_T_86 \| _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_88 = _legal_address_T_87 \| _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_89 = _legal_address_T_88 \| _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_90 = _legal_address_T_89 \| _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_91 = _legal_address_T_90 \| _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_92 = _legal_address_T_91 \| _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_93 = _legal_address_T_92 \| _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_94 = _legal_address_T_93 \| _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire _legal_address_T_95 = _legal_address_T_94 \| _legal_address_WIRE_11; // @[Parameters.scala:612:40] wire _legal_address_T_96 = _legal_address_T_95 \| _legal_address_WIRE_12; // @[Parameters.scala:612:40] wire _legal_address_T_97 = _legal_address_T_96 \| _legal_address_WIRE_13; // @[Parameters.scala:612:40] wire _legal_address_T_98 = _legal_address_T_97 \| _legal_address_WIRE_14; // @[Parameters.scala:612:40] wire _legal_address_T_99 = _legal_address_T_98 \| _legal_address_WIRE_15; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_99 \| _legal_address_WIRE_16; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C020000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C031000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C030000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_16 = {1'h0, _io_resp_cacheable_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_17 = _io_resp_cacheable_T_16 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_18 = _io_resp_cacheable_T_17; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_20 = _io_resp_cacheable_T_4 \| _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 \| _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_22 = _io_resp_cacheable_T_21 \| _io_resp_cacheable_T_19; // @[Parameters.scala:629:89] wire [40:0] _io_resp_cacheable_T_24 = {1'h0, _io_resp_cacheable_T_23}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24 & 41'h8C030000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_26 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_29 = {1'h0, _io_resp_cacheable_T_28}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_31 = _io_resp_cacheable_T_30; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_32 = _io_resp_cacheable_T_31 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_33 = _io_resp_cacheable_T_27 \| _io_resp_cacheable_T_32; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_35 = _io_resp_cacheable_T_33; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_36 = _io_resp_cacheable_T_35; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_36; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_37 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_37; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_36 = {1'h0, _io_resp_w_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_37 = _io_resp_w_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_38 = _io_resp_w_T_37; // @[Parameters.scala:137:46] wire _io_resp_w_T_39 = _io_resp_w_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_40 = _io_resp_w_T_4 \| _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_41 = _io_resp_w_T_40 \| _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_42 = _io_resp_w_T_41 \| _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_43 = _io_resp_w_T_42 \| _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_44 = _io_resp_w_T_43 \| _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_45 = _io_resp_w_T_44 \| _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_45 \| _io_resp_w_T_39; // @[Parameters.scala:629:89] wire _io_resp_w_T_52 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_w_T_48 = {1'h0, _io_resp_w_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_49 = _io_resp_w_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_50 = _io_resp_w_T_49; // @[Parameters.scala:137:46] wire _io_resp_w_T_51 = _io_resp_w_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_54 = _io_resp_w_T_52; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_54; // @[Mux.scala:30:73] assign _io_resp_w_T_55 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_36 = {1'h0, _io_resp_pp_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_37 = _io_resp_pp_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_38 = _io_resp_pp_T_37; // @[Parameters.scala:137:46] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_40 = _io_resp_pp_T_4 \| _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_41 = _io_resp_pp_T_40 \| _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_42 = _io_resp_pp_T_41 \| _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_43 = _io_resp_pp_T_42 \| _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_44 = _io_resp_pp_T_43 \| _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 \| _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_45 \| _io_resp_pp_T_39; // @[Parameters.scala:629:89] wire _io_resp_pp_T_52 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_pp_T_48 = {1'h0, _io_resp_pp_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_49 = _io_resp_pp_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_50 = _io_resp_pp_T_49; // @[Parameters.scala:137:46] wire _io_resp_pp_T_51 = _io_resp_pp_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_54 = _io_resp_pp_T_52; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_54; // @[Mux.scala:30:73] assign _io_resp_pp_T_55 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_36 = {1'h0, _io_resp_al_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_37 = _io_resp_al_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_38 = _io_resp_al_T_37; // @[Parameters.scala:137:46] wire _io_resp_al_T_39 = _io_resp_al_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_40 = _io_resp_al_T_4 \| _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_41 = _io_resp_al_T_40 \| _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_42 = _io_resp_al_T_41 \| _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_43 = _io_resp_al_T_42 \| _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_44 = _io_resp_al_T_43 \| _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_45 = _io_resp_al_T_44 \| _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_45 \| _io_resp_al_T_39; // @[Parameters.scala:629:89] wire _io_resp_al_T_52 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_al_T_48 = {1'h0, _io_resp_al_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_49 = _io_resp_al_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_50 = _io_resp_al_T_49; // @[Parameters.scala:137:46] wire _io_resp_al_T_51 = _io_resp_al_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_54 = _io_resp_al_T_52; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_54; // @[Mux.scala:30:73] assign _io_resp_al_T_55 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_36 = {1'h0, _io_resp_aa_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_37 = _io_resp_aa_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_38 = _io_resp_aa_T_37; // @[Parameters.scala:137:46] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_40 = _io_resp_aa_T_4 \| _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_41 = _io_resp_aa_T_40 \| _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_42 = _io_resp_aa_T_41 \| _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_43 = _io_resp_aa_T_42 \| _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_44 = _io_resp_aa_T_43 \| _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 \| _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_45 \| _io_resp_aa_T_39; // @[Parameters.scala:629:89] wire _io_resp_aa_T_52 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_aa_T_48 = {1'h0, _io_resp_aa_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_49 = _io_resp_aa_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_50 = _io_resp_aa_T_49; // @[Parameters.scala:137:46] wire _io_resp_aa_T_51 = _io_resp_aa_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_54 = _io_resp_aa_T_52; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_54; // @[Mux.scala:30:73] assign _io_resp_aa_T_55 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 \| _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 \| _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 \| _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 \| _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_76 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'hFFFFC000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'hFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_60 = {1'h0, _io_resp_x_T_59}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_61 = _io_resp_x_T_60 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_62 = _io_resp_x_T_61; // @[Parameters.scala:137:46] wire _io_resp_x_T_63 = _io_resp_x_T_62 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_65 = {1'h0, _io_resp_x_T_64}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_66 = _io_resp_x_T_65 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_67 = _io_resp_x_T_66; // @[Parameters.scala:137:46] wire _io_resp_x_T_68 = _io_resp_x_T_67 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_69 = _io_resp_x_T_33 \| _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_70 = _io_resp_x_T_69 \| _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_71 = _io_resp_x_T_70 \| _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_72 = _io_resp_x_T_71 \| _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_73 = _io_resp_x_T_72 \| _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_74 = _io_resp_x_T_73 \| _io_resp_x_T_63; // @[Parameters.scala:629:89] wire _io_resp_x_T_75 = _io_resp_x_T_74 \| _io_resp_x_T_68; // @[Parameters.scala:629:89] wire _io_resp_x_T_78 = _io_resp_x_T_76; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_78; // @[Mux.scala:30:73] assign _io_resp_x_T_79 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_79; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'hFFFFA000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'hFFFF8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'hFFFEB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_31 = {1'h0, _io_resp_eff_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_32 = _io_resp_eff_T_31 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_33 = _io_resp_eff_T_32; // @[Parameters.scala:137:46] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_35 = _io_resp_eff_T_4 \| _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_36 = _io_resp_eff_T_35 \| _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_37 = _io_resp_eff_T_36 \| _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_38 = _io_resp_eff_T_37 \| _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 \| _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_40 = _io_resp_eff_T_39 \| _io_resp_eff_T_34; // @[Parameters.scala:629:89] wire _io_resp_eff_T_64 = _io_resp_eff_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_eff_T_42 = {1'h0, _io_resp_eff_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_44 = _io_resp_eff_T_43; // @[Parameters.scala:137:46] wire _io_resp_eff_T_45 = _io_resp_eff_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_47 = {1'h0, _io_resp_eff_T_46}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_49 = _io_resp_eff_T_48; // @[Parameters.scala:137:46] wire _io_resp_eff_T_50 = _io_resp_eff_T_49 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_52 = {1'h0, _io_resp_eff_T_51}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_54 = _io_resp_eff_T_53; // @[Parameters.scala:137:46] wire _io_resp_eff_T_55 = _io_resp_eff_T_54 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_57 = {1'h0, _io_resp_eff_T_56}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_58 = _io_resp_eff_T_57 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_59 = _io_resp_eff_T_58; // @[Parameters.scala:137:46] wire _io_resp_eff_T_60 = _io_resp_eff_T_59 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_61 = _io_resp_eff_T_45 \| _io_resp_eff_T_50; // @[Parameters.scala:629:89] wire _io_resp_eff_T_62 = _io_resp_eff_T_61 \| _io_resp_eff_T_55; // @[Parameters.scala:629:89] wire _io_resp_eff_T_63 = _io_resp_eff_T_62 \| _io_resp_eff_T_60; // @[Parameters.scala:629:89] wire _io_resp_eff_T_66 = _io_resp_eff_T_64; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_66; // @[Mux.scala:30:73] assign _io_resp_eff_T_67 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_67; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_117( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_132 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RegisterFile.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import freechips.rocketchip.util._ import saturn.common._ class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { val io = IO(new ArbiterIO(new VectorReadReq, n)) val arb = Module(new RRArbiter(new VectorReadReq, n)) io <> arb.io val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) //assert(PopCount(oldest_oh) <= 1.U) when (oldest_oh.orR) { io.chosen := VecInit(oldest_oh).asUInt io.out.valid := true.B io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) for (i <- 0 until n) { io.in(i).ready := oldest_oh(i) && io.out.ready } } } class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Vec(n, Flipped(new VectorReadIO)) val out = Vec(banks, new VectorReadIO) }) val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } for (i <- 0 until banks) { io.out(i).req <> arbs(i).io.out } val bankOffset = log2Ceil(banks) for (i <- 0 until n) { val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) for (j <- 0 until banks) { arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest } io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) } } class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val read = Vec(reads, Flipped(new VectorReadIO)) val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) val write = Input(Valid(new VectorWrite(dLen))) val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) }) val ll_write_valid = RegInit(false.B) val ll_write_bits = Reg(new VectorWrite(dLen)) val vrf = Mem(rows, Vec(dLen, Bool())) val v0_mask = Mem(maskRows, Vec(dLen, Bool())) for (read <- io.read) { read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) read.resp := DontCare when (read.req.valid) { read.resp := vrf.read(read.req.bits.eg).asUInt } } for (mask_read <- io.mask_read) { mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) mask_read.resp := DontCare when (mask_read.req.valid) { mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt } } val write = WireInit(io.write) io.ll_write.ready := false.B if (vParams.vrfHiccupBuffer) { when (!io.write.valid) { // drain hiccup buffer write.valid := ll_write_valid \|\| io.ll_write.valid write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) ll_write_valid := false.B when (io.ll_write.valid && ll_write_valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } .elsewhen (!ll_write_valid) { // fill hiccup buffer when (io.ll_write.valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } } else { when (!io.write.valid) { io.ll_write.ready := true.B write.valid := io.ll_write.valid write.bits := io.ll_write.bits } } when (write.valid) { vrf.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) when (write.bits.eg < maskRows.U) { v0_mask.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) } } } class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val nBanks = vParams.vrfBanking // Support 1, 2, and 4 banks for the VRF require(nBanks == 1 \|\| nBanks == 2 \|\| nBanks == 4) val io = IO(new Bundle { val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) }) val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } reads.zipWithIndex.foreach { case (rc, i) => val xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.read(i) <> xbar.io.out(j) } xbar.io.in <> io.read(i) } maskReads.zipWithIndex.foreach { case (rc, i) => val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.mask_read(i) <> mask_xbar.io.out(j) } mask_xbar.io.in <> io.mask_read(i) } io.ll_writes.foreach(_.ready := false.B) vrf.zipWithIndex.foreach { case (rf, i) => val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) val bank_write_valid = bank_match.orR rf.io.write.valid := bank_write_valid rf.io.write.bits.data := bank_write_data rf.io.write.bits.mask := bank_write_mask rf.io.write.bits.eg := bank_write_eg >> vrfBankBits when (bank_write_valid) { PopCount(bank_match) === 1.U } val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) rf.io.ll_write <> ll_arb.io.out io.ll_writes.zipWithIndex.foreach { case (w, j) => ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits ll_arb.io.in(j).bits.data := w.bits.data ll_arb.io.in(j).bits.mask := w.bits.mask when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { w.ready := true.B } } } }	module RegisterFile( // @[RegisterFile.scala:120:7] input clock, // @[RegisterFile.scala:120:7] input reset, // @[RegisterFile.scala:120:7] output io_read_2_0_req_ready, // @[RegisterFile.scala:126:14] input io_read_2_0_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_2_0_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_2_0_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_2_0_resp, // @[RegisterFile.scala:126:14] output io_read_2_1_req_ready, // @[RegisterFile.scala:126:14] input io_read_2_1_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_2_1_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_2_1_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_2_1_resp, // @[RegisterFile.scala:126:14] output io_read_2_2_req_ready, // @[RegisterFile.scala:126:14] input io_read_2_2_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_2_2_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_2_2_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_2_2_resp, // @[RegisterFile.scala:126:14] output io_read_1_0_req_ready, // @[RegisterFile.scala:126:14] input io_read_1_0_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_1_0_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_1_0_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_1_0_resp, // @[RegisterFile.scala:126:14] output io_read_1_1_req_ready, // @[RegisterFile.scala:126:14] input io_read_1_1_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_1_1_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_1_1_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_1_1_resp, // @[RegisterFile.scala:126:14] output io_read_0_0_req_ready, // @[RegisterFile.scala:126:14] input io_read_0_0_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_0_0_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_0_0_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_0_0_resp, // @[RegisterFile.scala:126:14] output io_read_0_1_req_ready, // @[RegisterFile.scala:126:14] input io_read_0_1_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_0_1_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_0_1_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_0_1_resp, // @[RegisterFile.scala:126:14] output io_read_0_2_req_ready, // @[RegisterFile.scala:126:14] input io_read_0_2_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_0_2_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_0_2_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_0_2_resp, // @[RegisterFile.scala:126:14] output io_read_0_3_req_ready, // @[RegisterFile.scala:126:14] input io_read_0_3_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_0_3_req_bits_eg, // @[RegisterFile.scala:126:14] output [127:0] io_read_0_3_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_0_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_0_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_0_req_bits_eg, // @[RegisterFile.scala:126:14] input io_mask_read_0_0_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_0_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_1_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_1_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_1_req_bits_eg, // @[RegisterFile.scala:126:14] input io_mask_read_0_1_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_1_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_2_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_2_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_2_req_bits_eg, // @[RegisterFile.scala:126:14] input io_mask_read_0_2_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_2_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_3_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_3_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_3_req_bits_eg, // @[RegisterFile.scala:126:14] input io_mask_read_0_3_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_3_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_4_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_4_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_4_req_bits_eg, // @[RegisterFile.scala:126:14] input io_mask_read_0_4_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_4_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_5_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_5_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_5_req_bits_eg, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_5_resp, // @[RegisterFile.scala:126:14] input io_pipe_writes_0_valid, // @[RegisterFile.scala:126:14] input [5:0] io_pipe_writes_0_bits_eg, // @[RegisterFile.scala:126:14] input [127:0] io_pipe_writes_0_bits_data, // @[RegisterFile.scala:126:14] input [127:0] io_pipe_writes_0_bits_mask, // @[RegisterFile.scala:126:14] input io_pipe_writes_1_valid, // @[RegisterFile.scala:126:14] input [5:0] io_pipe_writes_1_bits_eg, // @[RegisterFile.scala:126:14] input [127:0] io_pipe_writes_1_bits_data, // @[RegisterFile.scala:126:14] input [127:0] io_pipe_writes_1_bits_mask, // @[RegisterFile.scala:126:14] output io_ll_writes_0_ready, // @[RegisterFile.scala:126:14] input io_ll_writes_0_valid, // @[RegisterFile.scala:126:14] input [5:0] io_ll_writes_0_bits_eg, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_0_bits_data, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_0_bits_mask, // @[RegisterFile.scala:126:14] input io_ll_writes_1_valid, // @[RegisterFile.scala:126:14] input [5:0] io_ll_writes_1_bits_eg, // @[RegisterFile.scala:126:14] output io_ll_writes_2_ready, // @[RegisterFile.scala:126:14] input io_ll_writes_2_valid, // @[RegisterFile.scala:126:14] input [5:0] io_ll_writes_2_bits_eg, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_2_bits_data, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_2_bits_mask, // @[RegisterFile.scala:126:14] output io_ll_writes_3_ready, // @[RegisterFile.scala:126:14] input io_ll_writes_3_valid, // @[RegisterFile.scala:126:14] input [5:0] io_ll_writes_3_bits_eg, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_3_bits_data, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_3_bits_mask // @[RegisterFile.scala:126:14] ); wire _ll_arb_3_io_in_0_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_3_io_in_2_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_3_io_in_3_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_3_io_out_valid; // @[RegisterFile.scala:167:24] wire [5:0] _ll_arb_3_io_out_bits_eg; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_3_io_out_bits_data; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_3_io_out_bits_mask; // @[RegisterFile.scala:167:24] wire _ll_arb_2_io_in_0_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_2_io_in_2_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_2_io_in_3_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_2_io_out_valid; // @[RegisterFile.scala:167:24] wire [5:0] _ll_arb_2_io_out_bits_eg; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_2_io_out_bits_data; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_2_io_out_bits_mask; // @[RegisterFile.scala:167:24] wire _ll_arb_1_io_in_0_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_1_io_in_2_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_1_io_in_3_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_1_io_out_valid; // @[RegisterFile.scala:167:24] wire [5:0] _ll_arb_1_io_out_bits_eg; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_1_io_out_bits_data; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_1_io_out_bits_mask; // @[RegisterFile.scala:167:24] wire _ll_arb_io_in_0_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_io_in_2_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_io_in_3_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_io_out_valid; // @[RegisterFile.scala:167:24] wire [5:0] _ll_arb_io_out_bits_eg; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_io_out_bits_data; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_io_out_bits_mask; // @[RegisterFile.scala:167:24] wire [5:0] _mask_xbar_io_out_0_req_bits_eg; // @[RegisterFile.scala:145:27] wire [5:0] _mask_xbar_io_out_1_req_bits_eg; // @[RegisterFile.scala:145:27] wire [5:0] _mask_xbar_io_out_2_req_bits_eg; // @[RegisterFile.scala:145:27] wire [5:0] _mask_xbar_io_out_3_req_bits_eg; // @[RegisterFile.scala:145:27] wire _xbar_2_io_out_0_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_2_io_out_0_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_2_io_out_1_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_2_io_out_1_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_2_io_out_2_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_2_io_out_2_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_2_io_out_3_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_2_io_out_3_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_1_io_out_0_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_1_io_out_0_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_1_io_out_1_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_1_io_out_1_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_1_io_out_2_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_1_io_out_2_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_1_io_out_3_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_1_io_out_3_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_io_out_0_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_io_out_0_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_io_out_1_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_io_out_1_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_io_out_2_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_io_out_2_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_io_out_3_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_io_out_3_req_bits_eg; // @[RegisterFile.scala:137:22] wire _vrf_3_io_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_3_io_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_3_io_read_1_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_3_io_read_1_resp; // @[RegisterFile.scala:134:38] wire _vrf_3_io_read_2_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_3_io_read_2_resp; // @[RegisterFile.scala:134:38] wire _vrf_3_io_mask_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_3_io_mask_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_3_io_ll_write_ready; // @[RegisterFile.scala:134:38] wire _vrf_2_io_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_2_io_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_2_io_read_1_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_2_io_read_1_resp; // @[RegisterFile.scala:134:38] wire _vrf_2_io_read_2_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_2_io_read_2_resp; // @[RegisterFile.scala:134:38] wire _vrf_2_io_mask_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_2_io_mask_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_2_io_ll_write_ready; // @[RegisterFile.scala:134:38] wire _vrf_1_io_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_1_io_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_1_io_read_1_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_1_io_read_1_resp; // @[RegisterFile.scala:134:38] wire _vrf_1_io_read_2_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_1_io_read_2_resp; // @[RegisterFile.scala:134:38] wire _vrf_1_io_mask_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_1_io_mask_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_1_io_ll_write_ready; // @[RegisterFile.scala:134:38] wire _vrf_0_io_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_0_io_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_0_io_read_1_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_0_io_read_1_resp; // @[RegisterFile.scala:134:38] wire _vrf_0_io_read_2_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_0_io_read_2_resp; // @[RegisterFile.scala:134:38] wire _vrf_0_io_mask_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_0_io_mask_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_0_io_ll_write_ready; // @[RegisterFile.scala:134:38] wire bank_match_0 = io_pipe_writes_0_bits_eg[1:0] == 2'h0 & io_pipe_writes_0_valid; // @[Bundles.scala:112:49] wire bank_match_1 = io_pipe_writes_1_bits_eg[1:0] == 2'h0 & io_pipe_writes_1_valid; // @[Bundles.scala:112:49] wire [5:0] ll_arb_io_in_0_bits_eg = {2'h0, io_ll_writes_0_bits_eg[5:2]}; // @[RegisterFile.scala:155:63, :172:{33,46}] wire [5:0] ll_arb_io_in_1_bits_eg = {2'h0, io_ll_writes_1_bits_eg[5:2]}; // @[RegisterFile.scala:155:63, :172:{33,46}] wire [5:0] ll_arb_io_in_2_bits_eg = {2'h0, io_ll_writes_2_bits_eg[5:2]}; // @[RegisterFile.scala:155:63, :172:{33,46}] wire [5:0] ll_arb_io_in_3_bits_eg = {2'h0, io_ll_writes_3_bits_eg[5:2]}; // @[RegisterFile.scala:155:63, :172:{33,46}] wire bank_match_0_1 = io_pipe_writes_0_bits_eg[1:0] == 2'h1 & io_pipe_writes_0_valid; // @[Bundles.scala:112:49] wire bank_match_1_1 = io_pipe_writes_1_bits_eg[1:0] == 2'h1 & io_pipe_writes_1_valid; // @[Bundles.scala:112:49] wire bank_match_0_2 = io_pipe_writes_0_bits_eg[1:0] == 2'h2 & io_pipe_writes_0_valid; // @[Bundles.scala:112:49] wire bank_match_1_2 = io_pipe_writes_1_bits_eg[1:0] == 2'h2 & io_pipe_writes_1_valid; // @[Bundles.scala:112:49] wire bank_match_0_3 = (&(io_pipe_writes_0_bits_eg[1:0])) & io_pipe_writes_0_valid; // @[Bundles.scala:112:49] wire bank_match_1_3 = (&(io_pipe_writes_1_bits_eg[1:0])) & io_pipe_writes_1_valid; // @[Bundles.scala:112:49] RegisterFileBank vrf_0 ( // @[RegisterFile.scala:134:38] .clock (clock), .reset (reset), .io_read_0_req_ready (_vrf_0_io_read_0_req_ready), .io_read_0_req_valid (_xbar_io_out_0_req_valid), // @[RegisterFile.scala:137:22] .io_read_0_req_bits_eg (_xbar_io_out_0_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_0_resp (_vrf_0_io_read_0_resp), .io_read_1_req_ready (_vrf_0_io_read_1_req_ready), .io_read_1_req_valid (_xbar_1_io_out_0_req_valid), // @[RegisterFile.scala:137:22] .io_read_1_req_bits_eg (_xbar_1_io_out_0_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_1_resp (_vrf_0_io_read_1_resp), .io_read_2_req_ready (_vrf_0_io_read_2_req_ready), .io_read_2_req_valid (_xbar_2_io_out_0_req_valid), // @[RegisterFile.scala:137:22] .io_read_2_req_bits_eg (_xbar_2_io_out_0_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_2_resp (_vrf_0_io_read_2_resp), .io_mask_read_0_req_ready (_vrf_0_io_mask_read_0_req_ready), .io_mask_read_0_req_bits_eg (_mask_xbar_io_out_0_req_bits_eg), // @[RegisterFile.scala:145:27] .io_mask_read_0_resp (_vrf_0_io_mask_read_0_resp), .io_write_valid (bank_match_0 \| bank_match_1), // @[RegisterFile.scala:155:72] .io_write_bits_eg ({2'h0, (bank_match_0 ? io_pipe_writes_0_bits_eg[5:2] : 4'h0) \| (bank_match_1 ? io_pipe_writes_1_bits_eg[5:2] : 4'h0)}), // @[Mux.scala:30:73] .io_write_bits_data ((bank_match_0 ? io_pipe_writes_0_bits_data : 128'h0) \| (bank_match_1 ? io_pipe_writes_1_bits_data : 128'h0)), // @[Mux.scala:30:73] .io_write_bits_mask ((bank_match_0 ? io_pipe_writes_0_bits_mask : 128'h0) \| (bank_match_1 ? io_pipe_writes_1_bits_mask : 128'h0)), // @[Mux.scala:30:73] .io_ll_write_ready (_vrf_0_io_ll_write_ready), .io_ll_write_valid (_ll_arb_io_out_valid), // @[RegisterFile.scala:167:24] .io_ll_write_bits_eg (_ll_arb_io_out_bits_eg), // @[RegisterFile.scala:167:24] .io_ll_write_bits_data (_ll_arb_io_out_bits_data), // @[RegisterFile.scala:167:24] .io_ll_write_bits_mask (_ll_arb_io_out_bits_mask) // @[RegisterFile.scala:167:24] ); // @[RegisterFile.scala:134:38] RegisterFileBank vrf_1 ( // @[RegisterFile.scala:134:38] .clock (clock), .reset (reset), .io_read_0_req_ready (_vrf_1_io_read_0_req_ready), .io_read_0_req_valid (_xbar_io_out_1_req_valid), // @[RegisterFile.scala:137:22] .io_read_0_req_bits_eg (_xbar_io_out_1_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_0_resp (_vrf_1_io_read_0_resp), .io_read_1_req_ready (_vrf_1_io_read_1_req_ready), .io_read_1_req_valid (_xbar_1_io_out_1_req_valid), // @[RegisterFile.scala:137:22] .io_read_1_req_bits_eg (_xbar_1_io_out_1_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_1_resp (_vrf_1_io_read_1_resp), .io_read_2_req_ready (_vrf_1_io_read_2_req_ready), .io_read_2_req_valid (_xbar_2_io_out_1_req_valid), // @[RegisterFile.scala:137:22] .io_read_2_req_bits_eg (_xbar_2_io_out_1_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_2_resp (_vrf_1_io_read_2_resp), .io_mask_read_0_req_ready (_vrf_1_io_mask_read_0_req_ready), .io_mask_read_0_req_bits_eg (_mask_xbar_io_out_1_req_bits_eg), // @[RegisterFile.scala:145:27] .io_mask_read_0_resp (_vrf_1_io_mask_read_0_resp), .io_write_valid (bank_match_0_1 \| bank_match_1_1), // @[RegisterFile.scala:155:72] .io_write_bits_eg ({2'h0, (bank_match_0_1 ? io_pipe_writes_0_bits_eg[5:2] : 4'h0) \| (bank_match_1_1 ? io_pipe_writes_1_bits_eg[5:2] : 4'h0)}), // @[Mux.scala:30:73] .io_write_bits_data ((bank_match_0_1 ? io_pipe_writes_0_bits_data : 128'h0) \| (bank_match_1_1 ? io_pipe_writes_1_bits_data : 128'h0)), // @[Mux.scala:30:73] .io_write_bits_mask ((bank_match_0_1 ? io_pipe_writes_0_bits_mask : 128'h0) \| (bank_match_1_1 ? io_pipe_writes_1_bits_mask : 128'h0)), // @[Mux.scala:30:73] .io_ll_write_ready (_vrf_1_io_ll_write_ready), .io_ll_write_valid (_ll_arb_1_io_out_valid), // @[RegisterFile.scala:167:24] .io_ll_write_bits_eg (_ll_arb_1_io_out_bits_eg), // @[RegisterFile.scala:167:24] .io_ll_write_bits_data (_ll_arb_1_io_out_bits_data), // @[RegisterFile.scala:167:24] .io_ll_write_bits_mask (_ll_arb_1_io_out_bits_mask) // @[RegisterFile.scala:167:24] ); // @[RegisterFile.scala:134:38] RegisterFileBank vrf_2 ( // @[RegisterFile.scala:134:38] .clock (clock), .reset (reset), .io_read_0_req_ready (_vrf_2_io_read_0_req_ready), .io_read_0_req_valid (_xbar_io_out_2_req_valid), // @[RegisterFile.scala:137:22] .io_read_0_req_bits_eg (_xbar_io_out_2_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_0_resp (_vrf_2_io_read_0_resp), .io_read_1_req_ready (_vrf_2_io_read_1_req_ready), .io_read_1_req_valid (_xbar_1_io_out_2_req_valid), // @[RegisterFile.scala:137:22] .io_read_1_req_bits_eg (_xbar_1_io_out_2_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_1_resp (_vrf_2_io_read_1_resp), .io_read_2_req_ready (_vrf_2_io_read_2_req_ready), .io_read_2_req_valid (_xbar_2_io_out_2_req_valid), // @[RegisterFile.scala:137:22] .io_read_2_req_bits_eg (_xbar_2_io_out_2_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_2_resp (_vrf_2_io_read_2_resp), .io_mask_read_0_req_ready (_vrf_2_io_mask_read_0_req_ready), .io_mask_read_0_req_bits_eg (_mask_xbar_io_out_2_req_bits_eg), // @[RegisterFile.scala:145:27] .io_mask_read_0_resp (_vrf_2_io_mask_read_0_resp), .io_write_valid (bank_match_0_2 \| bank_match_1_2), // @[RegisterFile.scala:155:72] .io_write_bits_eg ({2'h0, (bank_match_0_2 ? io_pipe_writes_0_bits_eg[5:2] : 4'h0) \| (bank_match_1_2 ? io_pipe_writes_1_bits_eg[5:2] : 4'h0)}), // @[Mux.scala:30:73] .io_write_bits_data ((bank_match_0_2 ? io_pipe_writes_0_bits_data : 128'h0) \| (bank_match_1_2 ? io_pipe_writes_1_bits_data : 128'h0)), // @[Mux.scala:30:73] .io_write_bits_mask ((bank_match_0_2 ? io_pipe_writes_0_bits_mask : 128'h0) \| (bank_match_1_2 ? io_pipe_writes_1_bits_mask : 128'h0)), // @[Mux.scala:30:73] .io_ll_write_ready (_vrf_2_io_ll_write_ready), .io_ll_write_valid (_ll_arb_2_io_out_valid), // @[RegisterFile.scala:167:24] .io_ll_write_bits_eg (_ll_arb_2_io_out_bits_eg), // @[RegisterFile.scala:167:24] .io_ll_write_bits_data (_ll_arb_2_io_out_bits_data), // @[RegisterFile.scala:167:24] .io_ll_write_bits_mask (_ll_arb_2_io_out_bits_mask) // @[RegisterFile.scala:167:24] ); // @[RegisterFile.scala:134:38] RegisterFileBank vrf_3 ( // @[RegisterFile.scala:134:38] .clock (clock), .reset (reset), .io_read_0_req_ready (_vrf_3_io_read_0_req_ready), .io_read_0_req_valid (_xbar_io_out_3_req_valid), // @[RegisterFile.scala:137:22] .io_read_0_req_bits_eg (_xbar_io_out_3_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_0_resp (_vrf_3_io_read_0_resp), .io_read_1_req_ready (_vrf_3_io_read_1_req_ready), .io_read_1_req_valid (_xbar_1_io_out_3_req_valid), // @[RegisterFile.scala:137:22] .io_read_1_req_bits_eg (_xbar_1_io_out_3_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_1_resp (_vrf_3_io_read_1_resp), .io_read_2_req_ready (_vrf_3_io_read_2_req_ready), .io_read_2_req_valid (_xbar_2_io_out_3_req_valid), // @[RegisterFile.scala:137:22] .io_read_2_req_bits_eg (_xbar_2_io_out_3_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_2_resp (_vrf_3_io_read_2_resp), .io_mask_read_0_req_ready (_vrf_3_io_mask_read_0_req_ready), .io_mask_read_0_req_bits_eg (_mask_xbar_io_out_3_req_bits_eg), // @[RegisterFile.scala:145:27] .io_mask_read_0_resp (_vrf_3_io_mask_read_0_resp), .io_write_valid (bank_match_0_3 \| bank_match_1_3), // @[RegisterFile.scala:155:72] .io_write_bits_eg ({2'h0, (bank_match_0_3 ? io_pipe_writes_0_bits_eg[5:2] : 4'h0) \| (bank_match_1_3 ? io_pipe_writes_1_bits_eg[5:2] : 4'h0)}), // @[Mux.scala:30:73] .io_write_bits_data ((bank_match_0_3 ? io_pipe_writes_0_bits_data : 128'h0) \| (bank_match_1_3 ? io_pipe_writes_1_bits_data : 128'h0)), // @[Mux.scala:30:73] .io_write_bits_mask ((bank_match_0_3 ? io_pipe_writes_0_bits_mask : 128'h0) \| (bank_match_1_3 ? io_pipe_writes_1_bits_mask : 128'h0)), // @[Mux.scala:30:73] .io_ll_write_ready (_vrf_3_io_ll_write_ready), .io_ll_write_valid (_ll_arb_3_io_out_valid), // @[RegisterFile.scala:167:24] .io_ll_write_bits_eg (_ll_arb_3_io_out_bits_eg), // @[RegisterFile.scala:167:24] .io_ll_write_bits_data (_ll_arb_3_io_out_bits_data), // @[RegisterFile.scala:167:24] .io_ll_write_bits_mask (_ll_arb_3_io_out_bits_mask) // @[RegisterFile.scala:167:24] ); // @[RegisterFile.scala:134:38] RegisterReadXbar xbar ( // @[RegisterFile.scala:137:22] .clock (clock), .io_in_0_req_ready (io_read_0_0_req_ready), .io_in_0_req_valid (io_read_0_0_req_valid), .io_in_0_req_bits_eg (io_read_0_0_req_bits_eg), .io_in_0_req_bits_oldest (io_read_0_0_req_bits_oldest), .io_in_0_resp (io_read_0_0_resp), .io_in_1_req_ready (io_read_0_1_req_ready), .io_in_1_req_valid (io_read_0_1_req_valid), .io_in_1_req_bits_eg (io_read_0_1_req_bits_eg), .io_in_1_req_bits_oldest (io_read_0_1_req_bits_oldest), .io_in_1_resp (io_read_0_1_resp), .io_in_2_req_ready (io_read_0_2_req_ready), .io_in_2_req_valid (io_read_0_2_req_valid), .io_in_2_req_bits_eg (io_read_0_2_req_bits_eg), .io_in_2_req_bits_oldest (io_read_0_2_req_bits_oldest), .io_in_2_resp (io_read_0_2_resp), .io_in_3_req_ready (io_read_0_3_req_ready), .io_in_3_req_valid (io_read_0_3_req_valid), .io_in_3_req_bits_eg (io_read_0_3_req_bits_eg), .io_in_3_resp (io_read_0_3_resp), .io_out_0_req_ready (_vrf_0_io_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_0_req_valid (_xbar_io_out_0_req_valid), .io_out_0_req_bits_eg (_xbar_io_out_0_req_bits_eg), .io_out_0_resp (_vrf_0_io_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_1_req_ready (_vrf_1_io_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_1_req_valid (_xbar_io_out_1_req_valid), .io_out_1_req_bits_eg (_xbar_io_out_1_req_bits_eg), .io_out_1_resp (_vrf_1_io_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_2_req_ready (_vrf_2_io_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_2_req_valid (_xbar_io_out_2_req_valid), .io_out_2_req_bits_eg (_xbar_io_out_2_req_bits_eg), .io_out_2_resp (_vrf_2_io_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_3_req_ready (_vrf_3_io_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_3_req_valid (_xbar_io_out_3_req_valid), .io_out_3_req_bits_eg (_xbar_io_out_3_req_bits_eg), .io_out_3_resp (_vrf_3_io_read_0_resp) // @[RegisterFile.scala:134:38] ); // @[RegisterFile.scala:137:22] RegisterReadXbar_1 xbar_1 ( // @[RegisterFile.scala:137:22] .clock (clock), .io_in_0_req_ready (io_read_1_0_req_ready), .io_in_0_req_valid (io_read_1_0_req_valid), .io_in_0_req_bits_eg (io_read_1_0_req_bits_eg), .io_in_0_req_bits_oldest (io_read_1_0_req_bits_oldest), .io_in_0_resp (io_read_1_0_resp), .io_in_1_req_ready (io_read_1_1_req_ready), .io_in_1_req_valid (io_read_1_1_req_valid), .io_in_1_req_bits_eg (io_read_1_1_req_bits_eg), .io_in_1_req_bits_oldest (io_read_1_1_req_bits_oldest), .io_in_1_resp (io_read_1_1_resp), .io_out_0_req_ready (_vrf_0_io_read_1_req_ready), // @[RegisterFile.scala:134:38] .io_out_0_req_valid (_xbar_1_io_out_0_req_valid), .io_out_0_req_bits_eg (_xbar_1_io_out_0_req_bits_eg), .io_out_0_resp (_vrf_0_io_read_1_resp), // @[RegisterFile.scala:134:38] .io_out_1_req_ready (_vrf_1_io_read_1_req_ready), // @[RegisterFile.scala:134:38] .io_out_1_req_valid (_xbar_1_io_out_1_req_valid), .io_out_1_req_bits_eg (_xbar_1_io_out_1_req_bits_eg), .io_out_1_resp (_vrf_1_io_read_1_resp), // @[RegisterFile.scala:134:38] .io_out_2_req_ready (_vrf_2_io_read_1_req_ready), // @[RegisterFile.scala:134:38] .io_out_2_req_valid (_xbar_1_io_out_2_req_valid), .io_out_2_req_bits_eg (_xbar_1_io_out_2_req_bits_eg), .io_out_2_resp (_vrf_2_io_read_1_resp), // @[RegisterFile.scala:134:38] .io_out_3_req_ready (_vrf_3_io_read_1_req_ready), // @[RegisterFile.scala:134:38] .io_out_3_req_valid (_xbar_1_io_out_3_req_valid), .io_out_3_req_bits_eg (_xbar_1_io_out_3_req_bits_eg), .io_out_3_resp (_vrf_3_io_read_1_resp) // @[RegisterFile.scala:134:38] ); // @[RegisterFile.scala:137:22] RegisterReadXbar_2 xbar_2 ( // @[RegisterFile.scala:137:22] .clock (clock), .io_in_0_req_ready (io_read_2_0_req_ready), .io_in_0_req_valid (io_read_2_0_req_valid), .io_in_0_req_bits_eg (io_read_2_0_req_bits_eg), .io_in_0_req_bits_oldest (io_read_2_0_req_bits_oldest), .io_in_0_resp (io_read_2_0_resp), .io_in_1_req_ready (io_read_2_1_req_ready), .io_in_1_req_valid (io_read_2_1_req_valid), .io_in_1_req_bits_eg (io_read_2_1_req_bits_eg), .io_in_1_req_bits_oldest (io_read_2_1_req_bits_oldest), .io_in_1_resp (io_read_2_1_resp), .io_in_2_req_ready (io_read_2_2_req_ready), .io_in_2_req_valid (io_read_2_2_req_valid), .io_in_2_req_bits_eg (io_read_2_2_req_bits_eg), .io_in_2_req_bits_oldest (io_read_2_2_req_bits_oldest), .io_in_2_resp (io_read_2_2_resp), .io_out_0_req_ready (_vrf_0_io_read_2_req_ready), // @[RegisterFile.scala:134:38] .io_out_0_req_valid (_xbar_2_io_out_0_req_valid), .io_out_0_req_bits_eg (_xbar_2_io_out_0_req_bits_eg), .io_out_0_resp (_vrf_0_io_read_2_resp), // @[RegisterFile.scala:134:38] .io_out_1_req_ready (_vrf_1_io_read_2_req_ready), // @[RegisterFile.scala:134:38] .io_out_1_req_valid (_xbar_2_io_out_1_req_valid), .io_out_1_req_bits_eg (_xbar_2_io_out_1_req_bits_eg), .io_out_1_resp (_vrf_1_io_read_2_resp), // @[RegisterFile.scala:134:38] .io_out_2_req_ready (_vrf_2_io_read_2_req_ready), // @[RegisterFile.scala:134:38] .io_out_2_req_valid (_xbar_2_io_out_2_req_valid), .io_out_2_req_bits_eg (_xbar_2_io_out_2_req_bits_eg), .io_out_2_resp (_vrf_2_io_read_2_resp), // @[RegisterFile.scala:134:38] .io_out_3_req_ready (_vrf_3_io_read_2_req_ready), // @[RegisterFile.scala:134:38] .io_out_3_req_valid (_xbar_2_io_out_3_req_valid), .io_out_3_req_bits_eg (_xbar_2_io_out_3_req_bits_eg), .io_out_3_resp (_vrf_3_io_read_2_resp) // @[RegisterFile.scala:134:38] ); // @[RegisterFile.scala:137:22] RegisterReadXbar_3 mask_xbar ( // @[RegisterFile.scala:145:27] .clock (clock), .io_in_0_req_ready (io_mask_read_0_0_req_ready), .io_in_0_req_valid (io_mask_read_0_0_req_valid), .io_in_0_req_bits_eg (io_mask_read_0_0_req_bits_eg), .io_in_0_req_bits_oldest (io_mask_read_0_0_req_bits_oldest), .io_in_0_resp (io_mask_read_0_0_resp), .io_in_1_req_ready (io_mask_read_0_1_req_ready), .io_in_1_req_valid (io_mask_read_0_1_req_valid), .io_in_1_req_bits_eg (io_mask_read_0_1_req_bits_eg), .io_in_1_req_bits_oldest (io_mask_read_0_1_req_bits_oldest), .io_in_1_resp (io_mask_read_0_1_resp), .io_in_2_req_ready (io_mask_read_0_2_req_ready), .io_in_2_req_valid (io_mask_read_0_2_req_valid), .io_in_2_req_bits_eg (io_mask_read_0_2_req_bits_eg), .io_in_2_req_bits_oldest (io_mask_read_0_2_req_bits_oldest), .io_in_2_resp (io_mask_read_0_2_resp), .io_in_3_req_ready (io_mask_read_0_3_req_ready), .io_in_3_req_valid (io_mask_read_0_3_req_valid), .io_in_3_req_bits_eg (io_mask_read_0_3_req_bits_eg), .io_in_3_req_bits_oldest (io_mask_read_0_3_req_bits_oldest), .io_in_3_resp (io_mask_read_0_3_resp), .io_in_4_req_ready (io_mask_read_0_4_req_ready), .io_in_4_req_valid (io_mask_read_0_4_req_valid), .io_in_4_req_bits_eg (io_mask_read_0_4_req_bits_eg), .io_in_4_req_bits_oldest (io_mask_read_0_4_req_bits_oldest), .io_in_4_resp (io_mask_read_0_4_resp), .io_in_5_req_ready (io_mask_read_0_5_req_ready), .io_in_5_req_valid (io_mask_read_0_5_req_valid), .io_in_5_req_bits_eg (io_mask_read_0_5_req_bits_eg), .io_in_5_resp (io_mask_read_0_5_resp), .io_out_0_req_ready (_vrf_0_io_mask_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_0_req_bits_eg (_mask_xbar_io_out_0_req_bits_eg), .io_out_0_resp (_vrf_0_io_mask_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_1_req_ready (_vrf_1_io_mask_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_1_req_bits_eg (_mask_xbar_io_out_1_req_bits_eg), .io_out_1_resp (_vrf_1_io_mask_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_2_req_ready (_vrf_2_io_mask_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_2_req_bits_eg (_mask_xbar_io_out_2_req_bits_eg), .io_out_2_resp (_vrf_2_io_mask_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_3_req_ready (_vrf_3_io_mask_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_3_req_bits_eg (_mask_xbar_io_out_3_req_bits_eg), .io_out_3_resp (_vrf_3_io_mask_read_0_resp) // @[RegisterFile.scala:134:38] ); // @[RegisterFile.scala:145:27] Arbiter4_VectorWrite ll_arb ( // @[RegisterFile.scala:167:24] .io_in_0_ready (_ll_arb_io_in_0_ready), .io_in_0_valid (io_ll_writes_0_valid & ~(\|(io_ll_writes_0_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_0_bits_eg (ll_arb_io_in_0_bits_eg), // @[RegisterFile.scala:172:33] .io_in_0_bits_data (io_ll_writes_0_bits_data), .io_in_0_bits_mask (io_ll_writes_0_bits_mask), .io_in_1_valid (io_ll_writes_1_valid & io_ll_writes_1_bits_eg[1:0] == 2'h0), // @[Bundles.scala:112:49] .io_in_1_bits_eg (ll_arb_io_in_1_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_ready (_ll_arb_io_in_2_ready), .io_in_2_valid (io_ll_writes_2_valid & ~(\|(io_ll_writes_2_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_2_bits_eg (ll_arb_io_in_2_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_bits_data (io_ll_writes_2_bits_data), .io_in_2_bits_mask (io_ll_writes_2_bits_mask), .io_in_3_ready (_ll_arb_io_in_3_ready), .io_in_3_valid (io_ll_writes_3_valid & ~(\|(io_ll_writes_3_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_3_bits_eg (ll_arb_io_in_3_bits_eg), // @[RegisterFile.scala:172:33] .io_in_3_bits_data (io_ll_writes_3_bits_data), .io_in_3_bits_mask (io_ll_writes_3_bits_mask), .io_out_ready (_vrf_0_io_ll_write_ready), // @[RegisterFile.scala:134:38] .io_out_valid (_ll_arb_io_out_valid), .io_out_bits_eg (_ll_arb_io_out_bits_eg), .io_out_bits_data (_ll_arb_io_out_bits_data), .io_out_bits_mask (_ll_arb_io_out_bits_mask) ); // @[RegisterFile.scala:167:24] Arbiter4_VectorWrite ll_arb_1 ( // @[RegisterFile.scala:167:24] .io_in_0_ready (_ll_arb_1_io_in_0_ready), .io_in_0_valid (io_ll_writes_0_valid & io_ll_writes_0_bits_eg[1:0] == 2'h1), // @[Bundles.scala:112:49] .io_in_0_bits_eg (ll_arb_io_in_0_bits_eg), // @[RegisterFile.scala:172:33] .io_in_0_bits_data (io_ll_writes_0_bits_data), .io_in_0_bits_mask (io_ll_writes_0_bits_mask), .io_in_1_valid (io_ll_writes_1_valid & io_ll_writes_1_bits_eg[1:0] == 2'h1), // @[Bundles.scala:112:49] .io_in_1_bits_eg (ll_arb_io_in_1_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_ready (_ll_arb_1_io_in_2_ready), .io_in_2_valid (io_ll_writes_2_valid & io_ll_writes_2_bits_eg[1:0] == 2'h1), // @[Bundles.scala:112:49] .io_in_2_bits_eg (ll_arb_io_in_2_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_bits_data (io_ll_writes_2_bits_data), .io_in_2_bits_mask (io_ll_writes_2_bits_mask), .io_in_3_ready (_ll_arb_1_io_in_3_ready), .io_in_3_valid (io_ll_writes_3_valid & io_ll_writes_3_bits_eg[1:0] == 2'h1), // @[Bundles.scala:112:49] .io_in_3_bits_eg (ll_arb_io_in_3_bits_eg), // @[RegisterFile.scala:172:33] .io_in_3_bits_data (io_ll_writes_3_bits_data), .io_in_3_bits_mask (io_ll_writes_3_bits_mask), .io_out_ready (_vrf_1_io_ll_write_ready), // @[RegisterFile.scala:134:38] .io_out_valid (_ll_arb_1_io_out_valid), .io_out_bits_eg (_ll_arb_1_io_out_bits_eg), .io_out_bits_data (_ll_arb_1_io_out_bits_data), .io_out_bits_mask (_ll_arb_1_io_out_bits_mask) ); // @[RegisterFile.scala:167:24] Arbiter4_VectorWrite ll_arb_2 ( // @[RegisterFile.scala:167:24] .io_in_0_ready (_ll_arb_2_io_in_0_ready), .io_in_0_valid (io_ll_writes_0_valid & io_ll_writes_0_bits_eg[1:0] == 2'h2), // @[Bundles.scala:112:49] .io_in_0_bits_eg (ll_arb_io_in_0_bits_eg), // @[RegisterFile.scala:172:33] .io_in_0_bits_data (io_ll_writes_0_bits_data), .io_in_0_bits_mask (io_ll_writes_0_bits_mask), .io_in_1_valid (io_ll_writes_1_valid & io_ll_writes_1_bits_eg[1:0] == 2'h2), // @[Bundles.scala:112:49] .io_in_1_bits_eg (ll_arb_io_in_1_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_ready (_ll_arb_2_io_in_2_ready), .io_in_2_valid (io_ll_writes_2_valid & io_ll_writes_2_bits_eg[1:0] == 2'h2), // @[Bundles.scala:112:49] .io_in_2_bits_eg (ll_arb_io_in_2_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_bits_data (io_ll_writes_2_bits_data), .io_in_2_bits_mask (io_ll_writes_2_bits_mask), .io_in_3_ready (_ll_arb_2_io_in_3_ready), .io_in_3_valid (io_ll_writes_3_valid & io_ll_writes_3_bits_eg[1:0] == 2'h2), // @[Bundles.scala:112:49] .io_in_3_bits_eg (ll_arb_io_in_3_bits_eg), // @[RegisterFile.scala:172:33] .io_in_3_bits_data (io_ll_writes_3_bits_data), .io_in_3_bits_mask (io_ll_writes_3_bits_mask), .io_out_ready (_vrf_2_io_ll_write_ready), // @[RegisterFile.scala:134:38] .io_out_valid (_ll_arb_2_io_out_valid), .io_out_bits_eg (_ll_arb_2_io_out_bits_eg), .io_out_bits_data (_ll_arb_2_io_out_bits_data), .io_out_bits_mask (_ll_arb_2_io_out_bits_mask) ); // @[RegisterFile.scala:167:24] Arbiter4_VectorWrite ll_arb_3 ( // @[RegisterFile.scala:167:24] .io_in_0_ready (_ll_arb_3_io_in_0_ready), .io_in_0_valid (io_ll_writes_0_valid & (&(io_ll_writes_0_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_0_bits_eg (ll_arb_io_in_0_bits_eg), // @[RegisterFile.scala:172:33] .io_in_0_bits_data (io_ll_writes_0_bits_data), .io_in_0_bits_mask (io_ll_writes_0_bits_mask), .io_in_1_valid (io_ll_writes_1_valid & (&(io_ll_writes_1_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_1_bits_eg (ll_arb_io_in_1_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_ready (_ll_arb_3_io_in_2_ready), .io_in_2_valid (io_ll_writes_2_valid & (&(io_ll_writes_2_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_2_bits_eg (ll_arb_io_in_2_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_bits_data (io_ll_writes_2_bits_data), .io_in_2_bits_mask (io_ll_writes_2_bits_mask), .io_in_3_ready (_ll_arb_3_io_in_3_ready), .io_in_3_valid (io_ll_writes_3_valid & (&(io_ll_writes_3_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_3_bits_eg (ll_arb_io_in_3_bits_eg), // @[RegisterFile.scala:172:33] .io_in_3_bits_data (io_ll_writes_3_bits_data), .io_in_3_bits_mask (io_ll_writes_3_bits_mask), .io_out_ready (_vrf_3_io_ll_write_ready), // @[RegisterFile.scala:134:38] .io_out_valid (_ll_arb_3_io_out_valid), .io_out_bits_eg (_ll_arb_3_io_out_bits_eg), .io_out_bits_data (_ll_arb_3_io_out_bits_data), .io_out_bits_mask (_ll_arb_3_io_out_bits_mask) ); // @[RegisterFile.scala:167:24] assign io_ll_writes_0_ready = _ll_arb_3_io_in_0_ready & (&(io_ll_writes_0_bits_eg[1:0])) \| _ll_arb_2_io_in_0_ready & io_ll_writes_0_bits_eg[1:0] == 2'h2 \| _ll_arb_1_io_in_0_ready & io_ll_writes_0_bits_eg[1:0] == 2'h1 \| _ll_arb_io_in_0_ready & ~(\|(io_ll_writes_0_bits_eg[1:0])); // @[Bundles.scala:112:49] assign io_ll_writes_2_ready = _ll_arb_3_io_in_2_ready & (&(io_ll_writes_2_bits_eg[1:0])) \| _ll_arb_2_io_in_2_ready & io_ll_writes_2_bits_eg[1:0] == 2'h2 \| _ll_arb_1_io_in_2_ready & io_ll_writes_2_bits_eg[1:0] == 2'h1 \| _ll_arb_io_in_2_ready & ~(\|(io_ll_writes_2_bits_eg[1:0])); // @[Bundles.scala:112:49] assign io_ll_writes_3_ready = _ll_arb_3_io_in_3_ready & (&(io_ll_writes_3_bits_eg[1:0])) \| _ll_arb_2_io_in_3_ready & io_ll_writes_3_bits_eg[1:0] == 2'h2 \| _ll_arb_1_io_in_3_ready & io_ll_writes_3_bits_eg[1:0] == 2'h1 \| _ll_arb_io_in_3_ready & ~(\|(io_ll_writes_3_bits_eg[1:0])); // @[Bundles.scala:112:49] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_33( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File WidthWidget.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ object WidthWidget { def split[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth require(inBits > outBits && inBits % outBits == 0) val ratio = inBits / outBits val count = RegInit(0.U(log2Ceil(ratio).W)) val first = count === 0.U val last = count === (ratio - 1).U val stored = Reg(UInt((inBits - outBits).W)) out.valid := in.valid out.bits := in.bits out.bits.head := in.bits.head && first out.bits.tail := in.bits.tail && last out.bits.payload := Mux(first, in.bits.payload, stored) in.ready := last && out.ready when (out.fire) { count := Mux(last, 0.U, count + 1.U) stored := Mux(first, in.bits.payload, stored) >> outBits } } def merge[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth require(outBits > inBits && outBits % inBits == 0) val ratio = outBits / inBits val count = RegInit(0.U(log2Ceil(ratio).W)) val first = count === 0.U val last = count === (ratio - 1).U val flit = Reg(out.bits.cloneType) val payload = Reg(Vec(ratio-1, UInt(inBits.W))) out.valid := in.valid && last out.bits := flit out.bits.tail := last && in.bits.tail out.bits.payload := Cat(in.bits.payload, payload.asUInt) in.ready := !last \|\| out.ready when (in.fire) { count := Mux(last, 0.U, count + 1.U) payload(count) := in.bits.payload when (first) { flit := in.bits } } } def apply[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth if (inBits == outBits) { out <> in } else if (inBits < outBits) { merge(in, out) } else { split(in, out) } } } class IngressWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new IngressChannelAdapterNode( slaveFn = { s => s.copy(payloadBits=srcBits) } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => WidthWidget(in.flit, out.flit) } } } object IngressWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = IngressChannelEphemeralNode() node } else { val ingress_width_widget = LazyModule(new IngressWidthWidget(srcBits)) ingress_width_widget.node } } } class EgressWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new EgressChannelAdapterNode( slaveFn = { s => s.copy(payloadBits=srcBits) } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => WidthWidget(in.flit, out.flit) } } } object EgressWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = EgressChannelEphemeralNode() node } else { val egress_width_widget = LazyModule(new EgressWidthWidget(srcBits)) egress_width_widget.node } } } class ChannelWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new ChannelAdapterNode( slaveFn = { s => val destBits = s.payloadBits if (srcBits > destBits) { val ratio = srcBits / destBits val virtualChannelParams = s.virtualChannelParams.map { vP => require(vP.bufferSize >= ratio) vP.copy(bufferSize = vP.bufferSize / ratio) } s.copy(payloadBits=srcBits, virtualChannelParams=virtualChannelParams) } else { val ratio = destBits / srcBits val virtualChannelParams = s.virtualChannelParams.map { vP => vP.copy(bufferSize = vP.bufferSize * ratio) } s.copy(payloadBits=srcBits, virtualChannelParams=virtualChannelParams) } } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val destBits = out.cParam.payloadBits in.vc_free := out.vc_free if (srcBits == destBits) { in.credit_return := out.credit_return out.flit <> in.flit } else if (srcBits > destBits) { require(srcBits % destBits == 0, s"$srcBits, $destBits") (in.flit zip out.flit) foreach { case (iF, oF) => val in_q = Module(new Queue(new Flit(in.cParam.payloadBits), in.cParam.virtualChannelParams.map(_.bufferSize).sum, pipe=true, flow=true)) in_q.io.enq.valid := iF.valid in_q.io.enq.bits := iF.bits assert(!(in_q.io.enq.valid && !in_q.io.enq.ready)) val in_flit = Wire(Irrevocable(new Flit(in.cParam.payloadBits))) in_flit.valid := in_q.io.deq.valid in_flit.bits := in_q.io.deq.bits in_q.io.deq.ready := in_flit.ready val out_flit = Wire(Irrevocable(new Flit(out.cParam.payloadBits))) oF.valid := out_flit.valid oF.bits := out_flit.bits out_flit.ready := true.B WidthWidget(in_flit, out_flit) } val ratio = srcBits / destBits val counts = RegInit(VecInit(Seq.fill(in.nVirtualChannels) { 0.U(log2Ceil(ratio).W) })) val in_credit_return = Wire(Vec(in.nVirtualChannels, Bool())) in.credit_return := in_credit_return.asUInt for (i <- 0 until in.nVirtualChannels) { in_credit_return(i) := false.B when (out.credit_return(i)) { val last = counts(i) === (ratio-1).U counts(i) := Mux(last, 0.U, counts(i) + 1.U) when (last) { in_credit_return(i) := true.B } } } } else { require(destBits % srcBits == 0) val in_flits = Wire(Vec(in.nVirtualChannels, Irrevocable(new Flit(in.cParam.payloadBits)))) val out_flits = Wire(Vec(in.nVirtualChannels, Irrevocable(new Flit(out.cParam.payloadBits)))) for (i <- 0 until in.nVirtualChannels) { val sel = in.flit.map(f => f.valid && f.bits.virt_channel_id === i.U) in_flits(i).valid := sel.orR in_flits(i).bits := Mux1H(sel, in.flit.map(_.bits)) out_flits(i).ready := sel.orR WidthWidget(in_flits(i), out_flits(i)) } for (i <- 0 until in.flit.size) { val sel = UIntToOH(in.flit(i).bits.virt_channel_id) out.flit(i).valid := Mux1H(sel, out_flits.map(_.valid)) out.flit(i).bits := Mux1H(sel, out_flits.map(_.bits)) } val ratio = destBits / srcBits val credits = RegInit(VecInit((0 until in.nVirtualChannels).map { i => 0.U(log2Ceil(ratioin.cParam.virtualChannelParams(i).bufferSize).W) })) val in_credit_return = Wire(Vec(in.nVirtualChannels, Bool())) in.credit_return := in_credit_return.asUInt for (i <- 0 until in.nVirtualChannels) { when (out.credit_return(i)) { in_credit_return(i) := true.B credits(i) := credits(i) + (ratio - 1).U } .otherwise { val empty = credits(i) === 0.U in_credit_return(i) := !empty credits(i) := Mux(empty, 0.U, credits(i) - 1.U) } } } } } } object ChannelWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = ChannelEphemeralNode() node } else { val channel_width_widget = LazyModule(new ChannelWidthWidget(srcBits)) channel_width_widget.node } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn \|\| noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }	module TLSplitACDxBENoC_be_router_12ClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_egress_width_widget_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [147:0] auto_egress_width_widget_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_width_widget_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [147:0] auto_ingress_width_widget_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_width_widget_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _egress_width_widget_auto_in_flit_ready; // @[WidthWidget.scala:111:43] wire _ingress_width_widget_auto_out_flit_valid; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_head; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_tail; // @[WidthWidget.scala:88:44] wire [36:0] _ingress_width_widget_auto_out_flit_bits_payload; // @[WidthWidget.scala:88:44] wire [4:0] _ingress_width_widget_auto_out_flit_bits_egress_id; // @[WidthWidget.scala:88:44] wire _routers_auto_egress_nodes_out_flit_valid; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_head; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_tail; // @[NoC.scala:67:22] wire [36:0] _routers_auto_egress_nodes_out_flit_bits_payload; // @[NoC.scala:67:22] wire _routers_auto_ingress_nodes_in_flit_ready; // @[NoC.scala:67:22] Router_28 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_egress_nodes_out_flit_ready (_egress_width_widget_auto_in_flit_ready), // @[WidthWidget.scala:111:43] .auto_egress_nodes_out_flit_valid (_routers_auto_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), .auto_ingress_nodes_in_flit_valid (_ingress_width_widget_auto_out_flit_valid), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id), // @[WidthWidget.scala:88:44] .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] IngressWidthWidget ingress_width_widget ( // @[WidthWidget.scala:88:44] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (auto_ingress_width_widget_in_flit_ready), .auto_in_flit_valid (auto_ingress_width_widget_in_flit_valid), .auto_in_flit_bits_head (auto_ingress_width_widget_in_flit_bits_head), .auto_in_flit_bits_payload (auto_ingress_width_widget_in_flit_bits_payload), .auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_flit_bits_egress_id), .auto_out_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), // @[NoC.scala:67:22] .auto_out_flit_valid (_ingress_width_widget_auto_out_flit_valid), .auto_out_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), .auto_out_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), .auto_out_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), .auto_out_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id) ); // @[WidthWidget.scala:88:44] EgressWidthWidget_1 egress_width_widget ( // @[WidthWidget.scala:111:43] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (_egress_width_widget_auto_in_flit_ready), .auto_in_flit_valid (_routers_auto_egress_nodes_out_flit_valid), // @[NoC.scala:67:22] .auto_in_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), // @[NoC.scala:67:22] .auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), // @[NoC.scala:67:22] .auto_in_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), // @[NoC.scala:67:22] .auto_out_flit_ready (auto_egress_width_widget_out_flit_ready), .auto_out_flit_valid (auto_egress_width_widget_out_flit_valid), .auto_out_flit_bits_head (auto_egress_width_widget_out_flit_bits_head), .auto_out_flit_bits_tail (auto_egress_width_widget_out_flit_bits_tail), .auto_out_flit_bits_payload (auto_egress_width_widget_out_flit_bits_payload) ); // @[WidthWidget.scala:111:43] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [511:0] c_sizes_set = 512'h0; // @[Monitor.scala:741:34] wire [255:0] c_opcodes_set = 256'h0; // @[Monitor.scala:740:34] wire [63:0] c_set = 64'h0; // @[Monitor.scala:738:34] wire [63:0] c_set_wo_ready = 64'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [5:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [5:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1267 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1267; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1267; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1340 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1340; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1340; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1340; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [63:0] inflight; // @[Monitor.scala:614:27] reg [255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [511:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [63:0] a_set; // @[Monitor.scala:626:34] wire [63:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [511:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [255:0] _a_opcode_lookup_T_6 = {252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [511:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [511:0] _a_size_lookup_T_6 = {504'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [511:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[511:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = {58'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [63:0] _GEN_4 = 64'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 64'h0; // @[OneHot.scala:58:35] wire _T_1193 = _T_1267 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1193 ? _a_set_T : 64'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1193 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1193 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1193 ? _a_opcodes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1193 ? _a_sizes_set_T_1[511:0] : 512'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [63:0] d_clr; // @[Monitor.scala:664:34] wire [63:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [511:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1239 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_6 = {58'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [63:0] _GEN_7 = 64'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1239 & ~d_release_ack ? _d_clr_wo_ready_T : 64'h0; // @[OneHot.scala:58:35] wire _T_1208 = _T_1340 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1208 ? _d_clr_T : 64'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1208 ? _d_opcodes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1208 ? _d_sizes_clr_T_5[511:0] : 512'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [63:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [63:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [63:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [255:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [511:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [511:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [511:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [63:0] inflight_1; // @[Monitor.scala:726:35] wire [63:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [511:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [511:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [255:0] _c_opcode_lookup_T_6 = {252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [511:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [511:0] _c_size_lookup_T_6 = {504'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [511:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[511:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [63:0] d_clr_1; // @[Monitor.scala:774:34] wire [63:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [511:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1311 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1311 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 64'h0; // @[OneHot.scala:58:35] wire _T_1293 = _T_1340 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1293 ? _d_clr_T_1 : 64'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1293 ? _d_opcodes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1293 ? _d_sizes_clr_T_11[511:0] : 512'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [63:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [63:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [511:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [511:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_43(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid \|\| io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }	module PriorityQueueStage_74( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File FunctionalUnit.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns.{VectorInstruction} abstract class FunctionalUnitIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val iss = new Bundle { val valid = Input(Bool()) val op = Input(new ExecuteMicroOp) val ready = Output(Bool()) } val scalar_write = Decoupled(new ScalarWrite) val set_vxsat = Output(Bool()) val set_fflags = Output(Valid(UInt(5.W))) } class PipelinedFunctionalUnitIO(depth: Int)(implicit p: Parameters) extends FunctionalUnitIO { val write = Valid(new VectorWrite(dLen)) val pipe = Input(Vec(depth, Valid(new ExecuteMicroOp))) val pipe0_stall = Output(Bool()) } class IterativeFunctionalUnitIO(implicit p: Parameters) extends FunctionalUnitIO { val write = Decoupled(new VectorWrite(dLen)) val hazard = Output(Valid(new PipeHazard(10))) val acc = Output(Bool()) val tail = Output(Bool()) val busy = Output(Bool()) } trait FunctionalUnitFactory { def insns: Seq[VectorInstruction] def generate(implicit p: Parameters): FunctionalUnit } abstract class FunctionalUnit(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io: FunctionalUnitIO } abstract class PipelinedFunctionalUnit(val depth: Int)(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new PipelinedFunctionalUnitIO(depth)) require (depth > 0) def narrow2_expand(bits: Seq[UInt], eew: UInt, upper: Bool, sext: Bool): Vec[UInt] = { val narrow_eew = (0 until 3).map { eew => Wire(Vec(dLenB >> (eew + 1), UInt((16 << eew).W))) } for (eew <- 0 until 3) { val in_vec = bits.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq for (i <- 0 until dLenB >> (eew + 1)) { val lo = Mux(upper, in_vec(i + (dLenB >> (eew + 1))), in_vec(i)) val hi = Fill(16 << eew, lo((8 << eew)-1) && sext) narrow_eew(eew)(i) := Cat(hi, lo) } } VecInit(narrow_eew.map(_.asUInt))(eew).asTypeOf(Vec(dLenB, UInt(8.W))) } } abstract class IterativeFunctionalUnit(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new IterativeFunctionalUnitIO) val valid = RegInit(false.B) val op = Reg(new ExecuteMicroOp) val last = Wire(Bool()) io.busy := valid io.hazard.bits.latency := DontCare when (io.iss.valid && io.iss.ready) { valid := true.B op := io.iss.op } .elsewhen (last) { valid := false.B } } File BitwisePipe.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns._ case object BitwisePipeFactory extends FunctionalUnitFactory { def insns = Seq( AND.VV, AND.VX, AND.VI, OR.VV, OR.VX, OR.VI, XOR.VV, XOR.VX, XOR.VI, MANDNOT.VV, MAND.VV, MOR.VV, MXOR.VV, MORNOT.VV, MNAND.VV, MNOR.VV, MXNOR.VV, REDAND.VV, REDOR.VV, REDXOR.VV, // Zvbb ANDN.VV, ANDN.VX ) def generate(implicit p: Parameters) = new BitwisePipe()(p) } class BitwisePipe(implicit p: Parameters) extends PipelinedFunctionalUnit(1)(p) { val supported_insns = BitwisePipeFactory.insns val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, Seq(BWAnd, BWOr, BWXor, BWInvOut, BWInv1)) io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched val in1 = Mux(ctrl.bool(BWInv1), ~io.pipe(0).bits.rvs1_data, io.pipe(0).bits.rvs1_data) val in2 = io.pipe(0).bits.rvs2_data val op = Mux1H(Seq( (ctrl.bool(BWAnd), (in1 & in2)), (ctrl.bool(BWOr) , (in1 \| in2)), (ctrl.bool(BWXor), (in1 ^ in2)) )) val out = Mux(ctrl.bool(BWInvOut), ~op, op) io.pipe0_stall := false.B io.write.valid := io.pipe(0).valid io.write.bits.eg := io.pipe(0).bits.wvd_eg io.write.bits.mask := Mux(io.pipe(0).bits.isOpm && !io.pipe(0).bits.acc, io.pipe(0).bits.full_tail_mask, FillInterleaved(8, io.pipe(0).bits.wmask)) io.write.bits.data := out io.set_vxsat := false.B io.set_fflags.valid := false.B io.set_fflags.bits := DontCare io.scalar_write.valid := false.B io.scalar_write.bits := DontCare }	module BitwisePipe( // @[BitwisePipe.scala:23:7] input [2:0] io_iss_op_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_iss_op_funct6, // @[FunctionalUnit.scala:49:14] output io_iss_ready, // @[FunctionalUnit.scala:49:14] output io_write_valid, // @[FunctionalUnit.scala:49:14] output [4:0] io_write_bits_eg, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_data, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_mask, // @[FunctionalUnit.scala:49:14] input io_pipe_0_valid, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs1_data, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs2_data, // @[FunctionalUnit.scala:49:14] input [7:0] io_pipe_0_bits_wmask, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_full_tail_mask, // @[FunctionalUnit.scala:49:14] input [4:0] io_pipe_0_bits_wvd_eg, // @[FunctionalUnit.scala:49:14] input [2:0] io_pipe_0_bits_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_pipe_0_bits_funct6, // @[FunctionalUnit.scala:49:14] input io_pipe_0_bits_acc // @[FunctionalUnit.scala:49:14] ); wire [3:0] _GEN = ~(io_pipe_0_bits_funct6[3:0]); // @[pla.scala:78:21] wire [2:0] _decode_andMatrixOutputs_T = {_GEN[0], _GEN[1], _GEN[2]}; // @[pla.scala:78:21, :91:29, :98:53] wire [2:0] _decode_andMatrixOutputs_T_7 = {_GEN[0], _GEN[1], io_pipe_0_bits_funct6[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [2:0] _GEN_0 = ~io_iss_op_funct3; // @[pla.scala:78:21] wire [4:0] _GEN_1 = ~(io_iss_op_funct6[5:1]); // @[pla.scala:78:21] wire [63:0] in1 = {64{\|{&_decode_andMatrixOutputs_T, &{_GEN[3], ~(io_pipe_0_bits_funct3[1])}, &_decode_andMatrixOutputs_T_7}}} ^ io_pipe_0_bits_rvs1_data; // @[pla.scala:78:21, :91:29, :98:{53,70}, :114:{19,36}] assign io_iss_ready = \|{&{io_iss_op_funct6[0], _GEN_1[0], _GEN_1[1], _GEN_1[3], _GEN_1[4], _GEN_0[0], _GEN_0[1]}, &{io_iss_op_funct6[0], _GEN_1[0], _GEN_1[1], _GEN_1[2], _GEN_1[3], _GEN_1[4], _GEN_0[0], _GEN_0[2]}, &{io_iss_op_funct6[1], _GEN_1[1], io_iss_op_funct6[3], _GEN_1[3], _GEN_1[4], _GEN_0[0], _GEN_0[1]}, &{io_iss_op_funct6[1], _GEN_1[1], _GEN_1[2], _GEN_1[3], _GEN_1[4], _GEN_0[0], io_iss_op_funct3[1], _GEN_0[2]}, &{io_iss_op_funct6[3], io_iss_op_funct6[4], _GEN_1[4], _GEN_0[0], io_iss_op_funct3[1], _GEN_0[2]}, &{io_iss_op_funct6[0], _GEN_1[1], io_iss_op_funct6[3], _GEN_1[3], _GEN_1[4], io_iss_op_funct3[0], io_iss_op_funct3[1], _GEN_0[2]}, &{io_iss_op_funct6[1], _GEN_1[1], io_iss_op_funct6[3], _GEN_1[3], _GEN_1[4], io_iss_op_funct3[0], io_iss_op_funct3[1], _GEN_0[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_write_valid = io_pipe_0_valid; // @[BitwisePipe.scala:23:7] assign io_write_bits_eg = io_pipe_0_bits_wvd_eg; // @[BitwisePipe.scala:23:7] assign io_write_bits_data = {64{\|{&{io_pipe_0_bits_funct6[0], io_pipe_0_bits_funct6[2]}, &{io_pipe_0_bits_funct6[1], io_pipe_0_bits_funct6[2]}}}} ^ (((\|{&_decode_andMatrixOutputs_T, &{io_pipe_0_bits_funct6[0], _GEN[1]}}) ? in1 & io_pipe_0_bits_rvs2_data : 64'h0) \| ((\|{&{_GEN[0], io_pipe_0_bits_funct6[1]}, &_decode_andMatrixOutputs_T_7}) ? in1 \| io_pipe_0_bits_rvs2_data : 64'h0) \| ((&{io_pipe_0_bits_funct6[0], io_pipe_0_bits_funct6[1]}) ? in1 ^ io_pipe_0_bits_rvs2_data : 64'h0)); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_write_bits_mask = (io_pipe_0_bits_funct3 == 3'h2 \| io_pipe_0_bits_funct3 == 3'h6) & ~io_pipe_0_bits_acc ? io_pipe_0_bits_full_tail_mask : {{8{io_pipe_0_bits_wmask[7]}}, {8{io_pipe_0_bits_wmask[6]}}, {8{io_pipe_0_bits_wmask[5]}}, {8{io_pipe_0_bits_wmask[4]}}, {8{io_pipe_0_bits_wmask[3]}}, {8{io_pipe_0_bits_wmask[2]}}, {8{io_pipe_0_bits_wmask[1]}}, {8{io_pipe_0_bits_wmask[0]}}}; // @[BitwisePipe.scala:23:7, :42:{28,51,54}, :44:20] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_15( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h0; // @[Edges.scala:92:37] wire _a_first_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:92:37] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire a_first_beats1_opdata = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire a_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] a_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h2; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_opcode = 3'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] io_in_a_bits_mask = 8'hF; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:657:53] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:657:61] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [4:0] _a_sizes_set_interm_T_1 = 5'h5; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'h4; // @[Monitor.scala:658:51] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [11:0] is_aligned_mask = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFFC; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC; // @[package.scala:243:71] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [28:0] _is_aligned_T = {27'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_0_1 = _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_0_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire mask_sub_1_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_1 = _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_3_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1081 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1081; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1081; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [28:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1004 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1004; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1004; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1081 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = {3'h0, a_set}; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'h5 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1053 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1053 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1125 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1125 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) && (vcalloc_q.io.enq.ready \|\| !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_\|\|_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }	module IngressUnit_23( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h13; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 4'hA : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'h9 : 4'h0); // @[Mux.scala:30:73] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_T_10[3], _route_buffer_io_enq_bits_flow_egress_node_T_10[2:0] \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 3'h5 : 3'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 3'h6 : 3'h0)}; // @[Mux.scala:30:73] wire [1:0] _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_4, 1'h0}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'hC; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'hC; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr \| (mask >> 1), ~(~addr \| mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked \|\| next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) \| ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) \| (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask \| UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) \| lsbMask) < comparand(lgMaxSize-1, 0) msbsLess \|\| (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous \|\| (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower \|\| beginsAfterUpper \|\| (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT \|\| rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) \| lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound \|\| straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r \|\| ignore) cur.cfg.w := aligned && (pmp.cfg.w \|\| ignore) cur.cfg.x := aligned && (pmp.cfg.x \|\| ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x }	module PMPChecker_s4_1( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire [10:0] _res_hit_lsbMask_T = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_3 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_3 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_16 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_2 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_6 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_29 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_4 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_9 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_42 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_6 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_12 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_55 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_8 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_15 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_68 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_10 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_18 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_81 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_12 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_21 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_94 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_14 = 11'hF0; // @[package.scala:243:71] wire [27:0] _res_hit_msbsLess_T_89 = 28'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [27:0] _res_hit_msbsEqual_T_103 = 28'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_124 = 28'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [3:0] _res_hit_lsbMask_T_1 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_4 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_1 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_4 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_17 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_3 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_7 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_30 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_5 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_10 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_43 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_7 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_13 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_56 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_9 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_16 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_69 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_11 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_19 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_82 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_13 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_22 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_95 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbsLess_T_104 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_15 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_straddlesLowerBound_T_131 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_straddlesLowerBound_T_134 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_2 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_5 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_1 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_14 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_5 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_18 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_15 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_1 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_31 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_8 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_31 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_29 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_2 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_48 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_11 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_44 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_43 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_3 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_65 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_14 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_57 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_57 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_4 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_82 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_17 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_70 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_71 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_5 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_99 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_20 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_83 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_85 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_6 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_116 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_23 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_96 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_99 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_7 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_133 = 4'hF; // @[package.scala:243:46] wire [2:0] io_size = 3'h4; // @[PMP.scala:143:7] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_lsbsLess = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_6 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_2 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_19 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_4 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_32 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_6 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_45 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_8 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_58 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_10 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_71 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_12 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_84 = 1'h0; // @[PMP.scala:83:30] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, 4'hF}; // @[package.scala:243:46] wire [27:0] _res_hit_msbMatch_T = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_6 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_10 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_12 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_18 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_20 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_24 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_30 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_30 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_36 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_42 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_40 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_48 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_54 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_50 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_60 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_66 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_60 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_72 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_78 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_70 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_84 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_90 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [3:0] _res_hit_lsbMatch_T = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_7 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_10 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_14 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_21 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_20 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_28 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_35 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_30 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_42 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_49 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_40 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_56 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_63 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_50 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_70 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_77 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_60 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_84 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_91 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_70 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_98 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_105 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_0 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_7 = res_hit_msbsLess; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 \| _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = \|_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_16 = \|_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound \| res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_2 = _res_aligned_pow2Aligned_T_1; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 4'h0; // @[package.scala:243:76] wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_1 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_1; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_1; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_1; // @[PMP.scala:168:32, :178:63] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_3 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_3; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_4 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_5 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_20 = res_hit_msbsLess_2; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 \| _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = \|_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_33 = \|_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 \| res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_5 = _res_aligned_pow2Aligned_T_4; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 4'h0; // @[package.scala:243:76] wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_6 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_6; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_6; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_6; // @[PMP.scala:168:32, :178:63] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_8 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_8; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_9 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_10 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_33 = res_hit_msbsLess_4; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 \| _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = \|_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_50 = \|_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 \| res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_8 = _res_aligned_pow2Aligned_T_7; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 4'h0; // @[package.scala:243:76] wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_11 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_11; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_11; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_11; // @[PMP.scala:168:32, :178:63] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_13 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_13; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_14 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_15 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_46 = res_hit_msbsLess_6; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 \| _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = \|_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_67 = \|_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 \| res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_11 = _res_aligned_pow2Aligned_T_10; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 4'h0; // @[package.scala:243:76] wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_16 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_16; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_16; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_16; // @[PMP.scala:168:32, :178:63] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_18 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_18; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_19 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_20 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_59 = res_hit_msbsLess_8; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 \| _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = \|_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_84 = \|_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 \| res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_14 = _res_aligned_pow2Aligned_T_13; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 4'h0; // @[package.scala:243:76] wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_21 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_21; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_21; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_21; // @[PMP.scala:168:32, :178:63] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_23 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_23; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_24 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_25 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_72 = res_hit_msbsLess_10; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 \| _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = \|_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_101 = \|_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 \| res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_17 = _res_aligned_pow2Aligned_T_16; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 4'h0; // @[package.scala:243:76] wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_26 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_26; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_26; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_26; // @[PMP.scala:168:32, :178:63] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_28 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_28; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_29 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_30 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_85 = res_hit_msbsLess_12; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 \| _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = \|_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_118 = \|_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 \| res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_20 = _res_aligned_pow2Aligned_T_19; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 4'h0; // @[package.scala:243:76] wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_31 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_31; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_31; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_31; // @[PMP.scala:168:32, :178:63] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_33 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_33; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_34 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [27:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 \| _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [27:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [3:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_135 = \|_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_23 = _res_aligned_pow2Aligned_T_22; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 4'h0; // @[package.scala:243:76] wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_35 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_35; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_35; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_35; // @[PMP.scala:168:32, :178:63] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_37 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_37; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_38 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_48( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File predictor.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} // A branch prediction for a single instruction class BranchPrediction(implicit p: Parameters) extends BoomBundle()(p) { // If this is a branch, do we take it? val taken = Bool() // Is this a branch? val is_br = Bool() // Is this a JAL? val is_jal = Bool() // What is the target of his branch/jump? Do we know the target? val predicted_pc = Valid(UInt(vaddrBitsExtended.W)) } // A branch prediction for a entire fetch-width worth of instructions // This is typically merged from individual predictions from the banked // predictor class BranchPredictionBundle(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val pc = UInt(vaddrBitsExtended.W) val preds = Vec(fetchWidth, new BranchPrediction) val meta = Output(Vec(nBanks, UInt(bpdMaxMetaLength.W))) val lhist = Output(Vec(nBanks, UInt(localHistoryLength.W))) } // A branch update for a fetch-width worth of instructions class BranchPredictionUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { // Indicates that this update is due to a speculated misprediction // Local predictors typically update themselves with speculative info // Global predictors only care about non-speculative updates val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(fetchWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update \|\| is_repair_update \|\| is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) // Mask of instructions which are branches. // If these are not cfi_idx, then they were predicted not taken val br_mask = UInt(fetchWidth.W) // Which CFI was taken/mispredicted (if any) val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W)) // Was the cfi taken? val cfi_taken = Bool() // Was the cfi mispredicted from the original prediction? val cfi_mispredicted = Bool() // Was the cfi a br? val cfi_is_br = Bool() // Was the cfi a jal/jalr? val cfi_is_jal = Bool() // Was the cfi a jalr val cfi_is_jalr = Bool() //val cfi_is_ret = Bool() val ghist = new GlobalHistory val lhist = Vec(nBanks, UInt(localHistoryLength.W)) // What did this CFI jump to? val target = UInt(vaddrBitsExtended.W) val meta = Vec(nBanks, UInt(bpdMaxMetaLength.W)) } // A branch update to a single bank class BranchPredictionBankUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(bankWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update \|\| is_repair_update \|\| is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) val br_mask = UInt(bankWidth.W) val cfi_idx = Valid(UInt(log2Ceil(bankWidth).W)) val cfi_taken = Bool() val cfi_mispredicted = Bool() val cfi_is_br = Bool() val cfi_is_jal = Bool() val cfi_is_jalr = Bool() val ghist = UInt(globalHistoryLength.W) val lhist = UInt(localHistoryLength.W) val target = UInt(vaddrBitsExtended.W) val meta = UInt(bpdMaxMetaLength.W) } class BranchPredictionRequest(implicit p: Parameters) extends BoomBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val ghist = new GlobalHistory } class BranchPredictionBankResponse(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val f1 = Vec(bankWidth, new BranchPrediction) val f2 = Vec(bankWidth, new BranchPrediction) val f3 = Vec(bankWidth, new BranchPrediction) } abstract class BranchPredictorBank(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val metaSz = 0 def nInputs = 1 val mems: Seq[Tuple3[String, Int, Int]] val io = IO(new Bundle { val f0_valid = Input(Bool()) val f0_pc = Input(UInt(vaddrBitsExtended.W)) val f0_mask = Input(UInt(bankWidth.W)) // Local history not available until end of f1 val f1_ghist = Input(UInt(globalHistoryLength.W)) val f1_lhist = Input(UInt(localHistoryLength.W)) val resp_in = Input(Vec(nInputs, new BranchPredictionBankResponse)) val resp = Output(new BranchPredictionBankResponse) // Store the meta as a UInt, use width inference to figure out the shape val f3_meta = Output(UInt(bpdMaxMetaLength.W)) val f3_fire = Input(Bool()) val update = Input(Valid(new BranchPredictionBankUpdate)) }) io.resp := io.resp_in(0) io.f3_meta := 0.U val s0_idx = fetchIdx(io.f0_pc) val s1_idx = RegNext(s0_idx) val s2_idx = RegNext(s1_idx) val s3_idx = RegNext(s2_idx) val s0_valid = io.f0_valid val s1_valid = RegNext(s0_valid) val s2_valid = RegNext(s1_valid) val s3_valid = RegNext(s2_valid) val s0_mask = io.f0_mask val s1_mask = RegNext(s0_mask) val s2_mask = RegNext(s1_mask) val s3_mask = RegNext(s2_mask) val s0_pc = io.f0_pc val s1_pc = RegNext(s0_pc) val s0_update = io.update val s0_update_idx = fetchIdx(io.update.bits.pc) val s0_update_valid = io.update.valid val s1_update = RegNext(s0_update) val s1_update_idx = RegNext(s0_update_idx) val s1_update_valid = RegNext(s0_update_valid) } class BranchPredictor(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val io = IO(new Bundle { // Requests and responses val f0_req = Input(Valid(new BranchPredictionRequest)) val resp = Output(new Bundle { val f1 = new BranchPredictionBundle val f2 = new BranchPredictionBundle val f3 = new BranchPredictionBundle }) val f3_fire = Input(Bool()) // Update val update = Input(Valid(new BranchPredictionUpdate)) }) var total_memsize = 0 val bpdStr = new StringBuilder bpdStr.append(BoomCoreStringPrefix("==Branch Predictor Memory Sizes==\n")) val banked_predictors = (0 until nBanks) map ( b => { val m = Module(if (useBPD) new ComposedBranchPredictorBank else new NullBranchPredictorBank) for ((n, d, w) <- m.mems) { bpdStr.append(BoomCoreStringPrefix(f"bank$b $n: $d x $w = ${d * w / 8}")) total_memsize = total_memsize + d * w / 8 } m }) bpdStr.append(BoomCoreStringPrefix(f"Total bpd size: ${total_memsize / 1024} KB\n")) override def toString: String = bpdStr.toString val banked_lhist_providers = Seq.fill(nBanks) { Module(if (localHistoryNSets > 0) new LocalBranchPredictorBank else new NullLocalBranchPredictorBank) } if (nBanks == 1) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) } else { require(nBanks == 2) banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(1).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(1).io.f1_lhist := banked_lhist_providers(1).io.f1_lhist when (bank(io.f0_req.bits.pc) === 0.U) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := ~(0.U(bankWidth.W)) } .otherwise { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_lhist_providers(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_predictors(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := ~(0.U(bankWidth.W)) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := fetchMask(io.f0_req.bits.pc) } when (RegNext(bank(io.f0_req.bits.pc) === 0.U)) { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) } .otherwise { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) } } for (i <- 0 until nBanks) { banked_lhist_providers(i).io.f3_taken_br := banked_predictors(i).io.resp.f3.map ( p => p.is_br && p.predicted_pc.valid && p.taken ).reduce(_\|\|_) } if (nBanks == 1) { io.resp.f1.preds := banked_predictors(0).io.resp.f1 io.resp.f2.preds := banked_predictors(0).io.resp.f2 io.resp.f3.preds := banked_predictors(0).io.resp.f3 io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist banked_predictors(0).io.f3_fire := io.f3_fire banked_lhist_providers(0).io.f3_fire := io.f3_fire } else { require(nBanks == 2) val b0_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(0).io.f0_valid))) val b1_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(1).io.f0_valid))) banked_predictors(0).io.f3_fire := b0_fire banked_predictors(1).io.f3_fire := b1_fire banked_lhist_providers(0).io.f3_fire := b0_fire banked_lhist_providers(1).io.f3_fire := b1_fire // The branch prediction metadata is stored un-shuffled io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.meta(1) := banked_predictors(1).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist io.resp.f3.lhist(1) := banked_lhist_providers(1).io.f3_lhist when (bank(io.resp.f1.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(0).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(1).io.resp.f1(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(1).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(0).io.resp.f1(i) } } when (bank(io.resp.f2.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(0).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(1).io.resp.f2(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(1).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(0).io.resp.f2(i) } } when (bank(io.resp.f3.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(0).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(1).io.resp.f3(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(1).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(0).io.resp.f3(i) } } } io.resp.f1.pc := RegNext(io.f0_req.bits.pc) io.resp.f2.pc := RegNext(io.resp.f1.pc) io.resp.f3.pc := RegNext(io.resp.f2.pc) // We don't care about meta from the f1 and f2 resps // Use the meta from the latest resp io.resp.f1.meta := DontCare io.resp.f2.meta := DontCare io.resp.f1.lhist := DontCare io.resp.f2.lhist := DontCare for (i <- 0 until nBanks) { banked_predictors(i).io.update.bits.is_mispredict_update := io.update.bits.is_mispredict_update banked_predictors(i).io.update.bits.is_repair_update := io.update.bits.is_repair_update banked_predictors(i).io.update.bits.meta := io.update.bits.meta(i) banked_predictors(i).io.update.bits.lhist := io.update.bits.lhist(i) banked_predictors(i).io.update.bits.cfi_idx.bits := io.update.bits.cfi_idx.bits banked_predictors(i).io.update.bits.cfi_taken := io.update.bits.cfi_taken banked_predictors(i).io.update.bits.cfi_mispredicted := io.update.bits.cfi_mispredicted banked_predictors(i).io.update.bits.cfi_is_br := io.update.bits.cfi_is_br banked_predictors(i).io.update.bits.cfi_is_jal := io.update.bits.cfi_is_jal banked_predictors(i).io.update.bits.cfi_is_jalr := io.update.bits.cfi_is_jalr banked_predictors(i).io.update.bits.target := io.update.bits.target banked_lhist_providers(i).io.update.mispredict := io.update.bits.is_mispredict_update banked_lhist_providers(i).io.update.repair := io.update.bits.is_repair_update banked_lhist_providers(i).io.update.lhist := io.update.bits.lhist(i) } if (nBanks == 1) { banked_predictors(0).io.update.valid := io.update.valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) } else { require(nBanks == 2) // Split the single update bundle for the fetchpacket into two updates // 1 for each bank. when (bank(io.update.bits.pc) === 0.U) { val b1_update_valid = io.update.valid && (!io.update.bits.cfi_idx.valid \|\| io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(1).io.update.valid := b1_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(1).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.valid := io.update.valid banked_predictors(1).io.update.valid := b1_update_valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(1).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(1) } .otherwise { val b0_update_valid = io.update.valid && !mayNotBeDualBanked(io.update.bits.pc) && (!io.update.bits.cfi_idx.valid \|\| io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(1).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(0).io.update.valid := b0_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(1).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(0).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.valid := io.update.valid banked_predictors(0).io.update.valid := b0_update_valid banked_predictors(1).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(1) } } when (io.update.valid) { when (io.update.bits.cfi_is_br && io.update.bits.cfi_idx.valid) { assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits)) } } } class NullBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val mems = Nil } File btb.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomBTBParams( nSets: Int = 128, nWays: Int = 2, offsetSz: Int = 13, extendedNSets: Int = 128 ) class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { override val nSets = params.nSets override val nWays = params.nWays val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1 val offsetSz = params.offsetSz val extendedNSets = params.extendedNSets require(isPow2(nSets)) require(isPow2(extendedNSets) \|\| extendedNSets == 0) require(extendedNSets <= nSets) require(extendedNSets >= 1) class BTBEntry extends Bundle { val offset = SInt(offsetSz.W) val extended = Bool() } val btbEntrySz = offsetSz + 1 class BTBMeta extends Bundle { val is_br = Bool() val tag = UInt(tagSz.W) } val btbMetaSz = tagSz + 1 class BTBPredictMeta extends Bundle { val write_way = UInt(log2Ceil(nWays).W) } val s1_meta = Wire(new BTBPredictMeta) val f3_meta = RegNext(RegNext(s1_meta)) io.f3_meta := f3_meta.asUInt override val metaSz = s1_meta.asUInt.getWidth val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) } val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) } val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W)) val mems = (((0 until nWays) map ({w:Int => Seq( (f"btb_meta_way$w", nSets, bankWidth * btbMetaSz), (f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended))) val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) }) val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) }) val s1_req_rebtb = ebtb.read(s0_idx, s0_valid) val s1_req_tag = s1_idx >> log2Ceil(nSets) val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W)))) val s1_is_br = Wire(Vec(bankWidth, Bool())) val s1_is_jal = Wire(Vec(bankWidth, Bool())) val s1_hit_ohs = VecInit((0 until bankWidth) map { i => VecInit((0 until nWays) map { w => s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0) }) }) val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_\|\|_) } val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) } for (w <- 0 until bankWidth) { val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w) val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w) s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w) s1_resp(w).bits := Mux( entry_btb.extended, s1_req_rebtb, (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt) s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br io.resp.f2(w) := io.resp_in(0).f2(w) io.resp.f3(w) := io.resp_in(0).f3(w) when (RegNext(s1_hits(w))) { io.resp.f2(w).predicted_pc := RegNext(s1_resp(w)) io.resp.f2(w).is_br := RegNext(s1_is_br(w)) io.resp.f2(w).is_jal := RegNext(s1_is_jal(w)) when (RegNext(s1_is_jal(w))) { io.resp.f2(w).taken := true.B } } when (RegNext(RegNext(s1_hits(w)))) { io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc) io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br) io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal) when (RegNext(RegNext(s1_is_jal(w)))) { io.resp.f3(w).taken := true.B } } } val alloc_way = if (nWays > 1) { val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0)) val l = log2Ceil(nWays) val nChunks = (r_metas.getWidth + l - 1) / l val chunks = (0 until nChunks) map { i => r_metas(min((i+1)l, r_metas.getWidth)-1, il) } chunks.reduce(_^_) } else { 0.U } s1_meta.write_way := Mux(s1_hits.reduce(_\|\|_), PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_\|_)), alloc_way) val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta) val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt val new_offset_value = (s1_update.bits.target.asSInt - (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt) val offset_is_extended = (new_offset_value > max_offset_value \|\| new_offset_value < min_offset_value) val s1_update_wbtb_data = Wire(new BTBEntry) s1_update_wbtb_data.extended := offset_is_extended s1_update_wbtb_data.offset := new_offset_value val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) & Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update)) val s1_update_wmeta_mask = ((s1_update_wbtb_mask \| s1_update.bits.br_mask) & (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) \| (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts) ) ) val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta)) for (w <- 0 until bankWidth) { s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets)) s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w) } for (w <- 0 until nWays) { when (doing_reset \|\| s1_update_meta.write_way === w.U \|\| (w == 0 && nWays == 1).B) { btb(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }), VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wbtb_mask).asBools ) meta(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }), VecInit(s1_update_wmeta_data.map(_.asUInt))), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmeta_mask).asBools ) } } when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) { ebtb.write(s1_update_idx, s1_update.bits.target) } }	module BTBBranchPredictorBank( // @[btb.scala:23:7] input clock, // @[btb.scala:23:7] input reset, // @[btb.scala:23:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [29:0] meta_1_MPORT_3_data_3; // @[btb.scala:183:12] wire [29:0] meta_1_MPORT_3_data_2; // @[btb.scala:183:12] wire [29:0] meta_1_MPORT_3_data_1; // @[btb.scala:183:12] wire [29:0] meta_1_MPORT_3_data_0; // @[btb.scala:183:12] wire [13:0] btb_1_MPORT_2_data_3; // @[btb.scala:172:12] wire [13:0] btb_1_MPORT_2_data_2; // @[btb.scala:172:12] wire [13:0] btb_1_MPORT_2_data_1; // @[btb.scala:172:12] wire [13:0] btb_1_MPORT_2_data_0; // @[btb.scala:172:12] wire [29:0] meta_0_MPORT_1_data_3; // @[btb.scala:183:12] wire [29:0] meta_0_MPORT_1_data_2; // @[btb.scala:183:12] wire [29:0] meta_0_MPORT_1_data_1; // @[btb.scala:183:12] wire [29:0] meta_0_MPORT_1_data_0; // @[btb.scala:183:12] wire [13:0] btb_0_MPORT_data_3; // @[btb.scala:172:12] wire [13:0] btb_0_MPORT_data_2; // @[btb.scala:172:12] wire [13:0] btb_0_MPORT_data_1; // @[btb.scala:172:12] wire [13:0] btb_0_MPORT_data_0; // @[btb.scala:172:12] wire _s1_update_meta_WIRE; // @[btb.scala:138:55] wire _s1_req_rmeta_WIRE_17_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_17_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_15_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_15_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_13_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_13_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_11_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_11_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_7_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_7_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_5_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_5_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_3_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_3_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_1_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_1_tag; // @[btb.scala:74:93] wire [12:0] _s1_req_rbtb_WIRE_17_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_17_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_15_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_15_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_13_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_13_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_11_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_11_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_7_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_7_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_5_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_5_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_3_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_3_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_1_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_1_extended; // @[btb.scala:73:93] wire [39:0] _ebtb_R0_data; // @[btb.scala:67:29] wire [55:0] _btb_1_R0_data; // @[btb.scala:66:47] wire [55:0] _btb_0_R0_data; // @[btb.scala:66:47] wire [119:0] _meta_1_R0_data; // @[btb.scala:65:47] wire [119:0] _meta_0_R0_data; // @[btb.scala:65:47] wire io_f0_valid_0 = io_f0_valid; // @[btb.scala:23:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[btb.scala:23:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[btb.scala:23:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[btb.scala:23:7] wire io_f3_fire_0 = io_f3_fire; // @[btb.scala:23:7] wire io_update_valid_0 = io_update_valid; // @[btb.scala:23:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[btb.scala:23:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[btb.scala:23:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[btb.scala:23:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[btb.scala:23:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[btb.scala:23:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[btb.scala:23:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[btb.scala:23:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[btb.scala:23:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[btb.scala:23:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[btb.scala:23:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[btb.scala:23:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[btb.scala:23:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[btb.scala:23:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[btb.scala:23:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[btb.scala:23:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[btb.scala:23:7] wire [11:0] _max_offset_value_T = 12'hFFF; // @[btb.scala:140:35] wire [12:0] _max_offset_value_T_1 = 13'hFFF; // @[btb.scala:140:{29,59}] wire [12:0] max_offset_value = 13'hFFF; // @[btb.scala:140:59] wire [12:0] _min_offset_value_T = 13'h1000; // @[btb.scala:141:{29,59}] wire [12:0] min_offset_value = 13'h1000; // @[btb.scala:141:59] wire io_f1_lhist = 1'h0; // @[btb.scala:23:7] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[btb.scala:23:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[btb.scala:23:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[btb.scala:23:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[btb.scala:23:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_0_taken_0; // @[btb.scala:23:7] wire io_resp_f2_0_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_0_is_jal_0; // @[btb.scala:23:7] wire io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_1_taken_0; // @[btb.scala:23:7] wire io_resp_f2_1_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_1_is_jal_0; // @[btb.scala:23:7] wire io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_2_taken_0; // @[btb.scala:23:7] wire io_resp_f2_2_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_2_is_jal_0; // @[btb.scala:23:7] wire io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_3_taken_0; // @[btb.scala:23:7] wire io_resp_f2_3_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_3_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_0_taken_0; // @[btb.scala:23:7] wire io_resp_f3_0_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_0_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_1_taken_0; // @[btb.scala:23:7] wire io_resp_f3_1_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_1_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_2_taken_0; // @[btb.scala:23:7] wire io_resp_f3_2_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_2_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_3_taken_0; // @[btb.scala:23:7] wire io_resp_f3_3_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_3_is_jal_0; // @[btb.scala:23:7] wire [119:0] io_f3_meta_0; // @[btb.scala:23:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35] wire [35:0] _s1_req_rbtb_WIRE = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rbtb_WIRE_10 = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rmeta_WIRE = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rmeta_WIRE_10 = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rebtb_WIRE = s0_idx; // @[frontend.scala:162:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_0_bits_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_1_bits_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_2_bits_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_3_bits_T = s1_pc; // @[predictor.scala:178:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] wire [39:0] _new_offset_value_T = s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [35:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire _s1_meta_write_way_T_13; // @[btb.scala:133:27] wire s1_meta_write_way; // @[btb.scala:52:21] reg f3_meta_REG_write_way; // @[btb.scala:53:32] reg f3_meta_write_way; // @[btb.scala:53:24] assign io_f3_meta_0 = {119'h0, f3_meta_write_way}; // @[btb.scala:23:7, :53:24, :56:14] reg doing_reset; // @[btb.scala:60:28] reg [6:0] reset_idx; // @[btb.scala:61:28] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[btb.scala:60:28, :61:28, :62:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[btb.scala:62:26] wire [29:0] _s1_req_rmeta_WIRE_2 = _meta_0_R0_data[29:0]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_4 = _meta_0_R0_data[59:30]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_6 = _meta_0_R0_data[89:60]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_8 = _meta_0_R0_data[119:90]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_12 = _meta_1_R0_data[29:0]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_14 = _meta_1_R0_data[59:30]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_16 = _meta_1_R0_data[89:60]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_18 = _meta_1_R0_data[119:90]; // @[btb.scala:65:47, :74:93] wire [13:0] _s1_req_rbtb_WIRE_2 = _btb_0_R0_data[13:0]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_4 = _btb_0_R0_data[27:14]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_6 = _btb_0_R0_data[41:28]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_8 = _btb_0_R0_data[55:42]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_12 = _btb_1_R0_data[13:0]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_14 = _btb_1_R0_data[27:14]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_16 = _btb_1_R0_data[41:28]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_18 = _btb_1_R0_data[55:42]; // @[btb.scala:66:47, :73:93] wire [6:0] _s1_req_rbtb_T = _s1_req_rbtb_WIRE[6:0]; // @[btb.scala:73:59] wire [12:0] _s1_req_rbtb_T_3; // @[btb.scala:73:93] wire _s1_req_rbtb_T_1; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_0_offset = _s1_req_rbtb_WIRE_1_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_0_extended = _s1_req_rbtb_WIRE_1_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_1 = _s1_req_rbtb_WIRE_2[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_1_extended = _s1_req_rbtb_T_1; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_2 = _s1_req_rbtb_WIRE_2[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_3 = _s1_req_rbtb_T_2; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_1_offset = _s1_req_rbtb_T_3; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_6; // @[btb.scala:73:93] wire _s1_req_rbtb_T_4; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_1_offset = _s1_req_rbtb_WIRE_3_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_1_extended = _s1_req_rbtb_WIRE_3_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_4 = _s1_req_rbtb_WIRE_4[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_3_extended = _s1_req_rbtb_T_4; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_5 = _s1_req_rbtb_WIRE_4[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_6 = _s1_req_rbtb_T_5; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_3_offset = _s1_req_rbtb_T_6; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_9; // @[btb.scala:73:93] wire _s1_req_rbtb_T_7; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_2_offset = _s1_req_rbtb_WIRE_5_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_2_extended = _s1_req_rbtb_WIRE_5_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_7 = _s1_req_rbtb_WIRE_6[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_5_extended = _s1_req_rbtb_T_7; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_8 = _s1_req_rbtb_WIRE_6[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_9 = _s1_req_rbtb_T_8; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_5_offset = _s1_req_rbtb_T_9; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_12; // @[btb.scala:73:93] wire _s1_req_rbtb_T_10; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_3_offset = _s1_req_rbtb_WIRE_7_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_3_extended = _s1_req_rbtb_WIRE_7_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_10 = _s1_req_rbtb_WIRE_8[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_7_extended = _s1_req_rbtb_T_10; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_11 = _s1_req_rbtb_WIRE_8[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_12 = _s1_req_rbtb_T_11; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_7_offset = _s1_req_rbtb_T_12; // @[btb.scala:73:93] wire [12:0] s1_req_rbtb_0_0_offset = _s1_req_rbtb_WIRE_9_0_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_0_extended = _s1_req_rbtb_WIRE_9_0_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_0_1_offset = _s1_req_rbtb_WIRE_9_1_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_1_extended = _s1_req_rbtb_WIRE_9_1_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_0_2_offset = _s1_req_rbtb_WIRE_9_2_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_2_extended = _s1_req_rbtb_WIRE_9_2_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_0_3_offset = _s1_req_rbtb_WIRE_9_3_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_3_extended = _s1_req_rbtb_WIRE_9_3_extended; // @[btb.scala:73:{29,52}] wire [6:0] _s1_req_rbtb_T_13 = _s1_req_rbtb_WIRE_10[6:0]; // @[btb.scala:73:59] wire [12:0] _s1_req_rbtb_T_16; // @[btb.scala:73:93] wire _s1_req_rbtb_T_14; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_0_offset = _s1_req_rbtb_WIRE_11_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_0_extended = _s1_req_rbtb_WIRE_11_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_14 = _s1_req_rbtb_WIRE_12[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_11_extended = _s1_req_rbtb_T_14; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_15 = _s1_req_rbtb_WIRE_12[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_16 = _s1_req_rbtb_T_15; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_11_offset = _s1_req_rbtb_T_16; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_19; // @[btb.scala:73:93] wire _s1_req_rbtb_T_17; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_1_offset = _s1_req_rbtb_WIRE_13_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_1_extended = _s1_req_rbtb_WIRE_13_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_17 = _s1_req_rbtb_WIRE_14[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_13_extended = _s1_req_rbtb_T_17; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_18 = _s1_req_rbtb_WIRE_14[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_19 = _s1_req_rbtb_T_18; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_13_offset = _s1_req_rbtb_T_19; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_22; // @[btb.scala:73:93] wire _s1_req_rbtb_T_20; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_2_offset = _s1_req_rbtb_WIRE_15_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_2_extended = _s1_req_rbtb_WIRE_15_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_20 = _s1_req_rbtb_WIRE_16[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_15_extended = _s1_req_rbtb_T_20; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_21 = _s1_req_rbtb_WIRE_16[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_22 = _s1_req_rbtb_T_21; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_15_offset = _s1_req_rbtb_T_22; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_25; // @[btb.scala:73:93] wire _s1_req_rbtb_T_23; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_3_offset = _s1_req_rbtb_WIRE_17_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_3_extended = _s1_req_rbtb_WIRE_17_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_23 = _s1_req_rbtb_WIRE_18[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_17_extended = _s1_req_rbtb_T_23; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_24 = _s1_req_rbtb_WIRE_18[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_25 = _s1_req_rbtb_T_24; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_17_offset = _s1_req_rbtb_T_25; // @[btb.scala:73:93] wire [12:0] s1_req_rbtb_1_0_offset = _s1_req_rbtb_WIRE_19_0_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_0_extended = _s1_req_rbtb_WIRE_19_0_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_1_1_offset = _s1_req_rbtb_WIRE_19_1_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_1_extended = _s1_req_rbtb_WIRE_19_1_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_1_2_offset = _s1_req_rbtb_WIRE_19_2_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_2_extended = _s1_req_rbtb_WIRE_19_2_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_1_3_offset = _s1_req_rbtb_WIRE_19_3_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_3_extended = _s1_req_rbtb_WIRE_19_3_extended; // @[btb.scala:73:{29,52}] wire [6:0] _s1_req_rmeta_T = _s1_req_rmeta_WIRE[6:0]; // @[btb.scala:74:60] wire _s1_req_rmeta_T_2; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_1; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_0_is_br = _s1_req_rmeta_WIRE_1_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_0_tag = _s1_req_rmeta_WIRE_1_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_1 = _s1_req_rmeta_WIRE_2[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_1_tag = _s1_req_rmeta_T_1; // @[btb.scala:74:93] assign _s1_req_rmeta_T_2 = _s1_req_rmeta_WIRE_2[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_1_is_br = _s1_req_rmeta_T_2; // @[btb.scala:74:93] wire _s1_req_rmeta_T_4; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_3; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_1_is_br = _s1_req_rmeta_WIRE_3_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_1_tag = _s1_req_rmeta_WIRE_3_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_3 = _s1_req_rmeta_WIRE_4[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_3_tag = _s1_req_rmeta_T_3; // @[btb.scala:74:93] assign _s1_req_rmeta_T_4 = _s1_req_rmeta_WIRE_4[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_3_is_br = _s1_req_rmeta_T_4; // @[btb.scala:74:93] wire _s1_req_rmeta_T_6; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_5; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_2_is_br = _s1_req_rmeta_WIRE_5_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_2_tag = _s1_req_rmeta_WIRE_5_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_5 = _s1_req_rmeta_WIRE_6[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_5_tag = _s1_req_rmeta_T_5; // @[btb.scala:74:93] assign _s1_req_rmeta_T_6 = _s1_req_rmeta_WIRE_6[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_5_is_br = _s1_req_rmeta_T_6; // @[btb.scala:74:93] wire _s1_req_rmeta_T_8; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_7; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_3_is_br = _s1_req_rmeta_WIRE_7_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_3_tag = _s1_req_rmeta_WIRE_7_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_7 = _s1_req_rmeta_WIRE_8[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_7_tag = _s1_req_rmeta_T_7; // @[btb.scala:74:93] assign _s1_req_rmeta_T_8 = _s1_req_rmeta_WIRE_8[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_7_is_br = _s1_req_rmeta_T_8; // @[btb.scala:74:93] wire s1_req_rmeta_0_0_is_br = _s1_req_rmeta_WIRE_9_0_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_0_tag = _s1_req_rmeta_WIRE_9_0_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_0_1_is_br = _s1_req_rmeta_WIRE_9_1_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_1_tag = _s1_req_rmeta_WIRE_9_1_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_0_2_is_br = _s1_req_rmeta_WIRE_9_2_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_2_tag = _s1_req_rmeta_WIRE_9_2_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_0_3_is_br = _s1_req_rmeta_WIRE_9_3_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_3_tag = _s1_req_rmeta_WIRE_9_3_tag; // @[btb.scala:74:{29,53}] wire [6:0] _s1_req_rmeta_T_9 = _s1_req_rmeta_WIRE_10[6:0]; // @[btb.scala:74:60] wire _s1_req_rmeta_T_11; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_10; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_0_is_br = _s1_req_rmeta_WIRE_11_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_0_tag = _s1_req_rmeta_WIRE_11_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_10 = _s1_req_rmeta_WIRE_12[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_11_tag = _s1_req_rmeta_T_10; // @[btb.scala:74:93] assign _s1_req_rmeta_T_11 = _s1_req_rmeta_WIRE_12[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_11_is_br = _s1_req_rmeta_T_11; // @[btb.scala:74:93] wire _s1_req_rmeta_T_13; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_12; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_1_is_br = _s1_req_rmeta_WIRE_13_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_1_tag = _s1_req_rmeta_WIRE_13_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_12 = _s1_req_rmeta_WIRE_14[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_13_tag = _s1_req_rmeta_T_12; // @[btb.scala:74:93] assign _s1_req_rmeta_T_13 = _s1_req_rmeta_WIRE_14[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_13_is_br = _s1_req_rmeta_T_13; // @[btb.scala:74:93] wire _s1_req_rmeta_T_15; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_14; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_2_is_br = _s1_req_rmeta_WIRE_15_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_2_tag = _s1_req_rmeta_WIRE_15_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_14 = _s1_req_rmeta_WIRE_16[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_15_tag = _s1_req_rmeta_T_14; // @[btb.scala:74:93] assign _s1_req_rmeta_T_15 = _s1_req_rmeta_WIRE_16[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_15_is_br = _s1_req_rmeta_T_15; // @[btb.scala:74:93] wire _s1_req_rmeta_T_17; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_16; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_3_is_br = _s1_req_rmeta_WIRE_17_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_3_tag = _s1_req_rmeta_WIRE_17_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_16 = _s1_req_rmeta_WIRE_18[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_17_tag = _s1_req_rmeta_T_16; // @[btb.scala:74:93] assign _s1_req_rmeta_T_17 = _s1_req_rmeta_WIRE_18[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_17_is_br = _s1_req_rmeta_T_17; // @[btb.scala:74:93] wire s1_req_rmeta_1_0_is_br = _s1_req_rmeta_WIRE_19_0_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_0_tag = _s1_req_rmeta_WIRE_19_0_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_1_1_is_br = _s1_req_rmeta_WIRE_19_1_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_1_tag = _s1_req_rmeta_WIRE_19_1_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_1_2_is_br = _s1_req_rmeta_WIRE_19_2_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_2_tag = _s1_req_rmeta_WIRE_19_2_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_1_3_is_br = _s1_req_rmeta_WIRE_19_3_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_3_tag = _s1_req_rmeta_WIRE_19_3_tag; // @[btb.scala:74:{29,53}] wire [28:0] _alloc_way_r_metas_WIRE_0 = s1_req_rmeta_0_0_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1 = s1_req_rmeta_0_1_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_2 = s1_req_rmeta_0_2_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_3 = s1_req_rmeta_0_3_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_0 = s1_req_rmeta_1_0_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_1 = s1_req_rmeta_1_1_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_2 = s1_req_rmeta_1_2_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_3 = s1_req_rmeta_1_3_tag; // @[btb.scala:74:29, :123:62] wire [6:0] _s1_req_rebtb_T = _s1_req_rebtb_WIRE[6:0]; // @[btb.scala:75:31] wire [28:0] s1_req_tag = s1_idx[35:7]; // @[predictor.scala:163:29] wire [28:0] _s1_hit_ohs_T = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_2 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_4 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_6 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_8 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_10 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_12 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_14 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _alloc_way_r_metas_T_3 = s1_req_tag; // @[btb.scala:76:29, :123:98] wire _s1_resp_0_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_0_bits_T_8; // @[btb.scala:94:28] wire _s1_resp_1_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_1_bits_T_8; // @[btb.scala:94:28] wire _s1_resp_2_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_2_bits_T_8; // @[btb.scala:94:28] wire _s1_resp_3_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_3_bits_T_8; // @[btb.scala:94:28] wire s1_resp_0_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_0_bits; // @[btb.scala:78:23] wire s1_resp_1_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_1_bits; // @[btb.scala:78:23] wire s1_resp_2_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_2_bits; // @[btb.scala:78:23] wire s1_resp_3_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_3_bits; // @[btb.scala:78:23] wire _s1_is_br_0_T_2; // @[btb.scala:98:54] wire _s1_is_br_1_T_2; // @[btb.scala:98:54] wire _s1_is_br_2_T_2; // @[btb.scala:98:54] wire _s1_is_br_3_T_2; // @[btb.scala:98:54] wire s1_is_br_0; // @[btb.scala:79:23] wire s1_is_br_1; // @[btb.scala:79:23] wire s1_is_br_2; // @[btb.scala:79:23] wire s1_is_br_3; // @[btb.scala:79:23] wire _s1_is_jal_0_T_3; // @[btb.scala:99:54] wire _s1_is_jal_1_T_3; // @[btb.scala:99:54] wire _s1_is_jal_2_T_3; // @[btb.scala:99:54] wire _s1_is_jal_3_T_3; // @[btb.scala:99:54] wire s1_is_jal_0; // @[btb.scala:80:23] wire s1_is_jal_1; // @[btb.scala:80:23] wire s1_is_jal_2; // @[btb.scala:80:23] wire s1_is_jal_3; // @[btb.scala:80:23] wire _s1_hit_ohs_T_1 = s1_req_rmeta_0_0_tag == _s1_hit_ohs_T; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_0 = _s1_hit_ohs_T_1; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_3 = s1_req_rmeta_1_0_tag == _s1_hit_ohs_T_2; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_1 = _s1_hit_ohs_T_3; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_0_0 = _s1_hit_ohs_WIRE_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_0_1 = _s1_hit_ohs_WIRE_1; // @[btb.scala:82:27, :83:12] wire _s1_hit_ohs_T_5 = s1_req_rmeta_0_1_tag == _s1_hit_ohs_T_4; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_1_0 = _s1_hit_ohs_T_5; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_7 = s1_req_rmeta_1_1_tag == _s1_hit_ohs_T_6; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_1_1 = _s1_hit_ohs_T_7; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_1_0 = _s1_hit_ohs_WIRE_1_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_1_1 = _s1_hit_ohs_WIRE_1_1; // @[btb.scala:82:27, :83:12] wire _s1_hit_ohs_T_9 = s1_req_rmeta_0_2_tag == _s1_hit_ohs_T_8; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_2_0 = _s1_hit_ohs_T_9; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_11 = s1_req_rmeta_1_2_tag == _s1_hit_ohs_T_10; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_2_1 = _s1_hit_ohs_T_11; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_2_0 = _s1_hit_ohs_WIRE_2_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_2_1 = _s1_hit_ohs_WIRE_2_1; // @[btb.scala:82:27, :83:12] wire _s1_hit_ohs_T_13 = s1_req_rmeta_0_3_tag == _s1_hit_ohs_T_12; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_3_0 = _s1_hit_ohs_T_13; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_15 = s1_req_rmeta_1_3_tag == _s1_hit_ohs_T_14; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_3_1 = _s1_hit_ohs_T_15; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_3_0 = _s1_hit_ohs_WIRE_3_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_3_1 = _s1_hit_ohs_WIRE_3_1; // @[btb.scala:82:27, :83:12] wire s1_hits_0 = s1_hit_ohs_0_0 \| s1_hit_ohs_0_1; // @[btb.scala:82:27, :87:55] wire s1_hits_1 = s1_hit_ohs_1_0 \| s1_hit_ohs_1_1; // @[btb.scala:82:27, :87:55] wire s1_hits_2 = s1_hit_ohs_2_0 \| s1_hit_ohs_2_1; // @[btb.scala:82:27, :87:55] wire s1_hits_3 = s1_hit_ohs_3_0 \| s1_hit_ohs_3_1; // @[btb.scala:82:27, :87:55] wire s1_hit_ways_0 = ~s1_hit_ohs_0_0; // @[Mux.scala:50:70] wire s1_hit_ways_1 = ~s1_hit_ohs_1_0; // @[Mux.scala:50:70] wire s1_hit_ways_2 = ~s1_hit_ohs_2_0; // @[Mux.scala:50:70] wire s1_hit_ways_3 = ~s1_hit_ohs_3_0; // @[Mux.scala:50:70] wire _s1_resp_0_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_0_valid_T_1 = _s1_resp_0_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_0_valid_T_2 = _s1_resp_0_valid_T_1 & s1_hits_0; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_0_valid = _s1_resp_0_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_0_bits_T_1 = {_s1_resp_0_bits_T[39], _s1_resp_0_bits_T}; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_0_bits_T_2 = _s1_resp_0_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_0_bits_T_3 = _s1_resp_0_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN = s1_hit_ways_0 ? s1_req_rbtb_1_0_offset : s1_req_rbtb_0_0_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_0_bits_T_4 = {_s1_resp_0_bits_T_3[39], _s1_resp_0_bits_T_3} + {{28{_GEN[12]}}, _GEN}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_0_bits_T_5 = _s1_resp_0_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_0_bits_T_6 = _s1_resp_0_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_0_bits_T_7 = _s1_resp_0_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_0_bits_T_8 = (s1_hit_ways_0 ? s1_req_rbtb_1_0_extended : s1_req_rbtb_0_0_extended) ? _ebtb_R0_data : _s1_resp_0_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_0_bits = _s1_resp_0_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_0_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_0_T_1 = _s1_is_br_0_T & s1_resp_0_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_0 = s1_hit_ways_0 ? s1_req_rmeta_1_0_is_br : s1_req_rmeta_0_0_is_br; // @[Mux.scala:50:70] assign _s1_is_br_0_T_2 = _s1_is_br_0_T_1 & _GEN_0; // @[btb.scala:98:{34,54}] assign s1_is_br_0 = _s1_is_br_0_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_0_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_0_T_1 = _s1_is_jal_0_T & s1_resp_0_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_0_T_2 = ~_GEN_0; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_0_T_3 = _s1_is_jal_0_T_1 & _s1_is_jal_0_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_0 = _s1_is_jal_0_T_3; // @[btb.scala:80:23, :99:54] reg REG; // @[btb.scala:104:18] reg io_resp_f2_0_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_0_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_0_predicted_pc_valid_0 = REG ? io_resp_f2_0_predicted_pc_REG_valid : io_resp_in_0_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_0_predicted_pc_bits_0 = REG ? io_resp_f2_0_predicted_pc_REG_bits : io_resp_in_0_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_0_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_0_is_br_0 = REG ? io_resp_f2_0_is_br_REG : io_resp_in_0_f2_0_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_0_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_0_is_jal_0 = REG ? io_resp_f2_0_is_jal_REG : io_resp_in_0_f2_0_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_1; // @[btb.scala:108:20] assign io_resp_f2_0_taken_0 = REG & REG_1 \| io_resp_in_0_f2_0_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_2; // @[btb.scala:112:26] reg REG_3; // @[btb.scala:112:18] reg io_resp_f3_0_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_0_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_0_predicted_pc_valid_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_valid : io_resp_in_0_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_0_predicted_pc_bits_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_bits : io_resp_in_0_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_0_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_0_is_br_0 = REG_3 ? io_resp_f3_0_is_br_REG : io_resp_in_0_f3_0_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_0_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_0_is_jal_0 = REG_3 ? io_resp_f3_0_is_jal_REG : io_resp_in_0_f3_0_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_4; // @[btb.scala:116:28] reg REG_5; // @[btb.scala:116:20] assign io_resp_f3_0_taken_0 = REG_3 & REG_5 \| io_resp_in_0_f3_0_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire _s1_resp_1_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_1_valid_T_1 = _s1_resp_1_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_1_valid_T_2 = _s1_resp_1_valid_T_1 & s1_hits_1; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_1_valid = _s1_resp_1_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_1_bits_T_1 = {_s1_resp_1_bits_T[39], _s1_resp_1_bits_T} + 41'h2; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_1_bits_T_2 = _s1_resp_1_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_1_bits_T_3 = _s1_resp_1_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN_1 = s1_hit_ways_1 ? s1_req_rbtb_1_1_offset : s1_req_rbtb_0_1_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_1_bits_T_4 = {_s1_resp_1_bits_T_3[39], _s1_resp_1_bits_T_3} + {{28{_GEN_1[12]}}, _GEN_1}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_1_bits_T_5 = _s1_resp_1_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_1_bits_T_6 = _s1_resp_1_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_1_bits_T_7 = _s1_resp_1_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_1_bits_T_8 = (s1_hit_ways_1 ? s1_req_rbtb_1_1_extended : s1_req_rbtb_0_1_extended) ? _ebtb_R0_data : _s1_resp_1_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_1_bits = _s1_resp_1_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_1_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_1_T_1 = _s1_is_br_1_T & s1_resp_1_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_2 = s1_hit_ways_1 ? s1_req_rmeta_1_1_is_br : s1_req_rmeta_0_1_is_br; // @[Mux.scala:50:70] assign _s1_is_br_1_T_2 = _s1_is_br_1_T_1 & _GEN_2; // @[btb.scala:98:{34,54}] assign s1_is_br_1 = _s1_is_br_1_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_1_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_1_T_1 = _s1_is_jal_1_T & s1_resp_1_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_1_T_2 = ~_GEN_2; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_1_T_3 = _s1_is_jal_1_T_1 & _s1_is_jal_1_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_1 = _s1_is_jal_1_T_3; // @[btb.scala:80:23, :99:54] reg REG_6; // @[btb.scala:104:18] reg io_resp_f2_1_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_1_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_1_predicted_pc_valid_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_valid : io_resp_in_0_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_1_predicted_pc_bits_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_bits : io_resp_in_0_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_1_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_1_is_br_0 = REG_6 ? io_resp_f2_1_is_br_REG : io_resp_in_0_f2_1_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_1_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_1_is_jal_0 = REG_6 ? io_resp_f2_1_is_jal_REG : io_resp_in_0_f2_1_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_7; // @[btb.scala:108:20] assign io_resp_f2_1_taken_0 = REG_6 & REG_7 \| io_resp_in_0_f2_1_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_8; // @[btb.scala:112:26] reg REG_9; // @[btb.scala:112:18] reg io_resp_f3_1_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_1_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_1_predicted_pc_valid_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_valid : io_resp_in_0_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_1_predicted_pc_bits_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_bits : io_resp_in_0_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_1_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_1_is_br_0 = REG_9 ? io_resp_f3_1_is_br_REG : io_resp_in_0_f3_1_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_1_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_1_is_jal_0 = REG_9 ? io_resp_f3_1_is_jal_REG : io_resp_in_0_f3_1_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_10; // @[btb.scala:116:28] reg REG_11; // @[btb.scala:116:20] assign io_resp_f3_1_taken_0 = REG_9 & REG_11 \| io_resp_in_0_f3_1_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire _s1_resp_2_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_2_valid_T_1 = _s1_resp_2_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_2_valid_T_2 = _s1_resp_2_valid_T_1 & s1_hits_2; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_2_valid = _s1_resp_2_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_2_bits_T_1 = {_s1_resp_2_bits_T[39], _s1_resp_2_bits_T} + 41'h4; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_2_bits_T_2 = _s1_resp_2_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_2_bits_T_3 = _s1_resp_2_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN_3 = s1_hit_ways_2 ? s1_req_rbtb_1_2_offset : s1_req_rbtb_0_2_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_2_bits_T_4 = {_s1_resp_2_bits_T_3[39], _s1_resp_2_bits_T_3} + {{28{_GEN_3[12]}}, _GEN_3}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_2_bits_T_5 = _s1_resp_2_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_2_bits_T_6 = _s1_resp_2_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_2_bits_T_7 = _s1_resp_2_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_2_bits_T_8 = (s1_hit_ways_2 ? s1_req_rbtb_1_2_extended : s1_req_rbtb_0_2_extended) ? _ebtb_R0_data : _s1_resp_2_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_2_bits = _s1_resp_2_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_2_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_2_T_1 = _s1_is_br_2_T & s1_resp_2_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_4 = s1_hit_ways_2 ? s1_req_rmeta_1_2_is_br : s1_req_rmeta_0_2_is_br; // @[Mux.scala:50:70] assign _s1_is_br_2_T_2 = _s1_is_br_2_T_1 & _GEN_4; // @[btb.scala:98:{34,54}] assign s1_is_br_2 = _s1_is_br_2_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_2_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_2_T_1 = _s1_is_jal_2_T & s1_resp_2_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_2_T_2 = ~_GEN_4; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_2_T_3 = _s1_is_jal_2_T_1 & _s1_is_jal_2_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_2 = _s1_is_jal_2_T_3; // @[btb.scala:80:23, :99:54] reg REG_12; // @[btb.scala:104:18] reg io_resp_f2_2_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_2_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_2_predicted_pc_valid_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_valid : io_resp_in_0_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_2_predicted_pc_bits_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_bits : io_resp_in_0_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_2_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_2_is_br_0 = REG_12 ? io_resp_f2_2_is_br_REG : io_resp_in_0_f2_2_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_2_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_2_is_jal_0 = REG_12 ? io_resp_f2_2_is_jal_REG : io_resp_in_0_f2_2_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_13; // @[btb.scala:108:20] assign io_resp_f2_2_taken_0 = REG_12 & REG_13 \| io_resp_in_0_f2_2_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_14; // @[btb.scala:112:26] reg REG_15; // @[btb.scala:112:18] reg io_resp_f3_2_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_2_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_2_predicted_pc_valid_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_valid : io_resp_in_0_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_2_predicted_pc_bits_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_bits : io_resp_in_0_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_2_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_2_is_br_0 = REG_15 ? io_resp_f3_2_is_br_REG : io_resp_in_0_f3_2_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_2_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_2_is_jal_0 = REG_15 ? io_resp_f3_2_is_jal_REG : io_resp_in_0_f3_2_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_16; // @[btb.scala:116:28] reg REG_17; // @[btb.scala:116:20] assign io_resp_f3_2_taken_0 = REG_15 & REG_17 \| io_resp_in_0_f3_2_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire _s1_resp_3_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_3_valid_T_1 = _s1_resp_3_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_3_valid_T_2 = _s1_resp_3_valid_T_1 & s1_hits_3; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_3_valid = _s1_resp_3_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_3_bits_T_1 = {_s1_resp_3_bits_T[39], _s1_resp_3_bits_T} + 41'h6; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_3_bits_T_2 = _s1_resp_3_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_3_bits_T_3 = _s1_resp_3_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN_5 = s1_hit_ways_3 ? s1_req_rbtb_1_3_offset : s1_req_rbtb_0_3_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_3_bits_T_4 = {_s1_resp_3_bits_T_3[39], _s1_resp_3_bits_T_3} + {{28{_GEN_5[12]}}, _GEN_5}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_3_bits_T_5 = _s1_resp_3_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_3_bits_T_6 = _s1_resp_3_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_3_bits_T_7 = _s1_resp_3_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_3_bits_T_8 = (s1_hit_ways_3 ? s1_req_rbtb_1_3_extended : s1_req_rbtb_0_3_extended) ? _ebtb_R0_data : _s1_resp_3_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_3_bits = _s1_resp_3_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_3_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_3_T_1 = _s1_is_br_3_T & s1_resp_3_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_6 = s1_hit_ways_3 ? s1_req_rmeta_1_3_is_br : s1_req_rmeta_0_3_is_br; // @[Mux.scala:50:70] assign _s1_is_br_3_T_2 = _s1_is_br_3_T_1 & _GEN_6; // @[btb.scala:98:{34,54}] assign s1_is_br_3 = _s1_is_br_3_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_3_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_3_T_1 = _s1_is_jal_3_T & s1_resp_3_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_3_T_2 = ~_GEN_6; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_3_T_3 = _s1_is_jal_3_T_1 & _s1_is_jal_3_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_3 = _s1_is_jal_3_T_3; // @[btb.scala:80:23, :99:54] reg REG_18; // @[btb.scala:104:18] reg io_resp_f2_3_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_3_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_3_predicted_pc_valid_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_valid : io_resp_in_0_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_3_predicted_pc_bits_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_bits : io_resp_in_0_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_3_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_3_is_br_0 = REG_18 ? io_resp_f2_3_is_br_REG : io_resp_in_0_f2_3_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_3_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_3_is_jal_0 = REG_18 ? io_resp_f2_3_is_jal_REG : io_resp_in_0_f2_3_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_19; // @[btb.scala:108:20] assign io_resp_f2_3_taken_0 = REG_18 & REG_19 \| io_resp_in_0_f2_3_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_20; // @[btb.scala:112:26] reg REG_21; // @[btb.scala:112:18] reg io_resp_f3_3_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_3_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_3_predicted_pc_valid_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_valid : io_resp_in_0_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_3_predicted_pc_bits_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_bits : io_resp_in_0_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_3_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_3_is_br_0 = REG_21 ? io_resp_f3_3_is_br_REG : io_resp_in_0_f3_3_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_3_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_3_is_jal_0 = REG_21 ? io_resp_f3_3_is_jal_REG : io_resp_in_0_f3_3_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_22; // @[btb.scala:116:28] reg REG_23; // @[btb.scala:116:20] assign io_resp_f3_3_taken_0 = REG_21 & REG_23 \| io_resp_in_0_f3_3_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire [28:0] _alloc_way_r_metas_WIRE_2_0_0 = _alloc_way_r_metas_WIRE_0; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_1 = _alloc_way_r_metas_WIRE_1; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_2 = _alloc_way_r_metas_WIRE_2; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_3 = _alloc_way_r_metas_WIRE_3; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_0 = _alloc_way_r_metas_WIRE_1_0; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_1 = _alloc_way_r_metas_WIRE_1_1; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_2 = _alloc_way_r_metas_WIRE_1_2; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_3 = _alloc_way_r_metas_WIRE_1_3; // @[btb.scala:123:{30,62}] wire [57:0] alloc_way_r_metas_lo = {_alloc_way_r_metas_WIRE_2_0_1, _alloc_way_r_metas_WIRE_2_0_0}; // @[btb.scala:123:{30,80}] wire [57:0] alloc_way_r_metas_hi = {_alloc_way_r_metas_WIRE_2_0_3, _alloc_way_r_metas_WIRE_2_0_2}; // @[btb.scala:123:{30,80}] wire [115:0] _alloc_way_r_metas_T = {alloc_way_r_metas_hi, alloc_way_r_metas_lo}; // @[btb.scala:123:80] wire [57:0] alloc_way_r_metas_lo_1 = {_alloc_way_r_metas_WIRE_2_1_1, _alloc_way_r_metas_WIRE_2_1_0}; // @[btb.scala:123:{30,80}] wire [57:0] alloc_way_r_metas_hi_1 = {_alloc_way_r_metas_WIRE_2_1_3, _alloc_way_r_metas_WIRE_2_1_2}; // @[btb.scala:123:{30,80}] wire [115:0] _alloc_way_r_metas_T_1 = {alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1}; // @[btb.scala:123:80] wire [231:0] _alloc_way_r_metas_T_2 = {_alloc_way_r_metas_T_1, _alloc_way_r_metas_T}; // @[btb.scala:123:80] wire [260:0] alloc_way_r_metas = {_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3}; // @[btb.scala:123:{22,80,98}] wire alloc_way_chunks_0 = alloc_way_r_metas[0]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_1 = alloc_way_r_metas[1]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_2 = alloc_way_r_metas[2]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_3 = alloc_way_r_metas[3]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_4 = alloc_way_r_metas[4]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_5 = alloc_way_r_metas[5]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_6 = alloc_way_r_metas[6]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_7 = alloc_way_r_metas[7]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_8 = alloc_way_r_metas[8]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_9 = alloc_way_r_metas[9]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_10 = alloc_way_r_metas[10]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_11 = alloc_way_r_metas[11]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_12 = alloc_way_r_metas[12]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_13 = alloc_way_r_metas[13]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_14 = alloc_way_r_metas[14]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_15 = alloc_way_r_metas[15]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_16 = alloc_way_r_metas[16]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_17 = alloc_way_r_metas[17]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_18 = alloc_way_r_metas[18]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_19 = alloc_way_r_metas[19]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_20 = alloc_way_r_metas[20]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_21 = alloc_way_r_metas[21]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_22 = alloc_way_r_metas[22]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_23 = alloc_way_r_metas[23]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_24 = alloc_way_r_metas[24]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_25 = alloc_way_r_metas[25]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_26 = alloc_way_r_metas[26]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_27 = alloc_way_r_metas[27]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_28 = alloc_way_r_metas[28]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_29 = alloc_way_r_metas[29]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_30 = alloc_way_r_metas[30]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_31 = alloc_way_r_metas[31]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_32 = alloc_way_r_metas[32]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_33 = alloc_way_r_metas[33]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_34 = alloc_way_r_metas[34]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_35 = alloc_way_r_metas[35]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_36 = alloc_way_r_metas[36]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_37 = alloc_way_r_metas[37]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_38 = alloc_way_r_metas[38]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_39 = alloc_way_r_metas[39]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_40 = alloc_way_r_metas[40]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_41 = alloc_way_r_metas[41]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_42 = alloc_way_r_metas[42]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_43 = alloc_way_r_metas[43]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_44 = alloc_way_r_metas[44]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_45 = alloc_way_r_metas[45]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_46 = alloc_way_r_metas[46]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_47 = alloc_way_r_metas[47]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_48 = alloc_way_r_metas[48]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_49 = alloc_way_r_metas[49]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_50 = alloc_way_r_metas[50]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_51 = alloc_way_r_metas[51]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_52 = alloc_way_r_metas[52]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_53 = alloc_way_r_metas[53]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_54 = alloc_way_r_metas[54]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_55 = alloc_way_r_metas[55]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_56 = alloc_way_r_metas[56]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_57 = alloc_way_r_metas[57]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_58 = alloc_way_r_metas[58]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_59 = alloc_way_r_metas[59]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_60 = alloc_way_r_metas[60]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_61 = alloc_way_r_metas[61]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_62 = alloc_way_r_metas[62]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_63 = alloc_way_r_metas[63]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_64 = alloc_way_r_metas[64]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_65 = alloc_way_r_metas[65]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_66 = alloc_way_r_metas[66]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_67 = alloc_way_r_metas[67]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_68 = alloc_way_r_metas[68]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_69 = alloc_way_r_metas[69]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_70 = alloc_way_r_metas[70]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_71 = alloc_way_r_metas[71]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_72 = alloc_way_r_metas[72]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_73 = alloc_way_r_metas[73]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_74 = alloc_way_r_metas[74]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_75 = alloc_way_r_metas[75]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_76 = alloc_way_r_metas[76]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_77 = alloc_way_r_metas[77]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_78 = alloc_way_r_metas[78]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_79 = alloc_way_r_metas[79]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_80 = alloc_way_r_metas[80]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_81 = alloc_way_r_metas[81]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_82 = alloc_way_r_metas[82]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_83 = alloc_way_r_metas[83]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_84 = alloc_way_r_metas[84]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_85 = alloc_way_r_metas[85]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_86 = alloc_way_r_metas[86]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_87 = alloc_way_r_metas[87]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_88 = alloc_way_r_metas[88]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_89 = alloc_way_r_metas[89]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_90 = alloc_way_r_metas[90]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_91 = alloc_way_r_metas[91]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_92 = alloc_way_r_metas[92]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_93 = alloc_way_r_metas[93]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_94 = alloc_way_r_metas[94]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_95 = alloc_way_r_metas[95]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_96 = alloc_way_r_metas[96]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_97 = alloc_way_r_metas[97]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_98 = alloc_way_r_metas[98]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_99 = alloc_way_r_metas[99]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_100 = alloc_way_r_metas[100]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_101 = alloc_way_r_metas[101]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_102 = alloc_way_r_metas[102]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_103 = alloc_way_r_metas[103]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_104 = alloc_way_r_metas[104]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_105 = alloc_way_r_metas[105]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_106 = alloc_way_r_metas[106]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_107 = alloc_way_r_metas[107]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_108 = alloc_way_r_metas[108]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_109 = alloc_way_r_metas[109]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_110 = alloc_way_r_metas[110]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_111 = alloc_way_r_metas[111]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_112 = alloc_way_r_metas[112]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_113 = alloc_way_r_metas[113]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_114 = alloc_way_r_metas[114]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_115 = alloc_way_r_metas[115]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_116 = alloc_way_r_metas[116]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_117 = alloc_way_r_metas[117]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_118 = alloc_way_r_metas[118]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_119 = alloc_way_r_metas[119]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_120 = alloc_way_r_metas[120]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_121 = alloc_way_r_metas[121]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_122 = alloc_way_r_metas[122]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_123 = alloc_way_r_metas[123]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_124 = alloc_way_r_metas[124]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_125 = alloc_way_r_metas[125]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_126 = alloc_way_r_metas[126]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_127 = alloc_way_r_metas[127]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_128 = alloc_way_r_metas[128]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_129 = alloc_way_r_metas[129]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_130 = alloc_way_r_metas[130]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_131 = alloc_way_r_metas[131]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_132 = alloc_way_r_metas[132]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_133 = alloc_way_r_metas[133]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_134 = alloc_way_r_metas[134]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_135 = alloc_way_r_metas[135]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_136 = alloc_way_r_metas[136]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_137 = alloc_way_r_metas[137]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_138 = alloc_way_r_metas[138]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_139 = alloc_way_r_metas[139]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_140 = alloc_way_r_metas[140]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_141 = alloc_way_r_metas[141]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_142 = alloc_way_r_metas[142]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_143 = alloc_way_r_metas[143]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_144 = alloc_way_r_metas[144]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_145 = alloc_way_r_metas[145]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_146 = alloc_way_r_metas[146]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_147 = alloc_way_r_metas[147]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_148 = alloc_way_r_metas[148]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_149 = alloc_way_r_metas[149]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_150 = alloc_way_r_metas[150]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_151 = alloc_way_r_metas[151]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_152 = alloc_way_r_metas[152]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_153 = alloc_way_r_metas[153]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_154 = alloc_way_r_metas[154]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_155 = alloc_way_r_metas[155]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_156 = alloc_way_r_metas[156]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_157 = alloc_way_r_metas[157]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_158 = alloc_way_r_metas[158]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_159 = alloc_way_r_metas[159]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_160 = alloc_way_r_metas[160]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_161 = alloc_way_r_metas[161]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_162 = alloc_way_r_metas[162]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_163 = alloc_way_r_metas[163]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_164 = alloc_way_r_metas[164]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_165 = alloc_way_r_metas[165]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_166 = alloc_way_r_metas[166]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_167 = alloc_way_r_metas[167]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_168 = alloc_way_r_metas[168]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_169 = alloc_way_r_metas[169]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_170 = alloc_way_r_metas[170]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_171 = alloc_way_r_metas[171]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_172 = alloc_way_r_metas[172]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_173 = alloc_way_r_metas[173]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_174 = alloc_way_r_metas[174]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_175 = alloc_way_r_metas[175]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_176 = alloc_way_r_metas[176]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_177 = alloc_way_r_metas[177]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_178 = alloc_way_r_metas[178]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_179 = alloc_way_r_metas[179]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_180 = alloc_way_r_metas[180]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_181 = alloc_way_r_metas[181]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_182 = alloc_way_r_metas[182]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_183 = alloc_way_r_metas[183]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_184 = alloc_way_r_metas[184]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_185 = alloc_way_r_metas[185]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_186 = alloc_way_r_metas[186]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_187 = alloc_way_r_metas[187]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_188 = alloc_way_r_metas[188]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_189 = alloc_way_r_metas[189]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_190 = alloc_way_r_metas[190]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_191 = alloc_way_r_metas[191]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_192 = alloc_way_r_metas[192]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_193 = alloc_way_r_metas[193]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_194 = alloc_way_r_metas[194]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_195 = alloc_way_r_metas[195]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_196 = alloc_way_r_metas[196]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_197 = alloc_way_r_metas[197]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_198 = alloc_way_r_metas[198]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_199 = alloc_way_r_metas[199]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_200 = alloc_way_r_metas[200]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_201 = alloc_way_r_metas[201]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_202 = alloc_way_r_metas[202]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_203 = alloc_way_r_metas[203]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_204 = alloc_way_r_metas[204]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_205 = alloc_way_r_metas[205]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_206 = alloc_way_r_metas[206]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_207 = alloc_way_r_metas[207]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_208 = alloc_way_r_metas[208]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_209 = alloc_way_r_metas[209]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_210 = alloc_way_r_metas[210]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_211 = alloc_way_r_metas[211]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_212 = alloc_way_r_metas[212]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_213 = alloc_way_r_metas[213]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_214 = alloc_way_r_metas[214]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_215 = alloc_way_r_metas[215]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_216 = alloc_way_r_metas[216]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_217 = alloc_way_r_metas[217]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_218 = alloc_way_r_metas[218]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_219 = alloc_way_r_metas[219]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_220 = alloc_way_r_metas[220]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_221 = alloc_way_r_metas[221]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_222 = alloc_way_r_metas[222]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_223 = alloc_way_r_metas[223]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_224 = alloc_way_r_metas[224]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_225 = alloc_way_r_metas[225]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_226 = alloc_way_r_metas[226]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_227 = alloc_way_r_metas[227]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_228 = alloc_way_r_metas[228]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_229 = alloc_way_r_metas[229]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_230 = alloc_way_r_metas[230]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_231 = alloc_way_r_metas[231]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_232 = alloc_way_r_metas[232]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_233 = alloc_way_r_metas[233]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_234 = alloc_way_r_metas[234]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_235 = alloc_way_r_metas[235]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_236 = alloc_way_r_metas[236]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_237 = alloc_way_r_metas[237]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_238 = alloc_way_r_metas[238]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_239 = alloc_way_r_metas[239]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_240 = alloc_way_r_metas[240]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_241 = alloc_way_r_metas[241]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_242 = alloc_way_r_metas[242]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_243 = alloc_way_r_metas[243]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_244 = alloc_way_r_metas[244]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_245 = alloc_way_r_metas[245]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_246 = alloc_way_r_metas[246]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_247 = alloc_way_r_metas[247]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_248 = alloc_way_r_metas[248]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_249 = alloc_way_r_metas[249]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_250 = alloc_way_r_metas[250]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_251 = alloc_way_r_metas[251]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_252 = alloc_way_r_metas[252]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_253 = alloc_way_r_metas[253]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_254 = alloc_way_r_metas[254]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_255 = alloc_way_r_metas[255]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_256 = alloc_way_r_metas[256]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_257 = alloc_way_r_metas[257]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_258 = alloc_way_r_metas[258]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_259 = alloc_way_r_metas[259]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_260 = alloc_way_r_metas[260]; // @[btb.scala:123:22, :127:14] wire _alloc_way_T = alloc_way_chunks_0 ^ alloc_way_chunks_1; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_1 = _alloc_way_T ^ alloc_way_chunks_2; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_2 = _alloc_way_T_1 ^ alloc_way_chunks_3; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_3 = _alloc_way_T_2 ^ alloc_way_chunks_4; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_4 = _alloc_way_T_3 ^ alloc_way_chunks_5; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_5 = _alloc_way_T_4 ^ alloc_way_chunks_6; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_6 = _alloc_way_T_5 ^ alloc_way_chunks_7; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_7 = _alloc_way_T_6 ^ alloc_way_chunks_8; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_8 = _alloc_way_T_7 ^ alloc_way_chunks_9; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_9 = _alloc_way_T_8 ^ alloc_way_chunks_10; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_10 = _alloc_way_T_9 ^ alloc_way_chunks_11; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_11 = _alloc_way_T_10 ^ alloc_way_chunks_12; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_12 = _alloc_way_T_11 ^ alloc_way_chunks_13; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_13 = _alloc_way_T_12 ^ alloc_way_chunks_14; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_14 = _alloc_way_T_13 ^ alloc_way_chunks_15; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_15 = _alloc_way_T_14 ^ alloc_way_chunks_16; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_16 = _alloc_way_T_15 ^ alloc_way_chunks_17; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_17 = _alloc_way_T_16 ^ alloc_way_chunks_18; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_18 = _alloc_way_T_17 ^ alloc_way_chunks_19; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_19 = _alloc_way_T_18 ^ alloc_way_chunks_20; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_20 = _alloc_way_T_19 ^ alloc_way_chunks_21; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_21 = _alloc_way_T_20 ^ alloc_way_chunks_22; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_22 = _alloc_way_T_21 ^ alloc_way_chunks_23; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_23 = _alloc_way_T_22 ^ alloc_way_chunks_24; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_24 = _alloc_way_T_23 ^ alloc_way_chunks_25; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_25 = _alloc_way_T_24 ^ alloc_way_chunks_26; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_26 = _alloc_way_T_25 ^ alloc_way_chunks_27; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_27 = _alloc_way_T_26 ^ alloc_way_chunks_28; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_28 = _alloc_way_T_27 ^ alloc_way_chunks_29; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_29 = _alloc_way_T_28 ^ alloc_way_chunks_30; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_30 = _alloc_way_T_29 ^ alloc_way_chunks_31; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_31 = _alloc_way_T_30 ^ alloc_way_chunks_32; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_32 = _alloc_way_T_31 ^ alloc_way_chunks_33; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_33 = _alloc_way_T_32 ^ alloc_way_chunks_34; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_34 = _alloc_way_T_33 ^ alloc_way_chunks_35; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_35 = _alloc_way_T_34 ^ alloc_way_chunks_36; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_36 = _alloc_way_T_35 ^ alloc_way_chunks_37; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_37 = _alloc_way_T_36 ^ alloc_way_chunks_38; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_38 = _alloc_way_T_37 ^ alloc_way_chunks_39; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_39 = _alloc_way_T_38 ^ alloc_way_chunks_40; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_40 = _alloc_way_T_39 ^ alloc_way_chunks_41; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_41 = _alloc_way_T_40 ^ alloc_way_chunks_42; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_42 = _alloc_way_T_41 ^ alloc_way_chunks_43; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_43 = _alloc_way_T_42 ^ alloc_way_chunks_44; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_44 = _alloc_way_T_43 ^ alloc_way_chunks_45; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_45 = _alloc_way_T_44 ^ alloc_way_chunks_46; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_46 = _alloc_way_T_45 ^ alloc_way_chunks_47; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_47 = _alloc_way_T_46 ^ alloc_way_chunks_48; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_48 = _alloc_way_T_47 ^ alloc_way_chunks_49; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_49 = _alloc_way_T_48 ^ alloc_way_chunks_50; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_50 = _alloc_way_T_49 ^ alloc_way_chunks_51; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_51 = _alloc_way_T_50 ^ alloc_way_chunks_52; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_52 = _alloc_way_T_51 ^ alloc_way_chunks_53; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_53 = _alloc_way_T_52 ^ alloc_way_chunks_54; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_54 = _alloc_way_T_53 ^ alloc_way_chunks_55; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_55 = _alloc_way_T_54 ^ alloc_way_chunks_56; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_56 = _alloc_way_T_55 ^ alloc_way_chunks_57; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_57 = _alloc_way_T_56 ^ alloc_way_chunks_58; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_58 = _alloc_way_T_57 ^ alloc_way_chunks_59; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_59 = _alloc_way_T_58 ^ alloc_way_chunks_60; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_60 = _alloc_way_T_59 ^ alloc_way_chunks_61; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_61 = _alloc_way_T_60 ^ alloc_way_chunks_62; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_62 = _alloc_way_T_61 ^ alloc_way_chunks_63; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_63 = _alloc_way_T_62 ^ alloc_way_chunks_64; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_64 = _alloc_way_T_63 ^ alloc_way_chunks_65; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_65 = _alloc_way_T_64 ^ alloc_way_chunks_66; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_66 = _alloc_way_T_65 ^ alloc_way_chunks_67; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_67 = _alloc_way_T_66 ^ alloc_way_chunks_68; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_68 = _alloc_way_T_67 ^ alloc_way_chunks_69; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_69 = _alloc_way_T_68 ^ alloc_way_chunks_70; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_70 = _alloc_way_T_69 ^ alloc_way_chunks_71; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_71 = _alloc_way_T_70 ^ alloc_way_chunks_72; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_72 = _alloc_way_T_71 ^ alloc_way_chunks_73; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_73 = _alloc_way_T_72 ^ alloc_way_chunks_74; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_74 = _alloc_way_T_73 ^ alloc_way_chunks_75; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_75 = _alloc_way_T_74 ^ alloc_way_chunks_76; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_76 = _alloc_way_T_75 ^ alloc_way_chunks_77; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_77 = _alloc_way_T_76 ^ alloc_way_chunks_78; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_78 = _alloc_way_T_77 ^ alloc_way_chunks_79; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_79 = _alloc_way_T_78 ^ alloc_way_chunks_80; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_80 = _alloc_way_T_79 ^ alloc_way_chunks_81; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_81 = _alloc_way_T_80 ^ alloc_way_chunks_82; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_82 = _alloc_way_T_81 ^ alloc_way_chunks_83; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_83 = _alloc_way_T_82 ^ alloc_way_chunks_84; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_84 = _alloc_way_T_83 ^ alloc_way_chunks_85; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_85 = _alloc_way_T_84 ^ alloc_way_chunks_86; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_86 = _alloc_way_T_85 ^ alloc_way_chunks_87; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_87 = _alloc_way_T_86 ^ alloc_way_chunks_88; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_88 = _alloc_way_T_87 ^ alloc_way_chunks_89; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_89 = _alloc_way_T_88 ^ alloc_way_chunks_90; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_90 = _alloc_way_T_89 ^ alloc_way_chunks_91; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_91 = _alloc_way_T_90 ^ alloc_way_chunks_92; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_92 = _alloc_way_T_91 ^ alloc_way_chunks_93; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_93 = _alloc_way_T_92 ^ alloc_way_chunks_94; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_94 = _alloc_way_T_93 ^ alloc_way_chunks_95; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_95 = _alloc_way_T_94 ^ alloc_way_chunks_96; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_96 = _alloc_way_T_95 ^ alloc_way_chunks_97; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_97 = _alloc_way_T_96 ^ alloc_way_chunks_98; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_98 = _alloc_way_T_97 ^ alloc_way_chunks_99; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_99 = _alloc_way_T_98 ^ alloc_way_chunks_100; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_100 = _alloc_way_T_99 ^ alloc_way_chunks_101; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_101 = _alloc_way_T_100 ^ alloc_way_chunks_102; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_102 = _alloc_way_T_101 ^ alloc_way_chunks_103; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_103 = _alloc_way_T_102 ^ alloc_way_chunks_104; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_104 = _alloc_way_T_103 ^ alloc_way_chunks_105; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_105 = _alloc_way_T_104 ^ alloc_way_chunks_106; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_106 = _alloc_way_T_105 ^ alloc_way_chunks_107; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_107 = _alloc_way_T_106 ^ alloc_way_chunks_108; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_108 = _alloc_way_T_107 ^ alloc_way_chunks_109; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_109 = _alloc_way_T_108 ^ alloc_way_chunks_110; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_110 = _alloc_way_T_109 ^ alloc_way_chunks_111; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_111 = _alloc_way_T_110 ^ alloc_way_chunks_112; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_112 = _alloc_way_T_111 ^ alloc_way_chunks_113; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_113 = _alloc_way_T_112 ^ alloc_way_chunks_114; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_114 = _alloc_way_T_113 ^ alloc_way_chunks_115; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_115 = _alloc_way_T_114 ^ alloc_way_chunks_116; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_116 = _alloc_way_T_115 ^ alloc_way_chunks_117; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_117 = _alloc_way_T_116 ^ alloc_way_chunks_118; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_118 = _alloc_way_T_117 ^ alloc_way_chunks_119; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_119 = _alloc_way_T_118 ^ alloc_way_chunks_120; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_120 = _alloc_way_T_119 ^ alloc_way_chunks_121; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_121 = _alloc_way_T_120 ^ alloc_way_chunks_122; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_122 = _alloc_way_T_121 ^ alloc_way_chunks_123; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_123 = _alloc_way_T_122 ^ alloc_way_chunks_124; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_124 = _alloc_way_T_123 ^ alloc_way_chunks_125; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_125 = _alloc_way_T_124 ^ alloc_way_chunks_126; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_126 = _alloc_way_T_125 ^ alloc_way_chunks_127; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_127 = _alloc_way_T_126 ^ alloc_way_chunks_128; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_128 = _alloc_way_T_127 ^ alloc_way_chunks_129; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_129 = _alloc_way_T_128 ^ alloc_way_chunks_130; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_130 = _alloc_way_T_129 ^ alloc_way_chunks_131; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_131 = _alloc_way_T_130 ^ alloc_way_chunks_132; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_132 = _alloc_way_T_131 ^ alloc_way_chunks_133; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_133 = _alloc_way_T_132 ^ alloc_way_chunks_134; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_134 = _alloc_way_T_133 ^ alloc_way_chunks_135; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_135 = _alloc_way_T_134 ^ alloc_way_chunks_136; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_136 = _alloc_way_T_135 ^ alloc_way_chunks_137; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_137 = _alloc_way_T_136 ^ alloc_way_chunks_138; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_138 = _alloc_way_T_137 ^ alloc_way_chunks_139; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_139 = _alloc_way_T_138 ^ alloc_way_chunks_140; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_140 = _alloc_way_T_139 ^ alloc_way_chunks_141; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_141 = _alloc_way_T_140 ^ alloc_way_chunks_142; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_142 = _alloc_way_T_141 ^ alloc_way_chunks_143; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_143 = _alloc_way_T_142 ^ alloc_way_chunks_144; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_144 = _alloc_way_T_143 ^ alloc_way_chunks_145; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_145 = _alloc_way_T_144 ^ alloc_way_chunks_146; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_146 = _alloc_way_T_145 ^ alloc_way_chunks_147; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_147 = _alloc_way_T_146 ^ alloc_way_chunks_148; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_148 = _alloc_way_T_147 ^ alloc_way_chunks_149; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_149 = _alloc_way_T_148 ^ alloc_way_chunks_150; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_150 = _alloc_way_T_149 ^ alloc_way_chunks_151; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_151 = _alloc_way_T_150 ^ alloc_way_chunks_152; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_152 = _alloc_way_T_151 ^ alloc_way_chunks_153; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_153 = _alloc_way_T_152 ^ alloc_way_chunks_154; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_154 = _alloc_way_T_153 ^ alloc_way_chunks_155; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_155 = _alloc_way_T_154 ^ alloc_way_chunks_156; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_156 = _alloc_way_T_155 ^ alloc_way_chunks_157; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_157 = _alloc_way_T_156 ^ alloc_way_chunks_158; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_158 = _alloc_way_T_157 ^ alloc_way_chunks_159; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_159 = _alloc_way_T_158 ^ alloc_way_chunks_160; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_160 = _alloc_way_T_159 ^ alloc_way_chunks_161; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_161 = _alloc_way_T_160 ^ alloc_way_chunks_162; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_162 = _alloc_way_T_161 ^ alloc_way_chunks_163; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_163 = _alloc_way_T_162 ^ alloc_way_chunks_164; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_164 = _alloc_way_T_163 ^ alloc_way_chunks_165; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_165 = _alloc_way_T_164 ^ alloc_way_chunks_166; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_166 = _alloc_way_T_165 ^ alloc_way_chunks_167; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_167 = _alloc_way_T_166 ^ alloc_way_chunks_168; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_168 = _alloc_way_T_167 ^ alloc_way_chunks_169; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_169 = _alloc_way_T_168 ^ alloc_way_chunks_170; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_170 = _alloc_way_T_169 ^ alloc_way_chunks_171; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_171 = _alloc_way_T_170 ^ alloc_way_chunks_172; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_172 = _alloc_way_T_171 ^ alloc_way_chunks_173; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_173 = _alloc_way_T_172 ^ alloc_way_chunks_174; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_174 = _alloc_way_T_173 ^ alloc_way_chunks_175; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_175 = _alloc_way_T_174 ^ alloc_way_chunks_176; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_176 = _alloc_way_T_175 ^ alloc_way_chunks_177; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_177 = _alloc_way_T_176 ^ alloc_way_chunks_178; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_178 = _alloc_way_T_177 ^ alloc_way_chunks_179; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_179 = _alloc_way_T_178 ^ alloc_way_chunks_180; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_180 = _alloc_way_T_179 ^ alloc_way_chunks_181; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_181 = _alloc_way_T_180 ^ alloc_way_chunks_182; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_182 = _alloc_way_T_181 ^ alloc_way_chunks_183; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_183 = _alloc_way_T_182 ^ alloc_way_chunks_184; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_184 = _alloc_way_T_183 ^ alloc_way_chunks_185; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_185 = _alloc_way_T_184 ^ alloc_way_chunks_186; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_186 = _alloc_way_T_185 ^ alloc_way_chunks_187; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_187 = _alloc_way_T_186 ^ alloc_way_chunks_188; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_188 = _alloc_way_T_187 ^ alloc_way_chunks_189; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_189 = _alloc_way_T_188 ^ alloc_way_chunks_190; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_190 = _alloc_way_T_189 ^ alloc_way_chunks_191; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_191 = _alloc_way_T_190 ^ alloc_way_chunks_192; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_192 = _alloc_way_T_191 ^ alloc_way_chunks_193; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_193 = _alloc_way_T_192 ^ alloc_way_chunks_194; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_194 = _alloc_way_T_193 ^ alloc_way_chunks_195; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_195 = _alloc_way_T_194 ^ alloc_way_chunks_196; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_196 = _alloc_way_T_195 ^ alloc_way_chunks_197; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_197 = _alloc_way_T_196 ^ alloc_way_chunks_198; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_198 = _alloc_way_T_197 ^ alloc_way_chunks_199; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_199 = _alloc_way_T_198 ^ alloc_way_chunks_200; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_200 = _alloc_way_T_199 ^ alloc_way_chunks_201; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_201 = _alloc_way_T_200 ^ alloc_way_chunks_202; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_202 = _alloc_way_T_201 ^ alloc_way_chunks_203; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_203 = _alloc_way_T_202 ^ alloc_way_chunks_204; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_204 = _alloc_way_T_203 ^ alloc_way_chunks_205; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_205 = _alloc_way_T_204 ^ alloc_way_chunks_206; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_206 = _alloc_way_T_205 ^ alloc_way_chunks_207; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_207 = _alloc_way_T_206 ^ alloc_way_chunks_208; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_208 = _alloc_way_T_207 ^ alloc_way_chunks_209; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_209 = _alloc_way_T_208 ^ alloc_way_chunks_210; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_210 = _alloc_way_T_209 ^ alloc_way_chunks_211; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_211 = _alloc_way_T_210 ^ alloc_way_chunks_212; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_212 = _alloc_way_T_211 ^ alloc_way_chunks_213; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_213 = _alloc_way_T_212 ^ alloc_way_chunks_214; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_214 = _alloc_way_T_213 ^ alloc_way_chunks_215; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_215 = _alloc_way_T_214 ^ alloc_way_chunks_216; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_216 = _alloc_way_T_215 ^ alloc_way_chunks_217; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_217 = _alloc_way_T_216 ^ alloc_way_chunks_218; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_218 = _alloc_way_T_217 ^ alloc_way_chunks_219; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_219 = _alloc_way_T_218 ^ alloc_way_chunks_220; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_220 = _alloc_way_T_219 ^ alloc_way_chunks_221; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_221 = _alloc_way_T_220 ^ alloc_way_chunks_222; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_222 = _alloc_way_T_221 ^ alloc_way_chunks_223; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_223 = _alloc_way_T_222 ^ alloc_way_chunks_224; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_224 = _alloc_way_T_223 ^ alloc_way_chunks_225; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_225 = _alloc_way_T_224 ^ alloc_way_chunks_226; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_226 = _alloc_way_T_225 ^ alloc_way_chunks_227; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_227 = _alloc_way_T_226 ^ alloc_way_chunks_228; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_228 = _alloc_way_T_227 ^ alloc_way_chunks_229; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_229 = _alloc_way_T_228 ^ alloc_way_chunks_230; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_230 = _alloc_way_T_229 ^ alloc_way_chunks_231; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_231 = _alloc_way_T_230 ^ alloc_way_chunks_232; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_232 = _alloc_way_T_231 ^ alloc_way_chunks_233; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_233 = _alloc_way_T_232 ^ alloc_way_chunks_234; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_234 = _alloc_way_T_233 ^ alloc_way_chunks_235; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_235 = _alloc_way_T_234 ^ alloc_way_chunks_236; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_236 = _alloc_way_T_235 ^ alloc_way_chunks_237; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_237 = _alloc_way_T_236 ^ alloc_way_chunks_238; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_238 = _alloc_way_T_237 ^ alloc_way_chunks_239; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_239 = _alloc_way_T_238 ^ alloc_way_chunks_240; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_240 = _alloc_way_T_239 ^ alloc_way_chunks_241; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_241 = _alloc_way_T_240 ^ alloc_way_chunks_242; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_242 = _alloc_way_T_241 ^ alloc_way_chunks_243; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_243 = _alloc_way_T_242 ^ alloc_way_chunks_244; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_244 = _alloc_way_T_243 ^ alloc_way_chunks_245; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_245 = _alloc_way_T_244 ^ alloc_way_chunks_246; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_246 = _alloc_way_T_245 ^ alloc_way_chunks_247; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_247 = _alloc_way_T_246 ^ alloc_way_chunks_248; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_248 = _alloc_way_T_247 ^ alloc_way_chunks_249; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_249 = _alloc_way_T_248 ^ alloc_way_chunks_250; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_250 = _alloc_way_T_249 ^ alloc_way_chunks_251; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_251 = _alloc_way_T_250 ^ alloc_way_chunks_252; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_252 = _alloc_way_T_251 ^ alloc_way_chunks_253; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_253 = _alloc_way_T_252 ^ alloc_way_chunks_254; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_254 = _alloc_way_T_253 ^ alloc_way_chunks_255; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_255 = _alloc_way_T_254 ^ alloc_way_chunks_256; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_256 = _alloc_way_T_255 ^ alloc_way_chunks_257; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_257 = _alloc_way_T_256 ^ alloc_way_chunks_258; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_258 = _alloc_way_T_257 ^ alloc_way_chunks_259; // @[btb.scala:127:14, :129:20] wire alloc_way = _alloc_way_T_258 ^ alloc_way_chunks_260; // @[btb.scala:127:14, :129:20] wire _s1_meta_write_way_T = s1_hits_0 \| s1_hits_1; // @[btb.scala:87:55, :133:44] wire _s1_meta_write_way_T_1 = _s1_meta_write_way_T \| s1_hits_2; // @[btb.scala:87:55, :133:44] wire _s1_meta_write_way_T_2 = _s1_meta_write_way_T_1 \| s1_hits_3; // @[btb.scala:87:55, :133:44] wire [1:0] _s1_meta_write_way_T_3 = {s1_hit_ohs_0_1, s1_hit_ohs_0_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_4 = {s1_hit_ohs_1_1, s1_hit_ohs_1_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_5 = {s1_hit_ohs_2_1, s1_hit_ohs_2_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_6 = {s1_hit_ohs_3_1, s1_hit_ohs_3_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_7 = _s1_meta_write_way_T_3 \| _s1_meta_write_way_T_4; // @[btb.scala:134:{38,54}] wire [1:0] _s1_meta_write_way_T_8 = _s1_meta_write_way_T_7 \| _s1_meta_write_way_T_5; // @[btb.scala:134:{38,54}] wire [1:0] _s1_meta_write_way_T_9 = _s1_meta_write_way_T_8 \| _s1_meta_write_way_T_6; // @[btb.scala:134:{38,54}] wire _s1_meta_write_way_T_10 = _s1_meta_write_way_T_9[0]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_11 = _s1_meta_write_way_T_9[1]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_12 = ~_s1_meta_write_way_T_10; // @[OneHot.scala:48:45] assign _s1_meta_write_way_T_13 = _s1_meta_write_way_T_2 ? _s1_meta_write_way_T_12 : alloc_way; // @[Mux.scala:50:70] assign s1_meta_write_way = _s1_meta_write_way_T_13; // @[btb.scala:52:21, :133:27] wire _s1_update_meta_T; // @[btb.scala:138:55] wire s1_update_meta_write_way; // @[btb.scala:138:55] assign _s1_update_meta_T = _s1_update_meta_WIRE; // @[btb.scala:138:55] assign _s1_update_meta_WIRE = s1_update_bits_meta[0]; // @[predictor.scala:184:30] assign s1_update_meta_write_way = _s1_update_meta_T; // @[btb.scala:138:55] wire [2:0] _new_offset_value_T_1 = {s1_update_bits_cfi_idx_bits, 1'h0}; // @[predictor.scala:184:30] wire [40:0] _new_offset_value_T_2 = {1'h0, s1_update_bits_pc} + {38'h0, _new_offset_value_T_1}; // @[predictor.scala:184:30] wire [39:0] _new_offset_value_T_3 = _new_offset_value_T_2[39:0]; // @[btb.scala:143:24] wire [39:0] _new_offset_value_T_4 = _new_offset_value_T_3; // @[btb.scala:143:{24,62}] wire [40:0] _new_offset_value_T_5 = {_new_offset_value_T[39], _new_offset_value_T} - {_new_offset_value_T_4[39], _new_offset_value_T_4}; // @[btb.scala:142:{49,56}, :143:62] wire [39:0] _new_offset_value_T_6 = _new_offset_value_T_5[39:0]; // @[btb.scala:142:56] wire [39:0] new_offset_value = _new_offset_value_T_6; // @[btb.scala:142:56] wire _offset_is_extended_T = $signed(new_offset_value) > 40'shFFF; // @[btb.scala:142:56, :144:46] wire _offset_is_extended_T_1 = $signed(new_offset_value) < -40'sh1000; // @[btb.scala:142:56, :145:46] wire offset_is_extended = _offset_is_extended_T \| _offset_is_extended_T_1; // @[btb.scala:144:{46,65}, :145:46] wire s1_update_wbtb_data_extended = offset_is_extended; // @[btb.scala:144:65, :148:34] wire [12:0] s1_update_wbtb_data_offset; // @[btb.scala:148:34] assign s1_update_wbtb_data_offset = new_offset_value[12:0]; // @[btb.scala:142:56, :148:34, :150:32] wire [3:0] _s1_update_wbtb_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35] wire _s1_update_wbtb_mask_T_1 = s1_update_bits_cfi_idx_valid & s1_update_valid; // @[predictor.scala:184:30] wire _s1_update_wbtb_mask_T_2 = _s1_update_wbtb_mask_T_1 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30] wire _GEN_7 = s1_update_bits_is_mispredict_update \| s1_update_bits_is_repair_update; // @[predictor.scala:96:49, :184:30] wire _s1_update_wbtb_mask_T_3; // @[predictor.scala:96:49] assign _s1_update_wbtb_mask_T_3 = _GEN_7; // @[predictor.scala:96:49] wire _s1_update_wmeta_mask_T_1; // @[predictor.scala:96:49] assign _s1_update_wmeta_mask_T_1 = _GEN_7; // @[predictor.scala:96:49] wire _s1_update_wbtb_mask_T_4 = \|s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30] wire _s1_update_wbtb_mask_T_5 = _s1_update_wbtb_mask_T_3 \| _s1_update_wbtb_mask_T_4; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wbtb_mask_T_6 = ~_s1_update_wbtb_mask_T_5; // @[predictor.scala:96:{26,69}] wire _s1_update_wbtb_mask_T_7 = _s1_update_wbtb_mask_T_2 & _s1_update_wbtb_mask_T_6; // @[predictor.scala:96:26] wire [3:0] _s1_update_wbtb_mask_T_8 = {4{_s1_update_wbtb_mask_T_7}}; // @[btb.scala:152:{9,97}] wire [3:0] s1_update_wbtb_mask = _s1_update_wbtb_mask_T & _s1_update_wbtb_mask_T_8; // @[OneHot.scala:58:35] wire [3:0] _s1_update_wmeta_mask_T = s1_update_wbtb_mask \| s1_update_bits_br_mask; // @[predictor.scala:184:30] wire _s1_update_wmeta_mask_T_2 = \|s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30] wire _s1_update_wmeta_mask_T_3 = _s1_update_wmeta_mask_T_1 \| _s1_update_wmeta_mask_T_2; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wmeta_mask_T_4 = ~_s1_update_wmeta_mask_T_3; // @[predictor.scala:96:{26,69}] wire _s1_update_wmeta_mask_T_5 = s1_update_valid & _s1_update_wmeta_mask_T_4; // @[predictor.scala:96:26, :184:30] wire [3:0] _s1_update_wmeta_mask_T_6 = {4{_s1_update_wmeta_mask_T_5}}; // @[btb.scala:155:{10,38}] wire [3:0] _s1_update_wmeta_mask_T_7 = {4{s1_update_valid}}; // @[predictor.scala:184:30] wire [3:0] _s1_update_wmeta_mask_T_8 = _s1_update_wmeta_mask_T_7 & s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] wire [3:0] _s1_update_wmeta_mask_T_9 = _s1_update_wmeta_mask_T_6 \| _s1_update_wmeta_mask_T_8; // @[btb.scala:155:{10,74}, :156:40] wire [3:0] s1_update_wmeta_mask = _s1_update_wmeta_mask_T & _s1_update_wmeta_mask_T_9; // @[btb.scala:154:{52,78}, :155:74] wire _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:162:43] wire _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:162:43] wire _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:162:43] wire _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:162:43] wire s1_update_wmeta_data_0_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_0_tag; // @[btb.scala:159:34] wire s1_update_wmeta_data_1_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_1_tag; // @[btb.scala:159:34] wire s1_update_wmeta_data_2_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_2_tag; // @[btb.scala:159:34] wire s1_update_wmeta_data_3_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_3_tag; // @[btb.scala:159:34] wire _s1_update_wmeta_data_0_tag_T = s1_update_bits_btb_mispredicts[0]; // @[predictor.scala:184:30] wire [28:0] _s1_update_wmeta_data_0_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_1_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_2_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_3_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_0_tag_T_2 = _s1_update_wmeta_data_0_tag_T ? 29'h0 : _s1_update_wmeta_data_0_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_0_tag = _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_0_is_br_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_0_is_br = _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:159:34, :163:62] wire _s1_update_wmeta_data_1_tag_T = s1_update_bits_btb_mispredicts[1]; // @[predictor.scala:184:30] assign _s1_update_wmeta_data_1_tag_T_2 = _s1_update_wmeta_data_1_tag_T ? 29'h0 : _s1_update_wmeta_data_1_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_1_tag = _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_1_is_br_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_1_is_br = _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:159:34, :163:62] wire _s1_update_wmeta_data_2_tag_T = s1_update_bits_btb_mispredicts[2]; // @[predictor.scala:184:30] assign _s1_update_wmeta_data_2_tag_T_2 = _s1_update_wmeta_data_2_tag_T ? 29'h0 : _s1_update_wmeta_data_2_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_2_tag = _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_2_is_br_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_2_is_br = _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:159:34, :163:62] wire _s1_update_wmeta_data_3_tag_T = s1_update_bits_btb_mispredicts[3]; // @[predictor.scala:184:30] assign _s1_update_wmeta_data_3_tag_T_2 = _s1_update_wmeta_data_3_tag_T ? 29'h0 : _s1_update_wmeta_data_3_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_3_tag = _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_3_is_br_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_3_is_br = _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:159:34, :163:62] wire btb_0_MPORT_en = doing_reset \| ~s1_update_meta_write_way; // @[btb.scala:60:28, :138:55, :167:{23,51}] wire [6:0] _T_34 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:185:30] assign btb_0_MPORT_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_0_MPORT_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_0_MPORT_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_0_MPORT_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign meta_0_MPORT_1_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_0_MPORT_1_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_0_MPORT_1_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_0_MPORT_1_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] wire btb_1_MPORT_2_en = doing_reset \| s1_update_meta_write_way; // @[btb.scala:60:28, :138:55, :167:23] wire [6:0] _T_69 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:185:30] assign btb_1_MPORT_2_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_1_MPORT_2_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_1_MPORT_2_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_1_MPORT_2_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign meta_1_MPORT_3_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_1_MPORT_3_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_1_MPORT_3_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_1_MPORT_3_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] always @(posedge clock) begin // @[btb.scala:23:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] f3_meta_REG_write_way <= s1_meta_write_way; // @[btb.scala:52:21, :53:32] f3_meta_write_way <= f3_meta_REG_write_way; // @[btb.scala:53:{24,32}] REG <= s1_hits_0; // @[btb.scala:87:55, :104:18] io_resp_f2_0_predicted_pc_REG_valid <= s1_resp_0_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_0_predicted_pc_REG_bits <= s1_resp_0_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_0_is_br_REG <= s1_is_br_0; // @[btb.scala:79:23, :106:44] io_resp_f2_0_is_jal_REG <= s1_is_jal_0; // @[btb.scala:80:23, :107:44] REG_1 <= s1_is_jal_0; // @[btb.scala:80:23, :108:20] REG_2 <= s1_hits_0; // @[btb.scala:87:55, :112:26] REG_3 <= REG_2; // @[btb.scala:112:{18,26}] io_resp_f3_0_predicted_pc_REG_valid <= io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_0_predicted_pc_REG_bits <= io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_0_is_br_REG <= io_resp_f2_0_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_0_is_jal_REG <= io_resp_f2_0_is_jal_0; // @[btb.scala:23:7, :115:44] REG_4 <= s1_is_jal_0; // @[btb.scala:80:23, :116:28] REG_5 <= REG_4; // @[btb.scala:116:{20,28}] REG_6 <= s1_hits_1; // @[btb.scala:87:55, :104:18] io_resp_f2_1_predicted_pc_REG_valid <= s1_resp_1_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_1_predicted_pc_REG_bits <= s1_resp_1_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_1_is_br_REG <= s1_is_br_1; // @[btb.scala:79:23, :106:44] io_resp_f2_1_is_jal_REG <= s1_is_jal_1; // @[btb.scala:80:23, :107:44] REG_7 <= s1_is_jal_1; // @[btb.scala:80:23, :108:20] REG_8 <= s1_hits_1; // @[btb.scala:87:55, :112:26] REG_9 <= REG_8; // @[btb.scala:112:{18,26}] io_resp_f3_1_predicted_pc_REG_valid <= io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_1_predicted_pc_REG_bits <= io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_1_is_br_REG <= io_resp_f2_1_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_1_is_jal_REG <= io_resp_f2_1_is_jal_0; // @[btb.scala:23:7, :115:44] REG_10 <= s1_is_jal_1; // @[btb.scala:80:23, :116:28] REG_11 <= REG_10; // @[btb.scala:116:{20,28}] REG_12 <= s1_hits_2; // @[btb.scala:87:55, :104:18] io_resp_f2_2_predicted_pc_REG_valid <= s1_resp_2_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_2_predicted_pc_REG_bits <= s1_resp_2_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_2_is_br_REG <= s1_is_br_2; // @[btb.scala:79:23, :106:44] io_resp_f2_2_is_jal_REG <= s1_is_jal_2; // @[btb.scala:80:23, :107:44] REG_13 <= s1_is_jal_2; // @[btb.scala:80:23, :108:20] REG_14 <= s1_hits_2; // @[btb.scala:87:55, :112:26] REG_15 <= REG_14; // @[btb.scala:112:{18,26}] io_resp_f3_2_predicted_pc_REG_valid <= io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_2_predicted_pc_REG_bits <= io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_2_is_br_REG <= io_resp_f2_2_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_2_is_jal_REG <= io_resp_f2_2_is_jal_0; // @[btb.scala:23:7, :115:44] REG_16 <= s1_is_jal_2; // @[btb.scala:80:23, :116:28] REG_17 <= REG_16; // @[btb.scala:116:{20,28}] REG_18 <= s1_hits_3; // @[btb.scala:87:55, :104:18] io_resp_f2_3_predicted_pc_REG_valid <= s1_resp_3_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_3_predicted_pc_REG_bits <= s1_resp_3_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_3_is_br_REG <= s1_is_br_3; // @[btb.scala:79:23, :106:44] io_resp_f2_3_is_jal_REG <= s1_is_jal_3; // @[btb.scala:80:23, :107:44] REG_19 <= s1_is_jal_3; // @[btb.scala:80:23, :108:20] REG_20 <= s1_hits_3; // @[btb.scala:87:55, :112:26] REG_21 <= REG_20; // @[btb.scala:112:{18,26}] io_resp_f3_3_predicted_pc_REG_valid <= io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_3_predicted_pc_REG_bits <= io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_3_is_br_REG <= io_resp_f2_3_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_3_is_jal_REG <= io_resp_f2_3_is_jal_0; // @[btb.scala:23:7, :115:44] REG_22 <= s1_is_jal_3; // @[btb.scala:80:23, :116:28] REG_23 <= REG_22; // @[btb.scala:116:{20,28}] if (reset) begin // @[btb.scala:23:7] doing_reset <= 1'h1; // @[btb.scala:60:28] reset_idx <= 7'h0; // @[btb.scala:61:28] end else begin // @[btb.scala:23:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[btb.scala:60:28, :61:28, :63:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[btb.scala:61:28, :62:26] end always @(posedge) meta_0 meta_0 ( // @[btb.scala:65:47] .R0_addr (_s1_req_rmeta_T), // @[btb.scala:74:60] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_meta_0_R0_data), .W0_addr (_T_34), // @[btb.scala:169:12] .W0_en (btb_0_MPORT_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({meta_0_MPORT_1_data_3, meta_0_MPORT_1_data_2, meta_0_MPORT_1_data_1, meta_0_MPORT_1_data_0}), // @[btb.scala:65:47, :183:12] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:60:28, :154:78, :186:12] ); // @[btb.scala:65:47] meta_1 meta_1 ( // @[btb.scala:65:47] .R0_addr (_s1_req_rmeta_T_9), // @[btb.scala:74:60] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_meta_1_R0_data), .W0_addr (_T_69), // @[btb.scala:169:12] .W0_en (btb_1_MPORT_2_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({meta_1_MPORT_3_data_3, meta_1_MPORT_3_data_2, meta_1_MPORT_3_data_1, meta_1_MPORT_3_data_0}), // @[btb.scala:65:47, :183:12] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:60:28, :154:78, :186:12] ); // @[btb.scala:65:47] btb_0 btb_0 ( // @[btb.scala:66:47] .R0_addr (_s1_req_rbtb_T), // @[btb.scala:73:59] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_btb_0_R0_data), .W0_addr (_T_34), // @[btb.scala:169:12] .W0_en (btb_0_MPORT_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({btb_0_MPORT_data_3, btb_0_MPORT_data_2, btb_0_MPORT_data_1, btb_0_MPORT_data_0}), // @[btb.scala:66:47, :172:12] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:60:28, :151:58, :175:12] ); // @[btb.scala:66:47] btb_1 btb_1 ( // @[btb.scala:66:47] .R0_addr (_s1_req_rbtb_T_13), // @[btb.scala:73:59] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_btb_1_R0_data), .W0_addr (_T_69), // @[btb.scala:169:12] .W0_en (btb_1_MPORT_2_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({btb_1_MPORT_2_data_3, btb_1_MPORT_2_data_2, btb_1_MPORT_2_data_1, btb_1_MPORT_2_data_0}), // @[btb.scala:66:47, :172:12] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:60:28, :151:58, :175:12] ); // @[btb.scala:66:47] ebtb ebtb ( // @[btb.scala:67:29] .R0_addr (_s1_req_rebtb_T), // @[btb.scala:75:31] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_ebtb_R0_data), .W0_addr (s1_update_idx[6:0]), // @[predictor.scala:185:30] .W0_en ((\|s1_update_wbtb_mask) & offset_is_extended), // @[btb.scala:144:65, :151:58, :194:{29,37}] .W0_clk (clock), .W0_data (s1_update_bits_target) // @[predictor.scala:184:30] ); // @[btb.scala:67:29] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[btb.scala:23:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[btb.scala:23:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[btb.scala:23:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[btb.scala:23:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[btb.scala:23:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[btb.scala:23:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[btb.scala:23:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[btb.scala:23:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[btb.scala:23:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[btb.scala:23:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[btb.scala:23:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[btb.scala:23:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_f3_meta = io_f3_meta_0; // @[btb.scala:23:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module ClockCrossingReg_w32_3( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [31:0] io_d, // @[SynchronizerReg.scala:195:14] output [31:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [31:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [31:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [31:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }	module EgressUnit_16( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_22 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_46( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_181( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_196 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }	module FPUFMAPipe_l3_f16( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input io_in_bits_vec, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [64:0] res_data; // @[FPU.scala:728:17] wire [16:0] _fma_io_out; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [15:0] one = 16'h8000; // @[FPU.scala:710:19] wire [16:0] _zero_T_1 = 17'h10000; // @[FPU.scala:711:57] wire io_out_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg in_vec; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = {48'h0, _zero_T[16], 16'h0}; // @[FPU.scala:711:{32,50}] assign io_out_out_bits_data = res_data; // @[Valid.scala:135:21] wire [4:0] res_exc; // @[FPU.scala:728:17] assign io_out_out_bits_exc = res_exc; // @[Valid.scala:135:21] assign res_data = {48'h0, _fma_io_out}; // @[FPU.scala:711:50, :719:19, :728:17, :729:12] assign io_out_valid = io_out_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_vec <= io_in_bits_vec_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h8000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 \| io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end always @(posedge) MulAddRecFNPipe_l2_e5_s11 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1[16:0]), // @[FPU.scala:708:15, :724:12] .io_b (in_in2[16:0]), // @[FPU.scala:708:15, :725:12] .io_c (in_in3[16:0]), // @[FPU.scala:708:15, :726:12] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (io_out_out_valid) ); // @[FPU.scala:719:19] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundRawFNToRecFN_e11_s53_12( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:299:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_12 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_detectTininess (io_detectTininess_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }	module FPUFMAPipe_l4_f16( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output io_out_valid, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [16:0] _fma_io_out; // @[FPU.scala:719:19] wire _fma_io_validout; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [15:0] one = 16'h8000; // @[FPU.scala:710:19] wire [16:0] _zero_T_1 = 17'h10000; // @[FPU.scala:711:57] wire io_in_bits_vec = 1'h0; // @[FPU.scala:697:7] wire io_out_pipe_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid_0; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = {48'h0, _zero_T[16], 16'h0}; // @[FPU.scala:711:{32,50}] wire [64:0] res_data; // @[FPU.scala:728:17] wire [4:0] res_exc; // @[FPU.scala:728:17] assign res_data = {48'h0, _fma_io_out}; // @[FPU.scala:711:50, :719:19, :728:17, :729:12] reg io_out_pipe_v; // @[Valid.scala:141:24] assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26] assign io_out_valid_0 = io_out_pipe_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h8000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 \| io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end if (_fma_io_validout) begin // @[FPU.scala:719:19] io_out_pipe_b_data <= res_data; // @[Valid.scala:142:26] io_out_pipe_b_exc <= res_exc; // @[Valid.scala:142:26] end if (reset) // @[FPU.scala:697:7] io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] else // @[FPU.scala:697:7] io_out_pipe_v <= _fma_io_validout; // @[Valid.scala:141:24] always @(posedge) MulAddRecFNPipe_l2_e5_s11 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1[16:0]), // @[FPU.scala:708:15, :724:12] .io_b (in_in2[16:0]), // @[FPU.scala:708:15, :725:12] .io_c (in_in3[16:0]), // @[FPU.scala:708:15, :726:12] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (_fma_io_validout) ); // @[FPU.scala:719:19] assign io_out_valid = io_out_valid_0; // @[FPU.scala:697:7] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLBuffer_a32d64s4k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_13 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s4k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s4k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_466( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_210 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_120( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_61( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_78 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth2 - 1)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) \|\| (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf \|\| io.b.isInf val notNaN_isZeroOut = io.a.isZero \|\| io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth2 - 1, 0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.invalidExc := isSigNaNRawFloat(io.a) \|\| isSigNaNRawFloat(io.b) \|\| notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN \|\| io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulFullRawFN_50( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T \| _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 \| io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 \| io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 \| _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 \| notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 \| io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_148( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }	module cc_banks_3_4( // @[DescribedSRAM.scala:17:26] input [14:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); cc_banks_0_ext cc_banks_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_101( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_12( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_25 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /* This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module IntSyncCrossingSource_n1x1_5( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_5 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired \|\| fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module Router_14( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_2_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_7; // @[Router.scala:136:32] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_2_to_20_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_7_occupied; // @[Router.scala:122:13] wire [2:0] _input_unit_2_from_20_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_20_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_20_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_20_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_17_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_0_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_0_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_0_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_0_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_0_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_0_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_0_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_0_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_0_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_17_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_20_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File NextLine.scala: package barf import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem.{CacheBlockBytes} case class SingleNextLinePrefetcherParams( ahead: Int = 4, waitForHit: Boolean = false, handleVA: Boolean = false ) extends CanInstantiatePrefetcher { def desc() = "Single Next-Line Prefetcher" def instantiate()(implicit p: Parameters) = Module(new SingleNextLinePrefetcher(this)(p)) } class SingleNextLinePrefetcher(params: SingleNextLinePrefetcherParams)(implicit p: Parameters) extends AbstractPrefetcher()(p) { // Assume 4KB pages val lowerBits = 12 - log2Ceil(p(CacheBlockBytes)) val s_idle :: s_wait :: s_active :: s_done :: Nil = Enum(4) val state = RegInit(s_idle) val write = Reg(Bool()) val block_upper = Reg(UInt()) val block_lower = Reg(UInt(lowerBits.W)) val prefetch = Reg(UInt(lowerBits.W)) val wrap = RegInit(false.B) val wrap_block_upper = block_upper + 1.U val delta = Mux(wrap, Cat(1.U(1.W), prefetch) - block_lower, prefetch - block_lower) val addr_hit = if (params.handleVA) { (io.snoop.bits.block >= Cat(block_upper, block_lower)) && (io.snoop.bits.block <= Cat(Mux(wrap, wrap_block_upper, block_upper), prefetch)) } else { (block_upper === io.snoop.bits.block >> lowerBits) && (io.snoop.bits.block(lowerBits-1,0) >= block_lower) && (io.snoop.bits.block(lowerBits-1,0) <= prefetch) } io.hit := state =/= s_idle && addr_hit val snoop_next_block = (io.snoop.bits.block(lowerBits-1,0) + 1.U)(lowerBits-1,0) when ((state === s_idle \|\| (state === s_wait && !io.hit)) && io.snoop.valid) { when (~io.snoop.bits.block(lowerBits-1,0) =/= 0.U \|\| params.handleVA.B) { state := (if (params.waitForHit) s_wait else s_active) } block_upper := io.snoop.bits.block >> lowerBits block_lower := io.snoop.bits.block prefetch := snoop_next_block when (params.handleVA.B && !io.hit) { wrap := snoop_next_block === 0.U } write := io.snoop.bits.write } io.request.valid := state === s_active io.request.bits.write := write io.request.bits.address := Cat(Mux(wrap, wrap_block_upper, block_upper), prefetch) << log2Up(io.request.bits.blockBytes) when (io.request.fire) { prefetch := prefetch + 1.U when (prefetch === ~(0.U(lowerBits.W))) { if (params.handleVA) { state := Mux(delta >= params.ahead.U, s_wait, s_active) prefetch := 0.U wrap := true.B } else { state := s_done prefetch := prefetch } } .elsewhen (delta >= params.ahead.U) { state := s_wait } .otherwise { state := s_active } } when (state === s_done && block_lower === prefetch) { state := s_idle } when (io.hit && io.snoop.valid) { when (state =/= s_done && io.snoop.bits.block =/= Cat(block_upper, block_lower)) { state := s_active } write := io.snoop.bits.write block_lower := io.snoop.bits.block block_upper := io.snoop.bits.block >> lowerBits when (io.snoop.bits.block(lowerBits-1,0) === prefetch) { prefetch := prefetch + 1.U } when (wrap && ((io.snoop.bits.block >> lowerBits) =/= block_upper)) { wrap := false.B } } } case class MultiNextLinePrefetcherParams( singles: Seq[SingleNextLinePrefetcherParams] = Seq.fill(4) { SingleNextLinePrefetcherParams() }, handleVA: Boolean = false ) extends CanInstantiatePrefetcher { def desc() = "Multi Next-Line Prefetcher" def instantiate()(implicit p: Parameters) = Module(new MultiNextLinePrefetcher(this)(p)) } class MultiNextLinePrefetcher(params: MultiNextLinePrefetcherParams)(implicit p: Parameters) extends AbstractPrefetcher()(p) { val singles = params.singles.map(_.copy(waitForHit=true, handleVA=params.handleVA).instantiate()) val any_hit = singles.map(_.io.hit).reduce(_\|\|_) singles.foreach(_.io.snoop.valid := false.B) singles.foreach(_.io.snoop.bits := io.snoop.bits) val replacer = ReplacementPolicy.fromString("lru", singles.size) when (io.snoop.valid) { for (s <- 0 until singles.size) { when (singles(s).io.hit \|\| (!any_hit && replacer.way === s.U)) { singles(s).io.snoop.valid := true.B replacer.miss } when (singles(s).io.hit) { replacer.access(s.U) } } } val arb = Module(new RRArbiter(new Prefetch, singles.size)) arb.io.in <> singles.map(_.io.request) io.request <> arb.io.out } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AMPM.scala: / --------------------------------------------------------------------- Access Map Pattern Matching Adapted from "Access map pattern matching for data cache prefetch" Yasuo Ishii, Mary Inaba, and Kei Hiraki. 2009. Access map pattern matching for data cache prefetch. In Proceedings of the 23rd international conference on Supercomputing (ICS '09). Association for Computing Machinery, New York, NY, USA, 499–500. https://doi.org/10.1145/1542275.1542349 --------------------------------------------------------------------- / package barf import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem.{CacheBlockBytes} case class SingleAMPMPrefetcherParams( entries: Int = 64, //Number of entries per access map N: Int = 16, //Number of cache lines per zone ) extends CanInstantiatePrefetcher { def desc() = "Single AMPM Prefetcher" def instantiate()(implicit p: Parameters) = Module(new AMPMPrefetcher(this)(p)) } class AMPMPrefetcher(params: SingleAMPMPrefetcherParams)(implicit p: Parameters) extends AbstractPrefetcher()(p) { val entries_bits = log2Ceil(params.entries) val line_bits = log2Ceil(params.N) val max_k = if (params.N % 2 == 0) { params.N / 2 } else { (params.N - 1) / 2} //----------------- memory access map table ----------------- val snoop_tag = io.snoop.bits.block >> (line_bits) val snoop_offset = io.snoop.bits.block(line_bits - 1, 0) val memory_access_map_table = Reg(Valid(new MemoryAccessMapBank(entries = params.entries, N = params.N))) val tag_candidate = Wire(UInt(params.N.W)) val prefetch_input = Wire(UInt(params.N.W)) val entry_existence_vec = Wire(Vec(params.entries, Bool())) val entry_existence = Wire(Bool()) val initial_state_vec = Wire(Vec(params.N, Bool())) val head = RegInit(0.U((entries_bits).W)) val already_accessed = Wire(Bool()) //Set initial state for new maps for (i <- 0 until params.N) { initial_state_vec(i) := snoop_offset === i.U } //Check table for map tag_candidate := 0.U val map_bank = memory_access_map_table for (j <- 0 until params.entries) { val map = map_bank.bits.maps(j) //found entry -> send to prefetch generator when (io.snoop.valid && map.valid && (map.bits.tag === snoop_tag)) { tag_candidate := map.bits.states.asUInt map.bits.states(snoop_offset) := true.B //set map entry to "accessed" entry_existence_vec(j) := true.B } .otherwise { entry_existence_vec(j) := false.B } } entry_existence := entry_existence_vec.reduce(_ \|\| _) //if entry not in table, add new entry when (!entry_existence && io.snoop.valid) { memory_access_map_table.bits.maps(head).bits.states := initial_state_vec memory_access_map_table.bits.maps(head).bits.tag := snoop_tag memory_access_map_table.bits.maps(head).valid := true.B head := head + 1.U } prefetch_input := tag_candidate already_accessed := prefetch_input(snoop_offset) //pattern matching val forward_map = Wire(UInt((params.N).W)) val backward_map = Wire(UInt((params.N).W)) val logic_pos = Wire(Vec(max_k, UInt())) val logic_neg = Wire(Vec(max_k, UInt())) val and_back_pos = Wire(Vec(max_k, UInt())) val and_back_pos_uint = Wire(UInt(max_k.W)) val and_back_neg = Wire(Vec(max_k, UInt())) val and_back_neg_uint = Wire(UInt(max_k.W)) val delta_uint = Wire(UInt(max_k.W)) forward_map := Reverse(prefetch_input << (params.N.U - snoop_offset - 1.U)) backward_map := prefetch_input >> snoop_offset //should be unsigned for (k <- 0 until max_k) { logic_pos(k) := forward_map(k) & (forward_map(2k) \| forward_map((2k)+1)) logic_neg(k) := backward_map(k) & (backward_map(2k) \| backward_map((2k)+1)) } for (i <- 0 until max_k) { and_back_pos(i) := logic_pos(i) & !backward_map(i) and_back_neg(i) := logic_neg(i) & !forward_map(i) } and_back_pos_uint := and_back_pos.asUInt and_back_neg_uint := and_back_neg.asUInt //Prioritize positive delta delta_uint := Mux(and_back_pos_uint =/= 0.U, and_back_pos_uint, and_back_neg_uint) //Buffer prefetches using queue val pref_out = Reg(Output(Flipped(Decoupled(new prefetch_req)))) val queue_out = Reg(Input(Flipped(Decoupled(new prefetch_req)))) val prefetch_active = RegInit(false.B) val reset_deq = RegInit(true.B) val prefetch_queue = Module(new Queue(new prefetch_req, entries=8, flow=true)) prefetch_queue.io.enq <> pref_out prefetch_queue.io.deq <> queue_out //Add generated prefetch to queue when (delta_uint =/= 0.U && io.snoop.valid && !already_accessed) { when (and_back_pos_uint =/= 0.U) { //Positive delta was selected pref_out.bits.addr := io.snoop.bits.block_address + (PriorityEncoder(delta_uint) << log2Up(io.snoop.bits.blockBytes)) } .otherwise { //Negative delta was selected pref_out.bits.addr := io.snoop.bits.block_address - (PriorityEncoder(delta_uint) << log2Up(io.snoop.bits.blockBytes)) } pref_out.bits.write := io.snoop.bits.write pref_out.valid := true.B prefetch_active := true.B } .otherwise { pref_out.valid := false.B } io.request.bits.address := prefetch_queue.io.deq.bits.addr io.request.valid := prefetch_active io.request.bits.write := prefetch_queue.io.deq.bits.write //Dequeue when (io.request.fire) { prefetch_queue.io.deq.ready := true.B reset_deq := true.B prefetch_active := false.B } when (reset_deq) { //reset dequeue ready prefetch_queue.io.deq.ready := false.B reset_deq := false.B } } //N is num cache lines per zone class MemoryAccessMap(val N: Int) extends Bundle { // false -> init, true -> access val states = Vec(N, Bool()) val tag = UInt() // top bits of mem address } class MemoryAccessMapBank(val entries: Int, val N: Int) extends Bundle { val maps = Vec(entries, Valid(new MemoryAccessMap(N))) } class prefetch_req extends Bundle { val addr = UInt() val write = Bool() } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AbstractPrefetcher.scala: package barf import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem.{CacheBlockBytes} trait CanInstantiatePrefetcher { def desc: String def instantiate()(implicit p: Parameters): AbstractPrefetcher } class Snoop(implicit val p: Parameters) extends Bundle { val blockBytes = p(CacheBlockBytes) val write = Bool() val address = UInt() def block = address >> log2Up(blockBytes) def block_address = block << log2Up(blockBytes) } class Prefetch(implicit val p: Parameters) extends Bundle { val blockBytes = p(CacheBlockBytes) val write = Bool() val address = UInt() def block = address >> log2Up(blockBytes) def block_address = block << log2Up(blockBytes) } class PrefetcherIO(implicit p: Parameters) extends Bundle { val snoop = Input(Valid(new Snoop)) val request = Decoupled(new Prefetch) val hit = Output(Bool()) } abstract class AbstractPrefetcher(implicit p: Parameters) extends Module { val io = IO(new PrefetcherIO) io.request.valid := false.B io.request.bits := DontCare io.request.bits.address := 0.U(1.W) io.hit := false.B } case class NullPrefetcherParams() extends CanInstantiatePrefetcher { def desc() = "Null Prefetcher" def instantiate()(implicit p: Parameters) = Module(new NullPrefetcher()(p)) } class NullPrefetcher(implicit p: Parameters) extends AbstractPrefetcher()(p) File TLPrefetcher.scala: package barf import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ case class TLPrefetcherParams( prefetchIds: Int = 4, prefetcher: String => Option[CanInstantiatePrefetcher] = _ => None ) case object TLPrefetcherKey extends Field[TLPrefetcherParams](TLPrefetcherParams()) class TLPrefetcher(implicit p: Parameters) extends LazyModule { val params = p(TLPrefetcherKey) def mapInputIds(masters: Seq[TLMasterParameters]) = TLXbar.assignRanges(masters.map(_.sourceId.size + params.prefetchIds)) val node = TLAdapterNode( clientFn = { cp => cp.v1copy(clients = (mapInputIds(cp.clients) zip cp.clients).map { case (range, c) => c.v1copy( sourceId = range )}) }, managerFn = { mp => mp } ) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val nClients = edgeOut.master.clients.size val outIdMap = edgeOut.master.clients.map(_.sourceId) val inIdMap = edgeIn.master.clients.map(_.sourceId) val snoop = Wire(Valid(new Snoop)) val snoop_client = Wire(UInt(log2Ceil(nClients).W)) // Implement prefetchers per client. val prefetchers = edgeOut.master.clients.zipWithIndex.map { case (c,i) => val pParams = params.prefetcher(c.name).getOrElse(NullPrefetcherParams()) println(s"Prefetcher for ${c.name}: ${pParams.desc}") val prefetcher = pParams.instantiate() prefetcher.io.snoop.valid := snoop.valid && snoop_client === i.U prefetcher.io.snoop.bits := snoop.bits prefetcher } val out_arb = Module(new RRArbiter(new Prefetch, nClients)) out_arb.io.in <> prefetchers.map(_.io.request) val tracker = RegInit(0.U(params.prefetchIds.W)) val next_tracker = PriorityEncoder(~tracker) val tracker_free = !tracker(next_tracker) def inIdAdjuster(source: UInt) = Mux1H((inIdMap zip outIdMap).map { case (i,o) => i.contains(source) -> (o.start.U \| (source - i.start.U)) }) def outIdAdjuster(source: UInt) = Mux1H((inIdMap zip outIdMap).map { case (i,o) => o.contains(source) -> (trim(source - o.start.U, i.size) + i.start.U) }) def outIdToPrefetchId(source: UInt) = Mux1H((inIdMap zip outIdMap).map { case (i,o) => o.contains(source) -> trim(source - (o.start + i.size).U, params.prefetchIds) }) def prefetchIdToOutId(source: UInt, client: UInt) = Mux1H((inIdMap zip outIdMap).zipWithIndex.map { case ((i,o),id) => (id.U === client) -> ((o.start + i.size).U +& source) }) def inIdToClientId(source: UInt) = Mux1H(inIdMap.zipWithIndex.map { case (i,id) => i.contains(source) -> id.U }) out <> in out.a.bits.source := inIdAdjuster(in.a.bits.source) in.b.bits.source := outIdAdjuster(out.b.bits.source) out.c.bits.source := inIdAdjuster(in.c.bits.source) val d_is_prefetch = out.d.bits.opcode === TLMessages.HintAck in.d.valid := out.d.valid && !d_is_prefetch when (d_is_prefetch) { out.d.ready := true.B } in.d.bits.source := outIdAdjuster(out.d.bits.source) tracker := (tracker ^ ((out.d.valid && d_is_prefetch) << outIdToPrefetchId(out.d.bits.source)) ^ ((out.a.fire && !in.a.valid) << next_tracker) ) snoop.valid := in.a.fire && edgeIn.manager.supportsAcquireBFast(in.a.bits.address, log2Ceil(p(CacheBlockBytes)).U) snoop.bits.address := in.a.bits.address val acq = in.a.bits.opcode.isOneOf(TLMessages.AcquireBlock, TLMessages.AcquirePerm) val toT = in.a.bits.param.isOneOf(TLPermissions.NtoT, TLPermissions.BtoT) val put = edgeIn.hasData(in.a.bits) snoop.bits.write := put \|\| (acq && toT) snoop_client := inIdToClientId(in.a.bits.source) val legal_address = edgeOut.manager.findSafe(out_arb.io.out.bits.block_address).reduce(_\|\|_) val (legal, hint) = edgeOut.Hint( prefetchIdToOutId(next_tracker, out_arb.io.chosen), out_arb.io.out.bits.block_address, log2Up(p(CacheBlockBytes)).U, Mux(out_arb.io.out.bits.write, TLHints.PREFETCH_WRITE, TLHints.PREFETCH_READ) ) out_arb.io.out.ready := false.B when (!in.a.valid) { out.a.valid := out_arb.io.out.valid && tracker_free && legal && legal_address out.a.bits := hint out_arb.io.out.ready := out.a.ready } when (!legal \|\| !legal_address) { out_arb.io.out.ready := true.B } } } } object TLPrefetcher { def apply()(implicit p: Parameters) = { val prefetcher = LazyModule(new TLPrefetcher) prefetcher.node } } case class TilePrefetchingMasterPortParams(tileId: Int, base: HierarchicalElementPortParamsLike) extends HierarchicalElementPortParamsLike { val where = base.where def injectNode(context: Attachable)(implicit p: Parameters): TLNode = { TLPrefetcher() := base.injectNode(context)(p) } }	module TLPrefetcher( // @[TLPrefetcher.scala:35:25] input clock, // @[TLPrefetcher.scala:35:25] input reset, // @[TLPrefetcher.scala:35:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire _out_arb_io_in_0_ready; // @[TLPrefetcher.scala:54:27] wire _out_arb_io_in_1_ready; // @[TLPrefetcher.scala:54:27] wire _out_arb_io_in_2_ready; // @[TLPrefetcher.scala:54:27] wire _out_arb_io_out_valid; // @[TLPrefetcher.scala:54:27] wire _out_arb_io_out_bits_write; // @[TLPrefetcher.scala:54:27] wire [31:0] _out_arb_io_out_bits_address; // @[TLPrefetcher.scala:54:27] wire [1:0] _out_arb_io_chosen; // @[TLPrefetcher.scala:54:27] wire _prefetchers_2_io_request_valid; // @[NextLine.scala:106:53] wire _prefetchers_2_io_request_bits_write; // @[NextLine.scala:106:53] wire [31:0] _prefetchers_2_io_request_bits_address; // @[NextLine.scala:106:53] wire _prefetchers_0_io_request_valid; // @[AMPM.scala:29:53] wire _prefetchers_0_io_request_bits_write; // @[AMPM.scala:29:53] wire [31:0] _prefetchers_0_io_request_bits_address; // @[AMPM.scala:29:53] wire auto_in_a_valid_0 = auto_in_a_valid; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[TLPrefetcher.scala:35:25] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[TLPrefetcher.scala:35:25] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[TLPrefetcher.scala:35:25] wire auto_in_b_ready_0 = auto_in_b_ready; // @[TLPrefetcher.scala:35:25] wire auto_in_c_valid_0 = auto_in_c_valid; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[TLPrefetcher.scala:35:25] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[TLPrefetcher.scala:35:25] wire auto_in_d_ready_0 = auto_in_d_ready; // @[TLPrefetcher.scala:35:25] wire auto_in_e_valid_0 = auto_in_e_valid; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[TLPrefetcher.scala:35:25] wire auto_out_a_ready_0 = auto_out_a_ready; // @[TLPrefetcher.scala:35:25] wire auto_out_b_valid_0 = auto_out_b_valid; // @[TLPrefetcher.scala:35:25] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[TLPrefetcher.scala:35:25] wire auto_out_c_ready_0 = auto_out_c_ready; // @[TLPrefetcher.scala:35:25] wire auto_out_d_valid_0 = auto_out_d_valid; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[TLPrefetcher.scala:35:25] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[TLPrefetcher.scala:35:25] wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[TLPrefetcher.scala:35:25] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[TLPrefetcher.scala:35:25] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[TLPrefetcher.scala:35:25] wire [2:0] _nodeIn_b_bits_source_T_19 = 3'h2; // @[Parameters.scala:46:9] wire [2:0] _nodeIn_d_bits_source_T_19 = 3'h2; // @[Parameters.scala:46:9] wire [5:0] _nodeIn_b_bits_source_T_6 = 6'h0; // @[TLPrefetcher.scala:65:44] wire [4:0] _nodeIn_b_bits_source_T_7 = 5'h0; // @[TLPrefetcher.scala:65:44] wire [5:0] _nodeIn_b_bits_source_T_17 = 6'h8; // @[TLPrefetcher.scala:65:44] wire [4:0] _nodeIn_b_bits_source_T_18 = 5'h8; // @[TLPrefetcher.scala:65:44] wire [5:0] _nodeIn_b_bits_source_T_27 = 6'h10; // @[TLPrefetcher.scala:65:44] wire [1:0] _nodeIn_b_bits_source_T_9 = 2'h0; // @[TLPrefetcher.scala:65:65] wire [1:0] _nodeIn_b_bits_source_T_32 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _nodeIn_b_bits_source_T_34 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _nodeIn_b_bits_source_T = 2'h2; // @[Parameters.scala:54:10] wire [1:0] _nodeIn_b_bits_source_T_11 = 2'h2; // @[Parameters.scala:54:10] wire [1:0] _nodeIn_b_bits_source_T_20 = 2'h2; // @[TLPrefetcher.scala:65:65] wire [1:0] _nodeIn_b_bits_source_T_21 = 2'h2; // @[Parameters.scala:54:10] wire [1:0] _nodeIn_d_bits_source_T_20 = 2'h2; // @[TLPrefetcher.scala:65:65] wire [1:0] a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _nodeIn_b_bits_source_T_29 = 4'h4; // @[TLPrefetcher.scala:62:52, :65:65] wire [3:0] _nodeIn_d_bits_source_T_29 = 4'h4; // @[TLPrefetcher.scala:62:52, :65:65] wire [3:0] _a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [2:0] _nodeIn_b_bits_source_T_30 = 3'h4; // @[TLPrefetcher.scala:65:65] wire [2:0] _nodeIn_d_bits_source_T_30 = 3'h4; // @[TLPrefetcher.scala:65:65] wire [2:0] _a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] hint_opcode = 3'h5; // @[Edges.scala:551:17] wire [2:0] a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [4:0] auto_out_b_bits_source = 5'h10; // @[TLPrefetcher.scala:35:25] wire [4:0] nodeOut_b_bits_source = 5'h10; // @[MixedNode.scala:542:17] wire [4:0] _nodeIn_b_bits_source_uncommonBits_T = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _nodeIn_b_bits_source_uncommonBits_T_1 = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _nodeIn_b_bits_source_uncommonBits_T_2 = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _nodeIn_b_bits_source_T_28 = 5'h10; // @[TLPrefetcher.scala:65:44] wire auto_in_e_ready = 1'h1; // @[TLPrefetcher.scala:35:25] wire auto_out_e_ready = 1'h1; // @[TLPrefetcher.scala:35:25] wire nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire nodeOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire _nodeOut_a_bits_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _nodeOut_a_bits_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_b_bits_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _nodeIn_b_bits_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_b_bits_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _nodeIn_b_bits_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_b_bits_source_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _nodeIn_b_bits_source_T_13 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_b_bits_source_T_15 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_b_bits_source_T_23 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_b_bits_source_T_25 = 1'h1; // @[Parameters.scala:57:20] wire _nodeOut_c_bits_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _nodeOut_c_bits_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_d_bits_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_d_bits_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_d_bits_source_T_13 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_d_bits_source_T_15 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_d_bits_source_T_23 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_d_bits_source_T_25 = 1'h1; // @[Parameters.scala:57:20] wire _tracker_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _tracker_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _tracker_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _tracker_T_14 = 1'h1; // @[Parameters.scala:57:20] wire _tracker_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _tracker_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _snoop_valid_T_20 = 1'h1; // @[Parameters.scala:91:44] wire _snoop_valid_T_21 = 1'h1; // @[Parameters.scala:684:29] wire _snoop_client_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _snoop_client_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_47 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_48 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_49 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_50 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire auto_in_b_bits_corrupt = 1'h0; // @[TLPrefetcher.scala:35:25] wire auto_out_b_bits_corrupt = 1'h0; // @[TLPrefetcher.scala:35:25] wire nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _nodeIn_b_bits_source_T_8 = 1'h0; // @[TLPrefetcher.scala:33:67] wire _nodeIn_b_bits_source_T_10 = 1'h0; // @[TLPrefetcher.scala:65:65] wire _nodeIn_b_bits_source_T_12 = 1'h0; // @[Parameters.scala:54:32] wire _nodeIn_b_bits_source_T_14 = 1'h0; // @[Parameters.scala:54:67] wire _nodeIn_b_bits_source_T_16 = 1'h0; // @[Parameters.scala:56:48] wire _nodeIn_b_bits_source_T_22 = 1'h0; // @[Parameters.scala:54:32] wire _nodeIn_b_bits_source_T_24 = 1'h0; // @[Parameters.scala:54:67] wire _nodeIn_b_bits_source_T_26 = 1'h0; // @[Parameters.scala:56:48] wire _nodeIn_b_bits_source_T_31 = 1'h0; // @[Mux.scala:30:73] wire _snoop_valid_T_1 = 1'h0; // @[Parameters.scala:684:29] wire _snoop_valid_T_19 = 1'h0; // @[Parameters.scala:684:54] wire _snoop_valid_T_34 = 1'h0; // @[Parameters.scala:686:26] wire _snoop_client_T_8 = 1'h0; // @[Mux.scala:30:73] wire _legal_T_10 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_46 = 1'h0; // @[Parameters.scala:684:54] wire hint_corrupt = 1'h0; // @[Edges.scala:551:17] wire a_mask_sub_sub_bit = 1'h0; // @[Misc.scala:210:26] wire a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire a_mask_sub_bit = 1'h0; // @[Misc.scala:210:26] wire _a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_mask_bit = 1'h0; // @[Misc.scala:210:26] wire [63:0] auto_in_b_bits_data = 64'h0; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_out_b_bits_data = 64'h0; // @[TLPrefetcher.scala:35:25] wire [63:0] nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] hint_data = 64'h0; // @[Edges.scala:551:17] wire [7:0] auto_in_b_bits_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] nodeIn_b_bits_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] hint_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] _a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire [2:0] auto_in_b_bits_source = 3'h0; // @[TLPrefetcher.scala:35:25] wire [2:0] nodeIn_b_bits_source = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_source_uncommonBits = 3'h0; // @[Parameters.scala:52:56] wire [2:0] nodeIn_b_bits_source_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] nodeIn_b_bits_source_uncommonBits_2 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _nodeIn_b_bits_source_T_33 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeIn_b_bits_source_T_35 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeIn_b_bits_source_WIRE = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_in_b_bits_size = 4'h6; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_out_b_bits_size = 4'h6; // @[TLPrefetcher.scala:35:25] wire [3:0] nodeIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] hint_size = 4'h6; // @[Edges.scala:551:17] wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[TLPrefetcher.scala:35:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] _a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire nodeIn_a_valid = auto_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire nodeIn_b_ready = auto_in_b_ready_0; // @[MixedNode.scala:551:17] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[MixedNode.scala:551:17] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[MixedNode.scala:551:17] wire nodeIn_d_ready = auto_in_d_ready_0; // @[MixedNode.scala:551:17] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[MixedNode.scala:542:17] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[MixedNode.scala:542:17] wire nodeOut_c_ready = auto_out_c_ready_0; // @[MixedNode.scala:542:17] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[TLPrefetcher.scala:35:25] wire [1:0] auto_in_b_bits_param_0; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_in_b_bits_address_0; // @[TLPrefetcher.scala:35:25] wire auto_in_b_valid_0; // @[TLPrefetcher.scala:35:25] wire auto_in_c_ready_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_d_bits_opcode_0; // @[TLPrefetcher.scala:35:25] wire [1:0] auto_in_d_bits_param_0; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_in_d_bits_size_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_d_bits_source_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_d_bits_sink_0; // @[TLPrefetcher.scala:35:25] wire auto_in_d_bits_denied_0; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_in_d_bits_data_0; // @[TLPrefetcher.scala:35:25] wire auto_in_d_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] wire auto_in_d_valid_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_a_bits_opcode_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_a_bits_param_0; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_out_a_bits_size_0; // @[TLPrefetcher.scala:35:25] wire [4:0] auto_out_a_bits_source_0; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_out_a_bits_address_0; // @[TLPrefetcher.scala:35:25] wire [7:0] auto_out_a_bits_mask_0; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_out_a_bits_data_0; // @[TLPrefetcher.scala:35:25] wire auto_out_a_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] wire auto_out_a_valid_0; // @[TLPrefetcher.scala:35:25] wire auto_out_b_ready_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_c_bits_opcode_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_c_bits_param_0; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_out_c_bits_size_0; // @[TLPrefetcher.scala:35:25] wire [4:0] auto_out_c_bits_source_0; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_out_c_bits_address_0; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_out_c_bits_data_0; // @[TLPrefetcher.scala:35:25] wire auto_out_c_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] wire auto_out_c_valid_0; // @[TLPrefetcher.scala:35:25] wire auto_out_d_ready_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_e_bits_sink_0; // @[TLPrefetcher.scala:35:25] wire auto_out_e_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] _nodeOut_a_bits_source_uncommonBits_T = nodeIn_a_bits_source; // @[Parameters.scala:52:29] wire [2:0] _snoop_client_uncommonBits_T = nodeIn_a_bits_source; // @[Parameters.scala:52:29] wire [31:0] snoop_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire [31:0] _snoop_valid_T_2 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[MixedNode.scala:551:17] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[MixedNode.scala:551:17] assign nodeOut_c_valid = nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_opcode = nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_param = nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_size = nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] _nodeOut_c_bits_source_uncommonBits_T = nodeIn_c_bits_source; // @[Parameters.scala:52:29] assign nodeOut_c_bits_address = nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_data = nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_corrupt = nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T_1; // @[TLPrefetcher.scala:82:33] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[MixedNode.scala:551:17] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] _nodeIn_d_bits_source_WIRE; // @[Mux.scala:30:73] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign nodeOut_e_valid = nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_e_bits_sink = nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[MixedNode.scala:542:17] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_param = nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_address = nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_c_ready = nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[MixedNode.scala:542:17] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[MixedNode.scala:542:17] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [4:0] _nodeOut_c_bits_source_WIRE; // @[Mux.scala:30:73] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[MixedNode.scala:542:17] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[MixedNode.scala:542:17] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[MixedNode.scala:542:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] _nodeIn_d_bits_source_uncommonBits_T = nodeOut_d_bits_source; // @[Parameters.scala:52:29] wire [4:0] _nodeIn_d_bits_source_uncommonBits_T_1 = nodeOut_d_bits_source; // @[Parameters.scala:52:29] wire [4:0] _nodeIn_d_bits_source_uncommonBits_T_2 = nodeOut_d_bits_source; // @[Parameters.scala:52:29] wire [4:0] _tracker_uncommonBits_T = nodeOut_d_bits_source; // @[Parameters.scala:52:29] wire [4:0] _tracker_uncommonBits_T_1 = nodeOut_d_bits_source; // @[Parameters.scala:52:29] wire [4:0] _tracker_uncommonBits_T_2 = nodeOut_d_bits_source; // @[Parameters.scala:52:29] assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire _snoop_valid_T_36; // @[TLPrefetcher.scala:90:32] wire _snoop_bits_write_T_1; // @[TLPrefetcher.scala:95:31] wire snoop_bits_write; // @[TLPrefetcher.scala:41:23] wire snoop_valid; // @[TLPrefetcher.scala:41:23] wire [1:0] _snoop_client_WIRE; // @[Mux.scala:30:73] wire [1:0] snoop_client; // @[TLPrefetcher.scala:42:30] wire _prefetcher_io_snoop_valid_T = snoop_client == 2'h0; // @[TLPrefetcher.scala:42:30, :49:66] wire _prefetcher_io_snoop_valid_T_1 = snoop_valid & _prefetcher_io_snoop_valid_T; // @[TLPrefetcher.scala:41:23, :49:{50,66}] wire _prefetcher_io_snoop_valid_T_2 = snoop_client == 2'h1; // @[TLPrefetcher.scala:42:30, :49:66] wire _prefetcher_io_snoop_valid_T_3 = snoop_valid & _prefetcher_io_snoop_valid_T_2; // @[TLPrefetcher.scala:41:23, :49:{50,66}] wire _prefetcher_io_snoop_valid_T_4 = snoop_client == 2'h2; // @[TLPrefetcher.scala:42:30, :49:66] wire _prefetcher_io_snoop_valid_T_5 = snoop_valid & _prefetcher_io_snoop_valid_T_4; // @[TLPrefetcher.scala:41:23, :49:{50,66}] reg [3:0] tracker; // @[TLPrefetcher.scala:57:28] wire [3:0] _next_tracker_T = ~tracker; // @[TLPrefetcher.scala:57:28, :58:42] wire _next_tracker_T_1 = _next_tracker_T[0]; // @[OneHot.scala:48:45] wire _next_tracker_T_2 = _next_tracker_T[1]; // @[OneHot.scala:48:45] wire _next_tracker_T_3 = _next_tracker_T[2]; // @[OneHot.scala:48:45] wire _next_tracker_T_4 = _next_tracker_T[3]; // @[OneHot.scala:48:45] wire [1:0] _next_tracker_T_5 = {1'h1, ~_next_tracker_T_3}; // @[OneHot.scala:48:45] wire [1:0] _next_tracker_T_6 = _next_tracker_T_2 ? 2'h1 : _next_tracker_T_5; // @[OneHot.scala:48:45] wire [1:0] next_tracker = _next_tracker_T_1 ? 2'h0 : _next_tracker_T_6; // @[OneHot.scala:48:45] wire [3:0] _GEN = {2'h0, next_tracker}; // @[Mux.scala:50:70] wire [3:0] _tracker_free_T = tracker >> _GEN; // @[TLPrefetcher.scala:57:28, :59:34] wire _tracker_free_T_1 = _tracker_free_T[0]; // @[TLPrefetcher.scala:59:34] wire tracker_free = ~_tracker_free_T_1; // @[TLPrefetcher.scala:59:{26,34}] wire nodeOut_a_bits_source_uncommonBits = _nodeOut_a_bits_source_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _nodeOut_a_bits_source_T = nodeIn_a_bits_source[2:1]; // @[Parameters.scala:54:10] wire [1:0] _snoop_client_T = nodeIn_a_bits_source[2:1]; // @[Parameters.scala:54:10] wire _nodeOut_a_bits_source_T_1 = _nodeOut_a_bits_source_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _nodeOut_a_bits_source_T_3 = _nodeOut_a_bits_source_T_1; // @[Parameters.scala:54:{32,67}] wire _nodeOut_a_bits_source_T_5 = _nodeOut_a_bits_source_T_3; // @[Parameters.scala:54:67, :56:48] wire [3:0] _nodeOut_a_bits_source_T_6 = {1'h0, nodeIn_a_bits_source}; // @[MixedNode.scala:551:17] wire [2:0] _nodeOut_a_bits_source_T_7 = _nodeOut_a_bits_source_T_6[2:0]; // @[TLPrefetcher.scala:62:52] wire [4:0] _nodeOut_a_bits_source_T_8 = {2'h2, _nodeOut_a_bits_source_T_7}; // @[TLPrefetcher.scala:62:{42,52}] wire _GEN_0 = nodeIn_a_bits_source == 3'h2; // @[Parameters.scala:46:9] wire _nodeOut_a_bits_source_T_9; // @[Parameters.scala:46:9] assign _nodeOut_a_bits_source_T_9 = _GEN_0; // @[Parameters.scala:46:9] wire _snoop_client_T_6; // @[Parameters.scala:46:9] assign _snoop_client_T_6 = _GEN_0; // @[Parameters.scala:46:9] wire [3:0] _nodeOut_a_bits_source_T_10 = _nodeOut_a_bits_source_T_6 - 4'h2; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_a_bits_source_T_11 = _nodeOut_a_bits_source_T_10[2:0]; // @[TLPrefetcher.scala:62:52] wire [3:0] _nodeOut_a_bits_source_T_12 = {1'h1, _nodeOut_a_bits_source_T_11}; // @[TLPrefetcher.scala:62:{42,52}] wire _GEN_1 = nodeIn_a_bits_source == 3'h4; // @[Parameters.scala:46:9] wire _nodeOut_a_bits_source_T_13; // @[Parameters.scala:46:9] assign _nodeOut_a_bits_source_T_13 = _GEN_1; // @[Parameters.scala:46:9] wire _snoop_client_T_7; // @[Parameters.scala:46:9] assign _snoop_client_T_7 = _GEN_1; // @[Parameters.scala:46:9] wire [3:0] _nodeOut_a_bits_source_T_14 = _nodeOut_a_bits_source_T_6 - 4'h4; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_a_bits_source_T_15 = _nodeOut_a_bits_source_T_14[2:0]; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_a_bits_source_T_16 = _nodeOut_a_bits_source_T_15; // @[TLPrefetcher.scala:62:{42,52}] wire [4:0] _nodeOut_a_bits_source_T_17 = _nodeOut_a_bits_source_T_5 ? _nodeOut_a_bits_source_T_8 : 5'h0; // @[Mux.scala:30:73] wire [3:0] _nodeOut_a_bits_source_T_18 = _nodeOut_a_bits_source_T_9 ? _nodeOut_a_bits_source_T_12 : 4'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_source_T_19 = _nodeOut_a_bits_source_T_13 ? _nodeOut_a_bits_source_T_16 : 3'h0; // @[Mux.scala:30:73] wire [4:0] _nodeOut_a_bits_source_T_20 = {_nodeOut_a_bits_source_T_17[4], _nodeOut_a_bits_source_T_17[3:0] \| _nodeOut_a_bits_source_T_18}; // @[Mux.scala:30:73] wire [4:0] _nodeOut_a_bits_source_T_21 = {_nodeOut_a_bits_source_T_20[4:3], _nodeOut_a_bits_source_T_20[2:0] \| _nodeOut_a_bits_source_T_19}; // @[Mux.scala:30:73] wire [4:0] _nodeOut_a_bits_source_WIRE = _nodeOut_a_bits_source_T_21; // @[Mux.scala:30:73] wire nodeOut_c_bits_source_uncommonBits = _nodeOut_c_bits_source_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _nodeOut_c_bits_source_T = nodeIn_c_bits_source[2:1]; // @[Parameters.scala:54:10] wire _nodeOut_c_bits_source_T_1 = _nodeOut_c_bits_source_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _nodeOut_c_bits_source_T_3 = _nodeOut_c_bits_source_T_1; // @[Parameters.scala:54:{32,67}] wire _nodeOut_c_bits_source_T_5 = _nodeOut_c_bits_source_T_3; // @[Parameters.scala:54:67, :56:48] wire [3:0] _nodeOut_c_bits_source_T_6 = {1'h0, nodeIn_c_bits_source}; // @[MixedNode.scala:551:17] wire [2:0] _nodeOut_c_bits_source_T_7 = _nodeOut_c_bits_source_T_6[2:0]; // @[TLPrefetcher.scala:62:52] wire [4:0] _nodeOut_c_bits_source_T_8 = {2'h2, _nodeOut_c_bits_source_T_7}; // @[TLPrefetcher.scala:62:{42,52}] wire _nodeOut_c_bits_source_T_9 = nodeIn_c_bits_source == 3'h2; // @[Parameters.scala:46:9] wire [3:0] _nodeOut_c_bits_source_T_10 = _nodeOut_c_bits_source_T_6 - 4'h2; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_c_bits_source_T_11 = _nodeOut_c_bits_source_T_10[2:0]; // @[TLPrefetcher.scala:62:52] wire [3:0] _nodeOut_c_bits_source_T_12 = {1'h1, _nodeOut_c_bits_source_T_11}; // @[TLPrefetcher.scala:62:{42,52}] wire _nodeOut_c_bits_source_T_13 = nodeIn_c_bits_source == 3'h4; // @[Parameters.scala:46:9] wire [3:0] _nodeOut_c_bits_source_T_14 = _nodeOut_c_bits_source_T_6 - 4'h4; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_c_bits_source_T_15 = _nodeOut_c_bits_source_T_14[2:0]; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_c_bits_source_T_16 = _nodeOut_c_bits_source_T_15; // @[TLPrefetcher.scala:62:{42,52}] wire [4:0] _nodeOut_c_bits_source_T_17 = _nodeOut_c_bits_source_T_5 ? _nodeOut_c_bits_source_T_8 : 5'h0; // @[Mux.scala:30:73] wire [3:0] _nodeOut_c_bits_source_T_18 = _nodeOut_c_bits_source_T_9 ? _nodeOut_c_bits_source_T_12 : 4'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_source_T_19 = _nodeOut_c_bits_source_T_13 ? _nodeOut_c_bits_source_T_16 : 3'h0; // @[Mux.scala:30:73] wire [4:0] _nodeOut_c_bits_source_T_20 = {_nodeOut_c_bits_source_T_17[4], _nodeOut_c_bits_source_T_17[3:0] \| _nodeOut_c_bits_source_T_18}; // @[Mux.scala:30:73] wire [4:0] _nodeOut_c_bits_source_T_21 = {_nodeOut_c_bits_source_T_20[4:3], _nodeOut_c_bits_source_T_20[2:0] \| _nodeOut_c_bits_source_T_19}; // @[Mux.scala:30:73] assign _nodeOut_c_bits_source_WIRE = _nodeOut_c_bits_source_T_21; // @[Mux.scala:30:73] assign nodeOut_c_bits_source = _nodeOut_c_bits_source_WIRE; // @[Mux.scala:30:73] wire d_is_prefetch = nodeOut_d_bits_opcode == 3'h2; // @[Parameters.scala:46:9] wire _nodeIn_d_valid_T = ~d_is_prefetch; // @[TLPrefetcher.scala:81:45, :82:36] assign _nodeIn_d_valid_T_1 = nodeOut_d_valid & _nodeIn_d_valid_T; // @[MixedNode.scala:542:17] assign nodeIn_d_valid = _nodeIn_d_valid_T_1; // @[MixedNode.scala:551:17] assign nodeOut_d_ready = d_is_prefetch \| nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire [2:0] nodeIn_d_bits_source_uncommonBits = _nodeIn_d_bits_source_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _nodeIn_d_bits_source_T = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire [1:0] _nodeIn_d_bits_source_T_11 = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire [1:0] _nodeIn_d_bits_source_T_21 = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire [1:0] _tracker_T_1 = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire [1:0] _tracker_T_10 = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire [1:0] _tracker_T_19 = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire _nodeIn_d_bits_source_T_1 = _nodeIn_d_bits_source_T == 2'h2; // @[Parameters.scala:54:{10,32}] wire _nodeIn_d_bits_source_T_3 = _nodeIn_d_bits_source_T_1; // @[Parameters.scala:54:{32,67}] wire _nodeIn_d_bits_source_T_5 = _nodeIn_d_bits_source_T_3; // @[Parameters.scala:54:67, :56:48] wire [5:0] _nodeIn_d_bits_source_T_27 = {1'h0, nodeOut_d_bits_source}; // @[MixedNode.scala:542:17] wire [5:0] _nodeIn_d_bits_source_T_6 = _nodeIn_d_bits_source_T_27 - 6'h10; // @[TLPrefetcher.scala:65:44] wire [4:0] _nodeIn_d_bits_source_T_7 = _nodeIn_d_bits_source_T_6[4:0]; // @[TLPrefetcher.scala:65:44] wire _nodeIn_d_bits_source_T_8 = _nodeIn_d_bits_source_T_7[0]; // @[TLPrefetcher.scala:33:67, :65:44] wire [1:0] _nodeIn_d_bits_source_T_9 = {1'h0, _nodeIn_d_bits_source_T_8}; // @[TLPrefetcher.scala:33:67, :65:65] wire _nodeIn_d_bits_source_T_10 = _nodeIn_d_bits_source_T_9[0]; // @[TLPrefetcher.scala:65:65] wire [2:0] nodeIn_d_bits_source_uncommonBits_1 = _nodeIn_d_bits_source_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _nodeIn_d_bits_source_T_12 = _nodeIn_d_bits_source_T_11 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _nodeIn_d_bits_source_T_14 = _nodeIn_d_bits_source_T_12; // @[Parameters.scala:54:{32,67}] wire _nodeIn_d_bits_source_T_16 = _nodeIn_d_bits_source_T_14; // @[Parameters.scala:54:67, :56:48] wire [5:0] _nodeIn_d_bits_source_T_17 = _nodeIn_d_bits_source_T_27 - 6'h8; // @[TLPrefetcher.scala:65:44] wire [4:0] _nodeIn_d_bits_source_T_18 = _nodeIn_d_bits_source_T_17[4:0]; // @[TLPrefetcher.scala:65:44] wire [2:0] nodeIn_d_bits_source_uncommonBits_2 = _nodeIn_d_bits_source_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _nodeIn_d_bits_source_T_22 = _nodeIn_d_bits_source_T_21 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _nodeIn_d_bits_source_T_24 = _nodeIn_d_bits_source_T_22; // @[Parameters.scala:54:{32,67}] wire _nodeIn_d_bits_source_T_26 = _nodeIn_d_bits_source_T_24; // @[Parameters.scala:54:67, :56:48] wire [4:0] _nodeIn_d_bits_source_T_28 = _nodeIn_d_bits_source_T_27[4:0]; // @[TLPrefetcher.scala:65:44] wire _nodeIn_d_bits_source_T_31 = _nodeIn_d_bits_source_T_5 & _nodeIn_d_bits_source_T_10; // @[Mux.scala:30:73] wire [1:0] _nodeIn_d_bits_source_T_32 = {_nodeIn_d_bits_source_T_16, 1'h0}; // @[Mux.scala:30:73] wire [2:0] _nodeIn_d_bits_source_T_33 = {_nodeIn_d_bits_source_T_26, 2'h0}; // @[Mux.scala:30:73] wire [1:0] _nodeIn_d_bits_source_T_34 = {1'h0, _nodeIn_d_bits_source_T_31} \| _nodeIn_d_bits_source_T_32; // @[Mux.scala:30:73] wire [2:0] _nodeIn_d_bits_source_T_35 = {1'h0, _nodeIn_d_bits_source_T_34} \| _nodeIn_d_bits_source_T_33; // @[Mux.scala:30:73] assign _nodeIn_d_bits_source_WIRE = _nodeIn_d_bits_source_T_35; // @[Mux.scala:30:73] assign nodeIn_d_bits_source = _nodeIn_d_bits_source_WIRE; // @[Mux.scala:30:73] wire _tracker_T = nodeOut_d_valid & d_is_prefetch; // @[MixedNode.scala:542:17] wire [2:0] tracker_uncommonBits = _tracker_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _tracker_T_2 = _tracker_T_1 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _tracker_T_4 = _tracker_T_2; // @[Parameters.scala:54:{32,67}] wire _tracker_T_6 = _tracker_T_4; // @[Parameters.scala:54:67, :56:48] wire [5:0] _tracker_T_7 = _nodeIn_d_bits_source_T_27 - 6'h12; // @[TLPrefetcher.scala:65:44, :68:43] wire [4:0] _tracker_T_8 = _tracker_T_7[4:0]; // @[TLPrefetcher.scala:68:43] wire [1:0] _tracker_T_9 = _tracker_T_8[1:0]; // @[TLPrefetcher.scala:33:67, :68:43] wire [2:0] tracker_uncommonBits_1 = _tracker_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _tracker_T_11 = _tracker_T_10 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _tracker_T_13 = _tracker_T_11; // @[Parameters.scala:54:{32,67}] wire _tracker_T_15 = _tracker_T_13; // @[Parameters.scala:54:67, :56:48] wire [5:0] _tracker_T_16 = _nodeIn_d_bits_source_T_27 - 6'h9; // @[TLPrefetcher.scala:65:44, :68:43] wire [4:0] _tracker_T_17 = _tracker_T_16[4:0]; // @[TLPrefetcher.scala:68:43] wire [1:0] _tracker_T_18 = _tracker_T_17[1:0]; // @[TLPrefetcher.scala:33:67, :68:43] wire [2:0] tracker_uncommonBits_2 = _tracker_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _tracker_T_20 = _tracker_T_19 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _tracker_T_22 = _tracker_T_20; // @[Parameters.scala:54:{32,67}] wire _tracker_T_24 = _tracker_T_22; // @[Parameters.scala:54:67, :56:48] wire [5:0] _tracker_T_25 = _nodeIn_d_bits_source_T_27 - 6'h1; // @[TLPrefetcher.scala:65:44, :68:43] wire [4:0] _tracker_T_26 = _tracker_T_25[4:0]; // @[TLPrefetcher.scala:68:43] wire [1:0] _tracker_T_27 = _tracker_T_26[1:0]; // @[TLPrefetcher.scala:33:67, :68:43] wire [1:0] _tracker_T_28 = _tracker_T_6 ? _tracker_T_9 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _tracker_T_29 = _tracker_T_15 ? _tracker_T_18 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _tracker_T_30 = _tracker_T_24 ? _tracker_T_27 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _tracker_T_31 = _tracker_T_28 \| _tracker_T_29; // @[Mux.scala:30:73] wire [1:0] _tracker_T_32 = _tracker_T_31 \| _tracker_T_30; // @[Mux.scala:30:73] wire [1:0] _tracker_WIRE = _tracker_T_32; // @[Mux.scala:30:73] wire [3:0] _tracker_T_33 = {3'h0, _tracker_T} << _tracker_WIRE; // @[Mux.scala:30:73] wire [3:0] _tracker_T_34 = tracker ^ _tracker_T_33; // @[TLPrefetcher.scala:57:28, :87:{9,43}] wire _tracker_T_35 = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35] wire _tracker_T_36 = ~nodeIn_a_valid; // @[MixedNode.scala:551:17] wire _tracker_T_37 = _tracker_T_35 & _tracker_T_36; // @[Decoupled.scala:51:35] wire [3:0] _tracker_T_38 = {3'h0, _tracker_T_37} << _GEN; // @[TLPrefetcher.scala:59:34, :88:{24,40}] wire [3:0] _tracker_T_39 = _tracker_T_34 ^ _tracker_T_38; // @[TLPrefetcher.scala:87:9, :88:{9,40}] wire _snoop_valid_T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire [32:0] _snoop_valid_T_3 = {1'h0, _snoop_valid_T_2}; // @[Parameters.scala:137:{31,41}] wire [32:0] _snoop_valid_T_4 = _snoop_valid_T_3 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _snoop_valid_T_5 = _snoop_valid_T_4; // @[Parameters.scala:137:46] wire _snoop_valid_T_6 = _snoop_valid_T_5 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _snoop_valid_T_7 = {nodeIn_a_bits_address[31:17], nodeIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] _snoop_valid_T_8 = {1'h0, _snoop_valid_T_7}; // @[Parameters.scala:137:{31,41}] wire [32:0] _snoop_valid_T_9 = _snoop_valid_T_8 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _snoop_valid_T_10 = _snoop_valid_T_9; // @[Parameters.scala:137:46] wire _snoop_valid_T_11 = _snoop_valid_T_10 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _snoop_valid_T_12 = {nodeIn_a_bits_address[31:28], nodeIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] _snoop_valid_T_13 = {1'h0, _snoop_valid_T_12}; // @[Parameters.scala:137:{31,41}] wire [32:0] _snoop_valid_T_14 = _snoop_valid_T_13 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _snoop_valid_T_15 = _snoop_valid_T_14; // @[Parameters.scala:137:46] wire _snoop_valid_T_16 = _snoop_valid_T_15 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _snoop_valid_T_17 = _snoop_valid_T_6 \| _snoop_valid_T_11; // @[Parameters.scala:685:42] wire _snoop_valid_T_18 = _snoop_valid_T_17 \| _snoop_valid_T_16; // @[Parameters.scala:685:42] wire [31:0] _snoop_valid_T_22 = {nodeIn_a_bits_address[31:28], nodeIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] _snoop_valid_T_23 = {1'h0, _snoop_valid_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] _snoop_valid_T_24 = _snoop_valid_T_23 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _snoop_valid_T_25 = _snoop_valid_T_24; // @[Parameters.scala:137:46] wire _snoop_valid_T_26 = _snoop_valid_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _snoop_valid_T_27 = nodeIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _snoop_valid_T_28 = {1'h0, _snoop_valid_T_27}; // @[Parameters.scala:137:{31,41}] wire [32:0] _snoop_valid_T_29 = _snoop_valid_T_28 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _snoop_valid_T_30 = _snoop_valid_T_29; // @[Parameters.scala:137:46] wire _snoop_valid_T_31 = _snoop_valid_T_30 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _snoop_valid_T_32 = _snoop_valid_T_26 \| _snoop_valid_T_31; // @[Parameters.scala:685:42] wire _snoop_valid_T_33 = _snoop_valid_T_32; // @[Parameters.scala:684:54, :685:42] wire _snoop_valid_T_35 = _snoop_valid_T_33; // @[Parameters.scala:684:54, :686:26] assign _snoop_valid_T_36 = _snoop_valid_T & _snoop_valid_T_35; // @[Decoupled.scala:51:35] assign snoop_valid = _snoop_valid_T_36; // @[TLPrefetcher.scala:41:23, :90:32] wire _acq_T = nodeIn_a_bits_opcode == 3'h6; // @[package.scala:16:47] wire _acq_T_1 = &nodeIn_a_bits_opcode; // @[package.scala:16:47] wire acq = _acq_T \| _acq_T_1; // @[package.scala:16:47, :81:59] wire _toT_T = nodeIn_a_bits_param == 3'h1; // @[package.scala:16:47] wire _toT_T_1 = nodeIn_a_bits_param == 3'h2; // @[package.scala:16:47] wire toT = _toT_T \| _toT_T_1; // @[package.scala:16:47, :81:59] wire _put_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire put = ~_put_opdata_T; // @[Edges.scala:92:{28,37}] wire _snoop_bits_write_T = acq & toT; // @[package.scala:81:59] assign _snoop_bits_write_T_1 = put \| _snoop_bits_write_T; // @[Edges.scala:92:28] assign snoop_bits_write = _snoop_bits_write_T_1; // @[TLPrefetcher.scala:41:23, :95:31] wire snoop_client_uncommonBits = _snoop_client_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire _snoop_client_T_1 = _snoop_client_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _snoop_client_T_3 = _snoop_client_T_1; // @[Parameters.scala:54:{32,67}] wire _snoop_client_T_5 = _snoop_client_T_3; // @[Parameters.scala:54:67, :56:48] wire _snoop_client_T_9 = _snoop_client_T_6; // @[Mux.scala:30:73] wire _snoop_client_T_11 = _snoop_client_T_9; // @[Mux.scala:30:73] wire [1:0] _snoop_client_T_10 = {_snoop_client_T_7, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _snoop_client_T_12 = {1'h0, _snoop_client_T_11} \| _snoop_client_T_10; // @[Mux.scala:30:73] assign _snoop_client_WIRE = _snoop_client_T_12; // @[Mux.scala:30:73] assign snoop_client = _snoop_client_WIRE; // @[Mux.scala:30:73] wire [25:0] _legal_address_T = _out_arb_io_out_bits_address[31:6]; // @[TLPrefetcher.scala:54:27] wire [31:0] _legal_address_T_1 = {_legal_address_T, 6'h0}; // @[AbstractPrefetcher.scala:30:23, :31:29] wire [31:0] _legal_address_T_2 = _legal_address_T_1; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_3 = {1'h0, _legal_address_T_2}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_4 = _legal_address_T_3 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_5 = _legal_address_T_4; // @[Parameters.scala:137:46] wire _legal_address_T_6 = _legal_address_T_5 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_6; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_7 = {_legal_address_T_1[31:13], _legal_address_T_1[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_8 = {1'h0, _legal_address_T_7}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_9 = _legal_address_T_8 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_10 = _legal_address_T_9; // @[Parameters.scala:137:46] wire _legal_address_T_11 = _legal_address_T_10 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_11; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_12 = {_legal_address_T_1[31:14], _legal_address_T_1[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_13 = {1'h0, _legal_address_T_12}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_14 = _legal_address_T_13 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_15 = _legal_address_T_14; // @[Parameters.scala:137:46] wire _legal_address_T_16 = _legal_address_T_15 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_16; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_17 = {_legal_address_T_1[31:17], _legal_address_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_18 = {1'h0, _legal_address_T_17}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_19 = _legal_address_T_18 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_20 = _legal_address_T_19; // @[Parameters.scala:137:46] wire _legal_address_T_21 = _legal_address_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_21; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_22 = {_legal_address_T_1[31:21], _legal_address_T_1[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_23 = {1'h0, _legal_address_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_24 = _legal_address_T_23 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_25 = _legal_address_T_24; // @[Parameters.scala:137:46] wire _legal_address_T_26 = _legal_address_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_26; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_27 = {_legal_address_T_1[31:21], _legal_address_T_1[20:0] ^ 21'h110000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_28 = {1'h0, _legal_address_T_27}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_29 = _legal_address_T_28 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_30 = _legal_address_T_29; // @[Parameters.scala:137:46] wire _legal_address_T_31 = _legal_address_T_30 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_31; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_32 = {_legal_address_T_1[31:26], _legal_address_T_1[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_33 = {1'h0, _legal_address_T_32}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_34 = _legal_address_T_33 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_35 = _legal_address_T_34; // @[Parameters.scala:137:46] wire _legal_address_T_36 = _legal_address_T_35 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_36; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_37 = {_legal_address_T_1[31:26], _legal_address_T_1[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_38 = {1'h0, _legal_address_T_37}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_39 = _legal_address_T_38 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_40 = _legal_address_T_39; // @[Parameters.scala:137:46] wire _legal_address_T_41 = _legal_address_T_40 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_41; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_42 = {_legal_address_T_1[31:28], _legal_address_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_43 = {1'h0, _legal_address_T_42}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_44 = _legal_address_T_43 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_45 = _legal_address_T_44; // @[Parameters.scala:137:46] wire _legal_address_T_46 = _legal_address_T_45 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_46; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_47 = {_legal_address_T_1[31:28], _legal_address_T_1[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_48 = {1'h0, _legal_address_T_47}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_49 = _legal_address_T_48 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_50 = _legal_address_T_49; // @[Parameters.scala:137:46] wire _legal_address_T_51 = _legal_address_T_50 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_51; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_52 = {_legal_address_T_1[31:29], _legal_address_T_1[28:0] ^ 29'h10020000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_53 = {1'h0, _legal_address_T_52}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_54 = _legal_address_T_53 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_55 = _legal_address_T_54; // @[Parameters.scala:137:46] wire _legal_address_T_56 = _legal_address_T_55 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_56; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_57 = _legal_address_T_1 ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_58 = {1'h0, _legal_address_T_57}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_59 = _legal_address_T_58 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_60 = _legal_address_T_59; // @[Parameters.scala:137:46] wire _legal_address_T_61 = _legal_address_T_60 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_61; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_WIRE_0 \| _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 \| _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 \| _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 \| _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 \| _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 \| _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 \| _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 \| _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_70 = _legal_address_T_69 \| _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_71 = _legal_address_T_70 \| _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_71 \| _legal_address_WIRE_11; // @[Parameters.scala:612:40] wire [4:0] _GEN_2 = {3'h0, next_tracker}; // @[Mux.scala:50:70] wire [4:0] _GEN_3 = (_out_arb_io_chosen == 2'h0 ? _GEN_2 - 5'hE : 5'h0) \| (_out_arb_io_chosen == 2'h1 ? _GEN_2 + 5'h9 : 5'h0); // @[Mux.scala:30:73] wire [31:0] _T_12 = {_legal_address_T, 6'h0}; // @[AbstractPrefetcher.scala:30:23, :31:29] wire [31:0] _legal_T_11; // @[Parameters.scala:137:31] assign _legal_T_11 = _T_12; // @[Parameters.scala:137:31] wire [31:0] hint_address; // @[Edges.scala:551:17] assign hint_address = _T_12; // @[Edges.scala:551:17] wire [31:0] _legal_T_4 = {_out_arb_io_out_bits_address[31:14], _out_arb_io_out_bits_address[13:6] ^ 8'hC0, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9E013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_63 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _legal_T_12 = {1'h0, _legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_13 = _legal_T_12 & 33'h9E012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_14 = _legal_T_13; // @[Parameters.scala:137:46] wire _legal_T_15 = _legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_out_arb_io_out_bits_address[31:17], _out_arb_io_out_bits_address[16:6] ^ 11'h400, 6'h0}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_16; // @[Parameters.scala:137:31] assign _legal_T_16 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_21; // @[Parameters.scala:137:31] assign _legal_T_21 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_17 = {1'h0, _legal_T_16}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_18 = _legal_T_17 & 33'h9C013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_19 = _legal_T_18; // @[Parameters.scala:137:46] wire _legal_T_20 = _legal_T_19 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_22 = {1'h0, _legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_23 = _legal_T_22 & 33'h9E010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_24 = _legal_T_23; // @[Parameters.scala:137:46] wire _legal_T_25 = _legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_26 = {_out_arb_io_out_bits_address[31:26], _out_arb_io_out_bits_address[25:6] ^ 20'h80000, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_27 = {1'h0, _legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_28 = _legal_T_27 & 33'h9E010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_29 = _legal_T_28; // @[Parameters.scala:137:46] wire _legal_T_30 = _legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_31 = {_out_arb_io_out_bits_address[31:28], _out_arb_io_out_bits_address[27:6] ^ 22'h300000, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_32 = {1'h0, _legal_T_31}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_33 = _legal_T_32 & 33'h9C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_34 = _legal_T_33; // @[Parameters.scala:137:46] wire _legal_T_35 = _legal_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_36 = {_out_arb_io_out_bits_address[31:29], _out_arb_io_out_bits_address[28:6] ^ 23'h400000, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_37 = {1'h0, _legal_T_36}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_38 = _legal_T_37 & 33'h9E013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_39 = _legal_T_38; // @[Parameters.scala:137:46] wire _legal_T_40 = _legal_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_41 = _legal_T_15 \| _legal_T_20; // @[Parameters.scala:685:42] wire _legal_T_42 = _legal_T_41 \| _legal_T_25; // @[Parameters.scala:685:42] wire _legal_T_43 = _legal_T_42 \| _legal_T_30; // @[Parameters.scala:685:42] wire _legal_T_44 = _legal_T_43 \| _legal_T_35; // @[Parameters.scala:685:42] wire _legal_T_45 = _legal_T_44 \| _legal_T_40; // @[Parameters.scala:685:42] wire [31:0] _legal_T_51 = {_out_arb_io_out_bits_address[31:28], _out_arb_io_out_bits_address[27:6] ^ 22'h200000, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_52 = {1'h0, _legal_T_51}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_53 = _legal_T_52 & 33'h9E010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_54 = _legal_T_53; // @[Parameters.scala:137:46] wire _legal_T_55 = _legal_T_54 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_56 = {_legal_address_T ^ 26'h2000000, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_57 = {1'h0, _legal_T_56}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_58 = _legal_T_57 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_59 = _legal_T_58; // @[Parameters.scala:137:46] wire _legal_T_60 = _legal_T_59 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_61 = _legal_T_55 \| _legal_T_60; // @[Parameters.scala:685:42] wire _legal_T_62 = _legal_T_61; // @[Parameters.scala:684:54, :685:42] wire _legal_T_64 = _legal_T_63; // @[Parameters.scala:686:26] wire legal = _legal_T_64 \| _legal_T_62; // @[Parameters.scala:684:54, :686:26] wire [2:0] hint_param; // @[Edges.scala:551:17] wire [4:0] hint_source; // @[Edges.scala:551:17] assign hint_param = {2'h0, _out_arb_io_out_bits_write}; // @[Edges.scala:551:17, :553:15] assign hint_source = {_GEN_3[4:3], _GEN_3[2:0] \| (_out_arb_io_chosen == 2'h2 ? {1'h0, next_tracker} + 3'h1 : 3'h0)}; // @[Mux.scala:30:73, :50:70] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T = a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _a_mask_sub_sub_acc_T_1 = a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_eq; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _nodeOut_a_valid_T = _out_arb_io_out_valid & tracker_free; // @[TLPrefetcher.scala:54:27, :59:26, :107:45] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & legal; // @[Parameters.scala:686:26] wire _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & legal_address; // @[TLPrefetcher.scala:98:95, :107:{61,70}] assign nodeOut_a_valid = nodeIn_a_valid ? nodeIn_a_valid : _nodeOut_a_valid_T_2; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_valid ? nodeIn_a_bits_opcode : 3'h5; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_valid ? nodeIn_a_bits_param : hint_param; // @[Edges.scala:551:17] assign nodeOut_a_bits_size = nodeIn_a_valid ? nodeIn_a_bits_size : 4'h6; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_valid ? _nodeOut_a_bits_source_WIRE : hint_source; // @[Mux.scala:30:73] assign nodeOut_a_bits_address = nodeIn_a_valid ? nodeIn_a_bits_address : hint_address; // @[Edges.scala:551:17] assign nodeOut_a_bits_mask = nodeIn_a_valid ? nodeIn_a_bits_mask : 8'hFF; // @[Misc.scala:222:10] assign nodeOut_a_bits_data = nodeIn_a_valid ? nodeIn_a_bits_data : 64'h0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_valid & nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] always @(posedge clock) begin // @[TLPrefetcher.scala:35:25] if (reset) // @[TLPrefetcher.scala:35:25] tracker <= 4'h0; // @[TLPrefetcher.scala:57:28] else // @[TLPrefetcher.scala:35:25] tracker <= _tracker_T_39; // @[TLPrefetcher.scala:57:28, :88:9] always @(posedge) TLMonitor_4 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AMPMPrefetcher prefetchers_0 ( // @[AMPM.scala:29:53] .clock (clock), .reset (reset), .io_snoop_valid (_prefetcher_io_snoop_valid_T_1), // @[TLPrefetcher.scala:49:50] .io_snoop_bits_write (snoop_bits_write), // @[TLPrefetcher.scala:41:23] .io_snoop_bits_address (snoop_bits_address), // @[TLPrefetcher.scala:41:23] .io_request_ready (_out_arb_io_in_0_ready), // @[TLPrefetcher.scala:54:27] .io_request_valid (_prefetchers_0_io_request_valid), .io_request_bits_write (_prefetchers_0_io_request_bits_write), .io_request_bits_address (_prefetchers_0_io_request_bits_address) ); // @[AMPM.scala:29:53] NullPrefetcher prefetchers_1 ( // @[AbstractPrefetcher.scala:51:53] .clock (clock), .reset (reset), .io_snoop_valid (_prefetcher_io_snoop_valid_T_3), // @[TLPrefetcher.scala:49:50] .io_snoop_bits_write (snoop_bits_write), // @[TLPrefetcher.scala:41:23] .io_snoop_bits_address (snoop_bits_address), // @[TLPrefetcher.scala:41:23] .io_request_ready (_out_arb_io_in_1_ready) // @[TLPrefetcher.scala:54:27] ); // @[AbstractPrefetcher.scala:51:53] MultiNextLinePrefetcher prefetchers_2 ( // @[NextLine.scala:106:53] .clock (clock), .reset (reset), .io_snoop_valid (_prefetcher_io_snoop_valid_T_5), // @[TLPrefetcher.scala:49:50] .io_snoop_bits_write (snoop_bits_write), // @[TLPrefetcher.scala:41:23] .io_snoop_bits_address (snoop_bits_address), // @[TLPrefetcher.scala:41:23] .io_request_ready (_out_arb_io_in_2_ready), // @[TLPrefetcher.scala:54:27] .io_request_valid (_prefetchers_2_io_request_valid), .io_request_bits_write (_prefetchers_2_io_request_bits_write), .io_request_bits_address (_prefetchers_2_io_request_bits_address) ); // @[NextLine.scala:106:53] RRArbiter_1 out_arb ( // @[TLPrefetcher.scala:54:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_io_in_0_ready), .io_in_0_valid (_prefetchers_0_io_request_valid), // @[AMPM.scala:29:53] .io_in_0_bits_write (_prefetchers_0_io_request_bits_write), // @[AMPM.scala:29:53] .io_in_0_bits_address (_prefetchers_0_io_request_bits_address), // @[AMPM.scala:29:53] .io_in_1_ready (_out_arb_io_in_1_ready), .io_in_2_ready (_out_arb_io_in_2_ready), .io_in_2_valid (_prefetchers_2_io_request_valid), // @[NextLine.scala:106:53] .io_in_2_bits_write (_prefetchers_2_io_request_bits_write), // @[NextLine.scala:106:53] .io_in_2_bits_address (_prefetchers_2_io_request_bits_address), // @[NextLine.scala:106:53] .io_out_ready (~legal \| ~legal_address \| ~nodeIn_a_valid & nodeOut_a_ready), // @[Parameters.scala:686:26] .io_out_valid (_out_arb_io_out_valid), .io_out_bits_write (_out_arb_io_out_bits_write), .io_out_bits_address (_out_arb_io_out_bits_address), .io_chosen (_out_arb_io_chosen) ); // @[TLPrefetcher.scala:54:27] assign auto_in_a_ready = auto_in_a_ready_0; // @[TLPrefetcher.scala:35:25] assign auto_in_b_valid = auto_in_b_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[TLPrefetcher.scala:35:25] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[TLPrefetcher.scala:35:25] assign auto_in_c_ready = auto_in_c_ready_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_valid = auto_in_d_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_valid = auto_out_a_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] assign auto_out_b_ready = auto_out_b_ready_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_valid = auto_out_c_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] assign auto_out_d_ready = auto_out_d_ready_0; // @[TLPrefetcher.scala:35:25] assign auto_out_e_valid = auto_out_e_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[TLPrefetcher.scala:35:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag / MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Plic.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.experimental._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.{Annotated, MuxT, property} import scala.math.min import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.SeqToAugmentedSeq class GatewayPLICIO extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) val complete = Input(Bool()) } class LevelGateway extends Module { val io = IO(new Bundle { val interrupt = Input(Bool()) val plic = new GatewayPLICIO }) val inFlight = RegInit(false.B) when (io.interrupt && io.plic.ready) { inFlight := true.B } when (io.plic.complete) { inFlight := false.B } io.plic.valid := io.interrupt && !inFlight } object PLICConsts { def maxDevices = 1023 def maxMaxHarts = 15872 def priorityBase = 0x0 def pendingBase = 0x1000 def enableBase = 0x2000 def hartBase = 0x200000 def claimOffset = 4 def priorityBytes = 4 def enableOffset(i: Int) = i * ((maxDevices+7)/8) def hartOffset(i: Int) = i * 0x1000 def enableBase(i: Int):Int = enableOffset(i) + enableBase def hartBase(i: Int):Int = hartOffset(i) + hartBase def size(maxHarts: Int): Int = { require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}") 1 << log2Ceil(hartBase(maxHarts)) } require(hartBase >= enableBase(maxMaxHarts)) } case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts) { require (maxPriorities >= 0) def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1) } case object PLICKey extends Field[Option[PLICParams]](None) case class PLICAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object PLICAttachKey extends Field(PLICAttachParams()) /** Platform-Level Interrupt Controller / class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // plic0 => max devices 1023 val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) { override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val extra = Map( "interrupt-controller" -> Nil, "riscv,ndev" -> Seq(ResourceInt(nDevices)), "riscv,max-priority" -> Seq(ResourceInt(nPriorities)), "#interrupt-cells" -> Seq(ResourceInt(1))) Description(name, mapping ++ extra) } } val node : TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes, undefZero = true, concurrency = 1) // limiting concurrency handles RAW hazards on claim registers val intnode: IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false, inputRequiresOutput = false) / Negotiated sizes / def nDevices: Int = intnode.edges.in.map(_.source.num).sum def minPriorities = min(params.maxPriorities, nDevices) def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1 def nHarts = intnode.edges.out.map(_.source.num).sum // Assign all the devices unique ranges lazy val sources = intnode.edges.in.map(_.source) lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten ResourceBinding { flatSources.foreach { s => s.resources.foreach { r => // +1 because interrupt 0 is reserved (s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) } } } } lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) val (io_devices, edgesIn) = intnode.in.unzip val (io_harts, _) = intnode.out.unzip // Compact the interrupt vector the same way val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten // This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence val harts = io_harts.flatten def getNInterrupts = interrupts.size println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):") flatSources.foreach { s => // +1 because 0 is reserved, +1-1 because the range is half-open println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}") } println("") require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}") require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}") require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}") require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}") // For now, use LevelGateways for all TL2 interrupts val gateways = interrupts.map { case i => val gateway = Module(new LevelGateway) gateway.io.interrupt := i gateway.io.plic } val prioBits = log2Ceil(nPriorities+1) val priority = if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W))) else WireDefault(VecInit.fill(nDevices max 1)(1.U)) val threshold = if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W))) else WireDefault(VecInit.fill(nHarts)(0.U)) val pending = RegInit(VecInit.fill(nDevices max 1){false.B}) / Construct the enable registers, chunked into 8-bit segments to reduce verilog size / val firstEnable = nDevices min 7 val fullEnables = (nDevices - firstEnable) / 8 val tailEnable = nDevices - firstEnable - 8fullEnables def enableRegs = (Reg(UInt(firstEnable.W)) +: Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++ (if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None) val enables = Seq.fill(nHarts) { enableRegs } val enableVec = VecInit(enables.map(x => Cat(x.reverse))) val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W)))) val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W))) val pendingUInt = Cat(pending.reverse) if(nDevices > 0) { for (hart <- 0 until nHarts) { val fanin = Module(new PLICFanIn(nDevices, prioBits)) fanin.io.prio := priority fanin.io.ip := enableVec(hart) & pendingUInt maxDevs(hart) := fanin.io.dev harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages) } } // Priority registers are 32-bit aligned so treat each as its own group. // Otherwise, the off-by-one nature of the priority registers gets confusing. require(PLICConsts.priorityBytes == 4, s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}") def priorityRegDesc(i: Int) = RegFieldDesc( name = s"priority_$i", desc = s"Acting priority of interrupt source $i", group = Some(s"priority_${i}"), groupDesc = Some(s"Acting priority of interrupt source ${i}"), reset = if (nPriorities > 0) None else Some(1)) def pendingRegDesc(i: Int) = RegFieldDesc( name = s"pending_$i", desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.", group = Some("pending"), groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."), volatile = true) def enableRegDesc(i: Int, j: Int, wide: Int) = { val low = if (j == 0) 1 else j8 val high = low + wide - 1 RegFieldDesc( name = s"enables_${j}", desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.", group = Some(s"enables_${i}"), groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source.")) } def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, priorityRegDesc(i)) } else { RegField.r(prioBits, x, priorityRegDesc(i)) } val priorityRegFields = priority.zipWithIndex.map { case (p, i) => PLICConsts.priorityBase+PLICConsts.priorityBytes(i+1) -> Seq(priorityRegField(p, i+1)) } val pendingRegFields = Seq(PLICConsts.pendingBase -> (RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))})) val enableRegFields = enables.zipWithIndex.map { case (e, i) => PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) => RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) } // When a hart reads a claim/complete register, then the // device which is currently its highest priority is no longer pending. // This code exploits the fact that, practically, only one claim/complete // register can be read at a time. We check for this because if the address map // were to change, it may no longer be true. // Note: PLIC doesn't care which hart reads the register. val claimer = Wire(Vec(nHarts, Bool())) assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_\|_) val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools) ((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) => g.ready := !p when (c \|\| g.valid) { p := !c } } // When a hart writes a claim/complete register, then // the written device (as long as it is actually enabled for that // hart) is marked complete. // This code exploits the fact that, practically, only one claim/complete register // can be written at a time. We check for this because if the address map // were to change, it may no longer be true. // Note -- PLIC doesn't care which hart writes the register. val completer = Wire(Vec(nHarts, Bool())) assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot val completerDev = Wire(UInt(log2Up(nDevices + 1).W)) val completedDevs = Mux(completer.reduce(_ \|\| _), UIntToOH(completerDev, nDevices+1), 0.U) (gateways zip completedDevs.asBools.tail) foreach { case (g, c) => g.complete := c } def thresholdRegDesc(i: Int) = RegFieldDesc( name = s"threshold_$i", desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.", reset = if (nPriorities > 0) None else Some(1)) def thresholdRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, thresholdRegDesc(i)) } else { RegField.r(prioBits, x, thresholdRegDesc(i)) } val hartRegFields = Seq.tabulate(nHarts) { i => PLICConsts.hartBase(i) -> Seq( thresholdRegField(threshold(i), i), RegField(32-prioBits), RegField(32, RegReadFn { valid => claimer(i) := valid (true.B, maxDevs(i)) }, RegWriteFn { (valid, data) => assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), "completerDev should be consistent for all harts") completerDev := data.extract(log2Ceil(nDevices+1)-1, 0) completer(i) := valid && enableVec0(i)(completerDev) true.B }, Some(RegFieldDesc(s"claim_complete_$i", s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." + s"Writing the interrupt number back completes the interrupt.", reset = None, wrType = Some(RegFieldWrType.MODIFY), rdAction = Some(RegFieldRdAction.MODIFY), volatile = true)) ) ) } node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_) if (nDevices >= 2) { val claimed = claimer(0) && maxDevs(0) > 0.U val completed = completer(0) property.cover(claimed && RegEnable(claimed, false.B, claimed \|\| completed), "TWO_CLAIMS", "two claims with no intervening complete") property.cover(completed && RegEnable(completed, false.B, claimed \|\| completed), "TWO_COMPLETES", "two completes with no intervening claim") val ep = enables(0).asUInt & pending.asUInt val ep2 = RegNext(ep) val diff = ep & ~ep2 property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle") if (nPriorities > 0) ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)), "THRESHOLD", "interrupt pending but less than threshold") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc) } } class PLICFanIn(nDevices: Int, prioBits: Int) extends Module { val io = IO(new Bundle { val prio = Flipped(Vec(nDevices, UInt(prioBits.W))) val ip = Flipped(UInt(nDevices.W)) val dev = UInt(log2Ceil(nDevices+1).W) val max = UInt(prioBits.W) }) def findMax(x: Seq[UInt]): (UInt, UInt) = { if (x.length > 1) { val half = 1 << (log2Ceil(x.length) - 1) val left = findMax(x take half) val right = findMax(x drop half) MuxT(left._1 >= right._1, left, (right._1, half.U \| right._2)) } else (x.head, 0.U) } val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) } val (maxPri, maxDev) = findMax(effectivePriority) io.max := maxPri // strips the always-constant high '1' bit io.dev := maxDev } /* Trait that will connect a PLIC to a subsystem / trait CanHavePeripheryPLIC { this: BaseSubsystem => val (plicOpt, plicDomainOpt) = p(PLICKey).map { params => val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere) val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain") val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) } plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } } plicDomainWrapper { plic.intnode := ibus.toPLIC } (plic, plicDomainWrapper) }.unzip }	module TLPLIC( // @[Plic.scala:132:9] input clock, // @[Plic.scala:132:9] input reset, // @[Plic.scala:132:9] input auto_int_in_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_1, // @[LazyModuleImp.scala:107:25] input auto_int_in_2, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_0, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [22:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [22:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire [1:0] _fanin_1_io_dev; // @[Plic.scala:189:27] wire [1:0] _fanin_1_io_max; // @[Plic.scala:189:27] wire [1:0] _fanin_io_dev; // @[Plic.scala:189:27] wire [1:0] _fanin_io_max; // @[Plic.scala:189:27] wire _gateways_gateway_2_io_plic_valid; // @[Plic.scala:160:27] wire _gateways_gateway_1_io_plic_valid; // @[Plic.scala:160:27] wire _gateways_gateway_io_plic_valid; // @[Plic.scala:160:27] wire auto_int_in_0_0 = auto_int_in_0; // @[Plic.scala:132:9] wire auto_int_in_1_0 = auto_int_in_1; // @[Plic.scala:132:9] wire auto_int_in_2_0 = auto_int_in_2; // @[Plic.scala:132:9] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Plic.scala:132:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Plic.scala:132:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Plic.scala:132:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Plic.scala:132:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Plic.scala:132:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Plic.scala:132:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Plic.scala:132:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Plic.scala:132:9] wire _out_T_115 = reset; // @[Plic.scala:298:19] wire _out_T_151 = reset; // @[Plic.scala:298:19] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_denied = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_corrupt = 1'h0; // @[Plic.scala:132:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _pending_WIRE_0 = 1'h0; // @[Plic.scala:172:55] wire _pending_WIRE_1 = 1'h0; // @[Plic.scala:172:55] wire _pending_WIRE_2 = 1'h0; // @[Plic.scala:172:55] wire _out_T_21 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_22 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_63 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_2 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_171 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_172 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_24 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_72 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_80 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_92 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_96 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_100 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_130 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_25 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_73 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_81 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_93 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_97 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_101 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_131 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_24 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_72 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_80 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_92 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_96 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_100 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_130 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_25 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_73 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_81 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_93 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_97 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_101 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_131 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [31:0] _out_prepend_T_10 = 32'h0; // @[RegisterRouter.scala:87:24] wire [22:0] out_maskMatch = 23'h7BF9EE; // @[RegisterRouter.scala:87:24] wire intnodeIn_0 = auto_int_in_0_0; // @[Plic.scala:132:9] wire intnodeIn_1 = auto_int_in_1_0; // @[Plic.scala:132:9] wire intnodeIn_2 = auto_int_in_2_0; // @[Plic.scala:132:9] wire x1_intnodeOut_0; // @[MixedNode.scala:542:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Plic.scala:132:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Plic.scala:132:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Plic.scala:132:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Plic.scala:132:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Plic.scala:132:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Plic.scala:132:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Plic.scala:132:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Plic.scala:132:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_1_0_0; // @[Plic.scala:132:9] wire auto_int_out_0_0_0; // @[Plic.scala:132:9] wire auto_in_a_ready_0; // @[Plic.scala:132:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Plic.scala:132:9] wire [1:0] auto_in_d_bits_size_0; // @[Plic.scala:132:9] wire [11:0] auto_in_d_bits_source_0; // @[Plic.scala:132:9] wire [63:0] auto_in_d_bits_data_0; // @[Plic.scala:132:9] wire auto_in_d_valid_0; // @[Plic.scala:132:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Plic.scala:132:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Plic.scala:132:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Plic.scala:132:9] wire [11:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Plic.scala:132:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Plic.scala:132:9] wire _intnodeOut_0_T; // @[Plic.scala:193:60] assign auto_int_out_0_0_0 = intnodeOut_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_1; // @[Plic.scala:193:60] assign auto_int_out_1_0_0 = x1_intnodeOut_0; // @[Plic.scala:132:9] reg [1:0] priority_0; // @[Plic.scala:167:31] reg [1:0] priority_1; // @[Plic.scala:167:31] wire [1:0] _out_T_43 = priority_1; // @[RegisterRouter.scala:87:24] reg [1:0] priority_2; // @[Plic.scala:167:31] reg [1:0] threshold_0; // @[Plic.scala:170:31] wire [1:0] _out_T_137 = threshold_0; // @[RegisterRouter.scala:87:24] reg [1:0] threshold_1; // @[Plic.scala:170:31] wire [1:0] _out_T_101 = threshold_1; // @[RegisterRouter.scala:87:24] reg pending_0; // @[Plic.scala:172:26] reg pending_1; // @[Plic.scala:172:26] reg pending_2; // @[Plic.scala:172:26] reg [2:0] enables_0_0; // @[Plic.scala:178:26] wire [2:0] enableVec_0 = enables_0_0; // @[Plic.scala:178:26, :182:28] reg [2:0] enables_1_0; // @[Plic.scala:178:26] wire [2:0] enableVec_1 = enables_1_0; // @[Plic.scala:178:26, :182:28] wire [3:0] _enableVec0_T = {enableVec_0, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [3:0] enableVec0_0 = _enableVec0_T; // @[Plic.scala:183:{29,52}] wire [3:0] _enableVec0_T_1 = {enableVec_1, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [3:0] enableVec0_1 = _enableVec0_T_1; // @[Plic.scala:183:{29,52}] reg [1:0] maxDevs_0; // @[Plic.scala:185:22] reg [1:0] maxDevs_1; // @[Plic.scala:185:22] wire [1:0] _GEN = {pending_2, pending_1}; // @[Plic.scala:172:26, :186:26] wire [1:0] pendingUInt_hi; // @[Plic.scala:186:26] assign pendingUInt_hi = _GEN; // @[Plic.scala:186:26] wire [1:0] ep_hi; // @[Plic.scala:323:44] assign ep_hi = _GEN; // @[Plic.scala:186:26, :323:44] wire [2:0] pendingUInt = {pendingUInt_hi, pending_0}; // @[Plic.scala:172:26, :186:26] wire [2:0] _fanin_io_ip_T = enableVec_0 & pendingUInt; // @[Plic.scala:182:28, :186:26, :191:40] reg [1:0] intnodeOut_0_REG; // @[Plic.scala:193:45] assign _intnodeOut_0_T = intnodeOut_0_REG > threshold_0; // @[Plic.scala:170:31, :193:{45,60}] assign intnodeOut_0 = _intnodeOut_0_T; // @[Plic.scala:193:60] wire [2:0] _fanin_io_ip_T_1 = enableVec_1 & pendingUInt; // @[Plic.scala:182:28, :186:26, :191:40] reg [1:0] intnodeOut_0_REG_1; // @[Plic.scala:193:45] assign _intnodeOut_0_T_1 = intnodeOut_0_REG_1 > threshold_1; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_0 = _intnodeOut_0_T_1; // @[Plic.scala:193:60] wire out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_10; // @[RegisterRouter.scala:87:24] wire claimer_0; // @[Plic.scala:250:23] wire claimer_1; // @[Plic.scala:250:23] wire [1:0] _claiming_T = claimer_0 ? maxDevs_0 : 2'h0; // @[Plic.scala:185:22, :250:23, :252:49] wire [1:0] _claiming_T_1 = claimer_1 ? maxDevs_1 : 2'h0; // @[Plic.scala:185:22, :250:23, :252:49] wire [1:0] claiming = _claiming_T \| _claiming_T_1; // @[Plic.scala:252:{49,92}] wire [1:0] claimedDevs_shiftAmount = claiming; // @[OneHot.scala:64:49] wire [3:0] _claimedDevs_T = 4'h1 << claimedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _claimedDevs_T_1 = _claimedDevs_T; // @[OneHot.scala:65:{12,27}] wire _claimedDevs_T_2 = _claimedDevs_T_1[0]; // @[OneHot.scala:65:27] wire claimedDevs_0 = _claimedDevs_T_2; // @[Plic.scala:253:{30,62}] wire _claimedDevs_T_3 = _claimedDevs_T_1[1]; // @[OneHot.scala:65:27] wire claimedDevs_1 = _claimedDevs_T_3; // @[Plic.scala:253:{30,62}] wire _claimedDevs_T_4 = _claimedDevs_T_1[2]; // @[OneHot.scala:65:27] wire claimedDevs_2 = _claimedDevs_T_4; // @[Plic.scala:253:{30,62}] wire _claimedDevs_T_5 = _claimedDevs_T_1[3]; // @[OneHot.scala:65:27] wire claimedDevs_3 = _claimedDevs_T_5; // @[Plic.scala:253:{30,62}] wire _gateway_io_plic_ready_T = ~pending_0; // @[Plic.scala:172:26, :256:18] wire _pending_0_T = ~claimedDevs_1; // @[Plic.scala:253:30, :257:34] wire _gateway_io_plic_ready_T_1 = ~pending_1; // @[Plic.scala:172:26, :256:18] wire _pending_1_T = ~claimedDevs_2; // @[Plic.scala:253:30, :257:34] wire _gateway_io_plic_ready_T_2 = ~pending_2; // @[Plic.scala:172:26, :256:18] wire _pending_2_T = ~claimedDevs_3; // @[Plic.scala:253:30, :257:34] wire _out_completer_0_T_2; // @[Plic.scala:301:35] wire _out_completer_1_T_2; // @[Plic.scala:301:35] wire completer_0; // @[Plic.scala:267:25] wire completer_1; // @[Plic.scala:267:25] wire [1:0] _out_completerDev_T_1; // @[package.scala:163:13] wire [1:0] completerDev; // @[Plic.scala:269:28] wire [1:0] completedDevs_shiftAmount = completerDev; // @[OneHot.scala:64:49] wire _completedDevs_T = completer_0 \| completer_1; // @[Plic.scala:267:25, :270:48] wire [3:0] _completedDevs_T_1 = 4'h1 << completedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _completedDevs_T_2 = _completedDevs_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] completedDevs = _completedDevs_T ? _completedDevs_T_2 : 4'h0; // @[OneHot.scala:65:27] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [22:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [24:0] _in_bits_index_T = nodeIn_a_bits_address[27:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[22:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_q_io_deq_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_14; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [22:0] out_findex = out_front_bits_index & 23'h7BF9EE; // @[RegisterRouter.scala:87:24] wire [22:0] out_bindex = _out_back_front_q_io_deq_bits_index & 23'h7BF9EE; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_12; // @[RegisterRouter.scala:87:24] assign _out_T_12 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_13; // @[RegisterRouter.scala:87:24] assign _out_T_13 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_84; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_68; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_84; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_68; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_4 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_4 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_14 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_14 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_4 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_4 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_14 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_14 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_15 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_56 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_164 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_1 = out_frontMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_1 = out_frontMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_15 = out_frontMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_15 = out_frontMask[3:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_1 = out_backMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_1 = out_backMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_15 = out_backMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_15 = out_backMask[3:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_24 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_23 = _out_back_front_q_io_deq_bits_data[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_173 = _out_back_front_q_io_deq_bits_data[3:1]; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [3:0] out_prepend = {enables_1_0, 1'h0}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_32 = out_prepend; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_33 = _out_T_32; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_2 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_2 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_8 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_8 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_11 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_11 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_2 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_2 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_8 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_8 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_11 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_11 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_35 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_36 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_37 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_34 = _out_back_front_q_io_deq_bits_data[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_92 = _out_back_front_q_io_deq_bits_data[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_128 = _out_back_front_q_io_deq_bits_data[1:0]; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_44 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_3 = out_frontMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_3 = out_frontMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_16 = out_frontMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_16 = out_frontMask[33:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_3 = out_backMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_3 = out_backMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_16 = out_backMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_16 = out_backMask[33:32]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_46 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_47 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_48 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_45 = _out_back_front_q_io_deq_bits_data[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_184 = _out_back_front_q_io_deq_bits_data[33:32]; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_51 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_52 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1 = {30'h0, _out_T_44}; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_1 = {priority_2, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_54 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_55 = _out_T_54; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = _out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = _out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = _out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = _out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_57 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_58 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_59 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_60 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_61 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_62 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_5 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_5 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire _out_romask_T_5 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_5 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_68 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_69 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_70 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_71 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_2 = {pending_0, 1'h0}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_72 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_73 = _out_T_72; // @[RegisterRouter.scala:87:24] wire [1:0] _out_prepend_T_3 = _out_T_73; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_6 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_6 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire _out_romask_T_6 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_6 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_75 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = _out_back_front_q_io_deq_bits_data[2]; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_79 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_80 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [2:0] out_prepend_3 = {pending_1, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_81 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_82 = _out_T_81; // @[RegisterRouter.scala:87:24] wire [2:0] _out_prepend_T_4 = _out_T_82; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_7 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_7 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire _out_romask_T_7 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_7 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = _out_back_front_q_io_deq_bits_data[3]; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [3:0] out_prepend_4 = {pending_2, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_90 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [1:0] _out_prepend_T_5 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [29:0] _out_rimask_T_9 = out_frontMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_wimask_T_9 = out_frontMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_rimask_T_12 = out_frontMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_wimask_T_12 = out_frontMask[31:2]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = \|_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [29:0] _out_romask_T_9 = out_backMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_womask_T_9 = out_backMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_romask_T_12 = out_backMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_womask_T_12 = out_backMask[31:2]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = \|_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire [29:0] _out_T_103 = _out_back_front_q_io_deq_bits_data[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_T_139 = _out_back_front_q_io_deq_bits_data[31:2]; // @[RegisterRouter.scala:87:24] wire _out_T_106 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [2:0] out_prepend_5 = {1'h0, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_110 = {29'h0, out_prepend_5}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_111 = _out_T_110; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_6 = _out_T_111; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_10 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_10 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_13 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_13 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_10 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_10 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_13 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_13 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] assign claimer_1 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire _out_T_119 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_112 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_148 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_113 = _out_T_112[1:0]; // @[package.scala:163:13] wire [1:0] _out_completerDev_T = _out_T_112[1:0]; // @[package.scala:163:13] wire _out_T_114 = completerDev == _out_T_113; // @[package.scala:163:13] wire _out_T_116 = ~_out_T_115; // @[Plic.scala:298:19] wire _out_T_117 = ~_out_T_114; // @[Plic.scala:298:{19,33}] wire [3:0] _GEN_2 = {2'h0, completerDev}; // @[Plic.scala:269:28, :301:51] wire [3:0] _out_completer_1_T = enableVec0_1 >> _GEN_2; // @[Plic.scala:183:29, :301:51] wire _out_completer_1_T_1 = _out_completer_1_T[0]; // @[Plic.scala:301:51] assign _out_completer_1_T_2 = out_f_woready_10 & _out_completer_1_T_1; // @[RegisterRouter.scala:87:24] assign completer_1 = _out_completer_1_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_122 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_123 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_124 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_125 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_6 = {maxDevs_1, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_126 = {30'h0, out_prepend_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = \|_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = \|_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_130 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_134 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_135 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_136 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24] wire [1:0] _out_prepend_T_7 = _out_T_138; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = \|_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = \|_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_141 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_145 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [2:0] out_prepend_7 = {1'h0, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_146 = {29'h0, out_prepend_7}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_8 = _out_T_147; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = \|_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = \|_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] assign claimer_0 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_156 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] wire _out_T_157 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_149 = _out_T_148[1:0]; // @[package.scala:163:13] assign _out_completerDev_T_1 = _out_T_148[1:0]; // @[package.scala:163:13] wire _out_T_150 = completerDev == _out_T_149; // @[package.scala:163:13] wire _out_T_152 = ~_out_T_151; // @[Plic.scala:298:19] wire _out_T_153 = ~_out_T_150; // @[Plic.scala:298:{19,33}]
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_145( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_401 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. / class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module TLXbar_mbus_i1_o2_a32d64s6k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [5:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [5:0] _addressC_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _addressC_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _requestBOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T = 6'h0; // @[Parameters.scala:52:29] wire [5:0] requestBOI_uncommonBits = 6'h0; // @[Parameters.scala:52:56] wire [5:0] _requestBOI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T_1 = 6'h0; // @[Parameters.scala:52:29] wire [5:0] requestBOI_uncommonBits_1 = 6'h0; // @[Parameters.scala:52:56] wire [5:0] _beatsBO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _beatsBO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _beatsBO_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _beatsCI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _portsBIO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _portsBIO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] portsBIO_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] _portsBIO_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _portsBIO_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] portsBIO_filtered_1_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] _portsCOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _portsCOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] portsCOI_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsCOI_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [27:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [5:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [5:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [5:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_5 = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [5:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [5:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [5:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address[27:0]; // @[Xbar.scala:216:19, :222:41] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [31:0] _requestAIO_T = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [5:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [5:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T \| _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid \| portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /* Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. / class ClientMetadata extends Bundle { /* Actual state information stored in this bundle / val state = UInt(ClientStates.width.W) /* Metadata equality / def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /* Is the block's data present in this cache / def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /* Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) / private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /* Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). / private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd \|\| param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /* Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). / def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /* Does a secondary miss on the block require another Acquire message / def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /* Metadata change on a returned Grant / def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /* Determine what state to go to based on Probe param / private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /* Translate cache control cmds into Probe param / private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /* Factories for ClientMetadata, including on reset / object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) \| wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /* @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSetsblockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined \|\| nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined \|\| nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBitsrowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /* Bundle definitions for HellaCache interfaces / trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /* Base classes for Diplomatic TL2 HellaCaches / abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB \|\| !m.executable \|\| m.regionType >= RegionType.TRACKED \|\| m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM \|\| cfg.blockBytes cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush \|\| cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated / case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /* Mix-ins for constructing tiles that have a HellaCache / trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /* Metadata array used for all HellaCaches / class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst \|\| io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File ECC.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR abstract class Decoding { def uncorrected: UInt def corrected: UInt def correctable: Bool def uncorrectable: Bool // If true, correctable should be ignored def error = correctable \|\| uncorrectable } abstract class Code { def canDetect: Boolean def canCorrect: Boolean def width(w0: Int): Int /* Takes the unencoded width and returns a list of indices indicating which * bits of the encoded value will be used for ecc / def eccIndices(width: Int): Seq[Int] /* Encode x to a codeword suitable for decode. * If poison is true, the decoded value will report uncorrectable * error despite uncorrected == corrected == x. / def encode(x: UInt, poison: Bool = false.B): UInt def decode(x: UInt): Decoding /* Copy the bits in x to the right bit positions in an encoded word, * so that x === decode(swizzle(x)).uncorrected; but don't generate * the other code bits, so decode(swizzle(x)).error might be true. * For codes for which this operation is not trivial, throw an * UnsupportedOperationException. / def swizzle(x: UInt): UInt } class IdentityCode extends Code { def canDetect = false def canCorrect = false def width(w0: Int) = w0 def eccIndices(width: Int) = Seq.empty[Int] def encode(x: UInt, poison: Bool = false.B) = { require (poison.isLit && poison.litValue == 0, "IdentityCode can not be poisoned") x } def swizzle(x: UInt) = x def decode(y: UInt) = new Decoding { def uncorrected = y def corrected = y def correctable = false.B def uncorrectable = false.B } } class ParityCode extends Code { def canDetect = true def canCorrect = false def width(w0: Int) = w0+1 def eccIndices(w0: Int) = Seq(w0) def encode(x: UInt, poison: Bool = false.B) = Cat(x.xorR ^ poison, x) def swizzle(x: UInt) = Cat(false.B, x) def decode(y: UInt) = new Decoding { val uncorrected = y(y.getWidth-2,0) val corrected = uncorrected val correctable = false.B val uncorrectable = y.xorR } } class SECCode extends Code { def canDetect = true def canCorrect = true // SEC codes may or may not be poisonous depending on the length // If the code is perfect, every non-codeword is correctable def poisonous(n: Int) = !isPow2(n+1) def width(k: Int) = { val m = log2Floor(k) + 1 k + m + (if((1 << m) < m+k+1) 1 else 0) } def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def swizzle(x: UInt) = { val k = x.getWidth val n = width(k) Cat(0.U((n-k).W), x) } // An (n=16, k=11) Hamming code is naturally encoded as: // PPxPxxxPxxxxxxxP where P are parity bits and x are data // Indexes typically start at 1, because then the P are on powers of two // In systematic coding, you put all the data in the front: // xxxxxxxxxxxPPPPP // Indexes typically start at 0, because Computer Science // For sanity when reading SRAMs, you want systematic form. private def impl(n: Int, k: Int) = { require (n >= 3 && k >= 1 && !isPow2(n)) val hamm2sys = IndexedSeq.tabulate(n+1) { i => if (i == 0) { n / undefined / } else if (isPow2(i)) { k + log2Ceil(i) } else { i - 1 - log2Ceil(i) } } val sys2hamm = hamm2sys.zipWithIndex.sortBy(_._1).map(_._2).toIndexedSeq def syndrome(j: Int) = { val bit = 1 << j ("b" + Seq.tabulate(n) { i => if ((sys2hamm(i) & bit) != 0) "1" else "0" }.reverse.mkString).U } (hamm2sys, sys2hamm, syndrome _) } def encode(x: UInt, poison: Bool = false.B) = { val k = x.getWidth val n = width(k) val (_, _, syndrome) = impl(n, k) require ((poison.isLit && poison.litValue == 0) \|\| poisonous(n), s"SEC code of length ${n} cannot be poisoned") / By setting the entire syndrome on poison, the corrected bit falls off the end of the code / val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j)(k-1, 0) & x).xorR ^ poison }.asUInt Cat(syndromeUInt, x) } def decode(y: UInt) = new Decoding { val n = y.getWidth val k = n - log2Ceil(n) val (_, sys2hamm, syndrome) = impl(n, k) val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j) & y).xorR }.asUInt val hammBadBitOH = UIntToOH(syndromeUInt, n+1) val sysBadBitOH = VecInit.tabulate(k) { i => hammBadBitOH(sys2hamm(i)) }.asUInt val uncorrected = y(k-1, 0) val corrected = uncorrected ^ sysBadBitOH val correctable = syndromeUInt.orR val uncorrectable = if (poisonous(n)) { syndromeUInt > n.U } else { false.B } } } class SECDEDCode extends Code { def canDetect = true def canCorrect = true private val sec = new SECCode private val par = new ParityCode def width(k: Int) = sec.width(k)+1 def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def encode(x: UInt, poison: Bool = false.B) = { // toggling two bits ensures the error is uncorrectable // to ensure corrected == uncorrected, we pick one redundant // bit from SEC (the highest); correcting it does not affect // corrected == uncorrected. the second toggled bit is the // parity bit, which also does not appear in the decoding val toggle_lo = Cat(poison.asUInt, poison.asUInt) val toggle_hi = toggle_lo << (sec.width(x.getWidth)-1) par.encode(sec.encode(x)) ^ toggle_hi } def swizzle(x: UInt) = par.swizzle(sec.swizzle(x)) def decode(x: UInt) = new Decoding { val secdec = sec.decode(x(x.getWidth-2,0)) val pardec = par.decode(x) val uncorrected = secdec.uncorrected val corrected = secdec.corrected val correctable = pardec.uncorrectable val uncorrectable = !pardec.uncorrectable && secdec.correctable } } object ErrGen { // generate a 1-bit error with approximate probability 2^-f def apply(width: Int, f: Int): UInt = { require(width > 0 && f >= 0 && log2Up(width) + f <= 16) UIntToOH(LFSR(16)(log2Up(width)+f-1,0))(width-1,0) } def apply(x: UInt, f: Int): UInt = x ^ apply(x.getWidth, f) } trait CanHaveErrors extends Bundle { val correctable: Option[ValidIO[UInt]] val uncorrectable: Option[ValidIO[UInt]] } case class ECCParams( bytes: Int = 1, code: Code = new IdentityCode, notifyErrors: Boolean = false, ) object Code { def fromString(s: Option[String]): Code = fromString(s.getOrElse("none")) def fromString(s: String): Code = s.toLowerCase match { case "none" => new IdentityCode case "identity" => new IdentityCode case "parity" => new ParityCode case "sec" => new SECCode case "secded" => new SECDEDCode case _ => throw new IllegalArgumentException("Unknown ECC type") } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class ECCTest(k: Int, timeout: Int = 500000) extends UnitTest(timeout) { val code = new SECDEDCode val n = code.width(k) // Brute force the decode space val test = RegInit(0.U((n+1).W)) val last = test(n) test := test + !last io.finished := RegNext(last, false.B) // Confirm the decoding matches the encoding val decoded = code.decode(test(n-1, 0)) val recoded = code.encode(decoded.corrected) val distance = PopCount(recoded ^ test) // Count the cases val correct = RegInit(0.U(n.W)) val correctable = RegInit(0.U(n.W)) val uncorrectable = RegInit(0.U(n.W)) when (!last) { when (decoded.uncorrectable) { assert (distance >= 2.U) // uncorrectable uncorrectable := uncorrectable + 1.U } .elsewhen (decoded.correctable) { assert (distance(0)) // correctable => odd bit errors correctable := correctable + 1.U } .otherwise { assert (distance === 0.U) // correct assert (decoded.uncorrected === decoded.corrected) correct := correct + 1.U } } // Expected number of each case val nCodes = BigInt(1) << n val nCorrect = BigInt(1) << k val nCorrectable = nCodes / 2 val nUncorrectable = nCodes - nCorrectable - nCorrect when (last) { assert (correct === nCorrect.U) assert (correctable === nCorrectable.U) assert (uncorrectable === nUncorrectable.U) } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /* =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} / class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /* request address from CPU. / val vaddr = UInt(vaddrBitsExtended.W) /* don't lookup TLB, bypass vaddr as paddr / val passthrough = Bool() /* granularity / val size = UInt(log2Ceil(lgMaxSize + 1).W) /* memory command. / val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /* virtualization mode / val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /* physical address / val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /* page fault exception / val pf = new TLBExceptions /* guest page fault exception / val gf = new TLBExceptions /* access exception / val ae = new TLBExceptions /* misaligned access exception / val ma = new TLBExceptions /* if this address is cacheable / val cacheable = Bool() /* if caches must allocate this address / val must_alloc = Bool() /* if this address is prefetchable for caches/ val prefetchable = Bool() /* size/cmd of request that generated this response/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /* pte.u user / val u = Bool() /* pte.g global / val g = Bool() /* access exception. * D$ -> PTW -> TLB AE * Alignment failed. / val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* supervisor write / val sw = Bool() /* supervisor execute / val sx = Bool() /* supervisor read / val sr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor excute / val hx = Bool() /* hypervisor read / val hr = Bool() /* prot_w / val pw = Bool() /* prot_x / val px = Bool() /* prot_r / val pr = Bool() /* PutPartial / val ppp = Bool() /* AMO logical / val pal = Bool() /* AMO arithmetic / val paa = Bool() /* get/put effects / val eff = Bool() /* cacheable / val c = Bool() /* fragmented_superpage support / val fragmented_superpage = Bool() } /* basic cell for TLB data / class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 \|\| !superpage) require(!superpageOnly \|\| superpage) val level = UInt(log2Ceil(pgLevels).W) /* use vpn as tag / val tag_vpn = UInt(vpnBits.W) /* tag in vitualization mode / val tag_v = Bool() /* entry data / val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /* valid bit / val valid = Vec(nSectors, Bool()) /* returns all entry data in this entry / def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /* returns the index of sector / private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /* returns the entry data matched with this vpn/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /* returns whether a sector hits / def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /* returns whether tag matches vpn / def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /* returns hit signal / def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore \|\| (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData / def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) \| data.ppn)(supervisorVPNBits - jpgLevelBits - 1, supervisorVPNBits - (j + 1)pgLevelBits)) } res } else { data.ppn } } /* does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data / def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries / case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /* =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * \|vaddr \| * \|ppn/vpn \| pgIndex \| * \| \| \| * \| \|nSets \|nSector \| \|}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB2+ITLB}}} @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. / class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /* request from Core / val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /* response to Core / val resp = Output(new TLBResp(lgMaxSize)) /* SFence Input / val sfence = Flipped(Valid(new SFenceReq)) /* IO to PTW / val ptw = new TLBPTWIO /* suppress a TLB refill, one cycle after a miss / val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /* index for sectored_Entry / val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /* TLB Entry / val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /* Superpage Entry / val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /* Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. / val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /* privilege mode / val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /* VS-stage translation enable / val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /* G-stage translation enable / val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /* Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) / val vm_enabled = (stage1_en \|\| stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /* refill signal / val do_refill = usingVM.B && io.ptw.resp.valid /* sfence invalidate refill / val invalidate_refill = state.isOneOf(s_request / don't care /, s_wait_invalidate) \|\| io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill \|\| io.req.bits.passthrough / PTW /), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction \|\| !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en \|\| r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s \|\| sum, entries.map(_.u).asUInt, 0.U) \| Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) \| entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr \| Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt \| Mux(mxr, entries.map(_.sx).asUInt, 0.U))) \| stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) \| stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) \| stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt \| Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) \| stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt \| stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt \| stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array \| final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array \| c_array val paa_array_if_cached = paa_array \| (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array \| (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U \|\| signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM \|\| (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write \|\| io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad \|\| usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) \| Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array \| ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array \| ~pw_array, 0.U) \| Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) \| Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) \| Mux(cmd_amo_logical, ~pal_array, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array, 0.U) \| Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array \| gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) \| Fill(all_entries.size, !vstage1_en) hit_mask \| ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) \|\| (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) \|\| (pf_st_array & hits).orR io.resp.pf.inst := bad_va \|\| (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) \|\| (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) \|\| (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa \|\| (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB \|\| m.supportsHint).B io.resp.miss := do_refill \|\| vsatp_mode_mismatch \|\| tlb_miss \|\| multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv \|\| hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits \|\| reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement / def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r \|\| w \|\| x \|\| c \|\| a \|\| l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet \|\| m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull \|\| m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet \|\| m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull \|\| m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial \|\| m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB \|\| m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT \|\| m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical \|\| m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic \|\| m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ \|\| _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /* PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss / class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /* PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info / class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /* ptw access exception / val ae_ptw = Bool() /* final access exception / val ae_final = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* hypervisor read / val hr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor execute / val hx = Bool() /* PTE to refill L1TLB * * source: L2TLB / val pte = new PTE /* pte pglevel / val level = UInt(log2Ceil(pgLevels).W) /* fragmented_superpage support / val fragmented_superpage = Bool() /* homogeneous for both pma and pmp / val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /* IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) / class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /* PTW performance statistics / class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /* Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core / class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /* enable clock generated by ptw / val clock_enabled = Output(Bool()) } /* PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format / class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* global mapping / val g = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() /* valid bit / val v = Bool() /* return true if find a pointer to next level page table / def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /* return true if find a leaf PTE / def leaf(dummy: Int = 0) = v && (r \|\| (x && !w)) && a /* user read / def ur(dummy: Int = 0) = sr() && u /* user write/ def uw(dummy: Int = 0) = sw() && u /* user execute / def ux(dummy: Int = 0) = sx() && u /* supervisor read / def sr(dummy: Int = 0) = leaf() && r /* supervisor write / def sw(dummy: Int = 0) = leaf() && w && d /* supervisor execute / def sx(dummy: Int = 0) = leaf() && x /* full permission: writable and executable in user mode / def isFullPerm(dummy: Int = 0) = uw() && ux() } /* L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format / class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() } /* PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation / class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /* to n TLB / val requestor = Flipped(Vec(n, new TLBPTWIO)) /* to HellaCache / val mem = new HellaCacheIO /* to Core * * contains CSRs info and performance statistics / val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /* Arbiter to arbite request from n TLB / val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready \|\| l2_refill_wire \|\| arb.io.out.valid \|\| io.dpath.sfence.valid \|\| io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM \|\| !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /* current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} / val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /* tlb request / val r_req = Reg(new PTWReq) /* current selected way in arbitor / val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /* pte for 2-stage translation / val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /* 2-stage translation both enable / val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r \|\| tmp.w \|\| tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)pgLevelBits-1, (pgLevels-2-i)pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /* address send to mem for enquerry / val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) \| vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr / val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBitsi), r_req.addr(((pgLevelBitsi) min vpnBits)-1, 0).padTo(pgLevelBitsi))) } /* PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation / def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid \| UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 \|\| usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /* the valid vec for the selected set(including n ways) / val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) \| mask g(way) := Mux(r_pte.g, g(way) \| mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid \|\| (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req \|\| state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit \|\| (state =/= s_wait1) \|\| resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor \|\| pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous \|\| pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final \|\| !r_req.vstage1 \|\| aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), aux_pte.ppn((pgLevels-i-1)pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req \|\| state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) \|\| (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 \|\| do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages \|\| aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf \|\| (pf && stage2) resp_hr := !stage2 \|\| (!pf && !gf && pte.ur()) resp_hw := !stage2 \|\| (!pf && !gf && pte.uw()) resp_hx := !stage2 \|\| (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), r_req.addr(((pgLevels-i-1)pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn / private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /* use hgatp and vpn to construct a new ppn / private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range / private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW / trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File DCache.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.amba.AMBAProt import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing} import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions} import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck} import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits trait InlineInstance { self: chisel3.experimental.BaseModule => chisel3.experimental.annotate( new chisel3.experimental.ChiselAnnotation { def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } ) } class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) with CanHaveErrors { val correctable = (cacheParams.tagCode.canCorrect \|\| cacheParams.dataCode.canCorrect).option(Valid(UInt(paddrBits.W))) val uncorrectable = (cacheParams.tagCode.canDetect \|\| cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W))) val bus = Valid(UInt(paddrBits.W)) } class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val addr = UInt(untagBits.W) val write = Bool() val wdata = UInt((encBits rowBytes / eccBytes).W) val wordMask = UInt((rowBytes / subWordBytes).W) val eccMask = UInt((wordBytes / eccBytes).W) val way_en = UInt(nWays.W) } class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Valid(new DCacheDataReq)) val resp = Output(Vec(nWays, UInt((req.bits.wdata.getWidth).W))) }) require(rowBits % subWordBits == 0, "rowBits must be a multiple of subWordBits") val eccMask = if (eccBits == subWordBits) Seq(true.B) else io.req.bits.eccMask.asBools val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i))) val wWords = io.req.bits.wdata.grouped(encBits * (subWordBits / eccBits)) val addr = io.req.bits.addr >> rowOffBits val data_arrays = Seq.tabulate(rowBits / subWordBits) { i => DescribedSRAM( name = s"${tileParams.baseName}_dcache_data_arrays_${i}", desc = "DCache Data Array", size = nSets * cacheBlockBytes / rowBytes, data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W)) ) } val rdata = for ((array , i) <- data_arrays.zipWithIndex) yield { val valid = io.req.valid && ((data_arrays.size == 1).B \|\| io.req.bits.wordMask(i)) when (valid && io.req.bits.write) { val wMaskSlice = (0 until wMask.size).filter(j => i % (wordBits/subWordBits) == (j % (wordBytes/eccBytes)) / (subWordBytes/eccBytes)).map(wMask(_)) val wData = wWords(i).grouped(encBits) array.write(addr, VecInit((0 until nWays).flatMap(i => wData)), wMaskSlice) } val data = array.read(addr, valid && !io.req.bits.write) data.grouped(subWordBits / eccBits).map(_.asUInt).toSeq } (io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt } } class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val write = Bool() val addr = UInt(vaddrBitsExtended.W) val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W) } class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) { override lazy val module = new DCacheModule(this) } class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) { val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2))) val s1_resp = Output(new TLBResp(coreDataBytes.log2)) val s2_kill = Input(Bool()) } class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val tECC = cacheParams.tagCode val dECC = cacheParams.dataCode require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits") require(eccBytes == 1 \|\| !dECC.isInstanceOf[IdentityCode]) require(cacheParams.silentDrop \|\| cacheParams.acquireBeforeRelease, "!silentDrop requires acquireBeforeRelease") val usingRMW = eccBytes > 1 \|\| usingAtomicsInCache val mmioOffset = outer.firstMMIO edge.manager.requireFifo(TLFIFOFixer.allVolatile) // TileLink pipelining MMIO requests val clock_en_reg = Reg(Bool()) io.cpu.clock_enabled := clock_en_reg val gated_clock = if (!cacheParams.clockGate) clock else ClockGate(clock, clock_en_reg, "dcache_clock_gate") class DCacheModuleImpl { // entering gated-clock domain val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages))) val pma_checker = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)) with InlineInstance) // tags val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays) /** Metadata Arbiter: * 0: Tag update on reset * 1: Tag update on ECC error * 2: Tag update on hit * 3: Tag update on refill * 4: Tag update on release * 5: Tag update on flush * 6: Tag update on probe * 7: Tag update on CPU request / val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance) val tag_array = DescribedSRAM( name = s"${tileParams.baseName}_dcache_tag_array", desc = "DCache Tag Array", size = nSets, data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data)) ) // data val data = Module(new DCacheDataArray) /* Data Arbiter * 0: data from pending store buffer * 1: data from TL-D refill * 2: release to TL-A * 3: hit path to CPU / val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance) dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default data.io.req.bits <> dataArb.io.out.bits data.io.req.valid := dataArb.io.out.valid dataArb.io.out.ready := true.B metaArb.io.out.ready := clock_en_reg val tl_out_a = Wire(chiselTypeOf(tl_out.a)) tl_out.a <> { val a_queue_depth = outer.crossing match { case RationalCrossing(_) => // TODO make this depend on the actual ratio? if (cacheParams.separateUncachedResp) (maxUncachedInFlight + 1) / 2 else 2 min maxUncachedInFlight-1 case SynchronousCrossing(BufferParams.none) => 1 // Need some buffering to guarantee livelock freedom case SynchronousCrossing(_) => 0 // Adequate buffering within the crossing case _: AsynchronousCrossing => 0 // Adequate buffering within the crossing case _: CreditedCrossing => 0 // Adequate buffering within the crossing } Queue(tl_out_a, a_queue_depth, flow = true) } val (tl_out_c, release_queue_empty) = if (cacheParams.acquireBeforeRelease) { val q = Module(new Queue(chiselTypeOf(tl_out.c.bits), cacheDataBeats, flow = true)) tl_out.c <> q.io.deq (q.io.enq, q.io.count === 0.U) } else { (tl_out.c, true.B) } val s1_valid = RegNext(io.cpu.req.fire, false.B) val s1_probe = RegNext(tl_out.b.fire, false.B) val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :( val s1_nack = WireDefault(false.B) val s1_valid_masked = s1_valid && !io.cpu.s1_kill val s1_valid_not_nacked = s1_valid && !s1_nack val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B) val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B) val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write val s0_req = WireInit(io.cpu.req.bits) s0_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0)) s0_req.idx.foreach(_ := Cat(metaArb.io.out.bits.idx, s0_req.addr(blockOffBits-1, 0))) when (!metaArb.io.in(7).ready) { s0_req.phys := true.B } val s1_req = RegEnable(s0_req, s0_clk_en) val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0)) val s0_tlb_req = WireInit(io.tlb_port.req.bits) when (!io.tlb_port.req.fire) { s0_tlb_req.passthrough := s0_req.phys s0_tlb_req.vaddr := s0_req.addr s0_tlb_req.size := s0_req.size s0_tlb_req.cmd := s0_req.cmd s0_tlb_req.prv := s0_req.dprv s0_tlb_req.v := s0_req.dv } val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en \|\| io.tlb_port.req.valid) val s1_read = isRead(s1_req.cmd) val s1_write = isWrite(s1_req.cmd) val s1_readwrite = s1_read \|\| s1_write val s1_sfence = s1_req.cmd === M_SFENCE \|\| s1_req.cmd === M_HFENCEV \|\| s1_req.cmd === M_HFENCEG val s1_flush_line = s1_req.cmd === M_FLUSH_ALL && s1_req.size(0) val s1_flush_valid = Reg(Bool()) val s1_waw_hazard = Wire(Bool()) val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: s_dummy :: s_voluntary_release :: Nil = Enum(10) val supports_flush = outer.flushOnFenceI \|\| coreParams.haveCFlush val flushed = RegInit(true.B) val flushing = RegInit(false.B) val flushing_req = Reg(chiselTypeOf(s1_req)) val cached_grant_wait = RegInit(false.B) val resetting = RegInit(false.B) val flushCounter = RegInit((nSets (nWays-1)).U(log2Ceil(nSets * nWays).W)) val release_ack_wait = RegInit(false.B) val release_ack_addr = Reg(UInt(paddrBits.W)) val release_state = RegInit(s_ready) val refill_way = Reg(UInt()) val any_pstore_valid = Wire(Bool()) val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty) val releaseWay = Wire(UInt()) io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack // I/O MSHRs val uncachedInFlight = RegInit(VecInit(Seq.fill(maxUncachedInFlight)(false.B))) val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq)) val uncachedResp = WireInit(new HellaCacheReq, DontCare) // hit initiation path val s0_read = isRead(io.cpu.req.bits.cmd) dataArb.io.in(3).valid := io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits) dataArb.io.in(3).bits := dataArb.io.in(1).bits dataArb.io.in(3).bits.write := false.B dataArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.idx.getOrElse(io.cpu.req.bits.addr) >> tagLSB, io.cpu.req.bits.addr(tagLSB-1, 0)) dataArb.io.in(3).bits.wordMask := { val mask = (subWordBytes.log2 until rowOffBits).foldLeft(1.U) { case (in, i) => val upper_mask = Mux((i >= wordBytes.log2).B \|\| io.cpu.req.bits.size <= i.U, 0.U, ((BigInt(1) << (1 << (i - subWordBytes.log2)))-1).U) val upper = Mux(io.cpu.req.bits.addr(i), in, 0.U) \| upper_mask val lower = Mux(io.cpu.req.bits.addr(i), 0.U, in) upper ## lower } Fill(subWordBytes / eccBytes, mask) } dataArb.io.in(3).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(3).bits.way_en := ~0.U(nWays.W) when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false.B } val s1_did_read = RegEnable(dataArb.io.in(3).ready && (io.cpu.req.valid && needsRead(io.cpu.req.bits)), s0_clk_en) val s1_read_mask = RegEnable(dataArb.io.in(3).bits.wordMask, s0_clk_en) metaArb.io.in(7).valid := io.cpu.req.valid metaArb.io.in(7).bits.write := false.B metaArb.io.in(7).bits.idx := dataArb.io.in(3).bits.addr(idxMSB, idxLSB) metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr metaArb.io.in(7).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(7).bits.data := metaArb.io.in(4).bits.data when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false.B } // address translation val s1_cmd_uses_tlb = s1_readwrite \|\| s1_flush_line \|\| s1_req.cmd === M_WOK io.ptw <> tlb.io.ptw tlb.io.kill := io.cpu.s2_kill \|\| s2_tlb_req_valid && io.tlb_port.s2_kill tlb.io.req.valid := s1_tlb_req_valid \|\| s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb tlb.io.req.bits := s1_tlb_req when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B } when (!s1_tlb_req_valid && s1_valid && s1_cmd_uses_tlb && tlb.io.resp.miss) { s1_nack := true.B } tlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence tlb.io.sfence.bits.rs1 := s1_req.size(0) tlb.io.sfence.bits.rs2 := s1_req.size(1) tlb.io.sfence.bits.asid := io.cpu.s1_data.data tlb.io.sfence.bits.addr := s1_req.addr tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG io.tlb_port.req.ready := clock_en_reg io.tlb_port.s1_resp := tlb.io.resp when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B } pma_checker.io <> DontCare pma_checker.io.req.bits.passthrough := true.B pma_checker.io.req.bits.vaddr := s1_req.addr pma_checker.io.req.bits.size := s1_req.size pma_checker.io.req.bits.cmd := s1_req.cmd pma_checker.io.req.bits.prv := s1_req.dprv pma_checker.io.req.bits.v := s1_req.dv val s1_paddr = Cat(Mux(s1_tlb_req_valid, s1_req.addr(paddrBits-1, pgIdxBits), tlb.io.resp.paddr >> pgIdxBits), s1_req.addr(pgIdxBits-1, 0)) val s1_victim_way = Wire(UInt()) val (s1_hit_way, s1_hit_state, s1_meta) = if (usingDataScratchpad) { val baseAddr = p(LookupByHartId)(_.dcache.flatMap(_.scratch.map(_.U)), io_hartid.get) \| io_mmio_address_prefix.get val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + (nSets * cacheBlockBytes).U val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) val dummyMeta = L1Metadata(0.U, ClientMetadata.onReset) (inScratchpad, hitState, Seq(tECC.encode(dummyMeta.asUInt))) } else { val metaReq = metaArb.io.out val metaIdx = metaReq.bits.idx when (metaReq.valid && metaReq.bits.write) { val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.asBools tag_array.write(metaIdx, VecInit(Seq.fill(nWays)(metaReq.bits.data)), wmask) } val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata)) val s1_tag = s1_paddr >> tagLSB val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt val s1_meta_hit_state = ( s1_meta_uncorrected.map(r => Mux(r.tag === s1_tag && !s1_flush_valid, r.coh.asUInt, 0.U)) .reduce (_\|_)).asTypeOf(chiselTypeOf(ClientMetadata.onReset)) (s1_meta_hit_way, s1_meta_hit_state, s1_meta) } val s1_data_way = WireDefault(if (nWays == 1) 1.U else Mux(inWriteback, releaseWay, s1_hit_way)) val tl_d_data_encoded = Wire(chiselTypeOf(encodeData(tl_out.d.bits.data, false.B))) val s1_all_data_ways = VecInit(data.io.resp ++ (!cacheParams.separateUncachedResp).option(tl_d_data_encoded)) val s1_mask_xwr = new StoreGen(s1_req.size, s1_req.addr, 0.U, wordBytes).mask val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, s1_mask_xwr) // for partial writes, s1_data.mask must be a subset of s1_mask_xwr assert(!(s1_valid_masked && s1_req.cmd === M_PWR) \|\| (s1_mask_xwr \| ~io.cpu.s1_data.mask).andR) val s2_valid = RegNext(s1_valid_masked && !s1_sfence, init=false.B) val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR val s2_probe = RegNext(s1_probe, init=false.B) val releaseInFlight = s1_probe \|\| s2_probe \|\| release_state =/= s_ready val s2_not_nacked_in_s1 = RegNext(!s1_nack) val s2_valid_not_nacked_in_s1 = s2_valid && s2_not_nacked_in_s1 val s2_valid_masked = s2_valid_no_xcpt && s2_not_nacked_in_s1 val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill val s2_req = Reg(chiselTypeOf(io.cpu.req.bits)) val s2_cmd_flush_all = s2_req.cmd === M_FLUSH_ALL && !s2_req.size(0) val s2_cmd_flush_line = s2_req.cmd === M_FLUSH_ALL && s2_req.size(0) val s2_tlb_xcpt = Reg(chiselTypeOf(tlb.io.resp)) val s2_pma = Reg(chiselTypeOf(tlb.io.resp)) val s2_uncached_resp_addr = Reg(chiselTypeOf(s2_req.addr)) // should be DCE'd in synthesis when (s1_valid_not_nacked \|\| s1_flush_valid) { s2_req := s1_req s2_req.addr := s1_paddr s2_tlb_xcpt := tlb.io.resp s2_pma := Mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp) } val s2_vaddr = Cat(RegEnable(s1_vaddr, s1_valid_not_nacked \|\| s1_flush_valid) >> tagLSB, s2_req.addr(tagLSB-1, 0)) val s2_read = isRead(s2_req.cmd) val s2_write = isWrite(s2_req.cmd) val s2_readwrite = s2_read \|\| s2_write val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) val s1_meta_decoded = s1_meta.map(tECC.decode(_)) val s1_meta_clk_en = s1_valid_not_nacked \|\| s1_flush_valid \|\| s1_probe val s2_meta_correctable_errors = s1_meta_decoded.map(m => RegEnable(m.correctable, s1_meta_clk_en)).asUInt val s2_meta_uncorrectable_errors = s1_meta_decoded.map(m => RegEnable(m.uncorrectable, s1_meta_clk_en)).asUInt val s2_meta_error_uncorrectable = s2_meta_uncorrectable_errors.orR val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_meta_clk_en).asTypeOf(new L1Metadata)) val s2_meta_error = (s2_meta_uncorrectable_errors \| s2_meta_correctable_errors).orR val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_data = { val wordsPerRow = rowBits / subWordBits val en = s1_valid \|\| inWriteback \|\| io.cpu.replay_next val word_en = Mux(inWriteback, Fill(wordsPerRow, 1.U), Mux(s1_did_read, s1_read_mask, 0.U)) val s1_way_words = s1_all_data_ways.map(_.grouped(dECC.width(eccBits) * (subWordBits / eccBits))) if (cacheParams.pipelineWayMux) { val s1_word_en = Mux(io.cpu.replay_next, 0.U, word_en) (for (i <- 0 until wordsPerRow) yield { val s2_way_en = RegEnable(Mux(s1_word_en(i), s1_data_way, 0.U), en) val s2_way_words = (0 until nWays).map(j => RegEnable(s1_way_words(j)(i), en && word_en(i))) (0 until nWays).map(j => Mux(s2_way_en(j), s2_way_words(j), 0.U)).reduce(_\|_) }).asUInt } else { val s1_word_en = Mux(!io.cpu.replay_next, word_en, UIntToOH(uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)), wordsPerRow)) (for (i <- 0 until wordsPerRow) yield { RegEnable(Mux1H(Mux(s1_word_en(i), s1_data_way, 0.U), s1_way_words.map(_(i))), en) }).asUInt } } val s2_probe_way = RegEnable(s1_hit_way, s1_probe) val s2_probe_state = RegEnable(s1_hit_state, s1_probe) val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked) val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked \|\| s1_flush_valid) val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked) val s2_store_merge = Wire(Bool()) val s2_hit_valid = s2_hit_state.isValid() val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val s2_data_error = s2_data_decoded.map(_.error).orR val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit val s2_no_alloc_hazard = if (!usingVM \|\| pgIdxBits >= untagBits) false.B else { // make sure that any in-flight non-allocating accesses are ordered before // any allocating accesses. this can only happen if aliasing is possible. val any_no_alloc_in_flight = Reg(Bool()) when (!uncachedInFlight.asUInt.orR) { any_no_alloc_in_flight := false.B } when (s2_valid && s2_req.no_alloc) { any_no_alloc_in_flight := true.B } val s1_need_check = any_no_alloc_in_flight \|\| s2_valid && s2_req.no_alloc val concerns = (uncachedInFlight zip uncachedReqs) :+ (s2_valid && s2_req.no_alloc, s2_req) val s1_uncached_hits = concerns.map { c => val concern_wmask = new StoreGen(c._2.size, c._2.addr, 0.U, wordBytes).mask val addr_match = (c._2.addr ^ s1_paddr)(pgIdxBits+pgLevelBits-1, wordBytes.log2) === 0.U val mask_match = (concern_wmask & s1_mask_xwr).orR \|\| c._2.cmd === M_PWR \|\| s1_req.cmd === M_PWR val cmd_match = isWrite(c._2.cmd) \|\| isWrite(s1_req.cmd) c._1 && s1_need_check && cmd_match && addr_match && mask_match } val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked) s2_uncached_hits.orR } val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard \|\| s2_store_merge) val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit val s2_uncached = !s2_pma.cacheable \|\| s2_req.no_alloc && !s2_pma.must_alloc && !s2_hit_valid val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR dontTouch(s2_valid_cached_miss) val s2_want_victimize = (!usingDataScratchpad).B && (s2_valid_cached_miss \|\| s2_valid_flush_line \|\| s2_valid_data_error \|\| s2_flush_valid) val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill val s2_victimize = s2_want_victimize && !s2_cannot_victimize val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked \|\| s1_flush_valid)) val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way) val s2_victim_tag = Mux(s2_valid_data_error \|\| s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag) val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh) val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) dontTouch(s2_victim_dirty) val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready val s2_dont_nack_misc = s2_valid_masked && !s2_meta_error && (supports_flush.B && s2_cmd_flush_all && flushed && !flushing \|\| supports_flush.B && s2_cmd_flush_line && !s2_hit \|\| s2_req.cmd === M_WOK) io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_misc && !s2_valid_hit when (io.cpu.s2_nack \|\| (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true.B } // tag updates on ECC errors val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected) metaArb.io.in(1).valid := s2_meta_error && (s2_valid_masked \|\| s2_flush_valid_pre_tag_ecc \|\| s2_probe) metaArb.io.in(1).bits.write := true.B metaArb.io.in(1).bits.way_en := s2_meta_uncorrectable_errors \| Mux(s2_meta_error_uncorrectable, 0.U, PriorityEncoderOH(s2_meta_correctable_errors)) metaArb.io.in(1).bits.idx := Mux(s2_probe, probeIdx(probe_bits), s2_vaddr(idxMSB, idxLSB)) metaArb.io.in(1).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(1).bits.idx << blockOffBits) metaArb.io.in(1).bits.data := tECC.encode { val new_meta = WireDefault(s2_first_meta_corrected) when (s2_meta_error_uncorrectable) { new_meta.coh := ClientMetadata.onReset } new_meta.asUInt } // tag updates on hit metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta metaArb.io.in(2).bits.write := !io.cpu.s2_kill metaArb.io.in(2).bits.way_en := s2_victim_or_hit_way metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(2).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(2).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_new_hit_state).asUInt) // load reservations and TL error reporting val s2_lr = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XLR val s2_sc = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XSC val lrscCount = RegInit(0.U) val lrscValid = lrscCount > lrscBackoff.U val lrscBackingOff = lrscCount > 0.U && !lrscValid val lrscAddr = Reg(UInt()) val lrscAddrMatch = lrscAddr === (s2_req.addr >> blockOffBits) val s2_sc_fail = s2_sc && !(lrscValid && lrscAddrMatch) when ((s2_valid_hit && s2_lr && !cached_grant_wait \|\| s2_valid_cached_miss) && !io.cpu.s2_kill) { lrscCount := Mux(s2_hit, (lrscCycles - 1).U, 0.U) lrscAddr := s2_req.addr >> blockOffBits } when (lrscCount > 0.U) { lrscCount := lrscCount - 1.U } when (s2_valid_not_killed && lrscValid) { lrscCount := lrscBackoff.U } when (s1_probe) { lrscCount := 0.U } // don't perform data correction if it might clobber a recent store val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid \|\| s2_valid) && usingDataScratchpad.B // pending store buffer val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write) val pstore1_addr = RegEnable(s1_vaddr, s1_valid_not_nacked && s1_write) val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write) val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write) val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write) val pstore1_storegen_data = WireDefault(pstore1_data) val pstore1_rmw = usingRMW.B && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write) val pstore1_merge_likely = s2_valid_not_nacked_in_s1 && s2_write && s2_store_merge val pstore1_merge = s2_store_valid && s2_store_merge val pstore2_valid = RegInit(false.B) val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard) val pstore_drain_on_miss = releaseInFlight \|\| RegNext(io.cpu.s2_nack) val pstore1_held = RegInit(false.B) val pstore1_valid_likely = s2_valid && s2_write \|\| pstore1_held def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill \|\| pstore1_held val pstore1_valid = s2_store_valid \|\| pstore1_held any_pstore_valid := pstore1_held \|\| pstore2_valid val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) \|\| pstore1_rmw) assert(pstore1_rmw \|\| pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid) ccover(pstore_drain_structural, "STORE_STRUCTURAL_HAZARD", "D$ read-modify-write structural hazard") ccover(pstore1_valid && pstore_drain_on_miss, "STORE_DRAIN_ON_MISS", "D$ store buffer drain on miss") ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") def should_pstore_drain(truly: Bool) = { val s2_kill = truly && io.cpu.s2_kill !pstore1_merge_likely && (usingRMW.B && pstore_drain_structural \|\| (((pstore1_valid_not_rmw(s2_kill) && !pstore1_rmw) \|\| pstore2_valid) && (pstore_drain_opportunistic \|\| pstore_drain_on_miss))) } val pstore_drain = should_pstore_drain(true.B) pstore1_held := (s2_store_valid && !s2_store_merge \|\| pstore1_held) && pstore2_valid && !pstore_drain val advance_pstore1 = (pstore1_valid \|\| s2_valid_correct) && (pstore2_valid === pstore_drain) pstore2_valid := pstore2_valid && !pstore_drain \|\| advance_pstore1 val pstore2_addr = RegEnable(Mux(s2_correct, s2_vaddr, pstore1_addr), advance_pstore1) val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1) val pstore2_storegen_data = { for (i <- 0 until wordBytes) yield RegEnable(pstore1_storegen_data(8(i+1)-1, 8i), advance_pstore1 \|\| pstore1_merge && pstore1_mask(i)) }.asUInt val pstore2_storegen_mask = { val mask = Reg(UInt(wordBytes.W)) when (advance_pstore1 \|\| pstore1_merge) { val mergedMask = pstore1_mask \| Mux(pstore1_merge, mask, 0.U) mask := ~Mux(s2_correct, 0.U, ~mergedMask) } mask } s2_store_merge := (if (eccBytes == 1) false.B else { ccover(pstore1_merge, "STORE_MERGED", "D$ store merged") // only merge stores to ECC granules that are already stored-to, to avoid // WAW hazards val wordMatch = (eccMask(pstore2_storegen_mask) \| ~eccMask(pstore1_mask)).andR val idxMatch = s2_vaddr(untagBits-1, log2Ceil(wordBytes)) === pstore2_addr(untagBits-1, log2Ceil(wordBytes)) val tagMatch = (s2_hit_way & pstore2_way).orR pstore2_valid && wordMatch && idxMatch && tagMatch }) dataArb.io.in(0).valid := should_pstore_drain(false.B) dataArb.io.in(0).bits.write := pstore_drain dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr) dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way) dataArb.io.in(0).bits.wdata := encodeData(Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data)), false.B) dataArb.io.in(0).bits.wordMask := { val eccMask = dataArb.io.in(0).bits.eccMask.asBools.grouped(subWordBytes/eccBytes).map(_.orR).toSeq.asUInt val wordMask = UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1, wordBytes.log2)) FillInterleaved(wordBytes/subWordBytes, wordMask) & Fill(rowBytes/wordBytes, eccMask) } dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)) // store->load RAW hazard detection def s1Depends(addr: UInt, mask: UInt) = addr(idxMSB, wordOffBits) === s1_vaddr(idxMSB, wordOffBits) && Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask_xwr)).orR, (mask & s1_mask_xwr).orR) val s1_hazard = (pstore1_valid_likely && s1Depends(pstore1_addr, pstore1_mask)) \|\| (pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask)) val s1_raw_hazard = s1_read && s1_hazard s1_waw_hazard := (if (eccBytes == 1) false.B else { ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") s1_write && (s1_hazard \|\| needsRead(s1_req) && !s1_did_read) }) when (s1_valid && s1_raw_hazard) { s1_nack := true.B } // performance hints to processor io.cpu.s2_nack_cause_raw := RegNext(s1_raw_hazard) \|\| !(!s2_waw_hazard \|\| s2_store_merge) // Prepare a TileLink request message that initiates a transaction val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR val acquire_address = (s2_req.addr >> idxLSB) << idxLSB val access_address = s2_req.addr val a_size = s2_req.size val a_data = Fill(beatWords, pstore1_data) val a_mask = pstore1_mask << (access_address.extract(beatBytes.log2-1, wordBytes.log2) << 3) val get = edge.Get(a_source, access_address, a_size)._2 val put = edge.Put(a_source, access_address, a_size, a_data)._2 val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array( M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached)) WireDefault(new TLBundleA(edge.bundle), DontCare) } tl_out_a.valid := !io.cpu.s2_kill && (s2_valid_uncached_pending \|\| (s2_valid_cached_miss && !(release_ack_wait && (s2_req.addr ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U) && (cacheParams.acquireBeforeRelease.B && !release_ack_wait && release_queue_empty \|\| !s2_victim_dirty))) tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param), Mux(!s2_write, get, Mux(s2_req.cmd === M_PWR, putpartial, Mux(!s2_read, put, atomics)))) // Drive APROT Bits tl_out_a.bits.user.lift(AMBAProt).foreach { x => val user_bit_cacheable = s2_pma.cacheable x.privileged := s2_req.dprv === PRV.M.U \|\| user_bit_cacheable // if the address is cacheable, enable outer caches x.bufferable := user_bit_cacheable x.modifiable := user_bit_cacheable x.readalloc := user_bit_cacheable x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := false.B x.secure := true.B } // Set pending bits for outstanding TileLink transaction val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset when (tl_out_a.fire) { when (s2_uncached) { (a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) => when (s) { f := true.B r := s2_req r.cmd := Mux(s2_write, Mux(s2_req.cmd === M_PWR, M_PWR, M_XWR), M_XRD) } } }.otherwise { cached_grant_wait := true.B refill_way := s2_victim_or_hit_way } } // grant val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) val (d_opc, grantIsUncached, grantIsUncachedData) = { val uncachedGrantOpcodesSansData = Seq(AccessAck, HintAck) val uncachedGrantOpcodesWithData = Seq(AccessAckData) val uncachedGrantOpcodes = uncachedGrantOpcodesWithData ++ uncachedGrantOpcodesSansData val whole_opc = tl_out.d.bits.opcode if (usingDataScratchpad) { assert(!tl_out.d.valid \|\| whole_opc.isOneOf(uncachedGrantOpcodes)) // the only valid TL-D messages are uncached, so we can do some pruning val opc = whole_opc(uncachedGrantOpcodes.map(_.getWidth).max - 1, 0) val data = DecodeLogic(opc, uncachedGrantOpcodesWithData, uncachedGrantOpcodesSansData) (opc, true.B, data) } else { (whole_opc, whole_opc.isOneOf(uncachedGrantOpcodes), whole_opc.isOneOf(uncachedGrantOpcodesWithData)) } } tl_d_data_encoded := encodeData(tl_out.d.bits.data, tl_out.d.bits.corrupt && !io.ptw.customCSRs.suppressCorruptOnGrantData && !grantIsUncached) val grantIsCached = d_opc.isOneOf(Grant, GrantData) val grantIsVoluntary = d_opc === ReleaseAck // Clears a different pending bit val grantIsRefill = d_opc === GrantData // Writes the data array val grantInProgress = RegInit(false.B) val blockProbeAfterGrantCount = RegInit(0.U) when (blockProbeAfterGrantCount > 0.U) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1.U } val canAcceptCachedGrant = !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release) tl_out.d.ready := Mux(grantIsCached, (!d_first \|\| tl_out.e.ready) && canAcceptCachedGrant, true.B) val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs) when (tl_out.d.fire) { when (grantIsCached) { grantInProgress := true.B assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") when(d_last) { cached_grant_wait := false.B grantInProgress := false.B blockProbeAfterGrantCount := (blockProbeAfterGrantCycles - 1).U replacer.miss } } .elsewhen (grantIsUncached) { (uncachedRespIdxOH.asBools zip uncachedInFlight) foreach { case (s, f) => when (s && d_last) { assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle! f := false.B } } when (grantIsUncachedData) { if (!cacheParams.separateUncachedResp) { if (!cacheParams.pipelineWayMux) s1_data_way := 1.U << nWays s2_req.cmd := M_XRD s2_req.size := uncachedResp.size s2_req.signed := uncachedResp.signed s2_req.tag := uncachedResp.tag s2_req.addr := { require(rowOffBits >= beatOffBits) val dontCareBits = s1_paddr >> rowOffBits << rowOffBits dontCareBits \| uncachedResp.addr(beatOffBits-1, 0) } s2_uncached_resp_addr := uncachedResp.addr } } } .elsewhen (grantIsVoluntary) { assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle! release_ack_wait := false.B } } // Finish TileLink transaction by issuing a GrantAck tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant tl_out.e.bits := edge.GrantAck(tl_out.d.bits) assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached)) // data refill // note this ready-valid signaling ignores E-channel backpressure, which // benignly means the data RAM might occasionally be redundantly written dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.e.valid := false.B tl_out.d.ready := false.B } if (!usingDataScratchpad) { dataArb.io.in(1).bits.write := true.B dataArb.io.in(1).bits.addr := (s2_vaddr >> idxLSB) << idxLSB \| d_address_inc dataArb.io.in(1).bits.way_en := refill_way dataArb.io.in(1).bits.wdata := tl_d_data_encoded dataArb.io.in(1).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(1).bits.eccMask := ~0.U((wordBytes / eccBytes).W) } else { dataArb.io.in(1).bits := dataArb.io.in(0).bits } // tag updates on refill // ignore backpressure from metaArb, which can only be caused by tag ECC // errors on hit-under-miss. failing to write the new tag will leave the // line invalid, so we'll simply request the line again later. metaArb.io.in(3).valid := grantIsCached && d_done && !tl_out.d.bits.denied metaArb.io.in(3).bits.write := true.B metaArb.io.in(3).bits.way_en := refill_way metaArb.io.in(3).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(3).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param)).asUInt) if (!cacheParams.separateUncachedResp) { // don't accept uncached grants if there's a structural hazard on s2_data... val blockUncachedGrant = Reg(Bool()) blockUncachedGrant := dataArb.io.out.valid when (grantIsUncachedData && (blockUncachedGrant \|\| s1_valid)) { tl_out.d.ready := false.B // ...but insert bubble to guarantee grant's eventual forward progress when (tl_out.d.valid) { io.cpu.req.ready := false.B dataArb.io.in(1).valid := true.B dataArb.io.in(1).bits.write := false.B blockUncachedGrant := !dataArb.io.in(1).ready } } } ccover(tl_out.d.valid && !tl_out.d.ready, "BLOCK_D", "D$ D-channel blocked") // Handle an incoming TileLink Probe message val block_probe_for_core_progress = blockProbeAfterGrantCount > 0.U \|\| lrscValid val block_probe_for_pending_release_ack = release_ack_wait && (tl_out.b.bits.address ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U val block_probe_for_ordering = releaseInFlight \|\| block_probe_for_pending_release_ack \|\| grantInProgress metaArb.io.in(6).valid := tl_out.b.valid && (!block_probe_for_core_progress \|\| lrscBackingOff) tl_out.b.ready := metaArb.io.in(6).ready && !(block_probe_for_core_progress \|\| block_probe_for_ordering \|\| s1_valid \|\| s2_valid) metaArb.io.in(6).bits.write := false.B metaArb.io.in(6).bits.idx := probeIdx(tl_out.b.bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, tl_out.b.bits.address) metaArb.io.in(6).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(6).bits.data := metaArb.io.in(4).bits.data // replacement policy s1_victim_way := (if (replacer.perSet && nWays > 1) { val repl_array = Mem(nSets, UInt(replacer.nBits.W)) val s1_repl_idx = s1_req.addr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_idx = s2_vaddr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_state = Reg(UInt(replacer.nBits.W)) val s2_new_repl_state = replacer.get_next_state(s2_repl_state, OHToUInt(s2_hit_way)) val s2_repl_wen = s2_valid_masked && s2_hit_way.orR && s2_repl_state =/= s2_new_repl_state val s1_repl_state = Mux(s2_repl_wen && s2_repl_idx === s1_repl_idx, s2_new_repl_state, repl_array(s1_repl_idx)) when (s1_valid_not_nacked) { s2_repl_state := s1_repl_state } val waddr = Mux(resetting, flushCounter(idxBits-1, 0), s2_repl_idx) val wdata = Mux(resetting, 0.U, s2_new_repl_state) val wen = resetting \|\| s2_repl_wen when (wen) { repl_array(waddr) := wdata } replacer.get_replace_way(s1_repl_state) } else { replacer.way }) // release val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c) val releaseRejected = Wire(Bool()) val s1_release_data_valid = RegNext(dataArb.io.in(2).fire) val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected) releaseRejected := s2_release_data_valid && !tl_out_c.fire val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid)) val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN) val cleanReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param) val dirtyReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param, data = 0.U) tl_out_c.valid := (s2_release_data_valid \|\| (!cacheParams.silentDrop.B && release_state === s_voluntary_release)) && !(c_first && release_ack_wait) tl_out_c.bits := nackResponseMessage val newCoh = WireDefault(probeNewCoh) releaseWay := s2_probe_way if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line \|\| s2_flush_valid \|\| io.cpu.s2_nack) val discard_line = s2_valid_flush_line && s2_req.size(1) \|\| s2_flush_valid && flushing_req.size(1) release_state := Mux(s2_victim_dirty && !discard_line, s_voluntary_writeback, Mux(!cacheParams.silentDrop.B && !release_ack_wait && release_queue_empty && s2_victim_state.isValid() && (s2_valid_flush_line \|\| s2_flush_valid \|\| s2_readwrite && !s2_hit_valid), s_voluntary_release, s_voluntary_write_meta)) probe_bits := addressToProbe(s2_vaddr, Cat(s2_victim_tag, s2_req.addr(tagLSB-1, idxLSB)) << idxLSB) } when (s2_probe) { val probeNack = WireDefault(true.B) when (s2_meta_error) { release_state := s_probe_retry }.elsewhen (s2_prb_ack_data) { release_state := s_probe_rep_dirty }.elsewhen (s2_probe_state.isValid()) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean) }.otherwise { tl_out_c.valid := true.B probeNack := !releaseDone release_state := Mux(releaseDone, s_ready, s_probe_rep_miss) } when (probeNack) { s1_nack := true.B } } when (release_state === s_probe_retry) { metaArb.io.in(6).valid := true.B metaArb.io.in(6).bits.idx := probeIdx(probe_bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address) when (metaArb.io.in(6).ready) { release_state := s_ready s1_probe := true.B } } when (release_state === s_probe_rep_miss) { tl_out_c.valid := true.B when (releaseDone) { release_state := s_ready } } when (release_state === s_probe_rep_clean) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state === s_probe_rep_dirty) { tl_out_c.bits := dirtyReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)) { when (release_state === s_voluntary_release) { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param)._2 }.otherwise { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param, data = 0.U)._2 } newCoh := voluntaryNewCoh releaseWay := s2_victim_or_hit_way when (releaseDone) { release_state := s_voluntary_write_meta } when (tl_out_c.fire && c_first) { release_ack_wait := true.B release_ack_addr := probe_bits.address } } tl_out_c.bits.source := probe_bits.source tl_out_c.bits.address := probe_bits.address tl_out_c.bits.data := s2_data_corrected tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable } tl_out_c.bits.user.lift(AMBAProt).foreach { x => x.fetch := false.B x.secure := true.B x.privileged := true.B x.bufferable := true.B x.modifiable := true.B x.readalloc := true.B x.writealloc := true.B } dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles.U dataArb.io.in(2).bits := dataArb.io.in(1).bits dataArb.io.in(2).bits.write := false.B dataArb.io.in(2).bits.addr := (probeIdx(probe_bits) << blockOffBits) \| (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits) dataArb.io.in(2).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(2).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(2).bits.way_en := ~0.U(nWays.W) metaArb.io.in(4).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta) metaArb.io.in(4).bits.write := true.B metaArb.io.in(4).bits.way_en := releaseWay metaArb.io.in(4).bits.idx := probeIdx(probe_bits) metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0)) metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt) when (metaArb.io.in(4).fire) { release_state := s_ready } // cached response (io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll io.cpu.resp.bits.has_data := s2_read io.cpu.resp.bits.replay := false.B io.cpu.s2_uncached := s2_uncached && !s2_hit io.cpu.s2_paddr := s2_req.addr io.cpu.s2_gpa := s2_tlb_xcpt.gpa io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte // report whether there are any outstanding accesses. disregard any // slave-port accesses, since they don't affect local memory ordering. val s1_isSlavePortAccess = s1_req.no_xcpt val s2_isSlavePortAccess = s2_req.no_xcpt io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess \|\| s2_valid && !s2_isSlavePortAccess \|\| cached_grant_wait \|\| uncachedInFlight.asUInt.orR) io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) \|\| uncachedInFlight.asUInt.orR val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt)) if (usingDataScratchpad) { assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC))) } else { ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked") } // uncached response val s1_uncached_data_word = { val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val words = tl_out.d.bits.data.grouped(wordBits) words(word_idx) } val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next) val doUncachedResp = RegNext(io.cpu.replay_next) io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc \|\| doUncachedResp) && !s2_data_error io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B when (doUncachedResp) { assert(!s2_valid_hit) io.cpu.resp.bits.replay := true.B io.cpu.resp.bits.addr := s2_uncached_resp_addr } io.cpu.uncached_resp.map { resp => resp.valid := tl_out.d.valid && grantIsUncachedData resp.bits.tag := uncachedResp.tag resp.bits.size := uncachedResp.size resp.bits.signed := uncachedResp.signed resp.bits.data := new LoadGen(uncachedResp.size, uncachedResp.signed, uncachedResp.addr, s1_uncached_data_word, false.B, wordBytes).data resp.bits.data_raw := s1_uncached_data_word when (grantIsUncachedData && !resp.ready) { tl_out.d.ready := false.B } } // load data subword mux/sign extension val s2_data_word = (0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)).reduce(_\|_) val s2_data_word_corrected = (0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)).reduce(_\|_) val s2_data_word_possibly_uncached = Mux(cacheParams.pipelineWayMux.B && doUncachedResp, s2_uncached_data_word, 0.U) \| s2_data_word val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word_possibly_uncached, s2_sc, wordBytes) io.cpu.resp.bits.data := loadgen.data \| s2_sc_fail io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_raw := s2_data_word io.cpu.resp.bits.store_data := pstore1_data // AMOs if (usingRMW) { val amoalus = (0 until coreDataBits / xLen).map { i => val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := pstore1_mask >> (i * xBytes) amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR) amoalu.io.lhs := s2_data_word >> (i * xLen) amoalu.io.rhs := pstore1_data >> (i * xLen) amoalu } pstore1_storegen_data := (if (!usingDataScratchpad) amoalus.map(_.io.out).asUInt else { val mask = FillInterleaved(8, Mux(s2_correct, 0.U, pstore1_mask)) amoalus.map(_.io.out_unmasked).asUInt & mask \| s2_data_word_corrected & ~mask }) } else if (!usingAtomics) { assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation") } if (coreParams.useVector) { edge.manager.managers.foreach { m => // Statically ensure that no-allocate accesses are permitted. // We could consider turning some of these into dynamic PMA checks. require(!m.supportsAcquireB \|\| m.supportsGet, "With a vector unit, cacheable memory must support Get") require(!m.supportsAcquireT \|\| m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial") } } // flushes if (!usingDataScratchpad) when (RegNext(reset.asBool)) { resetting := true.B } val flushCounterNext = flushCounter +& 1.U val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays.U val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0) ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush") ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush") s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait metaArb.io.in(5).valid := flushing && !flushed metaArb.io.in(5).bits.write := false.B metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0) metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits) metaArb.io.in(5).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. if (supports_flush) { when (s2_valid_masked && s2_cmd_flush_all) { when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) { flushing := true.B flushing_req := s2_req } } when (tl_out_a.fire && !s2_uncached) { flushed := false.B } when (flushing) { s1_victim_way := flushCounter >> log2Up(nSets) when (s2_flush_valid) { flushCounter := flushCounterNext when (flushDone) { flushed := true.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } when (flushed && release_state === s_ready && !release_ack_wait) { flushing := false.B } } } metaArb.io.in(0).valid := resetting metaArb.io.in(0).bits := metaArb.io.in(5).bits metaArb.io.in(0).bits.write := true.B metaArb.io.in(0).bits.way_en := ~0.U(nWays.W) metaArb.io.in(0).bits.data := tECC.encode(L1Metadata(0.U, ClientMetadata.onReset).asUInt) when (resetting) { flushCounter := flushCounterNext when (flushDone) { resetting := false.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } // gate the clock clock_en_reg := !cacheParams.clockGate.B \|\| io.ptw.customCSRs.disableDCacheClockGate \|\| io.cpu.keep_clock_enabled \|\| metaArb.io.out.valid \|\| // subsumes resetting \|\| flushing s1_probe \|\| s2_probe \|\| s1_valid \|\| s2_valid \|\| io.tlb_port.req.valid \|\| s1_tlb_req_valid \|\| s2_tlb_req_valid \|\| pstore1_held \|\| pstore2_valid \|\| release_state =/= s_ready \|\| release_ack_wait \|\| !release_queue_empty \|\| !tlb.io.req.ready \|\| cached_grant_wait \|\| uncachedInFlight.asUInt.orR \|\| lrscCount > 0.U \|\| blockProbeAfterGrantCount > 0.U // performance events io.cpu.perf.acquire := edge.done(tl_out_a) io.cpu.perf.release := edge.done(tl_out_c) io.cpu.perf.grant := tl_out.d.valid && d_last io.cpu.perf.tlbMiss := io.ptw.req.fire io.cpu.perf.storeBufferEmptyAfterLoad := !( (s1_valid && s1_write) \|\| ((s2_valid && s2_write && !s2_waw_hazard) \|\| pstore1_held) \|\| pstore2_valid) io.cpu.perf.storeBufferEmptyAfterStore := !( (s1_valid && s1_write) \|\| (s2_valid && s2_write && pstore1_rmw) \|\| ((s2_valid && s2_write && !s2_waw_hazard \|\| pstore1_held) && pstore2_valid)) io.cpu.perf.canAcceptStoreThenLoad := !( ((s2_valid && s2_write && pstore1_rmw) && (s1_valid && s1_write && !s1_waw_hazard)) \|\| (pstore2_valid && pstore1_valid_likely && (s1_valid && s1_write))) io.cpu.perf.canAcceptStoreThenRMW := io.cpu.perf.canAcceptStoreThenLoad && !pstore2_valid io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard \|\| pstore1_held) \|\| pstore2_valid)) io.cpu.perf.blocked := { // stop reporting blocked just before unblocking to avoid overly conservative stalling val beatsBeforeEnd = outer.crossing match { case SynchronousCrossing(_) => 2 case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2 case _: AsynchronousCrossing => 1 // likewise case _: CreditedCrossing => 1 // likewise } val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else { val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W)) when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U } refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U } cached_grant_wait && !near_end_of_refill } // report errors val (data_error, data_error_uncorrectable, data_error_addr) = if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else { (RegNext(tl_out_c.fire && inWriteback && s2_data_error), RegNext(s2_data_error_uncorrectable), probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register } { val error_addr = Mux(metaArb.io.in(1).valid, Cat(s2_first_meta_corrected.tag, metaArb.io.in(1).bits.addr(tagLSB-1, idxLSB)), data_error_addr >> idxLSB) << idxLSB io.errors.uncorrectable.foreach { u => u.valid := metaArb.io.in(1).valid && s2_meta_error_uncorrectable \|\| data_error && data_error_uncorrectable u.bits := error_addr } io.errors.correctable.foreach { c => c.valid := metaArb.io.in(1).valid \|\| data_error c.bits := error_addr io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } } } io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied \|\| tl_out.d.bits.corrupt) io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U) ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached") } if (usingDataScratchpad) { val data_error_cover = Seq( property.CoverBoolean(!data_error, Seq("no_data_error")), property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) property.cover(new property.CrossProperty( Seq(data_error_cover, request_source), Seq(), "MemorySystem;;Scratchpad Memory Bit Flip Cross Covers")) } else { val data_error_type = Seq( property.CoverBoolean(!s2_valid_data_error, Seq("no_data_error")), property.CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error"))) val data_error_dirty = Seq( property.CoverBoolean(!s2_victim_dirty, Seq("data_clean")), property.CoverBoolean(s2_victim_dirty, Seq("data_dirty"))) val request_source = if (supports_flush) { Seq( property.CoverBoolean(!flushing, Seq("access")), property.CoverBoolean(flushing, Seq("during_flush"))) } else { Seq(property.CoverBoolean(true.B, Seq("never_flush"))) } val tag_error_cover = Seq( property.CoverBoolean( !s2_meta_error, Seq("no_tag_error")), property.CoverBoolean( s2_meta_error && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")), property.CoverBoolean( s2_meta_error && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error"))) property.cover(new property.CrossProperty( Seq(data_error_type, data_error_dirty, request_source, tag_error_cover), Seq(), "MemorySystem;;Cache Memory Bit Flip Cross Covers")) } } // leaving gated-clock domain val dcacheImpl = withClock (gated_clock) { new DCacheModuleImpl } def encodeData(x: UInt, poison: Bool) = x.grouped(eccBits).map(dECC.encode(_, if (dECC.canDetect) poison else false.B)).asUInt def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_)) def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask)) def likelyNeedsRead(req: HellaCacheReq) = { val res = !req.cmd.isOneOf(M_XWR, M_PFW) \|\| req.size < log2Ceil(eccBytes).U assert(!needsRead(req) \|\| res) res } def needsRead(req: HellaCacheReq) = isRead(req.cmd) \|\| (isWrite(req.cmd) && (req.cmd === M_PWR \|\| req.size < log2Ceil(eccBytes).U)) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc) def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (!usingDataScratchpad) ccover(cond, label, desc) require(!usingVM \|\| tagLSB <= pgIdxBits, s"D$$ set size must not exceed ${1<<(pgIdxBits-10)} KiB; got ${(nSets * cacheBlockBytes)>>10} KiB") def tagLSB: Int = untagBits def probeIdx(b: TLBundleB): UInt = b.address(idxMSB, idxLSB) def addressToProbe(vaddr: UInt, paddr: UInt): TLBundleB = { val res = Wire(new TLBundleB(edge.bundle)) res :#= DontCare res.address := paddr res.source := (mmioOffset - 1).U res } def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = { if (!edge.manager.anySupportAcquireB) WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))) else edge.AcquireBlock(0.U, paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes.U, param)._2 } } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module DCache( // @[DCache.scala:101:7] input clock, // @[DCache.scala:101:7] input reset, // @[DCache.scala:101:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output io_cpu_req_ready, // @[HellaCache.scala:243:14] input io_cpu_req_valid, // @[HellaCache.scala:243:14] input [39:0] io_cpu_req_bits_addr, // @[HellaCache.scala:243:14] input [7:0] io_cpu_req_bits_tag, // @[HellaCache.scala:243:14] input [4:0] io_cpu_req_bits_cmd, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_size, // @[HellaCache.scala:243:14] input io_cpu_req_bits_signed, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_dprv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_dv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_phys, // @[HellaCache.scala:243:14] input io_cpu_req_bits_no_resp, // @[HellaCache.scala:243:14] input io_cpu_s1_kill, // @[HellaCache.scala:243:14] input [63:0] io_cpu_s1_data_data, // @[HellaCache.scala:243:14] input [7:0] io_cpu_s1_data_mask, // @[HellaCache.scala:243:14] output io_cpu_s2_nack, // @[HellaCache.scala:243:14] output io_cpu_s2_nack_cause_raw, // @[HellaCache.scala:243:14] output io_cpu_s2_uncached, // @[HellaCache.scala:243:14] output [31:0] io_cpu_s2_paddr, // @[HellaCache.scala:243:14] output io_cpu_resp_valid, // @[HellaCache.scala:243:14] output [39:0] io_cpu_resp_bits_addr, // @[HellaCache.scala:243:14] output [7:0] io_cpu_resp_bits_tag, // @[HellaCache.scala:243:14] output [4:0] io_cpu_resp_bits_cmd, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_size, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_signed, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_dprv, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_dv, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data, // @[HellaCache.scala:243:14] output [7:0] io_cpu_resp_bits_mask, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_replay, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_has_data, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_word_bypass, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_raw, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_store_data, // @[HellaCache.scala:243:14] output io_cpu_replay_next, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_st, // @[HellaCache.scala:243:14] output [39:0] io_cpu_s2_gpa, // @[HellaCache.scala:243:14] output io_cpu_ordered, // @[HellaCache.scala:243:14] output io_cpu_store_pending, // @[HellaCache.scala:243:14] output io_cpu_perf_acquire, // @[HellaCache.scala:243:14] output io_cpu_perf_release, // @[HellaCache.scala:243:14] output io_cpu_perf_grant, // @[HellaCache.scala:243:14] output io_cpu_perf_tlbMiss, // @[HellaCache.scala:243:14] output io_cpu_perf_blocked, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenRMW, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptLoadThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterStore, // @[HellaCache.scala:243:14] input io_cpu_keep_clock_enabled, // @[HellaCache.scala:243:14] input io_ptw_req_ready, // @[HellaCache.scala:243:14] output io_ptw_req_valid, // @[HellaCache.scala:243:14] output [26:0] io_ptw_req_bits_bits_addr, // @[HellaCache.scala:243:14] output io_ptw_req_bits_bits_need_gpa, // @[HellaCache.scala:243:14] input io_ptw_resp_valid, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_ptw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_final, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hr, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hx, // @[HellaCache.scala:243:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[HellaCache.scala:243:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_d, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_a, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_g, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_u, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_x, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_w, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_r, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_v, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_level, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_homogeneous, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_valid, // @[HellaCache.scala:243:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_is_pte, // @[HellaCache.scala:243:14] input [3:0] io_ptw_ptbr_mode, // @[HellaCache.scala:243:14] input [43:0] io_ptw_ptbr_ppn, // @[HellaCache.scala:243:14] input io_ptw_status_debug, // @[HellaCache.scala:243:14] input io_ptw_status_cease, // @[HellaCache.scala:243:14] input io_ptw_status_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_status_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_dprv, // @[HellaCache.scala:243:14] input io_ptw_status_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_prv, // @[HellaCache.scala:243:14] input io_ptw_status_v, // @[HellaCache.scala:243:14] input io_ptw_status_mpv, // @[HellaCache.scala:243:14] input io_ptw_status_gva, // @[HellaCache.scala:243:14] input io_ptw_status_tsr, // @[HellaCache.scala:243:14] input io_ptw_status_tw, // @[HellaCache.scala:243:14] input io_ptw_status_tvm, // @[HellaCache.scala:243:14] input io_ptw_status_mxr, // @[HellaCache.scala:243:14] input io_ptw_status_sum, // @[HellaCache.scala:243:14] input io_ptw_status_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_mpp, // @[HellaCache.scala:243:14] input io_ptw_status_spp, // @[HellaCache.scala:243:14] input io_ptw_status_mpie, // @[HellaCache.scala:243:14] input io_ptw_status_spie, // @[HellaCache.scala:243:14] input io_ptw_status_mie, // @[HellaCache.scala:243:14] input io_ptw_status_sie, // @[HellaCache.scala:243:14] input io_ptw_hstatus_spvp, // @[HellaCache.scala:243:14] input io_ptw_hstatus_spv, // @[HellaCache.scala:243:14] input io_ptw_hstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_debug, // @[HellaCache.scala:243:14] input io_ptw_gstatus_cease, // @[HellaCache.scala:243:14] input io_ptw_gstatus_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_gstatus_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_dprv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_prv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_v, // @[HellaCache.scala:243:14] input [22:0] io_ptw_gstatus_zero2, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mbe, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sbe, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_sxl, // @[HellaCache.scala:243:14] input [7:0] io_ptw_gstatus_zero1, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tsr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tw, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tvm, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mxr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sum, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_mpp, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_vs, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spp, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_ube, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_upie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_hie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_uie, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_0_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_0_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_1_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_1_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_2_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_2_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_3_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_3_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_4_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_4_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_5_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_5_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_6_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_6_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_7_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_7_mask, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[HellaCache.scala:243:14] ); wire [19:0] s2_meta_corrected_7_tag; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_7_coh_state; // @[DCache.scala:361:99] wire rockettile_dcache_tag_array_MPORT_en; // @[DCache.scala:310:27] wire s0_req_phys; // @[DCache.scala:192:24] wire [39:0] s0_req_addr; // @[DCache.scala:192:24] wire tl_out_a_valid; // @[DCache.scala:159:22] wire [127:0] tl_out_a_bits_data; // @[DCache.scala:159:22] wire [15:0] tl_out_a_bits_mask; // @[DCache.scala:159:22] wire [31:0] tl_out_a_bits_address; // @[DCache.scala:159:22] wire tl_out_a_bits_source; // @[DCache.scala:159:22] wire [3:0] tl_out_a_bits_size; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_param; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_opcode; // @[DCache.scala:159:22] wire [5:0] metaArb_io_out_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_in_0_valid; // @[DCache.scala:135:28] wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [175:0] _rockettile_dcache_tag_array_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22] wire [19:0] _pma_checker_entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_checker_pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_eff; // @[TLB.scala:422:19] wire [19:0] _pma_checker_mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire _tlb_io_req_ready; // @[DCache.scala:119:19] wire _tlb_io_resp_miss; // @[DCache.scala:119:19] wire [31:0] _tlb_io_resp_paddr; // @[DCache.scala:119:19] wire [39:0] _tlb_io_resp_gpa; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_st; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_st; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_st; // @[DCache.scala:119:19] wire _tlb_io_resp_cacheable; // @[DCache.scala:119:19] wire _tlb_io_resp_must_alloc; // @[DCache.scala:119:19] wire _tlb_io_resp_prefetchable; // @[DCache.scala:119:19] wire [1:0] _tlb_io_resp_size; // @[DCache.scala:119:19] wire [4:0] _tlb_io_resp_cmd; // @[DCache.scala:119:19] wire auto_out_a_ready_0 = auto_out_a_ready; // @[DCache.scala:101:7] wire auto_out_b_valid_0 = auto_out_b_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[DCache.scala:101:7] wire auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[DCache.scala:101:7] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[DCache.scala:101:7] wire [15:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[DCache.scala:101:7] wire [127:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[DCache.scala:101:7] wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[DCache.scala:101:7] wire auto_out_c_ready_0 = auto_out_c_ready; // @[DCache.scala:101:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DCache.scala:101:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DCache.scala:101:7] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DCache.scala:101:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DCache.scala:101:7] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DCache.scala:101:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DCache.scala:101:7] wire auto_out_e_ready_0 = auto_out_e_ready; // @[DCache.scala:101:7] wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[DCache.scala:101:7] wire [39:0] io_cpu_req_bits_addr_0 = io_cpu_req_bits_addr; // @[DCache.scala:101:7] wire [7:0] io_cpu_req_bits_tag_0 = io_cpu_req_bits_tag; // @[DCache.scala:101:7] wire [4:0] io_cpu_req_bits_cmd_0 = io_cpu_req_bits_cmd; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_size_0 = io_cpu_req_bits_size; // @[DCache.scala:101:7] wire io_cpu_req_bits_signed_0 = io_cpu_req_bits_signed; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_dprv_0 = io_cpu_req_bits_dprv; // @[DCache.scala:101:7] wire io_cpu_req_bits_dv_0 = io_cpu_req_bits_dv; // @[DCache.scala:101:7] wire io_cpu_req_bits_phys_0 = io_cpu_req_bits_phys; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_resp_0 = io_cpu_req_bits_no_resp; // @[DCache.scala:101:7] wire io_cpu_s1_kill_0 = io_cpu_s1_kill; // @[DCache.scala:101:7] wire [63:0] io_cpu_s1_data_data_0 = io_cpu_s1_data_data; // @[DCache.scala:101:7] wire [7:0] io_cpu_s1_data_mask_0 = io_cpu_s1_data_mask; // @[DCache.scala:101:7] wire io_cpu_keep_clock_enabled_0 = io_cpu_keep_clock_enabled; // @[DCache.scala:101:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[DCache.scala:101:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[DCache.scala:101:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[DCache.scala:101:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[DCache.scala:101:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[DCache.scala:101:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[DCache.scala:101:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[DCache.scala:101:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[DCache.scala:101:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[DCache.scala:101:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[DCache.scala:101:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[DCache.scala:101:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[DCache.scala:101:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[DCache.scala:101:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[DCache.scala:101:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[DCache.scala:101:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[DCache.scala:101:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[DCache.scala:101:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[DCache.scala:101:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[DCache.scala:101:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[DCache.scala:101:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[DCache.scala:101:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[DCache.scala:101:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[DCache.scala:101:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[DCache.scala:101:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[DCache.scala:101:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[DCache.scala:101:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[DCache.scala:101:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[DCache.scala:101:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[DCache.scala:101:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[DCache.scala:101:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[DCache.scala:101:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[DCache.scala:101:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[DCache.scala:101:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[DCache.scala:101:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[DCache.scala:101:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[DCache.scala:101:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[DCache.scala:101:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[DCache.scala:101:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[DCache.scala:101:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[DCache.scala:101:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[DCache.scala:101:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[DCache.scala:101:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[DCache.scala:101:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[DCache.scala:101:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[DCache.scala:101:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[DCache.scala:101:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[DCache.scala:101:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[DCache.scala:101:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[DCache.scala:101:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[DCache.scala:101:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_55 = reset; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_55 = reset; // @[DCache.scala:1186:11] wire auto_out_a_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire auto_out_c_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_alloc = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_xcpt = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_kill = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_mbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_ube = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_upie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_hie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_uie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_valid = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_passthrough = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_v = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s2_kill = 1'h0; // @[DCache.scala:101:7] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire pma_checker_io_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_miss = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_ld = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_st = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_asid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hg = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_ready = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_need_gpa = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_ptw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_final = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hx = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_d = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_a = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_g = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_u = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_homogeneous = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_kill = 1'h0; // @[DCache.scala:120:32] wire pma_checker_priv_v = 1'h0; // @[TLB.scala:369:34] wire pma_checker__stage1_en_T = 1'h0; // @[TLB.scala:374:41] wire pma_checker_stage1_en = 1'h0; // @[TLB.scala:374:29] wire pma_checker__vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire pma_checker__vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire pma_checker_vstage1_en = 1'h0; // @[TLB.scala:376:48] wire pma_checker__stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire pma_checker__stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire pma_checker_stage2_en = 1'h0; // @[TLB.scala:378:48] wire pma_checker__vm_enabled_T = 1'h0; // @[TLB.scala:399:31] wire pma_checker__vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45] wire pma_checker__vm_enabled_T_2 = 1'h0; // @[TLB.scala:399:64] wire pma_checker_vm_enabled = 1'h0; // @[TLB.scala:399:61] wire pma_checker__vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire pma_checker__vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire pma_checker__vsatp_mode_mismatch_T_2 = 1'h0; // @[TLB.scala:403:81] wire pma_checker_vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire pma_checker_do_refill = 1'h0; // @[TLB.scala:408:29] wire pma_checker__invalidate_refill_T = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_invalidate_refill = 1'h0; // @[TLB.scala:410:88] wire pma_checker__mpu_ppn_T = 1'h0; // @[TLB.scala:413:32] wire pma_checker_prot_r = 1'h0; // @[TLB.scala:429:55] wire pma_checker_prot_w = 1'h0; // @[TLB.scala:430:55] wire pma_checker_prot_x = 1'h0; // @[TLB.scala:434:55] wire pma_checker__sector_hits_T = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_0 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_9 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_10 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_1 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_17 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_18 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_2 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_24 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_25 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_26 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_3 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_32 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_33 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_34 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_4 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_40 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_41 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_42 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_5 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_48 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_49 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_50 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_6 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_56 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_57 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_58 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_7 = 1'h0; // @[TLB.scala:172:55] wire pma_checker_superpage_hits_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_4 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_9 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_0 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_18 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_23 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_1 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_32 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_37 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_2 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_46 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_51 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_3 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_0 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_1 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_2 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_3 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_4 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_5 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_6 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_7 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_52 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_57 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_62 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_8 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_67 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_72 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_77 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_9 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_82 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_87 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_92 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_10 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_97 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_102 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_107 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_11 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_4 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_112 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_117 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_122 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_12 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_refill_v = 1'h0; // @[TLB.scala:448:33] wire pma_checker_newEntry_u = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_g = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_ptw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_final = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_gf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_px = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire pma_checker__newEntry_g_T = 1'h0; // @[TLB.scala:453:25] wire pma_checker__newEntry_ae_stage2_T = 1'h0; // @[TLB.scala:456:53] wire pma_checker__newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire pma_checker__newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sr_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sr_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sr_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sr_T_5 = 1'h0; // @[PTW.scala:149:35] wire pma_checker__newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sw_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sw_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sw_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sw_T_5 = 1'h0; // @[PTW.scala:151:35] wire pma_checker__newEntry_sw_T_6 = 1'h0; // @[PTW.scala:151:40] wire pma_checker__newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sx_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sx_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sx_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35] wire pma_checker__waddr_T = 1'h0; // @[TLB.scala:477:45] wire pma_checker__superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker_sum = 1'h0; // @[TLB.scala:510:16] wire pma_checker__mxr_T = 1'h0; // @[TLB.scala:518:36] wire pma_checker_mxr = 1'h0; // @[TLB.scala:518:31] wire pma_checker__bad_va_T = 1'h0; // @[TLB.scala:568:21] wire pma_checker_bad_va = 1'h0; // @[TLB.scala:568:34] wire pma_checker_cmd_readx = 1'h0; // @[TLB.scala:575:37] wire pma_checker__gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire pma_checker__gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire pma_checker__gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60] wire pma_checker_tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43] wire pma_checker_tlb_hit = 1'h0; // @[TLB.scala:611:40] wire pma_checker__tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29] wire pma_checker__tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53] wire pma_checker_tlb_miss = 1'h0; // @[TLB.scala:613:64] wire pma_checker__state_vec_0_set_left_older_T = 1'h0; // @[Replacement.scala:196:43] wire pma_checker__state_vec_0_set_left_older_T_1 = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_vec_0_T_1 = 1'h0; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_2 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_T_4 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_vec_0_T_5 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_vec_0_T_6 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_set_left_older_T_2 = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_vec_0_T_12 = 1'h0; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_13 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_T_15 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_vec_0_T_16 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_vec_0_T_17 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_reg_set_left_older_T = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_reg_T = 1'h0; // @[package.scala:163:13] wire pma_checker__state_reg_T_1 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_reg_T_3 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_reg_T_4 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_reg_T_5 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits = 1'h0; // @[Misc.scala:183:49] wire pma_checker__io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28] wire pma_checker__io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire pma_checker__io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire pma_checker__io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire pma_checker__io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire pma_checker__io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire pma_checker__io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire pma_checker__io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire pma_checker__io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire pma_checker__io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire pma_checker__io_resp_miss_T = 1'h0; // @[TLB.scala:651:29] wire pma_checker__io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52] wire pma_checker__io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64] wire pma_checker__io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire pma_checker__io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29] wire pma_checker_r_superpage_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_superpage_repl_addr_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_r_superpage_repl_addr_right_subtree_state = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_superpage_repl_addr_T = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_superpage_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_superpage_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker__r_superpage_repl_addr_T_4 = 1'h0; // @[TLB.scala:757:16] wire pma_checker_r_sectored_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_older_1 = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_r_sectored_repl_addr_right_subtree_state_1 = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_sectored_repl_addr_T = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker_r_sectored_repl_addr_left_subtree_older_2 = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_r_sectored_repl_addr_right_subtree_state_2 = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_sectored_repl_addr_T_4 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_5 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_6 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker__r_sectored_repl_addr_valids_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_3 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_4 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_5 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_6 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_7 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_9 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_10 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_11 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_12 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_13 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_14 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_15 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_17 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_18 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_19 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_20 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_21 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_22 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_23 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_T_10 = 1'h0; // @[TLB.scala:757:16] wire pma_checker__r_sectored_hit_valid_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_3 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_4 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_5 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_6 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_sectored_hit_bits_T_3 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_sectored_hit_bits_T_5 = 1'h0; // @[CircuitMath.scala:28:8] wire pma_checker__r_superpage_hit_valid_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_valid_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_valid_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_superpage_hit_bits_T_3 = 1'h0; // @[CircuitMath.scala:28:8] wire pma_checker_hv = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_1 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_1 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_2 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_2 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_3 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_3 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_4 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_4 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_5 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_5 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_6 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_6 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_7 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_7 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_8 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_8 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_9 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_9 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_10 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_10 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_11 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_11 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_12 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_12 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_4 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire metaArb_io_in_1_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_6_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_7_bits_write = 1'h0; // @[DCache.scala:135:28] wire dataArb_io_in_2_bits_write = 1'h0; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_write = 1'h0; // @[DCache.scala:152:28] wire tl_out_a_bits_corrupt = 1'h0; // @[DCache.scala:159:22] wire nodeOut_a_deq_bits_corrupt = 1'h0; // @[Decoupled.scala:356:21] wire _s1_tlb_req_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire s0_req_no_alloc = 1'h0; // @[DCache.scala:192:24] wire s0_req_no_xcpt = 1'h0; // @[DCache.scala:192:24] wire s1_waw_hazard = 1'h0; // @[DCache.scala:216:27] wire _uncachedInFlight_WIRE_0 = 1'h0; // @[DCache.scala:236:41] wire _dataArb_io_in_3_valid_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _dataArb_io_in_3_valid_T_49 = 1'h0; // @[DCache.scala:1191:57] wire dataArb_io_in_3_bits_wordMask_mask_upper_mask = 1'h0; // @[DCache.scala:248:27] wire _s1_did_read_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _tlb_io_kill_T = 1'h0; // @[DCache.scala:272:53] wire _tlb_io_kill_T_1 = 1'h0; // @[DCache.scala:272:33] wire _s2_pma_T_gpa_is_pte = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_ld = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_st = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_inst = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_ma_inst = 1'h0; // @[DCache.scala:349:18] wire s2_meta_error_uncorrectable = 1'h0; // @[DCache.scala:360:66] wire s2_meta_error = 1'h0; // @[DCache.scala:362:83] wire s2_store_merge = 1'h0; // @[DCache.scala:388:28] wire _r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _s2_data_error_T = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_1 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_2 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_3 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_4 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_5 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_6 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_7 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_8 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_9 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_10 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_11 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_12 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_13 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_14 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_15 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_16 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_17 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_18 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_19 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_20 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_21 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_22 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_23 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_24 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_25 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_26 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_27 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_28 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_29 = 1'h0; // @[package.scala:81:59] wire s2_data_error = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_1 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_2 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_3 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_4 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_5 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_6 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_7 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_8 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_9 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_10 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_11 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_12 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_13 = 1'h0; // @[package.scala:81:59] wire s2_data_error_uncorrectable = 1'h0; // @[package.scala:81:59] wire s2_valid_data_error = 1'h0; // @[DCache.scala:421:63] wire s2_cannot_victimize = 1'h0; // @[DCache.scala:428:45] wire _r_T_73 = 1'h0; // @[Misc.scala:38:9] wire _r_T_77 = 1'h0; // @[Misc.scala:38:9] wire _r_T_81 = 1'h0; // @[Misc.scala:38:9] wire _r_T_119 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_121 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_137 = 1'h0; // @[Misc.scala:38:9] wire _r_T_141 = 1'h0; // @[Misc.scala:38:9] wire _r_T_145 = 1'h0; // @[Misc.scala:38:9] wire _s2_dont_nack_misc_T_2 = 1'h0; // @[DCache.scala:442:23] wire _s2_dont_nack_misc_T_3 = 1'h0; // @[DCache.scala:442:43] wire _s2_dont_nack_misc_T_5 = 1'h0; // @[DCache.scala:442:54] wire _s2_dont_nack_misc_T_6 = 1'h0; // @[DCache.scala:443:23] wire _s2_dont_nack_misc_T_8 = 1'h0; // @[DCache.scala:443:44] wire _s2_dont_nack_misc_T_9 = 1'h0; // @[DCache.scala:442:67] wire _s2_first_meta_corrected_T = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_1 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_2 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_3 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_4 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_5 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_6 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_7 = 1'h0; // @[Mux.scala:52:83] wire _metaArb_io_in_1_valid_T_2 = 1'h0; // @[DCache.scala:450:43] wire _metaArb_io_in_1_bits_way_en_T = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_1 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_2 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_3 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_4 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_5 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_6 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_7 = 1'h0; // @[OneHot.scala:85:71] wire _s2_correct_T_1 = 1'h0; // @[DCache.scala:487:34] wire _s2_correct_T_4 = 1'h0; // @[DCache.scala:487:55] wire s2_correct = 1'h0; // @[DCache.scala:487:97] wire _s2_valid_correct_T = 1'h0; // @[DCache.scala:489:60] wire s2_valid_correct = 1'h0; // @[DCache.scala:489:74] wire _pstore1_rmw_T_49 = 1'h0; // @[DCache.scala:1191:57] wire pstore1_merge_likely = 1'h0; // @[DCache.scala:499:68] wire pstore1_merge = 1'h0; // @[DCache.scala:500:38] wire _pstore_drain_opportunistic_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _pstore_drain_opportunistic_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _pstore_drain_opportunistic_T_60 = 1'h0; // @[DCache.scala:502:106] wire pstore_drain_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _pstore2_storegen_data_T_2 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_6 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_10 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_14 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_18 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_22 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_26 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_30 = 1'h0; // @[DCache.scala:528:95] wire dataArb_io_in_0_valid_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _io_cpu_s2_nack_cause_raw_T_2 = 1'h0; // @[DCache.scala:574:57] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire get_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire put_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _putpartial_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _putpartial_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire putpartial_corrupt = 1'h0; // @[Edges.scala:500:17] wire _atomics_WIRE_source = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_corrupt = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_1_source = 1'h0; // @[DCache.scala:587:38] wire _atomics_WIRE_1_corrupt = 1'h0; // @[DCache.scala:587:38] wire _atomics_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_40 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_93 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_99 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_152 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_158 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_2 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_211 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_217 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_3 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_270 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_276 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_4 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_329 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_335 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_5 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_388 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_394 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_6 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_447 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_453 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_7 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_506 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_512 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_8 = 1'h0; // @[Misc.scala:206:21] wire _atomics_T_1_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_3_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_5_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_7_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_9_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_11_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_13_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_15_corrupt = 1'h0; // @[DCache.scala:587:81] wire atomics_corrupt = 1'h0; // @[DCache.scala:587:81] wire _tl_out_a_valid_T_8 = 1'h0; // @[DCache.scala:607:44] wire _tl_out_a_valid_T_9 = 1'h0; // @[DCache.scala:607:65] wire _tl_out_a_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _tl_out_a_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _tl_out_a_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire tl_out_a_bits_a_source = 1'h0; // @[Edges.scala:346:17] wire tl_out_a_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire tl_out_a_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _tl_out_a_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire tl_out_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _tl_out_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_T_6_corrupt = 1'h0; // @[DCache.scala:611:8] wire _tl_out_a_bits_T_7_corrupt = 1'h0; // @[DCache.scala:610:8] wire _tl_out_a_bits_T_8_corrupt = 1'h0; // @[DCache.scala:609:8] wire _tl_out_a_bits_T_9_corrupt = 1'h0; // @[DCache.scala:608:23] wire nackResponseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire cleanReleaseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire dirtyReleaseMessage_corrupt = 1'h0; // @[Edges.scala:433:17] wire _nodeOut_c_valid_T = 1'h0; // @[DCache.scala:810:48] wire _nodeOut_c_valid_T_2 = 1'h0; // @[DCache.scala:810:74] wire _discard_line_T_2 = 1'h0; // @[DCache.scala:818:102] wire _release_state_T_2 = 1'h0; // @[DCache.scala:820:28] wire _release_state_T_4 = 1'h0; // @[DCache.scala:820:54] wire _release_state_T_5 = 1'h0; // @[DCache.scala:820:75] wire _release_state_T_7 = 1'h0; // @[DCache.scala:820:98] wire _release_state_T_12 = 1'h0; // @[DCache.scala:820:127] wire probe_bits_res_source = 1'h0; // @[DCache.scala:1202:19] wire probe_bits_res_corrupt = 1'h0; // @[DCache.scala:1202:19] wire _nodeOut_c_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_1 = 1'h0; // @[Parameters.scala:137:31] wire _nodeOut_c_bits_legal_T_10 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_15 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_25 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_30 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_31 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_32 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_legal = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_c_source = 1'h0; // @[Edges.scala:380:17] wire nodeOut_c_bits_c_corrupt = 1'h0; // @[Edges.scala:380:17] wire _nodeOut_c_bits_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_35 = 1'h0; // @[Parameters.scala:137:31] wire _nodeOut_c_bits_legal_T_44 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_49 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_52 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_59 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_64 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_65 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_66 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_67 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_legal_1 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_c_1_source = 1'h0; // @[Edges.scala:396:17] wire nodeOut_c_bits_c_1_corrupt = 1'h0; // @[Edges.scala:396:17] wire _nodeOut_c_bits_corrupt_T = 1'h0; // @[DCache.scala:887:42] wire _io_cpu_s2_xcpt_WIRE_miss = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gpa_is_pte = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_cacheable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_must_alloc = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_prefetchable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_T_gpa_is_pte = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_ld = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_st = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_inst = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_inst = 1'h0; // @[DCache.scala:933:24] wire _s2_data_word_possibly_uncached_T = 1'h0; // @[DCache.scala:972:73] wire io_cpu_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_word_bypass_doZero = 1'h0; // @[AMOALU.scala:43:31] wire _s1_flush_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire _s1_flush_valid_T_2 = 1'h0; // @[DCache.scala:1014:43] wire _s1_flush_valid_T_4 = 1'h0; // @[DCache.scala:1014:62] wire _s1_flush_valid_T_6 = 1'h0; // @[DCache.scala:1014:93] wire _s1_flush_valid_T_8 = 1'h0; // @[DCache.scala:1014:122] wire _metaArb_io_in_5_valid_T = 1'h0; // @[DCache.scala:1015:41] wire _metaArb_io_in_5_valid_T_1 = 1'h0; // @[DCache.scala:1015:38] wire _clock_en_reg_T_17 = 1'h0; // @[DCache.scala:1070:25] wire _io_cpu_perf_canAcceptLoadThenLoad_T_50 = 1'h0; // @[DCache.scala:1191:57] wire [63:0] io_cpu_req_bits_data = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] s0_req_data = 64'h0; // @[DCache.scala:192:24] wire [63:0] _s2_data_word_possibly_uncached_T_1 = 64'h0; // @[DCache.scala:972:43] wire [7:0] io_cpu_req_bits_mask = 8'h0; // @[DCache.scala:101:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[DCache.scala:101:7] wire [7:0] pma_checker_io_ptw_status_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_io_ptw_gstatus_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_r_sectored_repl_addr_valids = 8'h0; // @[package.scala:45:27] wire [7:0] pma_checker__r_sectored_hit_bits_T = 8'h0; // @[OneHot.scala:21:45] wire [7:0] metaArb_io_in_1_bits_way_en = 8'h0; // @[DCache.scala:135:28] wire [7:0] s0_req_mask = 8'h0; // @[DCache.scala:192:24] wire [7:0] s2_meta_correctable_errors = 8'h0; // @[package.scala:45:27] wire [7:0] s2_meta_uncorrectable_errors = 8'h0; // @[package.scala:45:27] wire [7:0] _s2_meta_error_T = 8'h0; // @[DCache.scala:362:53] wire [7:0] _metaArb_io_in_1_bits_way_en_T_8 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_9 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_10 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_11 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_12 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_13 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_14 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_15 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_16 = 8'h0; // @[DCache.scala:452:69] wire [7:0] _metaArb_io_in_1_bits_way_en_T_17 = 8'h0; // @[DCache.scala:452:64] wire [7:0] _pstore2_storegen_mask_mergedMask_T = 8'h0; // @[DCache.scala:533:42] wire io_cpu_clock_enabled = 1'h1; // @[DCache.scala:101:7] wire io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:101:7] wire io_ptw_status_sd = 1'h1; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd = 1'h1; // @[DCache.scala:101:7] wire io_tlb_port_req_ready = 1'h1; // @[DCache.scala:101:7] wire pma_checker_io_req_ready = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_passthrough = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:120:32] wire pma_checker__mpu_ppn_ignore_T = 1'h1; // @[TLB.scala:197:28] wire pma_checker_mpu_ppn_ignore = 1'h1; // @[TLB.scala:197:34] wire pma_checker__mpu_ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_mpu_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__mpu_priv_T = 1'h1; // @[TLB.scala:415:52] wire pma_checker__mpu_priv_T_1 = 1'h1; // @[TLB.scala:415:38] wire pma_checker__homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire pma_checker__deny_access_to_debug_T = 1'h1; // @[TLB.scala:428:39] wire pma_checker__sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_13 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_13 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_116 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_ignore_T_14 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_14 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_121 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hits_T = 1'h1; // @[TLB.scala:442:18] wire pma_checker__newEntry_sr_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sw_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sx_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__ppn_T = 1'h1; // @[TLB.scala:502:30] wire pma_checker__ppn_ignore_T = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_2 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_3 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_4 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_5 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_6 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_7 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_8 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_8 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_9 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_9 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83] wire pma_checker__stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire pma_checker__bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire pma_checker__gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire pma_checker__tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire pma_checker__tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56] wire pma_checker__tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67] wire pma_checker_state_vec_0_set_left_older = 1'h1; // @[Replacement.scala:196:33] wire pma_checker_state_vec_0_set_left_older_1 = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_vec_0_T_3 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_7 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_8 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker_state_vec_0_set_left_older_2 = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_vec_0_T_14 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_18 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_19 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker_state_reg_set_left_older = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_reg_T_2 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_reg_T_6 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_reg_T_7 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker__io_req_ready_T = 1'h1; // @[TLB.scala:631:25] wire pma_checker__io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire pma_checker__io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire pma_checker__r_superpage_repl_addr_T_6 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_7 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_8 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_9 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_12 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_13 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_14 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_15 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_16 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_17 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_18 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_19 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_13 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_13 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__ignore_T_14 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_14 = 1'h1; // @[TLB.scala:182:34] wire metaArb_io_in_0_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_0_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_1_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_2_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_3_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_4_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_out_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire dataArb_io_in_0_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_out_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire _dataArb_io_in_3_bits_wordMask_mask_upper_mask_T = 1'h1; // @[DCache.scala:248:76] wire _dataArb_io_in_3_bits_wordMask_mask_upper_mask_T_1 = 1'h1; // @[DCache.scala:248:52] wire _s2_valid_not_killed_T = 1'h1; // @[DCache.scala:338:48] wire _s2_flush_valid_T = 1'h1; // @[DCache.scala:363:54] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = 1'h1; // @[DCache.scala:397:74] wire _s2_valid_hit_pre_data_ecc_and_waw_T_1 = 1'h1; // @[DCache.scala:418:108] wire _s2_valid_hit_pre_data_ecc_T = 1'h1; // @[DCache.scala:420:73] wire _s2_valid_hit_pre_data_ecc_T_1 = 1'h1; // @[DCache.scala:420:88] wire _s2_valid_hit_T = 1'h1; // @[DCache.scala:422:51] wire _s2_valid_miss_T_1 = 1'h1; // @[DCache.scala:423:58] wire _s2_victimize_T = 1'h1; // @[DCache.scala:429:43] wire _r_T_117 = 1'h1; // @[Metadata.scala:140:24] wire _s2_dont_nack_misc_T = 1'h1; // @[DCache.scala:441:46] wire _s2_dont_nack_misc_T_4 = 1'h1; // @[DCache.scala:442:57] wire _metaArb_io_in_2_bits_write_T = 1'h1; // @[DCache.scala:463:34] wire _s2_valid_correct_T_1 = 1'h1; // @[DCache.scala:489:77] wire _pstore1_merge_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_opportunistic_T_61 = 1'h1; // @[DCache.scala:502:95] wire _pstore1_valid_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_T = 1'h1; // @[DCache.scala:516:5] wire _pstore_drain_T_3 = 1'h1; // @[DCache.scala:506:87] wire _pstore1_held_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore1_held_T_5 = 1'h1; // @[DCache.scala:521:38] wire _dataArb_io_in_0_valid_T = 1'h1; // @[DCache.scala:516:5] wire _dataArb_io_in_0_valid_T_3 = 1'h1; // @[DCache.scala:506:87] wire _io_cpu_s2_nack_cause_raw_T = 1'h1; // @[DCache.scala:574:59] wire _io_cpu_s2_nack_cause_raw_T_1 = 1'h1; // @[DCache.scala:574:74] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_41 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_42 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_43 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_44 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_59 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_100 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_101 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_102 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_103 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_118 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_119 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_120 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_121 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_159 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_160 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_161 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_177 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_178 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_179 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_180 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_220 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_221 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_236 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_237 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_238 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_239 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_277 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_278 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_279 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_280 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_295 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_296 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_297 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_298 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_336 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_337 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_338 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_339 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_354 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_355 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_356 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_357 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_395 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_396 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_397 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_398 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_413 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_414 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_415 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_416 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_454 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_455 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_456 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_457 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_472 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_473 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_474 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_475 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_513 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_514 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_515 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_516 = 1'h1; // @[Parameters.scala:684:29] wire _tl_out_a_valid_T = 1'h1; // @[DCache.scala:603:21] wire _tl_out_a_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _tl_out_a_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire tl_out_a_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire tl_out_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire tl_out_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire tl_out_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _nodeOut_c_bits_legal_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_16 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_17 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _nodeOut_c_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_39 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_50 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_51 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_53 = 1'h1; // @[Parameters.scala:91:44] wire _nodeOut_c_bits_legal_T_54 = 1'h1; // @[Parameters.scala:684:29] wire _io_cpu_resp_valid_T_1 = 1'h1; // @[DCache.scala:949:73] wire _io_cpu_replay_next_T_2 = 1'h1; // @[DCache.scala:950:65] wire _clock_en_reg_T = 1'h1; // @[DCache.scala:1060:19] wire _clock_en_reg_T_2 = 1'h1; // @[DCache.scala:1060:44] wire _clock_en_reg_T_3 = 1'h1; // @[DCache.scala:1061:46] wire _clock_en_reg_T_4 = 1'h1; // @[DCache.scala:1062:31] wire _clock_en_reg_T_5 = 1'h1; // @[DCache.scala:1063:26] wire _clock_en_reg_T_6 = 1'h1; // @[DCache.scala:1064:14] wire _clock_en_reg_T_7 = 1'h1; // @[DCache.scala:1064:26] wire _clock_en_reg_T_8 = 1'h1; // @[DCache.scala:1065:14] wire _clock_en_reg_T_9 = 1'h1; // @[DCache.scala:1065:26] wire _clock_en_reg_T_10 = 1'h1; // @[DCache.scala:1066:27] wire _clock_en_reg_T_11 = 1'h1; // @[DCache.scala:1067:22] wire _clock_en_reg_T_12 = 1'h1; // @[DCache.scala:1067:42] wire _clock_en_reg_T_13 = 1'h1; // @[DCache.scala:1068:18] wire _clock_en_reg_T_15 = 1'h1; // @[DCache.scala:1068:35] wire _clock_en_reg_T_16 = 1'h1; // @[DCache.scala:1069:31] wire _clock_en_reg_T_18 = 1'h1; // @[DCache.scala:1070:22] wire _clock_en_reg_T_20 = 1'h1; // @[DCache.scala:1070:46] wire _clock_en_reg_T_21 = 1'h1; // @[DCache.scala:1071:23] wire _clock_en_reg_T_23 = 1'h1; // @[DCache.scala:1072:23] wire _clock_en_reg_T_25 = 1'h1; // @[DCache.scala:1072:54] wire _clock_en_reg_T_27 = 1'h1; // @[DCache.scala:1073:21] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = 1'h1; // @[DCache.scala:1082:31] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = 1'h1; // @[DCache.scala:1087:31] wire _io_cpu_perf_canAcceptStoreThenLoad_T_3 = 1'h1; // @[DCache.scala:1089:72] wire _io_cpu_perf_canAcceptLoadThenLoad_T_56 = 1'h1; // @[DCache.scala:1092:115] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] pma_checker_io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_satp_asid = 16'h0; // @[TLB.scala:373:17] wire [15:0] _atomics_WIRE_mask = 16'h0; // @[DCache.scala:587:51] wire [15:0] _atomics_WIRE_1_mask = 16'h0; // @[DCache.scala:587:38] wire [15:0] probe_bits_res_mask = 16'h0; // @[DCache.scala:1202:19] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] pma_checker_io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_satp_mode = 4'h0; // @[TLB.scala:373:17] wire [3:0] pma_checker_real_hits_hi_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_lo = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi_1 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] pma_checker_lo_1 = 4'h0; // @[OneHot.scala:31:18] wire [3:0] pma_checker__multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39] wire [3:0] pma_checker_r_superpage_repl_addr_valids = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_repl_addr_valids_lo = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_repl_addr_valids_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_hit_bits_lo = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_r_sectored_hit_bits_hi = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_r_sectored_hit_bits_hi_1 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] pma_checker_r_sectored_hit_bits_lo_1 = 4'h0; // @[OneHot.scala:31:18] wire [3:0] pma_checker__r_sectored_hit_bits_T_2 = 4'h0; // @[OneHot.scala:32:28] wire [3:0] pma_checker__r_superpage_hit_bits_T = 4'h0; // @[OneHot.scala:21:45] wire [3:0] s2_meta_correctable_errors_lo = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_correctable_errors_hi = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_uncorrectable_errors_lo = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_uncorrectable_errors_hi = 4'h0; // @[package.scala:45:27] wire [3:0] _r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_63 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_127 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _atomics_WIRE_size = 4'h0; // @[DCache.scala:587:51] wire [3:0] _atomics_WIRE_1_size = 4'h0; // @[DCache.scala:587:38] wire [3:0] _metaArb_io_in_3_bits_data_T_5 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] probe_bits_res_size = 4'h0; // @[DCache.scala:1202:19] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] pma_checker_io_ptw_resp_bits_pte_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_satp_ppn = 44'h0; // @[TLB.scala:373:17] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[DCache.scala:101:7] wire [22:0] pma_checker_io_ptw_status_zero2 = 23'h0; // @[DCache.scala:120:32] wire [22:0] pma_checker_io_ptw_gstatus_zero2 = 23'h0; // @[DCache.scala:120:32] wire [1:0] io_ptw_status_xs = 2'h3; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[DCache.scala:101:7] wire [1:0] dataArb_io_in_1_bits_wordMask = 2'h3; // @[DCache.scala:152:28] wire [1:0] dataArb_io_in_2_bits_wordMask = 2'h3; // @[DCache.scala:152:28] wire [1:0] _s2_data_word_en_T = 2'h3; // @[DCache.scala:367:40] wire [1:0] _r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] tl_out_a_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _dataArb_io_in_1_bits_wordMask_T = 2'h3; // @[DCache.scala:731:39] wire [1:0] _metaArb_io_in_3_bits_data_T_8 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dataArb_io_in_2_bits_wordMask_T = 2'h3; // @[DCache.scala:904:37] wire [1:0] io_ptw_status_vs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_size = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_prv = 2'h0; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_resp_bits_level = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__special_entry_level_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_special_entry_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_waddr = 2'h0; // @[TLB.scala:477:22] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_1 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_2 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_3 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_4 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_5 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_6 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_7 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker__pr_array_T = 2'h0; // @[TLB.scala:529:26] wire [1:0] pma_checker__pw_array_T = 2'h0; // @[TLB.scala:531:26] wire [1:0] pma_checker__px_array_T = 2'h0; // @[TLB.scala:533:26] wire [1:0] pma_checker_lo_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_lo_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_2 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_lo_2 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__state_vec_0_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker__state_vec_0_T_11 = 2'h0; // @[Replacement.scala:207:62] wire [1:0] pma_checker_lo_3 = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_3 = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_4 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_lo_4 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker_state_reg_touch_way_sized = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker__multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37] wire [1:0] pma_checker__multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__r_superpage_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker_r_superpage_repl_addr_valids_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_superpage_repl_addr_valids_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__r_superpage_repl_addr_T_12 = 2'h0; // @[Mux.scala:50:70] wire [1:0] pma_checker__r_superpage_repl_addr_T_13 = 2'h0; // @[TLB.scala:757:8] wire [1:0] pma_checker__r_sectored_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker__r_sectored_repl_addr_T_7 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker__r_sectored_repl_addr_T_8 = 2'h0; // @[Replacement.scala:250:16] wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_hit_bits_lo_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_lo_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_2 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_r_sectored_hit_bits_lo_2 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__r_sectored_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:28] wire [1:0] pma_checker__r_sectored_hit_bits_T_6 = 2'h0; // @[OneHot.scala:32:10] wire [1:0] pma_checker_r_superpage_hit_bits_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_superpage_hit_bits_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_superpage_hit_bits_hi_1 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_r_superpage_hit_bits_lo_1 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__r_superpage_hit_bits_T_2 = 2'h0; // @[OneHot.scala:32:28] wire [1:0] pma_checker__r_superpage_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:10] wire [1:0] s1_meta_hit_state_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _s2_valid_no_xcpt_T_1 = 2'h0; // @[DCache.scala:332:54] wire [1:0] s2_meta_correctable_errors_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] _r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_75 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_79 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_83 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_87 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_91 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_139 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_143 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_147 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_151 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_155 = 2'h0; // @[Misc.scala:38:63] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _metaArb_io_in_3_bits_data_T_2 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _metaArb_io_in_3_bits_data_T_4 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] probe_bits_res_param = 2'h0; // @[DCache.scala:1202:19] wire [1:0] _nodeOut_c_bits_legal_T_2 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _nodeOut_c_bits_legal_T_36 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _io_cpu_s2_xcpt_WIRE_size = 2'h0; // @[DCache.scala:933:74] wire [1:0] metaArb_io_in_0_bits_data_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] metaArb_io_in_0_bits_data_meta_1_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:101:7] wire [29:0] pma_checker_io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_0_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_1_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_2_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_3_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_4_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_5_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_6_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_7_addr = 30'h0; // @[DCache.scala:120:32] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:101:7] wire [8:0] pma_checker_io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:120:32] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:101:7] wire [5:0] pma_checker_io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:120:32] wire [5:0] pma_checker_real_hits_lo = 6'h0; // @[package.scala:45:27] wire [5:0] pma_checker_special_entry_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker__multipleHits_T = 6'h0; // @[Misc.scala:181:37] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_req_bits_cmd = 5'h0; // @[DCache.scala:101:7] wire [4:0] pma_checker_io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:120:32] wire [4:0] _io_cpu_s2_xcpt_WIRE_cmd = 5'h0; // @[DCache.scala:933:74] wire [7:0] pma_checker__r_sectored_repl_addr_T_11 = 8'hFF; // @[TLB.scala:757:43] wire [7:0] metaArb_io_in_0_bits_way_en = 8'hFF; // @[DCache.scala:135:28] wire [7:0] dataArb_io_in_1_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_2_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_2_bits_way_en = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_way_en = 8'hFF; // @[DCache.scala:152:28] wire [7:0] _dataArb_io_in_3_bits_eccMask_T = 8'hFF; // @[DCache.scala:256:36] wire [7:0] _dataArb_io_in_3_bits_way_en_T = 8'hFF; // @[DCache.scala:257:35] wire [7:0] tl_out_a_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] tl_out_a_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] _dataArb_io_in_1_bits_eccMask_T = 8'hFF; // @[DCache.scala:732:38] wire [7:0] _dataArb_io_in_2_bits_eccMask_T = 8'hFF; // @[DCache.scala:905:36] wire [7:0] _dataArb_io_in_2_bits_way_en_T = 8'hFF; // @[DCache.scala:906:35] wire [7:0] _metaArb_io_in_0_bits_way_en_T = 8'hFF; // @[DCache.scala:1049:35] wire [2:0] pma_checker__r_sectored_repl_addr_T_20 = 3'h6; // @[Mux.scala:50:70] wire [2:0] tl_out_a_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] nodeOut_c_bits_c_opcode = 3'h6; // @[Edges.scala:380:17] wire [2:0] pma_checker_real_hits_lo_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_lo_hi = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_hi_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_special_entry_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_waddr_1 = 3'h0; // @[TLB.scala:485:22] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_state_vec_0_touch_way_sized = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38] wire [2:0] pma_checker__state_vec_0_T_10 = 3'h0; // @[Replacement.scala:203:16] wire [2:0] pma_checker__multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker__multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39] wire [2:0] pma_checker__multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker_r_sectored_repl_addr_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_r_sectored_repl_addr_right_subtree_state = 3'h0; // @[Replacement.scala:245:38] wire [2:0] pma_checker__r_sectored_repl_addr_T_9 = 3'h0; // @[Replacement.scala:249:12] wire [2:0] pma_checker__r_sectored_repl_addr_T_26 = 3'h0; // @[Mux.scala:50:70] wire [2:0] pma_checker__r_sectored_repl_addr_T_27 = 3'h0; // @[TLB.scala:757:8] wire [2:0] pma_checker__r_sectored_hit_bits_T_7 = 3'h0; // @[OneHot.scala:32:10] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] putpartial_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_param = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_1_opcode = 3'h0; // @[DCache.scala:587:38] wire [2:0] _atomics_WIRE_1_param = 3'h0; // @[DCache.scala:587:38] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] probe_bits_res_opcode = 3'h0; // @[DCache.scala:1202:19] wire [2:0] pma_checker__state_vec_0_T_9 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__state_vec_0_T_20 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__state_vec_0_T_21 = 3'h5; // @[Replacement.scala:206:16] wire [2:0] pma_checker__state_reg_T_8 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__r_sectored_repl_addr_T_21 = 3'h5; // @[Mux.scala:50:70] wire [2:0] nackResponseMessage_param = 3'h5; // @[Edges.scala:416:17] wire [2:0] dirtyReleaseMessage_opcode = 3'h5; // @[Edges.scala:433:17] wire [2:0] pma_checker__r_sectored_repl_addr_T_22 = 3'h4; // @[Mux.scala:50:70] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [2:0] nackResponseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [2:0] cleanReleaseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [1:0] pma_checker__r_superpage_repl_addr_T_11 = 2'h1; // @[Mux.scala:50:70] wire [1:0] _r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _metaArb_io_in_3_bits_data_T_6 = 2'h1; // @[Metadata.scala:25:15] wire [3:0] pma_checker__r_superpage_repl_addr_T_5 = 4'hF; // @[TLB.scala:757:43] wire [3:0] _r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] tl_out_a_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] tl_out_a_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] tl_out_a_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] tl_out_a_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [1:0] io_ptw_status_sxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] pma_checker_state_vec_0_hi = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker_state_vec_0_hi_1 = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker_state_reg_hi = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker__r_superpage_repl_addr_T_10 = 2'h2; // @[Mux.scala:50:70] wire [1:0] pma_checker__state_T = 2'h2; // @[TLB.scala:704:45] wire [1:0] _r_T_118 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_120 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_122 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] tl_out_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [2:0] pma_checker__r_sectored_repl_addr_T_23 = 3'h3; // @[Mux.scala:50:70] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] pma_checker__r_sectored_repl_addr_T_24 = 3'h2; // @[Mux.scala:50:70] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] pma_checker_mpu_priv = 3'h1; // @[TLB.scala:415:27] wire [2:0] pma_checker__r_sectored_repl_addr_T_25 = 3'h1; // @[Mux.scala:50:70] wire [2:0] putpartial_opcode = 3'h1; // @[Edges.scala:500:17] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [3:0] pma_checker_state_vec_0_hi_2 = 4'h8; // @[Replacement.scala:202:12] wire [3:0] _r_T_71 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_135 = 4'h8; // @[Metadata.scala:133:10] wire [11:0] pma_checker__gpa_hits_hit_mask_T_2 = 12'h0; // @[TLB.scala:606:24] wire [11:0] pma_checker__io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47] wire [26:0] pma_checker_io_ptw_req_bits_bits_addr = 27'h0; // @[DCache.scala:120:32] wire [26:0] pma_checker__io_resp_gpa_page_T_2 = 27'h0; // @[TLB.scala:657:58] wire [6:0] pma_checker__state_vec_0_T_22 = 7'h45; // @[Replacement.scala:202:12] wire [38:0] pma_checker_io_sfence_bits_addr = 39'h0; // @[DCache.scala:120:32] wire [38:0] pma_checker_io_ptw_resp_bits_gpa_bits = 39'h0; // @[DCache.scala:120:32] wire [39:0] io_tlb_port_req_bits_vaddr = 40'h0; // @[DCache.scala:101:7] wire [39:0] _io_cpu_s2_xcpt_WIRE_gpa = 40'h0; // @[DCache.scala:933:74] wire [21:0] pma_checker_special_entry_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] metaArb_io_in_0_bits_data = 22'h0; // @[DCache.scala:135:28] wire [21:0] _metaArb_io_in_0_bits_data_T = 22'h0; // @[DCache.scala:1050:85] wire [19:0] pma_checker_refill_ppn = 20'h0; // @[TLB.scala:406:44] wire [19:0] pma_checker_newEntry_ppn = 20'h0; // @[TLB.scala:449:24] wire [19:0] pma_checker__ppn_T_42 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_43 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_44 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_45 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_46 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_47 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_48 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_49 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_50 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_51 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_52 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_53 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_54 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_56 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_57 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_58 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_59 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_60 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_61 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_62 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_63 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_64 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_65 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_66 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_67 = 20'h0; // @[Mux.scala:30:73] wire [19:0] metaArb_io_in_0_bits_data_meta_1_tag = 20'h0; // @[HellaCache.scala:305:20] wire [31:0] pma_checker_io_ptw_status_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_gstatus_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_0_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_1_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_2_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_3_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_4_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_5_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_6_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_7_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] _atomics_WIRE_address = 32'h0; // @[DCache.scala:587:51] wire [31:0] _atomics_WIRE_1_address = 32'h0; // @[DCache.scala:587:38] wire [31:0] nodeOut_c_bits_c_address = 32'h0; // @[Edges.scala:380:17] wire [31:0] nodeOut_c_bits_c_1_address = 32'h0; // @[Edges.scala:396:17] wire [31:0] _io_cpu_s2_xcpt_WIRE_paddr = 32'h0; // @[DCache.scala:933:74] wire [3:0] _r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_65 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_129 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] tl_out_a_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [3:0] _release_state_T_13 = 4'h6; // @[DCache.scala:820:27] wire [3:0] nodeOut_c_bits_c_size = 4'h6; // @[Edges.scala:380:17] wire [3:0] nodeOut_c_bits_c_1_size = 4'h6; // @[Edges.scala:396:17] wire [127:0] get_data = 128'h0; // @[Edges.scala:460:17] wire [127:0] _atomics_WIRE_data = 128'h0; // @[DCache.scala:587:51] wire [127:0] _atomics_WIRE_1_data = 128'h0; // @[DCache.scala:587:38] wire [127:0] tl_out_a_bits_a_data = 128'h0; // @[Edges.scala:346:17] wire [127:0] nackResponseMessage_data = 128'h0; // @[Edges.scala:416:17] wire [127:0] cleanReleaseMessage_data = 128'h0; // @[Edges.scala:416:17] wire [127:0] dirtyReleaseMessage_data = 128'h0; // @[Edges.scala:433:17] wire [127:0] probe_bits_res_data = 128'h0; // @[DCache.scala:1202:19] wire [127:0] nodeOut_c_bits_c_data = 128'h0; // @[Edges.scala:380:17] wire [127:0] nodeOut_c_bits_c_1_data = 128'h0; // @[Edges.scala:396:17] wire [2:0] nodeOut_c_bits_c_1_opcode = 3'h7; // @[Edges.scala:396:17] wire [32:0] _nodeOut_c_bits_legal_T_27 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_28 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_29 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_61 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_62 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_63 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_23 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_24 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_57 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_58 = 33'h8000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_c_bits_legal_T_22 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _nodeOut_c_bits_legal_T_56 = 29'h8000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_13 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_14 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_47 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_48 = 33'hC000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_c_bits_legal_T_12 = 29'hC000000; // @[Parameters.scala:137:41] wire [28:0] _nodeOut_c_bits_legal_T_46 = 29'hC000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_8 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_9 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_42 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_43 = 33'h10000; // @[Parameters.scala:137:46] wire [17:0] _nodeOut_c_bits_legal_T_7 = 18'h10000; // @[Parameters.scala:137:41] wire [17:0] _nodeOut_c_bits_legal_T_41 = 18'h10000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_4 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_37 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_38 = 33'h0; // @[Parameters.scala:137:46] wire [3:0] _r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _metaArb_io_in_3_bits_data_T_9 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_67 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_131 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _metaArb_io_in_3_bits_data_T_7 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_62 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_126 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _metaArb_io_in_3_bits_data_T_3 = 4'h1; // @[Metadata.scala:86:10] wire [8:0] _s1_data_way_T_1 = 9'h100; // @[DCache.scala:694:32] wire [15:0] tl_out_a_bits_a_mask = 16'hFFFF; // @[Edges.scala:346:17] wire [15:0] _tl_out_a_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10] wire [3:0] _r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_66 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_130 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] tl_out_a_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [3:0] _r_T_70 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_134 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_69 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_133 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_68 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_132 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_64 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_128 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_61 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_125 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_60 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_124 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [13:0] pma_checker__gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] pma_checker_gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] pma_checker__gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] pma_checker_gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] pma_checker__gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] pma_checker_gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] pma_checker_gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] pma_checker__io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] pma_checker__io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] pma_checker__io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [6:0] pma_checker_real_hits_hi = 7'h0; // @[package.scala:45:27] wire [6:0] pma_checker__state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [6:0] pma_checker__multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39] wire [12:0] pma_checker_real_hits = 13'h0; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] pma_checker_stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] pma_checker__r_array_T_2 = 13'h0; // @[TLB.scala:520:74] wire [12:0] pma_checker__hr_array_T_2 = 13'h0; // @[TLB.scala:524:60] wire [12:0] pma_checker__gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [12:0] pma_checker__tlb_hit_T = 13'h0; // @[TLB.scala:611:28] wire [12:0] pma_checker__stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:68] wire [12:0] pma_checker__stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:95] wire [12:0] pma_checker_stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] pma_checker__hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] pma_checker__hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] pma_checker__hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] pma_checker__gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] pma_checker_gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] pma_checker__gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] pma_checker_gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [13:0] pma_checker_hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] pma_checker_hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] pma_checker_hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] pma_checker__must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] pma_checker__gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [30:0] pma_checker_special_entry_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_0_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_1_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_2_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_3_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_0_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_1_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_2_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_3_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_4_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_5_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_6_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_7_data_hi = 31'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_special_entry_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_0_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_1_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_2_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_3_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_0_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_1_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_2_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_3_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_4_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_5_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_6_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_7_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_special_entry_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [13:0] pma_checker_hits = 14'h2000; // @[TLB.scala:442:17] wire [9:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[DCache.scala:120:32] wire [31:0] _nodeOut_c_bits_legal_T_26 = 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _nodeOut_c_bits_legal_T_60 = 32'h80000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_11 = 28'hC000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_45 = 28'hC000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_21 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_55 = 28'h8000000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_c_bits_legal_T_6 = 17'h10000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_c_bits_legal_T_40 = 17'h10000; // @[Parameters.scala:137:31] wire [41:0] pma_checker__mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DCache.scala:101:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[DCache.scala:101:7] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[DCache.scala:101:7] wire [15:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[DCache.scala:101:7] wire [127:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[DCache.scala:101:7] wire nodeOut_c_ready = auto_out_c_ready_0; // @[DCache.scala:101:7] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DCache.scala:101:7] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DCache.scala:101:7] wire nodeOut_e_ready = auto_out_e_ready_0; // @[DCache.scala:101:7] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire metaArb_io_in_7_valid = io_cpu_req_valid_0; // @[DCache.scala:101:7, :135:28] wire [39:0] metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr_0; // @[DCache.scala:101:7, :135:28] wire [7:0] s0_req_tag = io_cpu_req_bits_tag_0; // @[DCache.scala:101:7, :192:24] wire [4:0] s0_req_cmd = io_cpu_req_bits_cmd_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_size = io_cpu_req_bits_size_0; // @[DCache.scala:101:7, :192:24] wire s0_req_signed = io_cpu_req_bits_signed_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_dprv = io_cpu_req_bits_dprv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_dv = io_cpu_req_bits_dv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_no_resp = io_cpu_req_bits_no_resp_0; // @[DCache.scala:101:7, :192:24] wire _io_cpu_s2_nack_T_5; // @[DCache.scala:445:86] wire _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:574:54] wire _io_cpu_s2_uncached_T_1; // @[DCache.scala:920:37] wire _io_cpu_resp_valid_T_2; // @[DCache.scala:949:70] wire [63:0] _io_cpu_resp_bits_data_T_24; // @[DCache.scala:974:41] wire s2_read; // @[Consts.scala:89:68] wire [63:0] _io_cpu_resp_bits_data_word_bypass_T_7; // @[AMOALU.scala:45:16] wire [63:0] s2_data_word; // @[DCache.scala:970:106] wire _io_cpu_replay_next_T_3; // @[DCache.scala:950:62] wire _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:933:24] wire _io_cpu_ordered_T_8; // @[DCache.scala:929:21] wire _io_cpu_store_pending_T_25; // @[DCache.scala:930:70] wire io_cpu_perf_acquire_done; // @[Edges.scala:233:22] wire io_cpu_perf_release_done; // @[Edges.scala:233:22] wire _io_cpu_perf_grant_T; // @[DCache.scala:1078:39] wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_T_1; // @[DCache.scala:1106:23] wire _io_cpu_perf_canAcceptStoreThenLoad_T_10; // @[DCache.scala:1088:41] wire _io_cpu_perf_canAcceptStoreThenRMW_T_1; // @[DCache.scala:1091:75] wire _io_cpu_perf_canAcceptLoadThenLoad_T_61; // @[DCache.scala:1092:40] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_7; // @[DCache.scala:1080:44] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_10; // @[DCache.scala:1084:45] wire _io_errors_bus_valid_T_2; // @[DCache.scala:1129:42] wire [2:0] auto_out_a_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_a_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_a_bits_size_0; // @[DCache.scala:101:7] wire auto_out_a_bits_source_0; // @[DCache.scala:101:7] wire [31:0] auto_out_a_bits_address_0; // @[DCache.scala:101:7] wire [15:0] auto_out_a_bits_mask_0; // @[DCache.scala:101:7] wire [127:0] auto_out_a_bits_data_0; // @[DCache.scala:101:7] wire auto_out_a_valid_0; // @[DCache.scala:101:7] wire auto_out_b_ready_0; // @[DCache.scala:101:7] wire [2:0] auto_out_c_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_c_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_c_bits_size_0; // @[DCache.scala:101:7] wire auto_out_c_bits_source_0; // @[DCache.scala:101:7] wire [31:0] auto_out_c_bits_address_0; // @[DCache.scala:101:7] wire [127:0] auto_out_c_bits_data_0; // @[DCache.scala:101:7] wire auto_out_c_valid_0; // @[DCache.scala:101:7] wire auto_out_d_ready_0; // @[DCache.scala:101:7] wire [3:0] auto_out_e_bits_sink_0; // @[DCache.scala:101:7] wire auto_out_e_valid_0; // @[DCache.scala:101:7] wire io_cpu_req_ready_0; // @[DCache.scala:101:7] wire [39:0] io_cpu_resp_bits_addr_0; // @[DCache.scala:101:7] wire [7:0] io_cpu_resp_bits_tag_0; // @[DCache.scala:101:7] wire [4:0] io_cpu_resp_bits_cmd_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_size_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_signed_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_dprv_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_dv_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_0; // @[DCache.scala:101:7] wire [7:0] io_cpu_resp_bits_mask_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_replay_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_has_data_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_word_bypass_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_raw_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_store_data_0; // @[DCache.scala:101:7] wire io_cpu_resp_valid_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_st_0; // @[DCache.scala:101:7] wire io_cpu_perf_acquire_0; // @[DCache.scala:101:7] wire io_cpu_perf_release_0; // @[DCache.scala:101:7] wire io_cpu_perf_grant_0; // @[DCache.scala:101:7] wire io_cpu_perf_tlbMiss_0; // @[DCache.scala:101:7] wire io_cpu_perf_blocked_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenRMW_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptLoadThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterStore_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_cause_raw_0; // @[DCache.scala:101:7] wire io_cpu_s2_uncached_0; // @[DCache.scala:101:7] wire [31:0] io_cpu_s2_paddr_0; // @[DCache.scala:101:7] wire io_cpu_replay_next_0; // @[DCache.scala:101:7] wire [39:0] io_cpu_s2_gpa_0; // @[DCache.scala:101:7] wire io_cpu_ordered_0; // @[DCache.scala:101:7] wire io_cpu_store_pending_0; // @[DCache.scala:101:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[DCache.scala:101:7] wire io_ptw_req_valid_0; // @[DCache.scala:101:7] wire io_errors_bus_valid; // @[DCache.scala:101:7] wire [31:0] io_errors_bus_bits; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_miss; // @[DCache.scala:101:7] wire [31:0] io_tlb_port_s1_resp_paddr; // @[DCache.scala:101:7] wire [39:0] io_tlb_port_s1_resp_gpa; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_cacheable; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_must_alloc; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_prefetchable; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_s1_resp_size; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_s1_resp_cmd; // @[DCache.scala:101:7] wire nodeOut_a_deq_ready = nodeOut_a_ready; // @[Decoupled.scala:356:21] wire nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DCache.scala:101:7] wire [3:0] nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DCache.scala:101:7] wire nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DCache.scala:101:7] wire [31:0] nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DCache.scala:101:7] wire [15:0] nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DCache.scala:101:7] wire [127:0] nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DCache.scala:101:7] wire _nodeOut_b_ready_T_4; // @[DCache.scala:770:44] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[DCache.scala:101:7] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[DCache.scala:101:7] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[DCache.scala:101:7] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[DCache.scala:101:7] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[DCache.scala:101:7] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[DCache.scala:101:7] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[DCache.scala:101:7] wire [127:0] s2_data_corrected; // @[package.scala:45:27] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[DCache.scala:101:7] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DCache.scala:101:7] wire uncachedRespIdxOH_shiftAmount = nodeOut_d_bits_source; // @[OneHot.scala:64:49] wire [3:0] nodeOut_e_bits_e_sink = nodeOut_d_bits_sink; // @[Edges.scala:451:17] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[DCache.scala:101:7] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_resp_size = pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [4:0] pma_checker_io_resp_cmd = pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [31:0] pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] wire pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire [39:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_v; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_st; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_resp_paddr; // @[DCache.scala:120:32] wire [39:0] pma_checker_io_resp_gpa; // @[DCache.scala:120:32] wire pma_checker_io_resp_cacheable; // @[DCache.scala:120:32] wire pma_checker_io_resp_must_alloc; // @[DCache.scala:120:32] wire pma_checker_io_resp_prefetchable; // @[DCache.scala:120:32] wire [26:0] pma_checker_vpn = pma_checker_io_req_bits_vaddr[38:12]; // @[TLB.scala:335:30] wire [26:0] pma_checker__mpu_ppn_T_24 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__mpu_ppn_T_28 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__sector_hits_T_3 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_11 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_19 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_27 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_35 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_43 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_51 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_59 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__superpage_hits_T = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_5 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_10 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_14 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_19 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_24 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_28 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_33 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_38 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_42 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_47 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_52 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_6 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_12 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_18 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_24 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_30 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_36 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_42 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_48 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_53 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_58 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_63 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_68 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_73 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_78 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_83 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_88 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_93 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_98 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_103 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_108 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_113 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_118 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__ppn_T_5 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_13 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_21 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_29 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_33 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_37 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire pma_checker_priv_s = pma_checker_io_req_bits_prv[0]; // @[TLB.scala:370:20] wire pma_checker_priv_uses_vm = ~(pma_checker_io_req_bits_prv[1]); // @[TLB.scala:372:27] wire [19:0] pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_1 = pma_checker__mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_fragmented_superpage = pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_2 = pma_checker__mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_c = pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_3 = pma_checker__mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_eff = pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_4 = pma_checker__mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_paa = pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_5 = pma_checker__mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pal = pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_6 = pma_checker__mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ppp = pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_7 = pma_checker__mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pr = pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_8 = pma_checker__mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_px = pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_9 = pma_checker__mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pw = pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_10 = pma_checker__mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hr = pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_11 = pma_checker__mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hx = pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_12 = pma_checker__mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hw = pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_13 = pma_checker__mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sr = pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_14 = pma_checker__mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sx = pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_15 = pma_checker__mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sw = pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_16 = pma_checker__mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_gf = pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_17 = pma_checker__mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pf = pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_18 = pma_checker__mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_stage2 = pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_19 = pma_checker__mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_final = pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_20 = pma_checker__mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_ptw = pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_21 = pma_checker__mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_g = pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_22 = pma_checker__mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_u = pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_23 = pma_checker__mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__mpu_ppn_WIRE_ppn = pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] pma_checker_mpu_ppn_res = _pma_checker_mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire [26:0] pma_checker__mpu_ppn_T_25 = {pma_checker__mpu_ppn_T_24[26:20], pma_checker__mpu_ppn_T_24[19:0] \| _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__mpu_ppn_T_26 = pma_checker__mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__mpu_ppn_T_27 = {pma_checker_mpu_ppn_res, pma_checker__mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__mpu_ppn_T_29 = {pma_checker__mpu_ppn_T_28[26:20], pma_checker__mpu_ppn_T_28[19:0] \| _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__mpu_ppn_T_30 = pma_checker__mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__mpu_ppn_T_31 = {pma_checker__mpu_ppn_T_27, pma_checker__mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] pma_checker__mpu_ppn_T_32 = pma_checker_io_req_bits_vaddr[39:12]; // @[TLB.scala:413:146] wire [27:0] pma_checker__mpu_ppn_T_33 = pma_checker__mpu_ppn_T_32; // @[TLB.scala:413:{20,146}] wire [27:0] pma_checker_mpu_ppn = pma_checker__mpu_ppn_T_33; // @[TLB.scala:412:20, :413:20] wire [11:0] pma_checker__mpu_physaddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52] wire [11:0] pma_checker__io_resp_paddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :652:46] wire [11:0] pma_checker__io_resp_gpa_offset_T_1 = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :658:82] wire [39:0] pma_checker_mpu_physaddr = {pma_checker_mpu_ppn, pma_checker__mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] pma_checker__homogeneous_T = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_67 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] pma_checker__deny_access_to_debug_T_1 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [2:0] pma_checker__mpu_priv_T_2 = {1'h0, pma_checker_io_req_bits_prv}; // @[TLB.scala:415:103] wire pma_checker_cacheable; // @[TLB.scala:425:41] wire pma_checker_newEntry_c = pma_checker_cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] pma_checker__homogeneous_T_1 = {1'h0, pma_checker__homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_2 = pma_checker__homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_3 = pma_checker__homogeneous_T_2; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_4 = pma_checker__homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_50 = pma_checker__homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN = {pma_checker_mpu_physaddr[39:14], pma_checker_mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_5; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_72; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_72 = _GEN; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_6 = {1'h0, pma_checker__homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_7 = pma_checker__homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_8 = pma_checker__homogeneous_T_7; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_9 = pma_checker__homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {pma_checker_mpu_physaddr[39:17], pma_checker_mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_10; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_60; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_60 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_77; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_77 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_109; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_109 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_116; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_116 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_11 = {1'h0, pma_checker__homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_12 = pma_checker__homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_13 = pma_checker__homogeneous_T_12; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_14 = pma_checker__homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_15 = {pma_checker_mpu_physaddr[39:21], pma_checker_mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_16 = {1'h0, pma_checker__homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_17 = pma_checker__homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_18 = pma_checker__homogeneous_T_17; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_19 = pma_checker__homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_20 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_21 = {1'h0, pma_checker__homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_22 = pma_checker__homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_23 = pma_checker__homogeneous_T_22; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_24 = pma_checker__homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_25 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_26 = {1'h0, pma_checker__homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_27 = pma_checker__homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_28 = pma_checker__homogeneous_T_27; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_29 = pma_checker__homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_30; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_30 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_82; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_82 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_97; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_97 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_31 = {1'h0, pma_checker__homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_32 = pma_checker__homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_33 = pma_checker__homogeneous_T_32; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_34 = pma_checker__homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_35 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_36 = {1'h0, pma_checker__homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_37 = pma_checker__homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_38 = pma_checker__homogeneous_T_37; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_39 = pma_checker__homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_40 = {pma_checker_mpu_physaddr[39:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_41 = {1'h0, pma_checker__homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_42 = pma_checker__homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_43 = pma_checker__homogeneous_T_42; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_44 = pma_checker__homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {pma_checker_mpu_physaddr[39:32], pma_checker_mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] pma_checker__homogeneous_T_45; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_45 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_87; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_87 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_102; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_102 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_46 = {1'h0, pma_checker__homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_47 = pma_checker__homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_48 = pma_checker__homogeneous_T_47; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_49 = pma_checker__homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_51 = pma_checker__homogeneous_T_50 \| pma_checker__homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_52 = pma_checker__homogeneous_T_51 \| pma_checker__homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_53 = pma_checker__homogeneous_T_52 \| pma_checker__homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_54 = pma_checker__homogeneous_T_53 \| pma_checker__homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_55 = pma_checker__homogeneous_T_54 \| pma_checker__homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_56 = pma_checker__homogeneous_T_55 \| pma_checker__homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_57 = pma_checker__homogeneous_T_56 \| pma_checker__homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_58 = pma_checker__homogeneous_T_57 \| pma_checker__homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire pma_checker_homogeneous = pma_checker__homogeneous_T_58 \| pma_checker__homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] pma_checker__homogeneous_T_61 = {1'h0, pma_checker__homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_62 = pma_checker__homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_63 = pma_checker__homogeneous_T_62; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_64 = pma_checker__homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_65 = pma_checker__homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_66 = ~pma_checker__homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__homogeneous_T_68 = {1'h0, pma_checker__homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_69 = pma_checker__homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_70 = pma_checker__homogeneous_T_69; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_71 = pma_checker__homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_92 = pma_checker__homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_73 = {1'h0, pma_checker__homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_74 = pma_checker__homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_75 = pma_checker__homogeneous_T_74; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_76 = pma_checker__homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_78 = {1'h0, pma_checker__homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_79 = pma_checker__homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_80 = pma_checker__homogeneous_T_79; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_81 = pma_checker__homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_83 = {1'h0, pma_checker__homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_84 = pma_checker__homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_85 = pma_checker__homogeneous_T_84; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_86 = pma_checker__homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_88 = {1'h0, pma_checker__homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_89 = pma_checker__homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_90 = pma_checker__homogeneous_T_89; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_91 = pma_checker__homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_93 = pma_checker__homogeneous_T_92 \| pma_checker__homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_94 = pma_checker__homogeneous_T_93 \| pma_checker__homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_95 = pma_checker__homogeneous_T_94 \| pma_checker__homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_96 = pma_checker__homogeneous_T_95 \| pma_checker__homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_98 = {1'h0, pma_checker__homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_99 = pma_checker__homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_100 = pma_checker__homogeneous_T_99; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_101 = pma_checker__homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_107 = pma_checker__homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_103 = {1'h0, pma_checker__homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_104 = pma_checker__homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_105 = pma_checker__homogeneous_T_104; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_106 = pma_checker__homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_108 = pma_checker__homogeneous_T_107 \| pma_checker__homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_110 = {1'h0, pma_checker__homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_111 = pma_checker__homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_112 = pma_checker__homogeneous_T_111; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_113 = pma_checker__homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_114 = pma_checker__homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_115 = ~pma_checker__homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__homogeneous_T_117 = {1'h0, pma_checker__homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_118 = pma_checker__homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_119 = pma_checker__homogeneous_T_118; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_120 = pma_checker__homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_121 = pma_checker__homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_122 = ~pma_checker__homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__deny_access_to_debug_T_2 = {1'h0, pma_checker__deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__deny_access_to_debug_T_3 = pma_checker__deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__deny_access_to_debug_T_4 = pma_checker__deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire pma_checker__deny_access_to_debug_T_5 = pma_checker__deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker_deny_access_to_debug = pma_checker__deny_access_to_debug_T_5; // @[TLB.scala:428:50] wire pma_checker__prot_r_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire pma_checker__prot_r_T_1 = _pma_checker_pma_io_resp_r & pma_checker__prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire pma_checker__prot_w_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire pma_checker__prot_w_T_1 = _pma_checker_pma_io_resp_w & pma_checker__prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire pma_checker__prot_x_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire pma_checker__prot_x_T_1 = _pma_checker_pma_io_resp_x & pma_checker__prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire [24:0] pma_checker__sector_hits_T_4 = pma_checker__sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_5 = pma_checker__sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_7 = pma_checker__sector_hits_T_5 & pma_checker__sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_12 = pma_checker__sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_13 = pma_checker__sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_15 = pma_checker__sector_hits_T_13 & pma_checker__sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_20 = pma_checker__sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_21 = pma_checker__sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_23 = pma_checker__sector_hits_T_21 & pma_checker__sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_28 = pma_checker__sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_29 = pma_checker__sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_31 = pma_checker__sector_hits_T_29 & pma_checker__sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_36 = pma_checker__sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_37 = pma_checker__sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_39 = pma_checker__sector_hits_T_37 & pma_checker__sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_44 = pma_checker__sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_45 = pma_checker__sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_47 = pma_checker__sector_hits_T_45 & pma_checker__sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_52 = pma_checker__sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_53 = pma_checker__sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_55 = pma_checker__sector_hits_T_53 & pma_checker__sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_60 = pma_checker__sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_61 = pma_checker__sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_63 = pma_checker__sector_hits_T_61 & pma_checker__sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire [8:0] pma_checker__superpage_hits_T_1 = pma_checker__superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_2 = pma_checker__superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_3 = pma_checker__superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_1 = pma_checker__superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_6 = pma_checker__superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_7 = pma_checker__superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_8 = pma_checker_superpage_hits_ignore_1 \| pma_checker__superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_11 = pma_checker__superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_12 = pma_checker__superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_15 = pma_checker__superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_16 = pma_checker__superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_17 = pma_checker__superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_4 = pma_checker__superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_20 = pma_checker__superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_21 = pma_checker__superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_22 = pma_checker_superpage_hits_ignore_4 \| pma_checker__superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_25 = pma_checker__superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_26 = pma_checker__superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_29 = pma_checker__superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_30 = pma_checker__superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_31 = pma_checker__superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_7 = pma_checker__superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_34 = pma_checker__superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_35 = pma_checker__superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_36 = pma_checker_superpage_hits_ignore_7 \| pma_checker__superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_39 = pma_checker__superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_40 = pma_checker__superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_43 = pma_checker__superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_44 = pma_checker__superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_45 = pma_checker__superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_10 = pma_checker__superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_48 = pma_checker__superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_49 = pma_checker__superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_50 = pma_checker_superpage_hits_ignore_10 \| pma_checker__superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_53 = pma_checker__superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_54 = pma_checker__superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] pma_checker_hitsVec_idx = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_1 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_2 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_3 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_4 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_5 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_6 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_7 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_24 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_48 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_72 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_96 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_120 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_144 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_168 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [24:0] pma_checker__hitsVec_T_1 = pma_checker__hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_2 = pma_checker__hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_4 = pma_checker__hitsVec_T_2 & pma_checker__hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_7 = pma_checker__hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_8 = pma_checker__hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_10 = pma_checker__hitsVec_T_8 & pma_checker__hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_13 = pma_checker__hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_14 = pma_checker__hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_16 = pma_checker__hitsVec_T_14 & pma_checker__hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_19 = pma_checker__hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_20 = pma_checker__hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_22 = pma_checker__hitsVec_T_20 & pma_checker__hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_25 = pma_checker__hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_26 = pma_checker__hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_28 = pma_checker__hitsVec_T_26 & pma_checker__hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_31 = pma_checker__hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_32 = pma_checker__hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_34 = pma_checker__hitsVec_T_32 & pma_checker__hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_37 = pma_checker__hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_38 = pma_checker__hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_40 = pma_checker__hitsVec_T_38 & pma_checker__hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_43 = pma_checker__hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_44 = pma_checker__hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_46 = pma_checker__hitsVec_T_44 & pma_checker__hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [8:0] pma_checker__hitsVec_T_49 = pma_checker__hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_50 = pma_checker__hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_51 = pma_checker__hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_1 = pma_checker__hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_54 = pma_checker__hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_55 = pma_checker__hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_56 = pma_checker_hitsVec_ignore_1 \| pma_checker__hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_59 = pma_checker__hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_60 = pma_checker__hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_64 = pma_checker__hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_65 = pma_checker__hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_66 = pma_checker__hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_4 = pma_checker__hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_69 = pma_checker__hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_70 = pma_checker__hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_71 = pma_checker_hitsVec_ignore_4 \| pma_checker__hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_74 = pma_checker__hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_75 = pma_checker__hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_79 = pma_checker__hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_80 = pma_checker__hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_81 = pma_checker__hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_7 = pma_checker__hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_84 = pma_checker__hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_85 = pma_checker__hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_86 = pma_checker_hitsVec_ignore_7 \| pma_checker__hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_89 = pma_checker__hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_90 = pma_checker__hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_94 = pma_checker__hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_95 = pma_checker__hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_96 = pma_checker__hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_10 = pma_checker__hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_99 = pma_checker__hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_100 = pma_checker__hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_101 = pma_checker_hitsVec_ignore_10 \| pma_checker__hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_104 = pma_checker__hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_105 = pma_checker__hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_109 = pma_checker__hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_110 = pma_checker__hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_111 = pma_checker__hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire [8:0] pma_checker__hitsVec_T_114 = pma_checker__hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_115 = pma_checker__hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_119 = pma_checker__hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_120 = pma_checker__hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker_newEntry_ppp; // @[TLB.scala:449:24] wire pma_checker_newEntry_pal; // @[TLB.scala:449:24] wire pma_checker_newEntry_paa; // @[TLB.scala:449:24] wire pma_checker_newEntry_eff; // @[TLB.scala:449:24] wire [1:0] _GEN_3 = {pma_checker_newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] _GEN_4 = {pma_checker_newEntry_pal, pma_checker_newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_lo_lo_hi = {pma_checker_special_entry_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_special_entry_data_0_lo_lo = {pma_checker_special_entry_data_0_lo_lo_hi, pma_checker_special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] _GEN_5 = {2'h0, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] pma_checker_special_entry_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [5:0] pma_checker_special_entry_data_0_lo_hi = {3'h0, pma_checker_special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_special_entry_data_0_lo = {pma_checker_special_entry_data_0_lo_hi, pma_checker_special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__special_entry_data_0_T = {31'h0, pma_checker_special_entry_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_0_data_0_lo_lo = {pma_checker_superpage_entries_0_data_0_lo_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_0_data_0_lo = {pma_checker_superpage_entries_0_data_0_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_0_data_0_T = {31'h0, pma_checker_superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_1_data_0_lo_lo = {pma_checker_superpage_entries_1_data_0_lo_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_1_data_0_lo = {pma_checker_superpage_entries_1_data_0_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_1_data_0_T = {31'h0, pma_checker_superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_2_data_0_lo_lo = {pma_checker_superpage_entries_2_data_0_lo_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_2_data_0_lo = {pma_checker_superpage_entries_2_data_0_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_2_data_0_T = {31'h0, pma_checker_superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_3_data_0_lo_lo = {pma_checker_superpage_entries_3_data_0_lo_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_3_data_0_lo = {pma_checker_superpage_entries_3_data_0_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_3_data_0_T = {31'h0, pma_checker_superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_0_data_lo_lo = {pma_checker_sectored_entries_0_0_data_lo_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_0_data_lo = {pma_checker_sectored_entries_0_0_data_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_0_data_T = {31'h0, pma_checker_sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_1_data_lo_lo = {pma_checker_sectored_entries_0_1_data_lo_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_1_data_lo = {pma_checker_sectored_entries_0_1_data_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_1_data_T = {31'h0, pma_checker_sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_2_data_lo_lo = {pma_checker_sectored_entries_0_2_data_lo_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_2_data_lo = {pma_checker_sectored_entries_0_2_data_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_2_data_T = {31'h0, pma_checker_sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_3_data_lo_lo = {pma_checker_sectored_entries_0_3_data_lo_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_3_data_lo = {pma_checker_sectored_entries_0_3_data_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_3_data_T = {31'h0, pma_checker_sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_4_data_lo_lo = {pma_checker_sectored_entries_0_4_data_lo_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_4_data_lo = {pma_checker_sectored_entries_0_4_data_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_4_data_T = {31'h0, pma_checker_sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_5_data_lo_lo = {pma_checker_sectored_entries_0_5_data_lo_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_5_data_lo = {pma_checker_sectored_entries_0_5_data_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_5_data_T = {31'h0, pma_checker_sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_6_data_lo_lo = {pma_checker_sectored_entries_0_6_data_lo_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_6_data_lo = {pma_checker_sectored_entries_0_6_data_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_6_data_T = {31'h0, pma_checker_sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_7_data_lo_lo = {pma_checker_sectored_entries_0_7_data_lo_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_7_data_lo = {pma_checker_sectored_entries_0_7_data_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_7_data_T = {31'h0, pma_checker_sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] pma_checker__entries_T_23; // @[TLB.scala:170:77] wire pma_checker__entries_T_22; // @[TLB.scala:170:77] wire pma_checker__entries_T_21; // @[TLB.scala:170:77] wire pma_checker__entries_T_20; // @[TLB.scala:170:77] wire pma_checker__entries_T_19; // @[TLB.scala:170:77] wire pma_checker__entries_T_18; // @[TLB.scala:170:77] wire pma_checker__entries_T_17; // @[TLB.scala:170:77] wire pma_checker__entries_T_16; // @[TLB.scala:170:77] wire pma_checker__entries_T_15; // @[TLB.scala:170:77] wire pma_checker__entries_T_14; // @[TLB.scala:170:77] wire pma_checker__entries_T_13; // @[TLB.scala:170:77] wire pma_checker__entries_T_12; // @[TLB.scala:170:77] wire pma_checker__entries_T_11; // @[TLB.scala:170:77] wire pma_checker__entries_T_10; // @[TLB.scala:170:77] wire pma_checker__entries_T_9; // @[TLB.scala:170:77] wire pma_checker__entries_T_8; // @[TLB.scala:170:77] wire pma_checker__entries_T_7; // @[TLB.scala:170:77] wire pma_checker__entries_T_6; // @[TLB.scala:170:77] wire pma_checker__entries_T_5; // @[TLB.scala:170:77] wire pma_checker__entries_T_4; // @[TLB.scala:170:77] wire pma_checker__entries_T_3; // @[TLB.scala:170:77] wire pma_checker__entries_T_2; // @[TLB.scala:170:77] wire pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_1 = pma_checker__entries_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_fragmented_superpage = pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_2 = pma_checker__entries_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_c = pma_checker__entries_T_2; // @[TLB.scala:170:77] assign pma_checker__entries_T_3 = pma_checker__entries_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_eff = pma_checker__entries_T_3; // @[TLB.scala:170:77] assign pma_checker__entries_T_4 = pma_checker__entries_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_paa = pma_checker__entries_T_4; // @[TLB.scala:170:77] assign pma_checker__entries_T_5 = pma_checker__entries_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pal = pma_checker__entries_T_5; // @[TLB.scala:170:77] assign pma_checker__entries_T_6 = pma_checker__entries_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ppp = pma_checker__entries_T_6; // @[TLB.scala:170:77] assign pma_checker__entries_T_7 = pma_checker__entries_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pr = pma_checker__entries_T_7; // @[TLB.scala:170:77] assign pma_checker__entries_T_8 = pma_checker__entries_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_px = pma_checker__entries_T_8; // @[TLB.scala:170:77] assign pma_checker__entries_T_9 = pma_checker__entries_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pw = pma_checker__entries_T_9; // @[TLB.scala:170:77] assign pma_checker__entries_T_10 = pma_checker__entries_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hr = pma_checker__entries_T_10; // @[TLB.scala:170:77] assign pma_checker__entries_T_11 = pma_checker__entries_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hx = pma_checker__entries_T_11; // @[TLB.scala:170:77] assign pma_checker__entries_T_12 = pma_checker__entries_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hw = pma_checker__entries_T_12; // @[TLB.scala:170:77] assign pma_checker__entries_T_13 = pma_checker__entries_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sr = pma_checker__entries_T_13; // @[TLB.scala:170:77] assign pma_checker__entries_T_14 = pma_checker__entries_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sx = pma_checker__entries_T_14; // @[TLB.scala:170:77] assign pma_checker__entries_T_15 = pma_checker__entries_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sw = pma_checker__entries_T_15; // @[TLB.scala:170:77] assign pma_checker__entries_T_16 = pma_checker__entries_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_gf = pma_checker__entries_T_16; // @[TLB.scala:170:77] assign pma_checker__entries_T_17 = pma_checker__entries_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pf = pma_checker__entries_T_17; // @[TLB.scala:170:77] assign pma_checker__entries_T_18 = pma_checker__entries_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_stage2 = pma_checker__entries_T_18; // @[TLB.scala:170:77] assign pma_checker__entries_T_19 = pma_checker__entries_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_final = pma_checker__entries_T_19; // @[TLB.scala:170:77] assign pma_checker__entries_T_20 = pma_checker__entries_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_ptw = pma_checker__entries_T_20; // @[TLB.scala:170:77] assign pma_checker__entries_T_21 = pma_checker__entries_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_g = pma_checker__entries_T_21; // @[TLB.scala:170:77] assign pma_checker__entries_T_22 = pma_checker__entries_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_u = pma_checker__entries_T_22; // @[TLB.scala:170:77] assign pma_checker__entries_T_23 = pma_checker__entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_ppn = pma_checker__entries_T_23; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_47; // @[TLB.scala:170:77] wire pma_checker__entries_T_46; // @[TLB.scala:170:77] wire pma_checker__entries_T_45; // @[TLB.scala:170:77] wire pma_checker__entries_T_44; // @[TLB.scala:170:77] wire pma_checker__entries_T_43; // @[TLB.scala:170:77] wire pma_checker__entries_T_42; // @[TLB.scala:170:77] wire pma_checker__entries_T_41; // @[TLB.scala:170:77] wire pma_checker__entries_T_40; // @[TLB.scala:170:77] wire pma_checker__entries_T_39; // @[TLB.scala:170:77] wire pma_checker__entries_T_38; // @[TLB.scala:170:77] wire pma_checker__entries_T_37; // @[TLB.scala:170:77] wire pma_checker__entries_T_36; // @[TLB.scala:170:77] wire pma_checker__entries_T_35; // @[TLB.scala:170:77] wire pma_checker__entries_T_34; // @[TLB.scala:170:77] wire pma_checker__entries_T_33; // @[TLB.scala:170:77] wire pma_checker__entries_T_32; // @[TLB.scala:170:77] wire pma_checker__entries_T_31; // @[TLB.scala:170:77] wire pma_checker__entries_T_30; // @[TLB.scala:170:77] wire pma_checker__entries_T_29; // @[TLB.scala:170:77] wire pma_checker__entries_T_28; // @[TLB.scala:170:77] wire pma_checker__entries_T_27; // @[TLB.scala:170:77] wire pma_checker__entries_T_26; // @[TLB.scala:170:77] wire pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_25 = pma_checker__entries_WIRE_3[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_fragmented_superpage = pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_26 = pma_checker__entries_WIRE_3[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_c = pma_checker__entries_T_26; // @[TLB.scala:170:77] assign pma_checker__entries_T_27 = pma_checker__entries_WIRE_3[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_eff = pma_checker__entries_T_27; // @[TLB.scala:170:77] assign pma_checker__entries_T_28 = pma_checker__entries_WIRE_3[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_paa = pma_checker__entries_T_28; // @[TLB.scala:170:77] assign pma_checker__entries_T_29 = pma_checker__entries_WIRE_3[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pal = pma_checker__entries_T_29; // @[TLB.scala:170:77] assign pma_checker__entries_T_30 = pma_checker__entries_WIRE_3[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ppp = pma_checker__entries_T_30; // @[TLB.scala:170:77] assign pma_checker__entries_T_31 = pma_checker__entries_WIRE_3[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pr = pma_checker__entries_T_31; // @[TLB.scala:170:77] assign pma_checker__entries_T_32 = pma_checker__entries_WIRE_3[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_px = pma_checker__entries_T_32; // @[TLB.scala:170:77] assign pma_checker__entries_T_33 = pma_checker__entries_WIRE_3[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pw = pma_checker__entries_T_33; // @[TLB.scala:170:77] assign pma_checker__entries_T_34 = pma_checker__entries_WIRE_3[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hr = pma_checker__entries_T_34; // @[TLB.scala:170:77] assign pma_checker__entries_T_35 = pma_checker__entries_WIRE_3[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hx = pma_checker__entries_T_35; // @[TLB.scala:170:77] assign pma_checker__entries_T_36 = pma_checker__entries_WIRE_3[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hw = pma_checker__entries_T_36; // @[TLB.scala:170:77] assign pma_checker__entries_T_37 = pma_checker__entries_WIRE_3[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sr = pma_checker__entries_T_37; // @[TLB.scala:170:77] assign pma_checker__entries_T_38 = pma_checker__entries_WIRE_3[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sx = pma_checker__entries_T_38; // @[TLB.scala:170:77] assign pma_checker__entries_T_39 = pma_checker__entries_WIRE_3[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sw = pma_checker__entries_T_39; // @[TLB.scala:170:77] assign pma_checker__entries_T_40 = pma_checker__entries_WIRE_3[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_gf = pma_checker__entries_T_40; // @[TLB.scala:170:77] assign pma_checker__entries_T_41 = pma_checker__entries_WIRE_3[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pf = pma_checker__entries_T_41; // @[TLB.scala:170:77] assign pma_checker__entries_T_42 = pma_checker__entries_WIRE_3[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_stage2 = pma_checker__entries_T_42; // @[TLB.scala:170:77] assign pma_checker__entries_T_43 = pma_checker__entries_WIRE_3[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_final = pma_checker__entries_T_43; // @[TLB.scala:170:77] assign pma_checker__entries_T_44 = pma_checker__entries_WIRE_3[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_ptw = pma_checker__entries_T_44; // @[TLB.scala:170:77] assign pma_checker__entries_T_45 = pma_checker__entries_WIRE_3[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_g = pma_checker__entries_T_45; // @[TLB.scala:170:77] assign pma_checker__entries_T_46 = pma_checker__entries_WIRE_3[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_u = pma_checker__entries_T_46; // @[TLB.scala:170:77] assign pma_checker__entries_T_47 = pma_checker__entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_2_ppn = pma_checker__entries_T_47; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_71; // @[TLB.scala:170:77] wire pma_checker__entries_T_70; // @[TLB.scala:170:77] wire pma_checker__entries_T_69; // @[TLB.scala:170:77] wire pma_checker__entries_T_68; // @[TLB.scala:170:77] wire pma_checker__entries_T_67; // @[TLB.scala:170:77] wire pma_checker__entries_T_66; // @[TLB.scala:170:77] wire pma_checker__entries_T_65; // @[TLB.scala:170:77] wire pma_checker__entries_T_64; // @[TLB.scala:170:77] wire pma_checker__entries_T_63; // @[TLB.scala:170:77] wire pma_checker__entries_T_62; // @[TLB.scala:170:77] wire pma_checker__entries_T_61; // @[TLB.scala:170:77] wire pma_checker__entries_T_60; // @[TLB.scala:170:77] wire pma_checker__entries_T_59; // @[TLB.scala:170:77] wire pma_checker__entries_T_58; // @[TLB.scala:170:77] wire pma_checker__entries_T_57; // @[TLB.scala:170:77] wire pma_checker__entries_T_56; // @[TLB.scala:170:77] wire pma_checker__entries_T_55; // @[TLB.scala:170:77] wire pma_checker__entries_T_54; // @[TLB.scala:170:77] wire pma_checker__entries_T_53; // @[TLB.scala:170:77] wire pma_checker__entries_T_52; // @[TLB.scala:170:77] wire pma_checker__entries_T_51; // @[TLB.scala:170:77] wire pma_checker__entries_T_50; // @[TLB.scala:170:77] wire pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_49 = pma_checker__entries_WIRE_5[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_fragmented_superpage = pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_50 = pma_checker__entries_WIRE_5[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_c = pma_checker__entries_T_50; // @[TLB.scala:170:77] assign pma_checker__entries_T_51 = pma_checker__entries_WIRE_5[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_eff = pma_checker__entries_T_51; // @[TLB.scala:170:77] assign pma_checker__entries_T_52 = pma_checker__entries_WIRE_5[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_paa = pma_checker__entries_T_52; // @[TLB.scala:170:77] assign pma_checker__entries_T_53 = pma_checker__entries_WIRE_5[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pal = pma_checker__entries_T_53; // @[TLB.scala:170:77] assign pma_checker__entries_T_54 = pma_checker__entries_WIRE_5[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ppp = pma_checker__entries_T_54; // @[TLB.scala:170:77] assign pma_checker__entries_T_55 = pma_checker__entries_WIRE_5[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pr = pma_checker__entries_T_55; // @[TLB.scala:170:77] assign pma_checker__entries_T_56 = pma_checker__entries_WIRE_5[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_px = pma_checker__entries_T_56; // @[TLB.scala:170:77] assign pma_checker__entries_T_57 = pma_checker__entries_WIRE_5[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pw = pma_checker__entries_T_57; // @[TLB.scala:170:77] assign pma_checker__entries_T_58 = pma_checker__entries_WIRE_5[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hr = pma_checker__entries_T_58; // @[TLB.scala:170:77] assign pma_checker__entries_T_59 = pma_checker__entries_WIRE_5[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hx = pma_checker__entries_T_59; // @[TLB.scala:170:77] assign pma_checker__entries_T_60 = pma_checker__entries_WIRE_5[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hw = pma_checker__entries_T_60; // @[TLB.scala:170:77] assign pma_checker__entries_T_61 = pma_checker__entries_WIRE_5[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sr = pma_checker__entries_T_61; // @[TLB.scala:170:77] assign pma_checker__entries_T_62 = pma_checker__entries_WIRE_5[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sx = pma_checker__entries_T_62; // @[TLB.scala:170:77] assign pma_checker__entries_T_63 = pma_checker__entries_WIRE_5[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sw = pma_checker__entries_T_63; // @[TLB.scala:170:77] assign pma_checker__entries_T_64 = pma_checker__entries_WIRE_5[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_gf = pma_checker__entries_T_64; // @[TLB.scala:170:77] assign pma_checker__entries_T_65 = pma_checker__entries_WIRE_5[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pf = pma_checker__entries_T_65; // @[TLB.scala:170:77] assign pma_checker__entries_T_66 = pma_checker__entries_WIRE_5[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_stage2 = pma_checker__entries_T_66; // @[TLB.scala:170:77] assign pma_checker__entries_T_67 = pma_checker__entries_WIRE_5[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_final = pma_checker__entries_T_67; // @[TLB.scala:170:77] assign pma_checker__entries_T_68 = pma_checker__entries_WIRE_5[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_ptw = pma_checker__entries_T_68; // @[TLB.scala:170:77] assign pma_checker__entries_T_69 = pma_checker__entries_WIRE_5[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_g = pma_checker__entries_T_69; // @[TLB.scala:170:77] assign pma_checker__entries_T_70 = pma_checker__entries_WIRE_5[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_u = pma_checker__entries_T_70; // @[TLB.scala:170:77] assign pma_checker__entries_T_71 = pma_checker__entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_4_ppn = pma_checker__entries_T_71; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_95; // @[TLB.scala:170:77] wire pma_checker__entries_T_94; // @[TLB.scala:170:77] wire pma_checker__entries_T_93; // @[TLB.scala:170:77] wire pma_checker__entries_T_92; // @[TLB.scala:170:77] wire pma_checker__entries_T_91; // @[TLB.scala:170:77] wire pma_checker__entries_T_90; // @[TLB.scala:170:77] wire pma_checker__entries_T_89; // @[TLB.scala:170:77] wire pma_checker__entries_T_88; // @[TLB.scala:170:77] wire pma_checker__entries_T_87; // @[TLB.scala:170:77] wire pma_checker__entries_T_86; // @[TLB.scala:170:77] wire pma_checker__entries_T_85; // @[TLB.scala:170:77] wire pma_checker__entries_T_84; // @[TLB.scala:170:77] wire pma_checker__entries_T_83; // @[TLB.scala:170:77] wire pma_checker__entries_T_82; // @[TLB.scala:170:77] wire pma_checker__entries_T_81; // @[TLB.scala:170:77] wire pma_checker__entries_T_80; // @[TLB.scala:170:77] wire pma_checker__entries_T_79; // @[TLB.scala:170:77] wire pma_checker__entries_T_78; // @[TLB.scala:170:77] wire pma_checker__entries_T_77; // @[TLB.scala:170:77] wire pma_checker__entries_T_76; // @[TLB.scala:170:77] wire pma_checker__entries_T_75; // @[TLB.scala:170:77] wire pma_checker__entries_T_74; // @[TLB.scala:170:77] wire pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_73 = pma_checker__entries_WIRE_7[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_fragmented_superpage = pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_74 = pma_checker__entries_WIRE_7[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_c = pma_checker__entries_T_74; // @[TLB.scala:170:77] assign pma_checker__entries_T_75 = pma_checker__entries_WIRE_7[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_eff = pma_checker__entries_T_75; // @[TLB.scala:170:77] assign pma_checker__entries_T_76 = pma_checker__entries_WIRE_7[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_paa = pma_checker__entries_T_76; // @[TLB.scala:170:77] assign pma_checker__entries_T_77 = pma_checker__entries_WIRE_7[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pal = pma_checker__entries_T_77; // @[TLB.scala:170:77] assign pma_checker__entries_T_78 = pma_checker__entries_WIRE_7[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ppp = pma_checker__entries_T_78; // @[TLB.scala:170:77] assign pma_checker__entries_T_79 = pma_checker__entries_WIRE_7[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pr = pma_checker__entries_T_79; // @[TLB.scala:170:77] assign pma_checker__entries_T_80 = pma_checker__entries_WIRE_7[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_px = pma_checker__entries_T_80; // @[TLB.scala:170:77] assign pma_checker__entries_T_81 = pma_checker__entries_WIRE_7[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pw = pma_checker__entries_T_81; // @[TLB.scala:170:77] assign pma_checker__entries_T_82 = pma_checker__entries_WIRE_7[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hr = pma_checker__entries_T_82; // @[TLB.scala:170:77] assign pma_checker__entries_T_83 = pma_checker__entries_WIRE_7[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hx = pma_checker__entries_T_83; // @[TLB.scala:170:77] assign pma_checker__entries_T_84 = pma_checker__entries_WIRE_7[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hw = pma_checker__entries_T_84; // @[TLB.scala:170:77] assign pma_checker__entries_T_85 = pma_checker__entries_WIRE_7[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sr = pma_checker__entries_T_85; // @[TLB.scala:170:77] assign pma_checker__entries_T_86 = pma_checker__entries_WIRE_7[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sx = pma_checker__entries_T_86; // @[TLB.scala:170:77] assign pma_checker__entries_T_87 = pma_checker__entries_WIRE_7[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sw = pma_checker__entries_T_87; // @[TLB.scala:170:77] assign pma_checker__entries_T_88 = pma_checker__entries_WIRE_7[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_gf = pma_checker__entries_T_88; // @[TLB.scala:170:77] assign pma_checker__entries_T_89 = pma_checker__entries_WIRE_7[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pf = pma_checker__entries_T_89; // @[TLB.scala:170:77] assign pma_checker__entries_T_90 = pma_checker__entries_WIRE_7[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_stage2 = pma_checker__entries_T_90; // @[TLB.scala:170:77] assign pma_checker__entries_T_91 = pma_checker__entries_WIRE_7[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_final = pma_checker__entries_T_91; // @[TLB.scala:170:77] assign pma_checker__entries_T_92 = pma_checker__entries_WIRE_7[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_ptw = pma_checker__entries_T_92; // @[TLB.scala:170:77] assign pma_checker__entries_T_93 = pma_checker__entries_WIRE_7[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_g = pma_checker__entries_T_93; // @[TLB.scala:170:77] assign pma_checker__entries_T_94 = pma_checker__entries_WIRE_7[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_u = pma_checker__entries_T_94; // @[TLB.scala:170:77] assign pma_checker__entries_T_95 = pma_checker__entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_6_ppn = pma_checker__entries_T_95; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_119; // @[TLB.scala:170:77] wire pma_checker__entries_T_118; // @[TLB.scala:170:77] wire pma_checker__entries_T_117; // @[TLB.scala:170:77] wire pma_checker__entries_T_116; // @[TLB.scala:170:77] wire pma_checker__entries_T_115; // @[TLB.scala:170:77] wire pma_checker__entries_T_114; // @[TLB.scala:170:77] wire pma_checker__entries_T_113; // @[TLB.scala:170:77] wire pma_checker__entries_T_112; // @[TLB.scala:170:77] wire pma_checker__entries_T_111; // @[TLB.scala:170:77] wire pma_checker__entries_T_110; // @[TLB.scala:170:77] wire pma_checker__entries_T_109; // @[TLB.scala:170:77] wire pma_checker__entries_T_108; // @[TLB.scala:170:77] wire pma_checker__entries_T_107; // @[TLB.scala:170:77] wire pma_checker__entries_T_106; // @[TLB.scala:170:77] wire pma_checker__entries_T_105; // @[TLB.scala:170:77] wire pma_checker__entries_T_104; // @[TLB.scala:170:77] wire pma_checker__entries_T_103; // @[TLB.scala:170:77] wire pma_checker__entries_T_102; // @[TLB.scala:170:77] wire pma_checker__entries_T_101; // @[TLB.scala:170:77] wire pma_checker__entries_T_100; // @[TLB.scala:170:77] wire pma_checker__entries_T_99; // @[TLB.scala:170:77] wire pma_checker__entries_T_98; // @[TLB.scala:170:77] wire pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_97 = pma_checker__entries_WIRE_9[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_fragmented_superpage = pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_98 = pma_checker__entries_WIRE_9[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_c = pma_checker__entries_T_98; // @[TLB.scala:170:77] assign pma_checker__entries_T_99 = pma_checker__entries_WIRE_9[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_eff = pma_checker__entries_T_99; // @[TLB.scala:170:77] assign pma_checker__entries_T_100 = pma_checker__entries_WIRE_9[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_paa = pma_checker__entries_T_100; // @[TLB.scala:170:77] assign pma_checker__entries_T_101 = pma_checker__entries_WIRE_9[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pal = pma_checker__entries_T_101; // @[TLB.scala:170:77] assign pma_checker__entries_T_102 = pma_checker__entries_WIRE_9[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ppp = pma_checker__entries_T_102; // @[TLB.scala:170:77] assign pma_checker__entries_T_103 = pma_checker__entries_WIRE_9[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pr = pma_checker__entries_T_103; // @[TLB.scala:170:77] assign pma_checker__entries_T_104 = pma_checker__entries_WIRE_9[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_px = pma_checker__entries_T_104; // @[TLB.scala:170:77] assign pma_checker__entries_T_105 = pma_checker__entries_WIRE_9[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pw = pma_checker__entries_T_105; // @[TLB.scala:170:77] assign pma_checker__entries_T_106 = pma_checker__entries_WIRE_9[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hr = pma_checker__entries_T_106; // @[TLB.scala:170:77] assign pma_checker__entries_T_107 = pma_checker__entries_WIRE_9[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hx = pma_checker__entries_T_107; // @[TLB.scala:170:77] assign pma_checker__entries_T_108 = pma_checker__entries_WIRE_9[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hw = pma_checker__entries_T_108; // @[TLB.scala:170:77] assign pma_checker__entries_T_109 = pma_checker__entries_WIRE_9[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sr = pma_checker__entries_T_109; // @[TLB.scala:170:77] assign pma_checker__entries_T_110 = pma_checker__entries_WIRE_9[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sx = pma_checker__entries_T_110; // @[TLB.scala:170:77] assign pma_checker__entries_T_111 = pma_checker__entries_WIRE_9[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sw = pma_checker__entries_T_111; // @[TLB.scala:170:77] assign pma_checker__entries_T_112 = pma_checker__entries_WIRE_9[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_gf = pma_checker__entries_T_112; // @[TLB.scala:170:77] assign pma_checker__entries_T_113 = pma_checker__entries_WIRE_9[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pf = pma_checker__entries_T_113; // @[TLB.scala:170:77] assign pma_checker__entries_T_114 = pma_checker__entries_WIRE_9[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_stage2 = pma_checker__entries_T_114; // @[TLB.scala:170:77] assign pma_checker__entries_T_115 = pma_checker__entries_WIRE_9[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_final = pma_checker__entries_T_115; // @[TLB.scala:170:77] assign pma_checker__entries_T_116 = pma_checker__entries_WIRE_9[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_ptw = pma_checker__entries_T_116; // @[TLB.scala:170:77] assign pma_checker__entries_T_117 = pma_checker__entries_WIRE_9[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_g = pma_checker__entries_T_117; // @[TLB.scala:170:77] assign pma_checker__entries_T_118 = pma_checker__entries_WIRE_9[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_u = pma_checker__entries_T_118; // @[TLB.scala:170:77] assign pma_checker__entries_T_119 = pma_checker__entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_8_ppn = pma_checker__entries_T_119; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_143; // @[TLB.scala:170:77] wire pma_checker__entries_T_142; // @[TLB.scala:170:77] wire pma_checker__entries_T_141; // @[TLB.scala:170:77] wire pma_checker__entries_T_140; // @[TLB.scala:170:77] wire pma_checker__entries_T_139; // @[TLB.scala:170:77] wire pma_checker__entries_T_138; // @[TLB.scala:170:77] wire pma_checker__entries_T_137; // @[TLB.scala:170:77] wire pma_checker__entries_T_136; // @[TLB.scala:170:77] wire pma_checker__entries_T_135; // @[TLB.scala:170:77] wire pma_checker__entries_T_134; // @[TLB.scala:170:77] wire pma_checker__entries_T_133; // @[TLB.scala:170:77] wire pma_checker__entries_T_132; // @[TLB.scala:170:77] wire pma_checker__entries_T_131; // @[TLB.scala:170:77] wire pma_checker__entries_T_130; // @[TLB.scala:170:77] wire pma_checker__entries_T_129; // @[TLB.scala:170:77] wire pma_checker__entries_T_128; // @[TLB.scala:170:77] wire pma_checker__entries_T_127; // @[TLB.scala:170:77] wire pma_checker__entries_T_126; // @[TLB.scala:170:77] wire pma_checker__entries_T_125; // @[TLB.scala:170:77] wire pma_checker__entries_T_124; // @[TLB.scala:170:77] wire pma_checker__entries_T_123; // @[TLB.scala:170:77] wire pma_checker__entries_T_122; // @[TLB.scala:170:77] wire pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_121 = pma_checker__entries_WIRE_11[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_fragmented_superpage = pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_122 = pma_checker__entries_WIRE_11[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_c = pma_checker__entries_T_122; // @[TLB.scala:170:77] assign pma_checker__entries_T_123 = pma_checker__entries_WIRE_11[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_eff = pma_checker__entries_T_123; // @[TLB.scala:170:77] assign pma_checker__entries_T_124 = pma_checker__entries_WIRE_11[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_paa = pma_checker__entries_T_124; // @[TLB.scala:170:77] assign pma_checker__entries_T_125 = pma_checker__entries_WIRE_11[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pal = pma_checker__entries_T_125; // @[TLB.scala:170:77] assign pma_checker__entries_T_126 = pma_checker__entries_WIRE_11[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ppp = pma_checker__entries_T_126; // @[TLB.scala:170:77] assign pma_checker__entries_T_127 = pma_checker__entries_WIRE_11[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pr = pma_checker__entries_T_127; // @[TLB.scala:170:77] assign pma_checker__entries_T_128 = pma_checker__entries_WIRE_11[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_px = pma_checker__entries_T_128; // @[TLB.scala:170:77] assign pma_checker__entries_T_129 = pma_checker__entries_WIRE_11[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pw = pma_checker__entries_T_129; // @[TLB.scala:170:77] assign pma_checker__entries_T_130 = pma_checker__entries_WIRE_11[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hr = pma_checker__entries_T_130; // @[TLB.scala:170:77] assign pma_checker__entries_T_131 = pma_checker__entries_WIRE_11[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hx = pma_checker__entries_T_131; // @[TLB.scala:170:77] assign pma_checker__entries_T_132 = pma_checker__entries_WIRE_11[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hw = pma_checker__entries_T_132; // @[TLB.scala:170:77] assign pma_checker__entries_T_133 = pma_checker__entries_WIRE_11[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sr = pma_checker__entries_T_133; // @[TLB.scala:170:77] assign pma_checker__entries_T_134 = pma_checker__entries_WIRE_11[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sx = pma_checker__entries_T_134; // @[TLB.scala:170:77] assign pma_checker__entries_T_135 = pma_checker__entries_WIRE_11[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sw = pma_checker__entries_T_135; // @[TLB.scala:170:77] assign pma_checker__entries_T_136 = pma_checker__entries_WIRE_11[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_gf = pma_checker__entries_T_136; // @[TLB.scala:170:77] assign pma_checker__entries_T_137 = pma_checker__entries_WIRE_11[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pf = pma_checker__entries_T_137; // @[TLB.scala:170:77] assign pma_checker__entries_T_138 = pma_checker__entries_WIRE_11[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_stage2 = pma_checker__entries_T_138; // @[TLB.scala:170:77] assign pma_checker__entries_T_139 = pma_checker__entries_WIRE_11[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_final = pma_checker__entries_T_139; // @[TLB.scala:170:77] assign pma_checker__entries_T_140 = pma_checker__entries_WIRE_11[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_ptw = pma_checker__entries_T_140; // @[TLB.scala:170:77] assign pma_checker__entries_T_141 = pma_checker__entries_WIRE_11[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_g = pma_checker__entries_T_141; // @[TLB.scala:170:77] assign pma_checker__entries_T_142 = pma_checker__entries_WIRE_11[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_u = pma_checker__entries_T_142; // @[TLB.scala:170:77] assign pma_checker__entries_T_143 = pma_checker__entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_10_ppn = pma_checker__entries_T_143; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_167; // @[TLB.scala:170:77] wire pma_checker__entries_T_166; // @[TLB.scala:170:77] wire pma_checker__entries_T_165; // @[TLB.scala:170:77] wire pma_checker__entries_T_164; // @[TLB.scala:170:77] wire pma_checker__entries_T_163; // @[TLB.scala:170:77] wire pma_checker__entries_T_162; // @[TLB.scala:170:77] wire pma_checker__entries_T_161; // @[TLB.scala:170:77] wire pma_checker__entries_T_160; // @[TLB.scala:170:77] wire pma_checker__entries_T_159; // @[TLB.scala:170:77] wire pma_checker__entries_T_158; // @[TLB.scala:170:77] wire pma_checker__entries_T_157; // @[TLB.scala:170:77] wire pma_checker__entries_T_156; // @[TLB.scala:170:77] wire pma_checker__entries_T_155; // @[TLB.scala:170:77] wire pma_checker__entries_T_154; // @[TLB.scala:170:77] wire pma_checker__entries_T_153; // @[TLB.scala:170:77] wire pma_checker__entries_T_152; // @[TLB.scala:170:77] wire pma_checker__entries_T_151; // @[TLB.scala:170:77] wire pma_checker__entries_T_150; // @[TLB.scala:170:77] wire pma_checker__entries_T_149; // @[TLB.scala:170:77] wire pma_checker__entries_T_148; // @[TLB.scala:170:77] wire pma_checker__entries_T_147; // @[TLB.scala:170:77] wire pma_checker__entries_T_146; // @[TLB.scala:170:77] wire pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_145 = pma_checker__entries_WIRE_13[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_fragmented_superpage = pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_146 = pma_checker__entries_WIRE_13[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_c = pma_checker__entries_T_146; // @[TLB.scala:170:77] assign pma_checker__entries_T_147 = pma_checker__entries_WIRE_13[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_eff = pma_checker__entries_T_147; // @[TLB.scala:170:77] assign pma_checker__entries_T_148 = pma_checker__entries_WIRE_13[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_paa = pma_checker__entries_T_148; // @[TLB.scala:170:77] assign pma_checker__entries_T_149 = pma_checker__entries_WIRE_13[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pal = pma_checker__entries_T_149; // @[TLB.scala:170:77] assign pma_checker__entries_T_150 = pma_checker__entries_WIRE_13[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ppp = pma_checker__entries_T_150; // @[TLB.scala:170:77] assign pma_checker__entries_T_151 = pma_checker__entries_WIRE_13[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pr = pma_checker__entries_T_151; // @[TLB.scala:170:77] assign pma_checker__entries_T_152 = pma_checker__entries_WIRE_13[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_px = pma_checker__entries_T_152; // @[TLB.scala:170:77] assign pma_checker__entries_T_153 = pma_checker__entries_WIRE_13[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pw = pma_checker__entries_T_153; // @[TLB.scala:170:77] assign pma_checker__entries_T_154 = pma_checker__entries_WIRE_13[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hr = pma_checker__entries_T_154; // @[TLB.scala:170:77] assign pma_checker__entries_T_155 = pma_checker__entries_WIRE_13[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hx = pma_checker__entries_T_155; // @[TLB.scala:170:77] assign pma_checker__entries_T_156 = pma_checker__entries_WIRE_13[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hw = pma_checker__entries_T_156; // @[TLB.scala:170:77] assign pma_checker__entries_T_157 = pma_checker__entries_WIRE_13[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sr = pma_checker__entries_T_157; // @[TLB.scala:170:77] assign pma_checker__entries_T_158 = pma_checker__entries_WIRE_13[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sx = pma_checker__entries_T_158; // @[TLB.scala:170:77] assign pma_checker__entries_T_159 = pma_checker__entries_WIRE_13[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sw = pma_checker__entries_T_159; // @[TLB.scala:170:77] assign pma_checker__entries_T_160 = pma_checker__entries_WIRE_13[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_gf = pma_checker__entries_T_160; // @[TLB.scala:170:77] assign pma_checker__entries_T_161 = pma_checker__entries_WIRE_13[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pf = pma_checker__entries_T_161; // @[TLB.scala:170:77] assign pma_checker__entries_T_162 = pma_checker__entries_WIRE_13[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_stage2 = pma_checker__entries_T_162; // @[TLB.scala:170:77] assign pma_checker__entries_T_163 = pma_checker__entries_WIRE_13[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_final = pma_checker__entries_T_163; // @[TLB.scala:170:77] assign pma_checker__entries_T_164 = pma_checker__entries_WIRE_13[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_ptw = pma_checker__entries_T_164; // @[TLB.scala:170:77] assign pma_checker__entries_T_165 = pma_checker__entries_WIRE_13[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_g = pma_checker__entries_T_165; // @[TLB.scala:170:77] assign pma_checker__entries_T_166 = pma_checker__entries_WIRE_13[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_u = pma_checker__entries_T_166; // @[TLB.scala:170:77] assign pma_checker__entries_T_167 = pma_checker__entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_12_ppn = pma_checker__entries_T_167; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_191; // @[TLB.scala:170:77] wire pma_checker__entries_T_190; // @[TLB.scala:170:77] wire pma_checker__entries_T_189; // @[TLB.scala:170:77] wire pma_checker__entries_T_188; // @[TLB.scala:170:77] wire pma_checker__entries_T_187; // @[TLB.scala:170:77] wire pma_checker__entries_T_186; // @[TLB.scala:170:77] wire pma_checker__entries_T_185; // @[TLB.scala:170:77] wire pma_checker__entries_T_184; // @[TLB.scala:170:77] wire pma_checker__entries_T_183; // @[TLB.scala:170:77] wire pma_checker__entries_T_182; // @[TLB.scala:170:77] wire pma_checker__entries_T_181; // @[TLB.scala:170:77] wire pma_checker__entries_T_180; // @[TLB.scala:170:77] wire pma_checker__entries_T_179; // @[TLB.scala:170:77] wire pma_checker__entries_T_178; // @[TLB.scala:170:77] wire pma_checker__entries_T_177; // @[TLB.scala:170:77] wire pma_checker__entries_T_176; // @[TLB.scala:170:77] wire pma_checker__entries_T_175; // @[TLB.scala:170:77] wire pma_checker__entries_T_174; // @[TLB.scala:170:77] wire pma_checker__entries_T_173; // @[TLB.scala:170:77] wire pma_checker__entries_T_172; // @[TLB.scala:170:77] wire pma_checker__entries_T_171; // @[TLB.scala:170:77] wire pma_checker__entries_T_170; // @[TLB.scala:170:77] wire pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_169 = pma_checker__entries_WIRE_15[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_fragmented_superpage = pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_170 = pma_checker__entries_WIRE_15[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_c = pma_checker__entries_T_170; // @[TLB.scala:170:77] assign pma_checker__entries_T_171 = pma_checker__entries_WIRE_15[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_eff = pma_checker__entries_T_171; // @[TLB.scala:170:77] assign pma_checker__entries_T_172 = pma_checker__entries_WIRE_15[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_paa = pma_checker__entries_T_172; // @[TLB.scala:170:77] assign pma_checker__entries_T_173 = pma_checker__entries_WIRE_15[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pal = pma_checker__entries_T_173; // @[TLB.scala:170:77] assign pma_checker__entries_T_174 = pma_checker__entries_WIRE_15[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ppp = pma_checker__entries_T_174; // @[TLB.scala:170:77] assign pma_checker__entries_T_175 = pma_checker__entries_WIRE_15[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pr = pma_checker__entries_T_175; // @[TLB.scala:170:77] assign pma_checker__entries_T_176 = pma_checker__entries_WIRE_15[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_px = pma_checker__entries_T_176; // @[TLB.scala:170:77] assign pma_checker__entries_T_177 = pma_checker__entries_WIRE_15[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pw = pma_checker__entries_T_177; // @[TLB.scala:170:77] assign pma_checker__entries_T_178 = pma_checker__entries_WIRE_15[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hr = pma_checker__entries_T_178; // @[TLB.scala:170:77] assign pma_checker__entries_T_179 = pma_checker__entries_WIRE_15[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hx = pma_checker__entries_T_179; // @[TLB.scala:170:77] assign pma_checker__entries_T_180 = pma_checker__entries_WIRE_15[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hw = pma_checker__entries_T_180; // @[TLB.scala:170:77] assign pma_checker__entries_T_181 = pma_checker__entries_WIRE_15[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sr = pma_checker__entries_T_181; // @[TLB.scala:170:77] assign pma_checker__entries_T_182 = pma_checker__entries_WIRE_15[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sx = pma_checker__entries_T_182; // @[TLB.scala:170:77] assign pma_checker__entries_T_183 = pma_checker__entries_WIRE_15[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sw = pma_checker__entries_T_183; // @[TLB.scala:170:77] assign pma_checker__entries_T_184 = pma_checker__entries_WIRE_15[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_gf = pma_checker__entries_T_184; // @[TLB.scala:170:77] assign pma_checker__entries_T_185 = pma_checker__entries_WIRE_15[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pf = pma_checker__entries_T_185; // @[TLB.scala:170:77] assign pma_checker__entries_T_186 = pma_checker__entries_WIRE_15[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_stage2 = pma_checker__entries_T_186; // @[TLB.scala:170:77] assign pma_checker__entries_T_187 = pma_checker__entries_WIRE_15[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_final = pma_checker__entries_T_187; // @[TLB.scala:170:77] assign pma_checker__entries_T_188 = pma_checker__entries_WIRE_15[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_ptw = pma_checker__entries_T_188; // @[TLB.scala:170:77] assign pma_checker__entries_T_189 = pma_checker__entries_WIRE_15[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_g = pma_checker__entries_T_189; // @[TLB.scala:170:77] assign pma_checker__entries_T_190 = pma_checker__entries_WIRE_15[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_u = pma_checker__entries_T_190; // @[TLB.scala:170:77] assign pma_checker__entries_T_191 = pma_checker__entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_14_ppn = pma_checker__entries_T_191; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_214; // @[TLB.scala:170:77] wire pma_checker__entries_T_213; // @[TLB.scala:170:77] wire pma_checker__entries_T_212; // @[TLB.scala:170:77] wire pma_checker__entries_T_211; // @[TLB.scala:170:77] wire pma_checker__entries_T_210; // @[TLB.scala:170:77] wire pma_checker__entries_T_209; // @[TLB.scala:170:77] wire pma_checker__entries_T_208; // @[TLB.scala:170:77] wire pma_checker__entries_T_207; // @[TLB.scala:170:77] wire pma_checker__entries_T_206; // @[TLB.scala:170:77] wire pma_checker__entries_T_205; // @[TLB.scala:170:77] wire pma_checker__entries_T_204; // @[TLB.scala:170:77] wire pma_checker__entries_T_203; // @[TLB.scala:170:77] wire pma_checker__entries_T_202; // @[TLB.scala:170:77] wire pma_checker__entries_T_201; // @[TLB.scala:170:77] wire pma_checker__entries_T_200; // @[TLB.scala:170:77] wire pma_checker__entries_T_199; // @[TLB.scala:170:77] wire pma_checker__entries_T_198; // @[TLB.scala:170:77] wire pma_checker__entries_T_197; // @[TLB.scala:170:77] wire pma_checker__entries_T_196; // @[TLB.scala:170:77] wire pma_checker__entries_T_195; // @[TLB.scala:170:77] wire pma_checker__entries_T_194; // @[TLB.scala:170:77] wire pma_checker__entries_T_193; // @[TLB.scala:170:77] wire pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_192 = pma_checker__entries_WIRE_17[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_fragmented_superpage = pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_193 = pma_checker__entries_WIRE_17[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_c = pma_checker__entries_T_193; // @[TLB.scala:170:77] assign pma_checker__entries_T_194 = pma_checker__entries_WIRE_17[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_eff = pma_checker__entries_T_194; // @[TLB.scala:170:77] assign pma_checker__entries_T_195 = pma_checker__entries_WIRE_17[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_paa = pma_checker__entries_T_195; // @[TLB.scala:170:77] assign pma_checker__entries_T_196 = pma_checker__entries_WIRE_17[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pal = pma_checker__entries_T_196; // @[TLB.scala:170:77] assign pma_checker__entries_T_197 = pma_checker__entries_WIRE_17[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ppp = pma_checker__entries_T_197; // @[TLB.scala:170:77] assign pma_checker__entries_T_198 = pma_checker__entries_WIRE_17[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pr = pma_checker__entries_T_198; // @[TLB.scala:170:77] assign pma_checker__entries_T_199 = pma_checker__entries_WIRE_17[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_px = pma_checker__entries_T_199; // @[TLB.scala:170:77] assign pma_checker__entries_T_200 = pma_checker__entries_WIRE_17[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pw = pma_checker__entries_T_200; // @[TLB.scala:170:77] assign pma_checker__entries_T_201 = pma_checker__entries_WIRE_17[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hr = pma_checker__entries_T_201; // @[TLB.scala:170:77] assign pma_checker__entries_T_202 = pma_checker__entries_WIRE_17[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hx = pma_checker__entries_T_202; // @[TLB.scala:170:77] assign pma_checker__entries_T_203 = pma_checker__entries_WIRE_17[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hw = pma_checker__entries_T_203; // @[TLB.scala:170:77] assign pma_checker__entries_T_204 = pma_checker__entries_WIRE_17[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sr = pma_checker__entries_T_204; // @[TLB.scala:170:77] assign pma_checker__entries_T_205 = pma_checker__entries_WIRE_17[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sx = pma_checker__entries_T_205; // @[TLB.scala:170:77] assign pma_checker__entries_T_206 = pma_checker__entries_WIRE_17[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sw = pma_checker__entries_T_206; // @[TLB.scala:170:77] assign pma_checker__entries_T_207 = pma_checker__entries_WIRE_17[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_gf = pma_checker__entries_T_207; // @[TLB.scala:170:77] assign pma_checker__entries_T_208 = pma_checker__entries_WIRE_17[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pf = pma_checker__entries_T_208; // @[TLB.scala:170:77] assign pma_checker__entries_T_209 = pma_checker__entries_WIRE_17[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_stage2 = pma_checker__entries_T_209; // @[TLB.scala:170:77] assign pma_checker__entries_T_210 = pma_checker__entries_WIRE_17[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_final = pma_checker__entries_T_210; // @[TLB.scala:170:77] assign pma_checker__entries_T_211 = pma_checker__entries_WIRE_17[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_ptw = pma_checker__entries_T_211; // @[TLB.scala:170:77] assign pma_checker__entries_T_212 = pma_checker__entries_WIRE_17[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_g = pma_checker__entries_T_212; // @[TLB.scala:170:77] assign pma_checker__entries_T_213 = pma_checker__entries_WIRE_17[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_u = pma_checker__entries_T_213; // @[TLB.scala:170:77] assign pma_checker__entries_T_214 = pma_checker__entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_16_ppn = pma_checker__entries_T_214; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_237; // @[TLB.scala:170:77] wire pma_checker__entries_T_236; // @[TLB.scala:170:77] wire pma_checker__entries_T_235; // @[TLB.scala:170:77] wire pma_checker__entries_T_234; // @[TLB.scala:170:77] wire pma_checker__entries_T_233; // @[TLB.scala:170:77] wire pma_checker__entries_T_232; // @[TLB.scala:170:77] wire pma_checker__entries_T_231; // @[TLB.scala:170:77] wire pma_checker__entries_T_230; // @[TLB.scala:170:77] wire pma_checker__entries_T_229; // @[TLB.scala:170:77] wire pma_checker__entries_T_228; // @[TLB.scala:170:77] wire pma_checker__entries_T_227; // @[TLB.scala:170:77] wire pma_checker__entries_T_226; // @[TLB.scala:170:77] wire pma_checker__entries_T_225; // @[TLB.scala:170:77] wire pma_checker__entries_T_224; // @[TLB.scala:170:77] wire pma_checker__entries_T_223; // @[TLB.scala:170:77] wire pma_checker__entries_T_222; // @[TLB.scala:170:77] wire pma_checker__entries_T_221; // @[TLB.scala:170:77] wire pma_checker__entries_T_220; // @[TLB.scala:170:77] wire pma_checker__entries_T_219; // @[TLB.scala:170:77] wire pma_checker__entries_T_218; // @[TLB.scala:170:77] wire pma_checker__entries_T_217; // @[TLB.scala:170:77] wire pma_checker__entries_T_216; // @[TLB.scala:170:77] wire pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_215 = pma_checker__entries_WIRE_19[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_fragmented_superpage = pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_216 = pma_checker__entries_WIRE_19[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_c = pma_checker__entries_T_216; // @[TLB.scala:170:77] assign pma_checker__entries_T_217 = pma_checker__entries_WIRE_19[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_eff = pma_checker__entries_T_217; // @[TLB.scala:170:77] assign pma_checker__entries_T_218 = pma_checker__entries_WIRE_19[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_paa = pma_checker__entries_T_218; // @[TLB.scala:170:77] assign pma_checker__entries_T_219 = pma_checker__entries_WIRE_19[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pal = pma_checker__entries_T_219; // @[TLB.scala:170:77] assign pma_checker__entries_T_220 = pma_checker__entries_WIRE_19[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ppp = pma_checker__entries_T_220; // @[TLB.scala:170:77] assign pma_checker__entries_T_221 = pma_checker__entries_WIRE_19[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pr = pma_checker__entries_T_221; // @[TLB.scala:170:77] assign pma_checker__entries_T_222 = pma_checker__entries_WIRE_19[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_px = pma_checker__entries_T_222; // @[TLB.scala:170:77] assign pma_checker__entries_T_223 = pma_checker__entries_WIRE_19[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pw = pma_checker__entries_T_223; // @[TLB.scala:170:77] assign pma_checker__entries_T_224 = pma_checker__entries_WIRE_19[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hr = pma_checker__entries_T_224; // @[TLB.scala:170:77] assign pma_checker__entries_T_225 = pma_checker__entries_WIRE_19[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hx = pma_checker__entries_T_225; // @[TLB.scala:170:77] assign pma_checker__entries_T_226 = pma_checker__entries_WIRE_19[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hw = pma_checker__entries_T_226; // @[TLB.scala:170:77] assign pma_checker__entries_T_227 = pma_checker__entries_WIRE_19[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sr = pma_checker__entries_T_227; // @[TLB.scala:170:77] assign pma_checker__entries_T_228 = pma_checker__entries_WIRE_19[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sx = pma_checker__entries_T_228; // @[TLB.scala:170:77] assign pma_checker__entries_T_229 = pma_checker__entries_WIRE_19[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sw = pma_checker__entries_T_229; // @[TLB.scala:170:77] assign pma_checker__entries_T_230 = pma_checker__entries_WIRE_19[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_gf = pma_checker__entries_T_230; // @[TLB.scala:170:77] assign pma_checker__entries_T_231 = pma_checker__entries_WIRE_19[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pf = pma_checker__entries_T_231; // @[TLB.scala:170:77] assign pma_checker__entries_T_232 = pma_checker__entries_WIRE_19[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_stage2 = pma_checker__entries_T_232; // @[TLB.scala:170:77] assign pma_checker__entries_T_233 = pma_checker__entries_WIRE_19[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_final = pma_checker__entries_T_233; // @[TLB.scala:170:77] assign pma_checker__entries_T_234 = pma_checker__entries_WIRE_19[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_ptw = pma_checker__entries_T_234; // @[TLB.scala:170:77] assign pma_checker__entries_T_235 = pma_checker__entries_WIRE_19[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_g = pma_checker__entries_T_235; // @[TLB.scala:170:77] assign pma_checker__entries_T_236 = pma_checker__entries_WIRE_19[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_u = pma_checker__entries_T_236; // @[TLB.scala:170:77] assign pma_checker__entries_T_237 = pma_checker__entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_18_ppn = pma_checker__entries_T_237; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_260; // @[TLB.scala:170:77] wire pma_checker__entries_T_259; // @[TLB.scala:170:77] wire pma_checker__entries_T_258; // @[TLB.scala:170:77] wire pma_checker__entries_T_257; // @[TLB.scala:170:77] wire pma_checker__entries_T_256; // @[TLB.scala:170:77] wire pma_checker__entries_T_255; // @[TLB.scala:170:77] wire pma_checker__entries_T_254; // @[TLB.scala:170:77] wire pma_checker__entries_T_253; // @[TLB.scala:170:77] wire pma_checker__entries_T_252; // @[TLB.scala:170:77] wire pma_checker__entries_T_251; // @[TLB.scala:170:77] wire pma_checker__entries_T_250; // @[TLB.scala:170:77] wire pma_checker__entries_T_249; // @[TLB.scala:170:77] wire pma_checker__entries_T_248; // @[TLB.scala:170:77] wire pma_checker__entries_T_247; // @[TLB.scala:170:77] wire pma_checker__entries_T_246; // @[TLB.scala:170:77] wire pma_checker__entries_T_245; // @[TLB.scala:170:77] wire pma_checker__entries_T_244; // @[TLB.scala:170:77] wire pma_checker__entries_T_243; // @[TLB.scala:170:77] wire pma_checker__entries_T_242; // @[TLB.scala:170:77] wire pma_checker__entries_T_241; // @[TLB.scala:170:77] wire pma_checker__entries_T_240; // @[TLB.scala:170:77] wire pma_checker__entries_T_239; // @[TLB.scala:170:77] wire pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_238 = pma_checker__entries_WIRE_21[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_fragmented_superpage = pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_239 = pma_checker__entries_WIRE_21[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_c = pma_checker__entries_T_239; // @[TLB.scala:170:77] assign pma_checker__entries_T_240 = pma_checker__entries_WIRE_21[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_eff = pma_checker__entries_T_240; // @[TLB.scala:170:77] assign pma_checker__entries_T_241 = pma_checker__entries_WIRE_21[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_paa = pma_checker__entries_T_241; // @[TLB.scala:170:77] assign pma_checker__entries_T_242 = pma_checker__entries_WIRE_21[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pal = pma_checker__entries_T_242; // @[TLB.scala:170:77] assign pma_checker__entries_T_243 = pma_checker__entries_WIRE_21[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ppp = pma_checker__entries_T_243; // @[TLB.scala:170:77] assign pma_checker__entries_T_244 = pma_checker__entries_WIRE_21[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pr = pma_checker__entries_T_244; // @[TLB.scala:170:77] assign pma_checker__entries_T_245 = pma_checker__entries_WIRE_21[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_px = pma_checker__entries_T_245; // @[TLB.scala:170:77] assign pma_checker__entries_T_246 = pma_checker__entries_WIRE_21[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pw = pma_checker__entries_T_246; // @[TLB.scala:170:77] assign pma_checker__entries_T_247 = pma_checker__entries_WIRE_21[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hr = pma_checker__entries_T_247; // @[TLB.scala:170:77] assign pma_checker__entries_T_248 = pma_checker__entries_WIRE_21[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hx = pma_checker__entries_T_248; // @[TLB.scala:170:77] assign pma_checker__entries_T_249 = pma_checker__entries_WIRE_21[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hw = pma_checker__entries_T_249; // @[TLB.scala:170:77] assign pma_checker__entries_T_250 = pma_checker__entries_WIRE_21[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sr = pma_checker__entries_T_250; // @[TLB.scala:170:77] assign pma_checker__entries_T_251 = pma_checker__entries_WIRE_21[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sx = pma_checker__entries_T_251; // @[TLB.scala:170:77] assign pma_checker__entries_T_252 = pma_checker__entries_WIRE_21[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sw = pma_checker__entries_T_252; // @[TLB.scala:170:77] assign pma_checker__entries_T_253 = pma_checker__entries_WIRE_21[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_gf = pma_checker__entries_T_253; // @[TLB.scala:170:77] assign pma_checker__entries_T_254 = pma_checker__entries_WIRE_21[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pf = pma_checker__entries_T_254; // @[TLB.scala:170:77] assign pma_checker__entries_T_255 = pma_checker__entries_WIRE_21[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_stage2 = pma_checker__entries_T_255; // @[TLB.scala:170:77] assign pma_checker__entries_T_256 = pma_checker__entries_WIRE_21[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_final = pma_checker__entries_T_256; // @[TLB.scala:170:77] assign pma_checker__entries_T_257 = pma_checker__entries_WIRE_21[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_ptw = pma_checker__entries_T_257; // @[TLB.scala:170:77] assign pma_checker__entries_T_258 = pma_checker__entries_WIRE_21[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_g = pma_checker__entries_T_258; // @[TLB.scala:170:77] assign pma_checker__entries_T_259 = pma_checker__entries_WIRE_21[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_u = pma_checker__entries_T_259; // @[TLB.scala:170:77] assign pma_checker__entries_T_260 = pma_checker__entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_20_ppn = pma_checker__entries_T_260; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_283; // @[TLB.scala:170:77] wire pma_checker__entries_T_282; // @[TLB.scala:170:77] wire pma_checker__entries_T_281; // @[TLB.scala:170:77] wire pma_checker__entries_T_280; // @[TLB.scala:170:77] wire pma_checker__entries_T_279; // @[TLB.scala:170:77] wire pma_checker__entries_T_278; // @[TLB.scala:170:77] wire pma_checker__entries_T_277; // @[TLB.scala:170:77] wire pma_checker__entries_T_276; // @[TLB.scala:170:77] wire pma_checker__entries_T_275; // @[TLB.scala:170:77] wire pma_checker__entries_T_274; // @[TLB.scala:170:77] wire pma_checker__entries_T_273; // @[TLB.scala:170:77] wire pma_checker__entries_T_272; // @[TLB.scala:170:77] wire pma_checker__entries_T_271; // @[TLB.scala:170:77] wire pma_checker__entries_T_270; // @[TLB.scala:170:77] wire pma_checker__entries_T_269; // @[TLB.scala:170:77] wire pma_checker__entries_T_268; // @[TLB.scala:170:77] wire pma_checker__entries_T_267; // @[TLB.scala:170:77] wire pma_checker__entries_T_266; // @[TLB.scala:170:77] wire pma_checker__entries_T_265; // @[TLB.scala:170:77] wire pma_checker__entries_T_264; // @[TLB.scala:170:77] wire pma_checker__entries_T_263; // @[TLB.scala:170:77] wire pma_checker__entries_T_262; // @[TLB.scala:170:77] wire pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_261 = pma_checker__entries_WIRE_23[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_fragmented_superpage = pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_262 = pma_checker__entries_WIRE_23[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_c = pma_checker__entries_T_262; // @[TLB.scala:170:77] assign pma_checker__entries_T_263 = pma_checker__entries_WIRE_23[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_eff = pma_checker__entries_T_263; // @[TLB.scala:170:77] assign pma_checker__entries_T_264 = pma_checker__entries_WIRE_23[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_paa = pma_checker__entries_T_264; // @[TLB.scala:170:77] assign pma_checker__entries_T_265 = pma_checker__entries_WIRE_23[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pal = pma_checker__entries_T_265; // @[TLB.scala:170:77] assign pma_checker__entries_T_266 = pma_checker__entries_WIRE_23[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ppp = pma_checker__entries_T_266; // @[TLB.scala:170:77] assign pma_checker__entries_T_267 = pma_checker__entries_WIRE_23[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pr = pma_checker__entries_T_267; // @[TLB.scala:170:77] assign pma_checker__entries_T_268 = pma_checker__entries_WIRE_23[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_px = pma_checker__entries_T_268; // @[TLB.scala:170:77] assign pma_checker__entries_T_269 = pma_checker__entries_WIRE_23[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pw = pma_checker__entries_T_269; // @[TLB.scala:170:77] assign pma_checker__entries_T_270 = pma_checker__entries_WIRE_23[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hr = pma_checker__entries_T_270; // @[TLB.scala:170:77] assign pma_checker__entries_T_271 = pma_checker__entries_WIRE_23[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hx = pma_checker__entries_T_271; // @[TLB.scala:170:77] assign pma_checker__entries_T_272 = pma_checker__entries_WIRE_23[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hw = pma_checker__entries_T_272; // @[TLB.scala:170:77] assign pma_checker__entries_T_273 = pma_checker__entries_WIRE_23[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sr = pma_checker__entries_T_273; // @[TLB.scala:170:77] assign pma_checker__entries_T_274 = pma_checker__entries_WIRE_23[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sx = pma_checker__entries_T_274; // @[TLB.scala:170:77] assign pma_checker__entries_T_275 = pma_checker__entries_WIRE_23[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sw = pma_checker__entries_T_275; // @[TLB.scala:170:77] assign pma_checker__entries_T_276 = pma_checker__entries_WIRE_23[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_gf = pma_checker__entries_T_276; // @[TLB.scala:170:77] assign pma_checker__entries_T_277 = pma_checker__entries_WIRE_23[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pf = pma_checker__entries_T_277; // @[TLB.scala:170:77] assign pma_checker__entries_T_278 = pma_checker__entries_WIRE_23[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_stage2 = pma_checker__entries_T_278; // @[TLB.scala:170:77] assign pma_checker__entries_T_279 = pma_checker__entries_WIRE_23[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_final = pma_checker__entries_T_279; // @[TLB.scala:170:77] assign pma_checker__entries_T_280 = pma_checker__entries_WIRE_23[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_ptw = pma_checker__entries_T_280; // @[TLB.scala:170:77] assign pma_checker__entries_T_281 = pma_checker__entries_WIRE_23[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_g = pma_checker__entries_T_281; // @[TLB.scala:170:77] assign pma_checker__entries_T_282 = pma_checker__entries_WIRE_23[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_u = pma_checker__entries_T_282; // @[TLB.scala:170:77] assign pma_checker__entries_T_283 = pma_checker__entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_22_ppn = pma_checker__entries_T_283; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_306; // @[TLB.scala:170:77] wire pma_checker__entries_T_305; // @[TLB.scala:170:77] wire pma_checker__entries_T_304; // @[TLB.scala:170:77] wire pma_checker__entries_T_303; // @[TLB.scala:170:77] wire pma_checker__entries_T_302; // @[TLB.scala:170:77] wire pma_checker__entries_T_301; // @[TLB.scala:170:77] wire pma_checker__entries_T_300; // @[TLB.scala:170:77] wire pma_checker__entries_T_299; // @[TLB.scala:170:77] wire pma_checker__entries_T_298; // @[TLB.scala:170:77] wire pma_checker__entries_T_297; // @[TLB.scala:170:77] wire pma_checker__entries_T_296; // @[TLB.scala:170:77] wire pma_checker__entries_T_295; // @[TLB.scala:170:77] wire pma_checker__entries_T_294; // @[TLB.scala:170:77] wire pma_checker__entries_T_293; // @[TLB.scala:170:77] wire pma_checker__entries_T_292; // @[TLB.scala:170:77] wire pma_checker__entries_T_291; // @[TLB.scala:170:77] wire pma_checker__entries_T_290; // @[TLB.scala:170:77] wire pma_checker__entries_T_289; // @[TLB.scala:170:77] wire pma_checker__entries_T_288; // @[TLB.scala:170:77] wire pma_checker__entries_T_287; // @[TLB.scala:170:77] wire pma_checker__entries_T_286; // @[TLB.scala:170:77] wire pma_checker__entries_T_285; // @[TLB.scala:170:77] wire pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_284 = pma_checker__entries_WIRE_25[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_fragmented_superpage = pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_285 = pma_checker__entries_WIRE_25[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_c = pma_checker__entries_T_285; // @[TLB.scala:170:77] assign pma_checker__entries_T_286 = pma_checker__entries_WIRE_25[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_eff = pma_checker__entries_T_286; // @[TLB.scala:170:77] assign pma_checker__entries_T_287 = pma_checker__entries_WIRE_25[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_paa = pma_checker__entries_T_287; // @[TLB.scala:170:77] assign pma_checker__entries_T_288 = pma_checker__entries_WIRE_25[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pal = pma_checker__entries_T_288; // @[TLB.scala:170:77] assign pma_checker__entries_T_289 = pma_checker__entries_WIRE_25[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ppp = pma_checker__entries_T_289; // @[TLB.scala:170:77] assign pma_checker__entries_T_290 = pma_checker__entries_WIRE_25[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pr = pma_checker__entries_T_290; // @[TLB.scala:170:77] assign pma_checker__entries_T_291 = pma_checker__entries_WIRE_25[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_px = pma_checker__entries_T_291; // @[TLB.scala:170:77] assign pma_checker__entries_T_292 = pma_checker__entries_WIRE_25[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pw = pma_checker__entries_T_292; // @[TLB.scala:170:77] assign pma_checker__entries_T_293 = pma_checker__entries_WIRE_25[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hr = pma_checker__entries_T_293; // @[TLB.scala:170:77] assign pma_checker__entries_T_294 = pma_checker__entries_WIRE_25[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hx = pma_checker__entries_T_294; // @[TLB.scala:170:77] assign pma_checker__entries_T_295 = pma_checker__entries_WIRE_25[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hw = pma_checker__entries_T_295; // @[TLB.scala:170:77] assign pma_checker__entries_T_296 = pma_checker__entries_WIRE_25[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sr = pma_checker__entries_T_296; // @[TLB.scala:170:77] assign pma_checker__entries_T_297 = pma_checker__entries_WIRE_25[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sx = pma_checker__entries_T_297; // @[TLB.scala:170:77] assign pma_checker__entries_T_298 = pma_checker__entries_WIRE_25[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sw = pma_checker__entries_T_298; // @[TLB.scala:170:77] assign pma_checker__entries_T_299 = pma_checker__entries_WIRE_25[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_gf = pma_checker__entries_T_299; // @[TLB.scala:170:77] assign pma_checker__entries_T_300 = pma_checker__entries_WIRE_25[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pf = pma_checker__entries_T_300; // @[TLB.scala:170:77] assign pma_checker__entries_T_301 = pma_checker__entries_WIRE_25[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_stage2 = pma_checker__entries_T_301; // @[TLB.scala:170:77] assign pma_checker__entries_T_302 = pma_checker__entries_WIRE_25[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_final = pma_checker__entries_T_302; // @[TLB.scala:170:77] assign pma_checker__entries_T_303 = pma_checker__entries_WIRE_25[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_ptw = pma_checker__entries_T_303; // @[TLB.scala:170:77] assign pma_checker__entries_T_304 = pma_checker__entries_WIRE_25[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_g = pma_checker__entries_T_304; // @[TLB.scala:170:77] assign pma_checker__entries_T_305 = pma_checker__entries_WIRE_25[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_u = pma_checker__entries_T_305; // @[TLB.scala:170:77] assign pma_checker__entries_T_306 = pma_checker__entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_24_ppn = pma_checker__entries_T_306; // @[TLB.scala:170:77] wire [1:0] pma_checker_ppn_res = _pma_checker_entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore = pma_checker__ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_1 = pma_checker_ppn_ignore ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_2 = {pma_checker__ppn_T_1[26:20], pma_checker__ppn_T_1[19:0] \| _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_3 = pma_checker__ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_4 = {pma_checker_ppn_res, pma_checker__ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_6 = {pma_checker__ppn_T_5[26:20], pma_checker__ppn_T_5[19:0] \| _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_7 = pma_checker__ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_8 = {pma_checker__ppn_T_4, pma_checker__ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_1 = _pma_checker_entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_2 = pma_checker__ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_9 = pma_checker_ppn_ignore_2 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_10 = {pma_checker__ppn_T_9[26:20], pma_checker__ppn_T_9[19:0] \| _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_11 = pma_checker__ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_12 = {pma_checker_ppn_res_1, pma_checker__ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_14 = {pma_checker__ppn_T_13[26:20], pma_checker__ppn_T_13[19:0] \| _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_15 = pma_checker__ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_16 = {pma_checker__ppn_T_12, pma_checker__ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_2 = _pma_checker_entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_4 = pma_checker__ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_17 = pma_checker_ppn_ignore_4 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_18 = {pma_checker__ppn_T_17[26:20], pma_checker__ppn_T_17[19:0] \| _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_19 = pma_checker__ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_20 = {pma_checker_ppn_res_2, pma_checker__ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_22 = {pma_checker__ppn_T_21[26:20], pma_checker__ppn_T_21[19:0] \| _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_23 = pma_checker__ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_24 = {pma_checker__ppn_T_20, pma_checker__ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_3 = _pma_checker_entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_6 = pma_checker__ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_25 = pma_checker_ppn_ignore_6 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_26 = {pma_checker__ppn_T_25[26:20], pma_checker__ppn_T_25[19:0] \| _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_27 = pma_checker__ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_28 = {pma_checker_ppn_res_3, pma_checker__ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_30 = {pma_checker__ppn_T_29[26:20], pma_checker__ppn_T_29[19:0] \| _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_31 = pma_checker__ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_32 = {pma_checker__ppn_T_28, pma_checker__ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_4 = _pma_checker_entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire [26:0] pma_checker__ppn_T_34 = {pma_checker__ppn_T_33[26:20], pma_checker__ppn_T_33[19:0] \| _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_35 = pma_checker__ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_36 = {pma_checker_ppn_res_4, pma_checker__ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_38 = {pma_checker__ppn_T_37[26:20], pma_checker__ppn_T_37[19:0] \| _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_39 = pma_checker__ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_40 = {pma_checker__ppn_T_36, pma_checker__ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] pma_checker__ppn_T_41 = pma_checker_vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] pma_checker__ppn_T_55 = pma_checker__ppn_T_41; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_68 = pma_checker__ppn_T_55; // @[Mux.scala:30:73] wire [19:0] pma_checker_ppn = pma_checker__ppn_T_68; // @[Mux.scala:30:73] wire [1:0] pma_checker_ptw_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_ptw, _pma_checker_entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_lo = {pma_checker_ptw_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_ptw, _pma_checker_entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_hi = {pma_checker_ptw_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_ae_array_lo = {pma_checker_ptw_ae_array_lo_hi, pma_checker_ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_ptw, _pma_checker_entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_hi_lo = {pma_checker_ptw_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_ptw, _pma_checker_entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_ptw, _pma_checker_entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_ae_array_hi_hi = {pma_checker_ptw_ae_array_hi_hi_hi, pma_checker_ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_ae_array_hi = {pma_checker_ptw_ae_array_hi_hi, pma_checker_ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_ae_array_T = {pma_checker_ptw_ae_array_hi, pma_checker_ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_ae_array = {1'h0, pma_checker__ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_final, _pma_checker_entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_lo = {pma_checker_final_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_final, _pma_checker_entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_hi = {pma_checker_final_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_final_ae_array_lo = {pma_checker_final_ae_array_lo_hi, pma_checker_final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_final, _pma_checker_entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_hi_lo = {pma_checker_final_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_final, _pma_checker_entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_final, _pma_checker_entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_final_ae_array_hi_hi = {pma_checker_final_ae_array_hi_hi_hi, pma_checker_final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_final_ae_array_hi = {pma_checker_final_ae_array_hi_hi, pma_checker_final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__final_ae_array_T = {pma_checker_final_ae_array_hi, pma_checker_final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_final_ae_array = {1'h0, pma_checker__final_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pf, _pma_checker_entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_lo = {pma_checker_ptw_pf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pf, _pma_checker_entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_hi = {pma_checker_ptw_pf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_pf_array_lo = {pma_checker_ptw_pf_array_lo_hi, pma_checker_ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pf, _pma_checker_entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_hi_lo = {pma_checker_ptw_pf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_pf, _pma_checker_entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_pf, _pma_checker_entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_pf_array_hi_hi = {pma_checker_ptw_pf_array_hi_hi_hi, pma_checker_ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_pf_array_hi = {pma_checker_ptw_pf_array_hi_hi, pma_checker_ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_pf_array_T = {pma_checker_ptw_pf_array_hi, pma_checker_ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_pf_array = {1'h0, pma_checker__ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_gf, _pma_checker_entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_lo = {pma_checker_ptw_gf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_gf, _pma_checker_entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_hi = {pma_checker_ptw_gf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_gf_array_lo = {pma_checker_ptw_gf_array_lo_hi, pma_checker_ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_gf, _pma_checker_entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_hi_lo = {pma_checker_ptw_gf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_gf, _pma_checker_entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_gf, _pma_checker_entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_gf_array_hi_hi = {pma_checker_ptw_gf_array_hi_hi_hi, pma_checker_ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_gf_array_hi = {pma_checker_ptw_gf_array_hi_hi, pma_checker_ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_gf_array_T = {pma_checker_ptw_gf_array_hi, pma_checker_ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_gf_array = {1'h0, pma_checker__ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] pma_checker__gf_ld_array_T_3 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] pma_checker__gf_st_array_T_2 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] pma_checker__gf_inst_array_T_1 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire pma_checker__priv_rw_ok_T = ~pma_checker_priv_s; // @[TLB.scala:370:20, :513:24] wire pma_checker__priv_rw_ok_T_1 = pma_checker__priv_rw_ok_T; // @[TLB.scala:513:{24,32}] wire [1:0] _GEN_6 = {_pma_checker_entries_barrier_2_io_y_u, _pma_checker_entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo = {pma_checker_priv_rw_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_7 = {_pma_checker_entries_barrier_5_io_y_u, _pma_checker_entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_hi = {pma_checker_priv_rw_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo = {pma_checker_priv_rw_ok_lo_hi, pma_checker_priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_8 = {_pma_checker_entries_barrier_8_io_y_u, _pma_checker_entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo = {pma_checker_priv_rw_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_9 = {_pma_checker_entries_barrier_10_io_y_u, _pma_checker_entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] _GEN_10 = {_pma_checker_entries_barrier_12_io_y_u, _pma_checker_entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [3:0] pma_checker_priv_rw_ok_hi_hi = {pma_checker_priv_rw_ok_hi_hi_hi, pma_checker_priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi = {pma_checker_priv_rw_ok_hi_hi, pma_checker_priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_2 = {pma_checker_priv_rw_ok_hi, pma_checker_priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_3 = pma_checker__priv_rw_ok_T_1 ? pma_checker__priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo_1 = {pma_checker_priv_rw_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_rw_ok_lo_hi_1 = {pma_checker_priv_rw_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo_1 = {pma_checker_priv_rw_ok_lo_hi_1, pma_checker_priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo_1 = {pma_checker_priv_rw_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_rw_ok_hi_hi_1 = {pma_checker_priv_rw_ok_hi_hi_hi_1, pma_checker_priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi_1 = {pma_checker_priv_rw_ok_hi_hi_1, pma_checker_priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_4 = {pma_checker_priv_rw_ok_hi_1, pma_checker_priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_5 = ~pma_checker__priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_6 = pma_checker_priv_s ? pma_checker__priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] pma_checker_priv_rw_ok = pma_checker__priv_rw_ok_T_3 \| pma_checker__priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] pma_checker_priv_x_ok_lo_lo = {pma_checker_priv_x_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi = {pma_checker_priv_x_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo = {pma_checker_priv_x_ok_lo_hi, pma_checker_priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo = {pma_checker_priv_x_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi = {pma_checker_priv_x_ok_hi_hi_hi, pma_checker_priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi = {pma_checker_priv_x_ok_hi_hi, pma_checker_priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T = {pma_checker_priv_x_ok_hi, pma_checker_priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_1 = ~pma_checker__priv_x_ok_T; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_lo_lo_1 = {pma_checker_priv_x_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi_1 = {pma_checker_priv_x_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo_1 = {pma_checker_priv_x_ok_lo_hi_1, pma_checker_priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo_1 = {pma_checker_priv_x_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi_1 = {pma_checker_priv_x_ok_hi_hi_hi_1, pma_checker_priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi_1 = {pma_checker_priv_x_ok_hi_hi_1, pma_checker_priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_2 = {pma_checker_priv_x_ok_hi_1, pma_checker_priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker_priv_x_ok = pma_checker_priv_s ? pma_checker__priv_x_ok_T_1 : pma_checker__priv_x_ok_T_2; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_stage2, _pma_checker_entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_lo = {pma_checker_stage1_bypass_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_stage2, _pma_checker_entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_hi = {pma_checker_stage1_bypass_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_stage1_bypass_lo = {pma_checker_stage1_bypass_lo_hi, pma_checker_stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_stage2, _pma_checker_entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_hi_lo = {pma_checker_stage1_bypass_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_stage2, _pma_checker_entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_stage2, _pma_checker_entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_stage1_bypass_hi_hi = {pma_checker_stage1_bypass_hi_hi_hi, pma_checker_stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_stage1_bypass_hi = {pma_checker_stage1_bypass_hi_hi, pma_checker_stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T_3 = {pma_checker_stage1_bypass_hi, pma_checker_stage1_bypass_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sr, _pma_checker_entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_lo = {pma_checker_r_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sr, _pma_checker_entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_hi = {pma_checker_r_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo = {pma_checker_r_array_lo_hi, pma_checker_r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sr, _pma_checker_entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_hi_lo = {pma_checker_r_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sr, _pma_checker_entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sr, _pma_checker_entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_r_array_hi_hi = {pma_checker_r_array_hi_hi_hi, pma_checker_r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi = {pma_checker_r_array_hi_hi, pma_checker_r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T = {pma_checker_r_array_hi, pma_checker_r_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_3 = pma_checker__r_array_T; // @[package.scala:45:27] wire [1:0] _GEN_11 = {_pma_checker_entries_barrier_2_io_y_sx, _pma_checker_entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_lo_hi_1 = _GEN_11; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_lo_hi = _GEN_11; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_lo_1 = {pma_checker_r_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_12 = {_pma_checker_entries_barrier_5_io_y_sx, _pma_checker_entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_hi_hi_1 = _GEN_12; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_hi_hi = _GEN_12; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_hi_1 = {pma_checker_r_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo_1 = {pma_checker_r_array_lo_hi_1, pma_checker_r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_13 = {_pma_checker_entries_barrier_8_io_y_sx, _pma_checker_entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_lo_hi_1 = _GEN_13; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_lo_hi = _GEN_13; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_hi_lo_1 = {pma_checker_r_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_14 = {_pma_checker_entries_barrier_10_io_y_sx, _pma_checker_entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_lo_1 = _GEN_14; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_lo = _GEN_14; // @[package.scala:45:27] wire [1:0] _GEN_15 = {_pma_checker_entries_barrier_12_io_y_sx, _pma_checker_entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_hi_1 = _GEN_15; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_hi = _GEN_15; // @[package.scala:45:27] wire [3:0] pma_checker_r_array_hi_hi_1 = {pma_checker_r_array_hi_hi_hi_1, pma_checker_r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi_1 = {pma_checker_r_array_hi_hi_1, pma_checker_r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_1 = {pma_checker_r_array_hi_1, pma_checker_r_array_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_4 = pma_checker_priv_rw_ok & pma_checker__r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] pma_checker__r_array_T_5 = pma_checker__r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] pma_checker_r_array = {1'h1, pma_checker__r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] pma_checker__pf_ld_array_T = pma_checker_r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] pma_checker_w_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sw, _pma_checker_entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_lo = {pma_checker_w_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sw, _pma_checker_entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_hi = {pma_checker_w_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_w_array_lo = {pma_checker_w_array_lo_hi, pma_checker_w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_w_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sw, _pma_checker_entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_hi_lo = {pma_checker_w_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sw, _pma_checker_entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sw, _pma_checker_entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_w_array_hi_hi = {pma_checker_w_array_hi_hi_hi, pma_checker_w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_w_array_hi = {pma_checker_w_array_hi_hi, pma_checker_w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T = {pma_checker_w_array_hi, pma_checker_w_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_1 = pma_checker_priv_rw_ok & pma_checker__w_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_2 = pma_checker__w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] pma_checker_w_array = {1'h1, pma_checker__w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] pma_checker_x_array_lo_lo = {pma_checker_x_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_x_array_lo_hi = {pma_checker_x_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_x_array_lo = {pma_checker_x_array_lo_hi, pma_checker_x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_x_array_hi_lo = {pma_checker_x_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_x_array_hi_hi = {pma_checker_x_array_hi_hi_hi, pma_checker_x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_x_array_hi = {pma_checker_x_array_hi_hi, pma_checker_x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T = {pma_checker_x_array_hi, pma_checker_x_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_1 = pma_checker_priv_x_ok & pma_checker__x_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_2 = pma_checker__x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] pma_checker_x_array = {1'h1, pma_checker__x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] pma_checker_hr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hr, _pma_checker_entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_lo = {pma_checker_hr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hr, _pma_checker_entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_hi = {pma_checker_hr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo = {pma_checker_hr_array_lo_hi, pma_checker_hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hr, _pma_checker_entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_hi_lo = {pma_checker_hr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hr, _pma_checker_entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hr, _pma_checker_entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hr_array_hi_hi = {pma_checker_hr_array_hi_hi_hi, pma_checker_hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi = {pma_checker_hr_array_hi_hi, pma_checker_hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T = {pma_checker_hr_array_hi, pma_checker_hr_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_3 = pma_checker__hr_array_T; // @[package.scala:45:27] wire [1:0] _GEN_16 = {_pma_checker_entries_barrier_2_io_y_hx, _pma_checker_entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_lo_hi_1 = _GEN_16; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_lo_hi = _GEN_16; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_lo_1 = {pma_checker_hr_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_17 = {_pma_checker_entries_barrier_5_io_y_hx, _pma_checker_entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_hi_hi_1 = _GEN_17; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_hi_hi = _GEN_17; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_hi_1 = {pma_checker_hr_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo_1 = {pma_checker_hr_array_lo_hi_1, pma_checker_hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_18 = {_pma_checker_entries_barrier_8_io_y_hx, _pma_checker_entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_lo_hi_1 = _GEN_18; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_lo_hi = _GEN_18; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_hi_lo_1 = {pma_checker_hr_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_19 = {_pma_checker_entries_barrier_10_io_y_hx, _pma_checker_entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_lo_1 = _GEN_19; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_lo = _GEN_19; // @[package.scala:45:27] wire [1:0] _GEN_20 = {_pma_checker_entries_barrier_12_io_y_hx, _pma_checker_entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_hi_1 = _GEN_20; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_hi = _GEN_20; // @[package.scala:45:27] wire [3:0] pma_checker_hr_array_hi_hi_1 = {pma_checker_hr_array_hi_hi_hi_1, pma_checker_hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi_1 = {pma_checker_hr_array_hi_hi_1, pma_checker_hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_1 = {pma_checker_hr_array_hi_1, pma_checker_hr_array_lo_1}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hw, _pma_checker_entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_lo = {pma_checker_hw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hw, _pma_checker_entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_hi = {pma_checker_hw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hw_array_lo = {pma_checker_hw_array_lo_hi, pma_checker_hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hw, _pma_checker_entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_hi_lo = {pma_checker_hw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hw, _pma_checker_entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hw, _pma_checker_entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hw_array_hi_hi = {pma_checker_hw_array_hi_hi_hi, pma_checker_hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hw_array_hi = {pma_checker_hw_array_hi_hi, pma_checker_hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hw_array_T = {pma_checker_hw_array_hi, pma_checker_hw_array_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_lo_lo = {pma_checker_hx_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hx_array_lo_hi = {pma_checker_hx_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hx_array_lo = {pma_checker_hx_array_lo_hi, pma_checker_hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_hi_lo = {pma_checker_hx_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hx_array_hi_hi = {pma_checker_hx_array_hi_hi_hi, pma_checker_hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hx_array_hi = {pma_checker_hx_array_hi_hi, pma_checker_hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hx_array_T = {pma_checker_hx_array_hi, pma_checker_hx_array_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pr, _pma_checker_entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_lo = {pma_checker_pr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pr, _pma_checker_entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_hi = {pma_checker_pr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_lo = {pma_checker_pr_array_lo_hi, pma_checker_pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pr, _pma_checker_entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_lo = {pma_checker_pr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pr, _pma_checker_entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_hi = {pma_checker_pr_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_hi = {pma_checker_pr_array_hi_hi, pma_checker_pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pr_array_T_1 = {pma_checker_pr_array_hi, pma_checker_pr_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pr_array_T_2 = {2'h0, pma_checker__pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_21 = pma_checker_ptw_ae_array \| pma_checker_final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] pma_checker__pr_array_T_3; // @[TLB.scala:529:104] assign pma_checker__pr_array_T_3 = _GEN_21; // @[TLB.scala:529:104] wire [13:0] pma_checker__pw_array_T_3; // @[TLB.scala:531:104] assign pma_checker__pw_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :531:104] wire [13:0] pma_checker__px_array_T_3; // @[TLB.scala:533:104] assign pma_checker__px_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :533:104] wire [13:0] pma_checker__pr_array_T_4 = ~pma_checker__pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pma_checker_pr_array = pma_checker__pr_array_T_2 & pma_checker__pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] pma_checker_pw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pw, _pma_checker_entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_lo = {pma_checker_pw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pw, _pma_checker_entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_hi = {pma_checker_pw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_lo = {pma_checker_pw_array_lo_hi, pma_checker_pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pw, _pma_checker_entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_lo = {pma_checker_pw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pw, _pma_checker_entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_hi = {pma_checker_pw_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_hi = {pma_checker_pw_array_hi_hi, pma_checker_pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pw_array_T_1 = {pma_checker_pw_array_hi, pma_checker_pw_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_2 = {2'h0, pma_checker__pw_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_4 = ~pma_checker__pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pma_checker_pw_array = pma_checker__pw_array_T_2 & pma_checker__pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] pma_checker_px_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_px, _pma_checker_entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_lo = {pma_checker_px_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_px, _pma_checker_entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_hi = {pma_checker_px_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_lo = {pma_checker_px_array_lo_hi, pma_checker_px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_px_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_px, _pma_checker_entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_lo = {pma_checker_px_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_px, _pma_checker_entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_hi = {pma_checker_px_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_hi = {pma_checker_px_array_hi_hi, pma_checker_px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__px_array_T_1 = {pma_checker_px_array_hi, pma_checker_px_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_2 = {2'h0, pma_checker__px_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_4 = ~pma_checker__px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] pma_checker_px_array = pma_checker__px_array_T_2 & pma_checker__px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] pma_checker__eff_array_T = {2{_pma_checker_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] pma_checker_eff_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_eff, _pma_checker_entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_lo = {pma_checker_eff_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_eff, _pma_checker_entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_hi = {pma_checker_eff_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_lo = {pma_checker_eff_array_lo_hi, pma_checker_eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_eff_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_eff, _pma_checker_entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_lo = {pma_checker_eff_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_eff, _pma_checker_entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_hi = {pma_checker_eff_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_hi = {pma_checker_eff_array_hi_hi, pma_checker_eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__eff_array_T_1 = {pma_checker_eff_array_hi, pma_checker_eff_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_eff_array = {pma_checker__eff_array_T, pma_checker__eff_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__c_array_T = {2{pma_checker_cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_22 = {_pma_checker_entries_barrier_2_io_y_c, _pma_checker_entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_lo = {pma_checker_c_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_23 = {_pma_checker_entries_barrier_5_io_y_c, _pma_checker_entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_hi = {pma_checker_c_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_lo = {pma_checker_c_array_lo_hi, pma_checker_c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_24 = {_pma_checker_entries_barrier_8_io_y_c, _pma_checker_entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_lo = {pma_checker_c_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_25 = {_pma_checker_entries_barrier_11_io_y_c, _pma_checker_entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_hi = {pma_checker_c_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_hi = {pma_checker_c_array_hi_hi, pma_checker_c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__c_array_T_1 = {pma_checker_c_array_hi, pma_checker_c_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_c_array = {pma_checker__c_array_T, pma_checker__c_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_lrscAllowed = pma_checker_c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] pma_checker__ppp_array_T = {2{_pma_checker_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] pma_checker_ppp_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ppp, _pma_checker_entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_lo = {pma_checker_ppp_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ppp, _pma_checker_entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_hi = {pma_checker_ppp_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_lo = {pma_checker_ppp_array_lo_hi, pma_checker_ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ppp_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ppp, _pma_checker_entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_lo = {pma_checker_ppp_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_ppp, _pma_checker_entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_hi = {pma_checker_ppp_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_hi = {pma_checker_ppp_array_hi_hi, pma_checker_ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__ppp_array_T_1 = {pma_checker_ppp_array_hi, pma_checker_ppp_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array = {pma_checker__ppp_array_T, pma_checker__ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__paa_array_T = {2{_pma_checker_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] pma_checker_paa_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_paa, _pma_checker_entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_lo = {pma_checker_paa_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_paa, _pma_checker_entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_hi = {pma_checker_paa_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_lo = {pma_checker_paa_array_lo_hi, pma_checker_paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_paa_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_paa, _pma_checker_entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_lo = {pma_checker_paa_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_paa, _pma_checker_entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_hi = {pma_checker_paa_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_hi = {pma_checker_paa_array_hi_hi, pma_checker_paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__paa_array_T_1 = {pma_checker_paa_array_hi, pma_checker_paa_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_paa_array = {pma_checker__paa_array_T, pma_checker__paa_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__pal_array_T = {2{_pma_checker_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pma_checker_pal_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pal, _pma_checker_entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_lo = {pma_checker_pal_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pal, _pma_checker_entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_hi = {pma_checker_pal_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_lo = {pma_checker_pal_array_lo_hi, pma_checker_pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pal_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pal, _pma_checker_entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_lo = {pma_checker_pal_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pal, _pma_checker_entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_hi = {pma_checker_pal_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_hi = {pma_checker_pal_array_hi_hi, pma_checker_pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pal_array_T_1 = {pma_checker_pal_array_hi, pma_checker_pal_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_pal_array = {pma_checker__pal_array_T, pma_checker__pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array_if_cached = pma_checker_ppp_array \| pma_checker_c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] pma_checker_paa_array_if_cached = pma_checker_paa_array \| pma_checker_c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pma_checker_pal_array_if_cached = pma_checker_pal_array \| pma_checker_c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire pma_checker__prefetchable_array_T = pma_checker_cacheable & pma_checker_homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] pma_checker__prefetchable_array_T_1 = {pma_checker__prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] pma_checker_prefetchable_array_lo_lo = {pma_checker_prefetchable_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_lo_hi = {pma_checker_prefetchable_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_lo = {pma_checker_prefetchable_array_lo_hi, pma_checker_prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_prefetchable_array_hi_lo = {pma_checker_prefetchable_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_hi_hi = {pma_checker_prefetchable_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_hi = {pma_checker_prefetchable_array_hi_hi, pma_checker_prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__prefetchable_array_T_2 = {pma_checker_prefetchable_array_hi, pma_checker_prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_prefetchable_array = {pma_checker__prefetchable_array_T_1, pma_checker__prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] pma_checker__misaligned_T = 4'h1 << pma_checker_io_req_bits_size; // @[OneHot.scala:58:35] wire [4:0] pma_checker__misaligned_T_1 = {1'h0, pma_checker__misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] pma_checker__misaligned_T_2 = pma_checker__misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] pma_checker__misaligned_T_3 = {36'h0, pma_checker_io_req_bits_vaddr[3:0] & pma_checker__misaligned_T_2}; // @[TLB.scala:550:{39,69}] wire pma_checker_misaligned = \|pma_checker__misaligned_T_3; // @[TLB.scala:550:{39,77}] wire [39:0] pma_checker_bad_va_maskedVAddr = pma_checker_io_req_bits_vaddr & 40'hC000000000; // @[TLB.scala:559:43] wire pma_checker__bad_va_T_2 = pma_checker_bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire pma_checker__bad_va_T_3 = pma_checker_bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire pma_checker__bad_va_T_4 = pma_checker__bad_va_T_3; // @[TLB.scala:560:{71,86}] wire pma_checker__bad_va_T_5 = pma_checker__bad_va_T_2 \| pma_checker__bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire pma_checker__bad_va_T_6 = ~pma_checker__bad_va_T_5; // @[TLB.scala:560:{37,59}] wire pma_checker__bad_va_T_7 = pma_checker__bad_va_T_6; // @[TLB.scala:560:{34,37}] wire _GEN_26 = pma_checker_io_req_bits_cmd == 5'h6; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T = _GEN_26; // @[package.scala:16:47] wire pma_checker__cmd_read_T_2; // @[package.scala:16:47] assign pma_checker__cmd_read_T_2 = _GEN_26; // @[package.scala:16:47] wire _GEN_27 = pma_checker_io_req_bits_cmd == 5'h7; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T_1 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_read_T_3; // @[package.scala:16:47] assign pma_checker__cmd_read_T_3 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_write_T_3; // @[Consts.scala:90:66] assign pma_checker__cmd_write_T_3 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_2 = pma_checker__cmd_lrsc_T \| pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_lrsc = pma_checker__cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_28 = pma_checker_io_req_bits_cmd == 5'h4; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_read_T_7; // @[package.scala:16:47] assign pma_checker__cmd_read_T_7 = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_write_T_5; // @[package.scala:16:47] assign pma_checker__cmd_write_T_5 = _GEN_28; // @[package.scala:16:47] wire _GEN_29 = pma_checker_io_req_bits_cmd == 5'h9; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_1 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_read_T_8; // @[package.scala:16:47] assign pma_checker__cmd_read_T_8 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_write_T_6; // @[package.scala:16:47] assign pma_checker__cmd_write_T_6 = _GEN_29; // @[package.scala:16:47] wire _GEN_30 = pma_checker_io_req_bits_cmd == 5'hA; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_2 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_read_T_9; // @[package.scala:16:47] assign pma_checker__cmd_read_T_9 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_write_T_7; // @[package.scala:16:47] assign pma_checker__cmd_write_T_7 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = pma_checker_io_req_bits_cmd == 5'hB; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_3 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_read_T_10; // @[package.scala:16:47] assign pma_checker__cmd_read_T_10 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_write_T_8; // @[package.scala:16:47] assign pma_checker__cmd_write_T_8 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_4 = pma_checker__cmd_amo_logical_T \| pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_5 = pma_checker__cmd_amo_logical_T_4 \| pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_6 = pma_checker__cmd_amo_logical_T_5 \| pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_logical = pma_checker__cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_32 = pma_checker_io_req_bits_cmd == 5'h8; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_read_T_14; // @[package.scala:16:47] assign pma_checker__cmd_read_T_14 = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_write_T_12; // @[package.scala:16:47] assign pma_checker__cmd_write_T_12 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = pma_checker_io_req_bits_cmd == 5'hC; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_1 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_read_T_15; // @[package.scala:16:47] assign pma_checker__cmd_read_T_15 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_write_T_13; // @[package.scala:16:47] assign pma_checker__cmd_write_T_13 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = pma_checker_io_req_bits_cmd == 5'hD; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_2 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_read_T_16; // @[package.scala:16:47] assign pma_checker__cmd_read_T_16 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_write_T_14; // @[package.scala:16:47] assign pma_checker__cmd_write_T_14 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = pma_checker_io_req_bits_cmd == 5'hE; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_3 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_read_T_17; // @[package.scala:16:47] assign pma_checker__cmd_read_T_17 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_write_T_15; // @[package.scala:16:47] assign pma_checker__cmd_write_T_15 = _GEN_35; // @[package.scala:16:47] wire _GEN_36 = pma_checker_io_req_bits_cmd == 5'hF; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_4 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_read_T_18; // @[package.scala:16:47] assign pma_checker__cmd_read_T_18 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_write_T_16; // @[package.scala:16:47] assign pma_checker__cmd_write_T_16 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_5 = pma_checker__cmd_amo_arithmetic_T \| pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_6 = pma_checker__cmd_amo_arithmetic_T_5 \| pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_7 = pma_checker__cmd_amo_arithmetic_T_6 \| pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_8 = pma_checker__cmd_amo_arithmetic_T_7 \| pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_arithmetic = pma_checker__cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_37 = pma_checker_io_req_bits_cmd == 5'h11; // @[TLB.scala:573:41] wire pma_checker_cmd_put_partial; // @[TLB.scala:573:41] assign pma_checker_cmd_put_partial = _GEN_37; // @[TLB.scala:573:41] wire pma_checker__cmd_write_T_1; // @[Consts.scala:90:49] assign pma_checker__cmd_write_T_1 = _GEN_37; // @[TLB.scala:573:41] wire pma_checker__cmd_read_T = pma_checker_io_req_bits_cmd == 5'h0; // @[package.scala:16:47] wire _GEN_38 = pma_checker_io_req_bits_cmd == 5'h10; // @[package.scala:16:47] wire pma_checker__cmd_read_T_1; // @[package.scala:16:47] assign pma_checker__cmd_read_T_1 = _GEN_38; // @[package.scala:16:47] wire pma_checker__cmd_readx_T; // @[TLB.scala:575:56] assign pma_checker__cmd_readx_T = _GEN_38; // @[package.scala:16:47] wire pma_checker__cmd_read_T_4 = pma_checker__cmd_read_T \| pma_checker__cmd_read_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_5 = pma_checker__cmd_read_T_4 \| pma_checker__cmd_read_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_6 = pma_checker__cmd_read_T_5 \| pma_checker__cmd_read_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_11 = pma_checker__cmd_read_T_7 \| pma_checker__cmd_read_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_12 = pma_checker__cmd_read_T_11 \| pma_checker__cmd_read_T_9; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_13 = pma_checker__cmd_read_T_12 \| pma_checker__cmd_read_T_10; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_19 = pma_checker__cmd_read_T_14 \| pma_checker__cmd_read_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_20 = pma_checker__cmd_read_T_19 \| pma_checker__cmd_read_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_21 = pma_checker__cmd_read_T_20 \| pma_checker__cmd_read_T_17; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_22 = pma_checker__cmd_read_T_21 \| pma_checker__cmd_read_T_18; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_23 = pma_checker__cmd_read_T_13 \| pma_checker__cmd_read_T_22; // @[package.scala:81:59] wire pma_checker_cmd_read = pma_checker__cmd_read_T_6 \| pma_checker__cmd_read_T_23; // @[package.scala:81:59] wire pma_checker__cmd_write_T = pma_checker_io_req_bits_cmd == 5'h1; // @[DCache.scala:120:32] wire pma_checker__cmd_write_T_2 = pma_checker__cmd_write_T \| pma_checker__cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire pma_checker__cmd_write_T_4 = pma_checker__cmd_write_T_2 \| pma_checker__cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire pma_checker__cmd_write_T_9 = pma_checker__cmd_write_T_5 \| pma_checker__cmd_write_T_6; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_10 = pma_checker__cmd_write_T_9 \| pma_checker__cmd_write_T_7; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_11 = pma_checker__cmd_write_T_10 \| pma_checker__cmd_write_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_17 = pma_checker__cmd_write_T_12 \| pma_checker__cmd_write_T_13; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_18 = pma_checker__cmd_write_T_17 \| pma_checker__cmd_write_T_14; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_19 = pma_checker__cmd_write_T_18 \| pma_checker__cmd_write_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_20 = pma_checker__cmd_write_T_19 \| pma_checker__cmd_write_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_21 = pma_checker__cmd_write_T_11 \| pma_checker__cmd_write_T_20; // @[package.scala:81:59] wire pma_checker_cmd_write = pma_checker__cmd_write_T_4 \| pma_checker__cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire pma_checker__cmd_write_perms_T = pma_checker_io_req_bits_cmd == 5'h5; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_1 = pma_checker_io_req_bits_cmd == 5'h17; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_2 = pma_checker__cmd_write_perms_T \| pma_checker__cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_write_perms = pma_checker_cmd_write \| pma_checker__cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] pma_checker__ae_array_T = pma_checker_misaligned ? pma_checker_eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] pma_checker__ae_array_T_1 = ~pma_checker_lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] pma_checker__ae_array_T_2 = pma_checker_cmd_lrsc ? pma_checker__ae_array_T_1 : 14'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [13:0] pma_checker_ae_array = pma_checker__ae_array_T \| pma_checker__ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [13:0] pma_checker__ae_ld_array_T = ~pma_checker_pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] pma_checker__ae_ld_array_T_1 = pma_checker_ae_array \| pma_checker__ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] pma_checker_ae_ld_array = pma_checker_cmd_read ? pma_checker__ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] pma_checker__ae_st_array_T = ~pma_checker_pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] pma_checker__ae_st_array_T_1 = pma_checker_ae_array \| pma_checker__ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] pma_checker__ae_st_array_T_2 = pma_checker_cmd_write_perms ? pma_checker__ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] pma_checker__ae_st_array_T_3 = ~pma_checker_ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] pma_checker__ae_st_array_T_4 = pma_checker_cmd_put_partial ? pma_checker__ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] pma_checker__ae_st_array_T_5 = pma_checker__ae_st_array_T_2 \| pma_checker__ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] pma_checker__ae_st_array_T_6 = ~pma_checker_pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] pma_checker__ae_st_array_T_7 = pma_checker_cmd_amo_logical ? pma_checker__ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [13:0] pma_checker__ae_st_array_T_8 = pma_checker__ae_st_array_T_5 \| pma_checker__ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [13:0] pma_checker__ae_st_array_T_9 = ~pma_checker_paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] pma_checker__ae_st_array_T_10 = pma_checker_cmd_amo_arithmetic ? pma_checker__ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [13:0] pma_checker_ae_st_array = pma_checker__ae_st_array_T_8 \| pma_checker__ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [13:0] pma_checker__must_alloc_array_T = ~pma_checker_ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] pma_checker__must_alloc_array_T_1 = pma_checker_cmd_put_partial ? pma_checker__must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_2 = ~pma_checker_pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] pma_checker__must_alloc_array_T_3 = pma_checker_cmd_amo_logical ? pma_checker__must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_4 = pma_checker__must_alloc_array_T_1 \| pma_checker__must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [13:0] pma_checker__must_alloc_array_T_5 = ~pma_checker_paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] pma_checker__must_alloc_array_T_6 = pma_checker_cmd_amo_arithmetic ? pma_checker__must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [13:0] pma_checker__must_alloc_array_T_7 = pma_checker__must_alloc_array_T_4 \| pma_checker__must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [13:0] pma_checker__must_alloc_array_T_9 = {14{pma_checker_cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [13:0] pma_checker_must_alloc_array = pma_checker__must_alloc_array_T_7 \| pma_checker__must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [13:0] pma_checker__pf_ld_array_T_1 = ~pma_checker__pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] pma_checker__pf_ld_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] pma_checker__pf_ld_array_T_3 = pma_checker__pf_ld_array_T_1 & pma_checker__pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] pma_checker__pf_ld_array_T_4 = pma_checker__pf_ld_array_T_3 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] pma_checker__pf_ld_array_T_5 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] pma_checker__pf_ld_array_T_6 = pma_checker__pf_ld_array_T_4 & pma_checker__pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pma_checker_pf_ld_array = pma_checker_cmd_read ? pma_checker__pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] pma_checker__pf_st_array_T = ~pma_checker_w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] pma_checker__pf_st_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] pma_checker__pf_st_array_T_2 = pma_checker__pf_st_array_T & pma_checker__pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] pma_checker__pf_st_array_T_3 = pma_checker__pf_st_array_T_2 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] pma_checker__pf_st_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] pma_checker__pf_st_array_T_5 = pma_checker__pf_st_array_T_3 & pma_checker__pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pma_checker_pf_st_array = pma_checker_cmd_write_perms ? pma_checker__pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] pma_checker__pf_inst_array_T = ~pma_checker_x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] pma_checker__pf_inst_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] pma_checker__pf_inst_array_T_2 = pma_checker__pf_inst_array_T & pma_checker__pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] pma_checker__pf_inst_array_T_3 = pma_checker__pf_inst_array_T_2 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] pma_checker__pf_inst_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pma_checker_pf_inst_array = pma_checker__pf_inst_array_T_3 & pma_checker__pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] pma_checker__gf_ld_array_T_4 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] pma_checker__gf_ld_array_T_5 = pma_checker__gf_ld_array_T_3 & pma_checker__gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] pma_checker__gf_st_array_T_3 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] pma_checker__gf_st_array_T_4 = pma_checker__gf_st_array_T_2 & pma_checker__gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] pma_checker__gf_inst_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] pma_checker__gf_inst_array_T_3 = pma_checker__gf_inst_array_T_1 & pma_checker__gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire pma_checker__gpa_hits_hit_mask_T = pma_checker_vpn == 27'h0; // @[TLB.scala:335:30, :606:73] wire [13:0] pma_checker__io_resp_pf_ld_T_1 = pma_checker_pf_ld_array & 14'h2000; // @[TLB.scala:597:24, :633:57] wire pma_checker__io_resp_pf_ld_T_2 = \|pma_checker__io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign pma_checker__io_resp_pf_ld_T_3 = pma_checker__io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}] assign pma_checker_io_resp_pf_ld = pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire [13:0] pma_checker__io_resp_pf_st_T_1 = pma_checker_pf_st_array & 14'h2000; // @[TLB.scala:598:24, :634:64] wire pma_checker__io_resp_pf_st_T_2 = \|pma_checker__io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign pma_checker__io_resp_pf_st_T_3 = pma_checker__io_resp_pf_st_T_2; // @[TLB.scala:634:{48,72}] assign pma_checker_io_resp_pf_st = pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire [13:0] pma_checker__io_resp_pf_inst_T = pma_checker_pf_inst_array & 14'h2000; // @[TLB.scala:599:67, :635:47] wire pma_checker__io_resp_pf_inst_T_1 = \|pma_checker__io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign pma_checker__io_resp_pf_inst_T_2 = pma_checker__io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}] assign pma_checker_io_resp_pf_inst = pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire [13:0] pma_checker__io_resp_ae_ld_T = pma_checker_ae_ld_array & 14'h2000; // @[TLB.scala:586:24, :641:33] assign pma_checker__io_resp_ae_ld_T_1 = \|pma_checker__io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign pma_checker_io_resp_ae_ld = pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire [13:0] pma_checker__io_resp_ae_st_T = pma_checker_ae_st_array & 14'h2000; // @[TLB.scala:590:53, :642:33] assign pma_checker__io_resp_ae_st_T_1 = \|pma_checker__io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign pma_checker_io_resp_ae_st = pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire [13:0] pma_checker__io_resp_ae_inst_T = ~pma_checker_px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] pma_checker__io_resp_ae_inst_T_1 = pma_checker__io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:643:{23,33}] assign pma_checker__io_resp_ae_inst_T_2 = \|pma_checker__io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign pma_checker_io_resp_ae_inst = pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] assign pma_checker__io_resp_ma_ld_T = pma_checker_misaligned & pma_checker_cmd_read; // @[TLB.scala:550:77, :645:31] assign pma_checker_io_resp_ma_ld = pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] assign pma_checker__io_resp_ma_st_T = pma_checker_misaligned & pma_checker_cmd_write; // @[TLB.scala:550:77, :646:31] assign pma_checker_io_resp_ma_st = pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire [13:0] pma_checker__io_resp_cacheable_T = pma_checker_c_array & 14'h2000; // @[TLB.scala:537:20, :648:33] assign pma_checker__io_resp_cacheable_T_1 = \|pma_checker__io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign pma_checker_io_resp_cacheable = pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire [13:0] pma_checker__io_resp_must_alloc_T = pma_checker_must_alloc_array & 14'h2000; // @[TLB.scala:595:46, :649:43] assign pma_checker__io_resp_must_alloc_T_1 = \|pma_checker__io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign pma_checker_io_resp_must_alloc = pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire [13:0] pma_checker__io_resp_prefetchable_T = pma_checker_prefetchable_array & 14'h2000; // @[TLB.scala:547:31, :650:47] wire pma_checker__io_resp_prefetchable_T_1 = \|pma_checker__io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign pma_checker__io_resp_prefetchable_T_2 = pma_checker__io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign pma_checker_io_resp_prefetchable = pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] assign pma_checker__io_resp_paddr_T_1 = {pma_checker_ppn, pma_checker__io_resp_paddr_T}; // @[Mux.scala:30:73] assign pma_checker_io_resp_paddr = pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [27:0] pma_checker__io_resp_gpa_page_T_1 = {1'h0, pma_checker_vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] pma_checker_io_resp_gpa_page = pma_checker__io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [11:0] pma_checker_io_resp_gpa_offset = pma_checker__io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign pma_checker__io_resp_gpa_T = {pma_checker_io_resp_gpa_page, pma_checker_io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign pma_checker_io_resp_gpa = pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker_ignore_1 = pma_checker__ignore_T_1; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_4 = pma_checker__ignore_T_4; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_7 = pma_checker__ignore_T_7; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_10 = pma_checker__ignore_T_10; // @[TLB.scala:182:{28,34}] wire replace; // @[Replacement.scala:37:29] wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17] wire metaArb__grant_T = metaArb_io_in_0_valid; // @[Arbiter.scala:45:68] wire [39:0] _metaArb_io_in_5_bits_addr_T_2; // @[DCache.scala:1018:36] wire [5:0] _metaArb_io_in_5_bits_idx_T; // @[DCache.scala:1017:44] wire metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire [39:0] _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:454:36] wire [5:0] _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:453:35] wire [21:0] _metaArb_io_in_1_bits_data_T; // @[DCache.scala:458:14] wire metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_2_valid_T; // @[DCache.scala:462:63] wire [39:0] _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:466:36] wire [5:0] _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:465:40] wire [7:0] s2_victim_or_hit_way; // @[DCache.scala:432:33] wire [21:0] _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:467:97] wire metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_3_valid_T_2; // @[DCache.scala:741:53] wire [39:0] _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:745:36] wire [5:0] _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:744:40] wire [21:0] _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:746:134] wire metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59] wire [39:0] _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:912:36] wire [5:0] _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:1200:47] wire [7:0] releaseWay; // @[DCache.scala:232:24] wire [21:0] _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:913:97] wire metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire [5:0] _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:263:58] wire metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [5:0] _s1_meta_WIRE = metaArb_io_out_bits_idx; // @[DCache.scala:135:28, :314:35] wire [39:0] metaArb_io_in_0_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_0_bits_idx; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_1_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_1_bits_idx; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_1_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_1_ready; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_2_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_2_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_2_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_2_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_2_ready; // @[DCache.scala:135:28] wire metaArb_io_in_2_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_3_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_3_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_3_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_3_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_3_ready; // @[DCache.scala:135:28] wire metaArb_io_in_3_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_4_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_4_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_4_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_4_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_4_ready; // @[DCache.scala:135:28] wire metaArb_io_in_4_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_5_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_5_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_5_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_5_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_5_ready; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_6_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_6_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_6_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_6_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_6_ready; // @[DCache.scala:135:28] wire metaArb_io_in_6_valid; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_7_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_7_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_7_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_7_ready; // @[DCache.scala:135:28] wire metaArb_io_out_bits_write; // @[DCache.scala:135:28] wire [39:0] metaArb_io_out_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_out_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_out_bits_data; // @[DCache.scala:135:28] wire metaArb_io_out_valid; // @[DCache.scala:135:28] wire [2:0] metaArb_io_chosen; // @[DCache.scala:135:28] assign metaArb_io_chosen = metaArb_io_in_0_valid ? 3'h0 : metaArb_io_in_2_valid ? 3'h2 : metaArb_io_in_3_valid ? 3'h3 : metaArb_io_in_4_valid ? 3'h4 : {2'h3, ~metaArb_io_in_6_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17] assign metaArb_io_out_bits_write = metaArb_io_in_0_valid \| metaArb_io_in_2_valid \| metaArb_io_in_3_valid \| metaArb_io_in_4_valid; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_addr = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_addr : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_addr : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_addr : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_addr : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_addr : metaArb_io_in_7_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_idx = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_idx : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_idx : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_idx : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_idx : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_idx : metaArb_io_in_7_bits_idx; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_way_en = metaArb_io_in_0_valid ? 8'hFF : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_way_en : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_way_en : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_way_en : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_way_en : metaArb_io_in_7_bits_way_en; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_data = metaArb_io_in_0_valid ? 22'h0 : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_data : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_data : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_data : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_data : metaArb_io_in_7_bits_data; // @[Arbiter.scala:143:15, :145:26, :147:19] wire metaArb__grant_T_1 = metaArb__grant_T \| metaArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_2 = metaArb__grant_T_1 \| metaArb_io_in_3_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_3 = metaArb__grant_T_2 \| metaArb_io_in_4_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_4 = metaArb__grant_T_3; // @[Arbiter.scala:45:68] wire metaArb__grant_T_5 = metaArb__grant_T_4 \| metaArb_io_in_6_valid; // @[Arbiter.scala:45:68] wire metaArb_grant_1 = ~metaArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign metaArb__io_in_1_ready_T = metaArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_2 = ~metaArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_2_ready_T = metaArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_3 = ~metaArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_3_ready_T = metaArb_grant_3; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_4 = ~metaArb__grant_T_2; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_4_ready_T = metaArb_grant_4; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_5 = ~metaArb__grant_T_3; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_5_ready_T = metaArb_grant_5; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_6 = ~metaArb__grant_T_4; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_6_ready_T = metaArb_grant_6; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_7 = ~metaArb__grant_T_5; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_7_ready_T = metaArb_grant_7; // @[Arbiter.scala:45:78, :153:19] assign metaArb_io_in_1_ready = metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_2_ready = metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_3_ready = metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_4_ready = metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_5_ready = metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_6_ready = metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_7_ready = metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_out_valid_T = ~metaArb_grant_7; // @[Arbiter.scala:45:78, :154:19] assign metaArb__io_out_valid_T_1 = metaArb__io_out_valid_T \| metaArb_io_in_7_valid; // @[Arbiter.scala:154:{19,31}] assign metaArb_io_out_valid = metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _s1_meta_T_1; // @[DCache.scala:314:59] wire wmask_0; // @[DCache.scala:311:74] wire wmask_1; // @[DCache.scala:311:74] wire wmask_2; // @[DCache.scala:311:74] wire wmask_3; // @[DCache.scala:311:74] wire wmask_4; // @[DCache.scala:311:74] wire wmask_5; // @[DCache.scala:311:74] wire wmask_6; // @[DCache.scala:311:74] wire wmask_7; // @[DCache.scala:311:74] wire [21:0] _s1_meta_uncorrected_WIRE = _rockettile_dcache_tag_array_RW0_rdata[21:0]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_1 = _rockettile_dcache_tag_array_RW0_rdata[43:22]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_2 = _rockettile_dcache_tag_array_RW0_rdata[65:44]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_3 = _rockettile_dcache_tag_array_RW0_rdata[87:66]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_4 = _rockettile_dcache_tag_array_RW0_rdata[109:88]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_5 = _rockettile_dcache_tag_array_RW0_rdata[131:110]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_6 = _rockettile_dcache_tag_array_RW0_rdata[153:132]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_7 = _rockettile_dcache_tag_array_RW0_rdata[175:154]; // @[DescribedSRAM.scala:17:26] wire _dataArb_io_in_0_valid_T_12; // @[DCache.scala:516:27] wire pstore_drain; // @[DCache.scala:516:27] wire [127:0] _dataArb_io_in_0_bits_wdata_T_18; // @[package.scala:45:27] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_4; // @[DCache.scala:555:55] wire [7:0] _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:550:38] wire dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire [127:0] tl_d_data_encoded; // @[DCache.scala:324:31] wire dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_2_valid_T_1; // @[DCache.scala:900:41] wire [11:0] _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:903:72] wire dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_3_valid_T_58; // @[DCache.scala:242:46] wire dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [11:0] dataArb_io_in_0_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_write; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala:152:28] wire [1:0] dataArb_io_in_0_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_0_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_1_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_write; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_1_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_1_ready; // @[DCache.scala:152:28] wire dataArb_io_in_1_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_2_bits_addr; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_2_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_2_ready; // @[DCache.scala:152:28] wire dataArb_io_in_2_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_3_bits_addr; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala:152:28] wire [1:0] dataArb_io_in_3_bits_wordMask; // @[DCache.scala:152:28] wire dataArb_io_in_3_ready; // @[DCache.scala:152:28] wire dataArb_io_in_3_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_out_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_out_bits_write; // @[DCache.scala:152:28] wire [127:0] dataArb_io_out_bits_wdata; // @[DCache.scala:152:28] wire [1:0] dataArb_io_out_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_eccMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_out_valid; // @[DCache.scala:152:28] wire [1:0] dataArb_io_chosen; // @[DCache.scala:152:28] assign dataArb_io_chosen = dataArb_io_in_0_valid ? 2'h0 : dataArb_io_in_1_valid ? 2'h1 : {1'h1, ~dataArb_io_in_2_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17] assign dataArb_io_out_bits_addr = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_addr : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_addr : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_addr : dataArb_io_in_3_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_write = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_write : dataArb_io_in_1_valid & dataArb_io_in_1_bits_write; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_wdata = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wdata : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_wdata : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_wdata : dataArb_io_in_3_bits_wdata; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_wordMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wordMask : dataArb_io_in_1_valid \| dataArb_io_in_2_valid ? 2'h3 : dataArb_io_in_3_bits_wordMask; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_eccMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_eccMask : 8'hFF; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_way_en = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_way_en : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_way_en : 8'hFF; // @[Arbiter.scala:145:26, :147:19] wire dataArb__grant_T = dataArb_io_in_0_valid \| dataArb_io_in_1_valid; // @[Arbiter.scala:45:68] wire dataArb__grant_T_1 = dataArb__grant_T \| dataArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire dataArb_grant_1 = ~dataArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign dataArb__io_in_1_ready_T = dataArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_2 = ~dataArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_2_ready_T = dataArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_3 = ~dataArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_3_ready_T = dataArb_grant_3; // @[Arbiter.scala:45:78, :153:19] assign dataArb_io_in_1_ready = dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_2_ready = dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_3_ready = dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire dataArb__io_out_valid_T = ~dataArb_grant_3; // @[Arbiter.scala:45:78, :154:19] assign dataArb__io_out_valid_T_1 = dataArb__io_out_valid_T \| dataArb_io_in_3_valid; // @[Arbiter.scala:154:{19,31}] assign dataArb_io_out_valid = dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _tl_out_a_valid_T_14; // @[DCache.scala:603:37] assign nodeOut_a_deq_valid = tl_out_a_valid; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_9_opcode; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_opcode = tl_out_a_bits_opcode; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_9_param; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_param = tl_out_a_bits_param; // @[Decoupled.scala:356:21] wire [3:0] _tl_out_a_bits_T_9_size; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_size = tl_out_a_bits_size; // @[Decoupled.scala:356:21] wire _tl_out_a_bits_T_9_source; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_source = tl_out_a_bits_source; // @[Decoupled.scala:356:21] wire [31:0] _tl_out_a_bits_T_9_address; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_address = tl_out_a_bits_address; // @[Decoupled.scala:356:21] wire [15:0] _tl_out_a_bits_T_9_mask; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_mask = tl_out_a_bits_mask; // @[Decoupled.scala:356:21] wire [127:0] _tl_out_a_bits_T_9_data; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_data = tl_out_a_bits_data; // @[Decoupled.scala:356:21] wire tl_out_a_ready; // @[DCache.scala:159:22] assign tl_out_a_ready = nodeOut_a_deq_ready; // @[Decoupled.scala:356:21] assign nodeOut_a_valid = nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_opcode = nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_param = nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_size = nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_source = nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_address = nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_mask = nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_data = nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] wire _s1_valid_T = io_cpu_req_ready_0 & io_cpu_req_valid_0; // @[Decoupled.scala:51:35] reg s1_valid; // @[DCache.scala:182:25] wire _GEN_39 = nodeOut_b_ready & nodeOut_b_valid; // @[Decoupled.scala:51:35] wire _s1_probe_T; // @[Decoupled.scala:51:35] assign _s1_probe_T = _GEN_39; // @[Decoupled.scala:51:35] wire _probe_bits_T; // @[Decoupled.scala:51:35] assign _probe_bits_T = _GEN_39; // @[Decoupled.scala:51:35] reg s1_probe; // @[DCache.scala:183:25] reg [2:0] probe_bits_opcode; // @[DCache.scala:184:29] reg [1:0] probe_bits_param; // @[DCache.scala:184:29] reg [3:0] probe_bits_size; // @[DCache.scala:184:29] wire [3:0] nackResponseMessage_size = probe_bits_size; // @[Edges.scala:416:17] wire [3:0] cleanReleaseMessage_size = probe_bits_size; // @[Edges.scala:416:17] wire [3:0] dirtyReleaseMessage_size = probe_bits_size; // @[Edges.scala:433:17] reg probe_bits_source; // @[DCache.scala:184:29] assign nodeOut_c_bits_source = probe_bits_source; // @[DCache.scala:184:29] wire nackResponseMessage_source = probe_bits_source; // @[Edges.scala:416:17] wire cleanReleaseMessage_source = probe_bits_source; // @[Edges.scala:416:17] wire dirtyReleaseMessage_source = probe_bits_source; // @[Edges.scala:433:17] reg [31:0] probe_bits_address; // @[DCache.scala:184:29] assign nodeOut_c_bits_address = probe_bits_address; // @[DCache.scala:184:29] wire [31:0] nackResponseMessage_address = probe_bits_address; // @[Edges.scala:416:17] wire [31:0] cleanReleaseMessage_address = probe_bits_address; // @[Edges.scala:416:17] wire [31:0] dirtyReleaseMessage_address = probe_bits_address; // @[Edges.scala:433:17] reg [15:0] probe_bits_mask; // @[DCache.scala:184:29] reg [127:0] probe_bits_data; // @[DCache.scala:184:29] reg probe_bits_corrupt; // @[DCache.scala:184:29] wire s1_nack; // @[DCache.scala:185:28] wire _s1_valid_masked_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37] wire s1_valid_masked = s1_valid & _s1_valid_masked_T; // @[DCache.scala:182:25, :186:{34,37}] wire _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala:185:28, :187:41] wire s1_valid_not_nacked = s1_valid & _s1_valid_not_nacked_T; // @[DCache.scala:182:25, :187:{38,41}] wire _s0_clk_en_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43] wire s0_clk_en = metaArb_io_out_valid & _s0_clk_en_T; // @[DCache.scala:135:28, :190:{40,43}] wire _s1_tlb_req_T = s0_clk_en; // @[DCache.scala:190:40, :208:52] wire [39:0] _s0_req_addr_T_2; // @[DCache.scala:193:21] wire [39:0] s0_tlb_req_vaddr = s0_req_addr; // @[DCache.scala:192:24, :199:28] wire [4:0] s0_tlb_req_cmd = s0_req_cmd; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_size = s0_req_size; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_prv = s0_req_dprv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_v = s0_req_dv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_passthrough = s0_req_phys; // @[DCache.scala:192:24, :199:28] wire [33:0] _s0_req_addr_T = metaArb_io_out_bits_addr[39:6]; // @[DCache.scala:135:28, :193:47] wire [5:0] _s0_req_addr_T_1 = io_cpu_req_bits_addr_0[5:0]; // @[DCache.scala:101:7, :193:84] assign _s0_req_addr_T_2 = {_s0_req_addr_T, _s0_req_addr_T_1}; // @[DCache.scala:193:{21,47,84}] assign s0_req_addr = _s0_req_addr_T_2; // @[DCache.scala:192:24, :193:21] assign s0_req_phys = ~metaArb_io_in_7_ready \| io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :135:28, :192:24, :195:{9,34,48}] reg [39:0] s1_req_addr; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_vaddr = s1_req_addr; // @[DCache.scala:120:32, :196:25] reg [7:0] s1_req_tag; // @[DCache.scala:196:25] reg [4:0] s1_req_cmd; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala:120:32, :196:25] reg [1:0] s1_req_size; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala:120:32, :196:25] wire [1:0] s1_mask_xwr_size = s1_req_size; // @[DCache.scala:196:25] reg s1_req_signed; // @[DCache.scala:196:25] reg [1:0] s1_req_dprv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_prv = s1_req_dprv; // @[DCache.scala:120:32, :196:25] reg s1_req_dv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_v = s1_req_dv; // @[DCache.scala:120:32, :196:25] reg s1_req_phys; // @[DCache.scala:196:25] reg s1_req_no_resp; // @[DCache.scala:196:25] reg s1_req_no_alloc; // @[DCache.scala:196:25] reg s1_req_no_xcpt; // @[DCache.scala:196:25] reg [63:0] s1_req_data; // @[DCache.scala:196:25] reg [7:0] s1_req_mask; // @[DCache.scala:196:25] wire [27:0] _s1_vaddr_T = s1_req_addr[39:12]; // @[DCache.scala:196:25, :197:56] wire [11:0] _s1_vaddr_T_1 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :197:78] wire [11:0] _s1_paddr_T_3 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :197:78, :298:125] wire [39:0] s1_vaddr = {_s1_vaddr_T, _s1_vaddr_T_1}; // @[DCache.scala:197:{21,56,78}] reg [39:0] s1_tlb_req_vaddr; // @[DCache.scala:208:29] reg s1_tlb_req_passthrough; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_size; // @[DCache.scala:208:29] reg [4:0] s1_tlb_req_cmd; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_prv; // @[DCache.scala:208:29] reg s1_tlb_req_v; // @[DCache.scala:208:29] wire _GEN_40 = s1_req_cmd == 5'h0; // @[package.scala:16:47] wire _s1_read_T; // @[package.scala:16:47] assign _s1_read_T = _GEN_40; // @[package.scala:16:47] wire _pstore1_rmw_T; // @[package.scala:16:47] assign _pstore1_rmw_T = _GEN_40; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_1; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_1 = _GEN_40; // @[package.scala:16:47] wire _GEN_41 = s1_req_cmd == 5'h10; // @[package.scala:16:47] wire _s1_read_T_1; // @[package.scala:16:47] assign _s1_read_T_1 = _GEN_41; // @[package.scala:16:47] wire _pstore1_rmw_T_1; // @[package.scala:16:47] assign _pstore1_rmw_T_1 = _GEN_41; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_2; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_2 = _GEN_41; // @[package.scala:16:47] wire _GEN_42 = s1_req_cmd == 5'h6; // @[package.scala:16:47] wire _s1_read_T_2; // @[package.scala:16:47] assign _s1_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _pstore1_rmw_T_2; // @[package.scala:16:47] assign _pstore1_rmw_T_2 = _GEN_42; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_3; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_3 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = s1_req_cmd == 5'h7; // @[package.scala:16:47] wire _s1_read_T_3; // @[package.scala:16:47] assign _s1_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _s1_write_T_3; // @[Consts.scala:90:66] assign _s1_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_3; // @[package.scala:16:47] assign _pstore1_rmw_T_3 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_28; // @[Consts.scala:90:66] assign _pstore1_rmw_T_28 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_4; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_4 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_29; // @[Consts.scala:90:66] assign _io_cpu_perf_canAcceptLoadThenLoad_T_29 = _GEN_43; // @[package.scala:16:47] wire _s1_read_T_4 = _s1_read_T \| _s1_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_read_T_5 = _s1_read_T_4 \| _s1_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_read_T_6 = _s1_read_T_5 \| _s1_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_44 = s1_req_cmd == 5'h4; // @[package.scala:16:47] wire _s1_read_T_7; // @[package.scala:16:47] assign _s1_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _s1_write_T_5; // @[package.scala:16:47] assign _s1_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_7; // @[package.scala:16:47] assign _pstore1_rmw_T_7 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_30; // @[package.scala:16:47] assign _pstore1_rmw_T_30 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_8; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_8 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_31; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_31 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = s1_req_cmd == 5'h9; // @[package.scala:16:47] wire _s1_read_T_8; // @[package.scala:16:47] assign _s1_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _s1_write_T_6; // @[package.scala:16:47] assign _s1_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_8; // @[package.scala:16:47] assign _pstore1_rmw_T_8 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_31; // @[package.scala:16:47] assign _pstore1_rmw_T_31 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_9; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_9 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_32; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_32 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = s1_req_cmd == 5'hA; // @[package.scala:16:47] wire _s1_read_T_9; // @[package.scala:16:47] assign _s1_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _s1_write_T_7; // @[package.scala:16:47] assign _s1_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_9; // @[package.scala:16:47] assign _pstore1_rmw_T_9 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_32; // @[package.scala:16:47] assign _pstore1_rmw_T_32 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_10; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_10 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_33; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_33 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = s1_req_cmd == 5'hB; // @[package.scala:16:47] wire _s1_read_T_10; // @[package.scala:16:47] assign _s1_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _s1_write_T_8; // @[package.scala:16:47] assign _s1_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_10; // @[package.scala:16:47] assign _pstore1_rmw_T_10 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_33; // @[package.scala:16:47] assign _pstore1_rmw_T_33 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_11; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_11 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_34; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_34 = _GEN_47; // @[package.scala:16:47] wire _s1_read_T_11 = _s1_read_T_7 \| _s1_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_read_T_12 = _s1_read_T_11 \| _s1_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_read_T_13 = _s1_read_T_12 \| _s1_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_48 = s1_req_cmd == 5'h8; // @[package.scala:16:47] wire _s1_read_T_14; // @[package.scala:16:47] assign _s1_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _s1_write_T_12; // @[package.scala:16:47] assign _s1_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_14; // @[package.scala:16:47] assign _pstore1_rmw_T_14 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_37; // @[package.scala:16:47] assign _pstore1_rmw_T_37 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_15; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_15 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_38; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_38 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = s1_req_cmd == 5'hC; // @[package.scala:16:47] wire _s1_read_T_15; // @[package.scala:16:47] assign _s1_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _s1_write_T_13; // @[package.scala:16:47] assign _s1_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_15; // @[package.scala:16:47] assign _pstore1_rmw_T_15 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_38; // @[package.scala:16:47] assign _pstore1_rmw_T_38 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_16; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_16 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_39; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_39 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = s1_req_cmd == 5'hD; // @[package.scala:16:47] wire _s1_read_T_16; // @[package.scala:16:47] assign _s1_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _s1_write_T_14; // @[package.scala:16:47] assign _s1_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_16; // @[package.scala:16:47] assign _pstore1_rmw_T_16 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_39; // @[package.scala:16:47] assign _pstore1_rmw_T_39 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_17; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_17 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_40; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_40 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = s1_req_cmd == 5'hE; // @[package.scala:16:47] wire _s1_read_T_17; // @[package.scala:16:47] assign _s1_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _s1_write_T_15; // @[package.scala:16:47] assign _s1_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_17; // @[package.scala:16:47] assign _pstore1_rmw_T_17 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_40; // @[package.scala:16:47] assign _pstore1_rmw_T_40 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_18; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_18 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_41; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_41 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = s1_req_cmd == 5'hF; // @[package.scala:16:47] wire _s1_read_T_18; // @[package.scala:16:47] assign _s1_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _s1_write_T_16; // @[package.scala:16:47] assign _s1_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _pstore1_rmw_T_18; // @[package.scala:16:47] assign _pstore1_rmw_T_18 = _GEN_52; // @[package.scala:16:47] wire _pstore1_rmw_T_41; // @[package.scala:16:47] assign _pstore1_rmw_T_41 = _GEN_52; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_19; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_19 = _GEN_52; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_42; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_42 = _GEN_52; // @[package.scala:16:47] wire _s1_read_T_19 = _s1_read_T_14 \| _s1_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_read_T_20 = _s1_read_T_19 \| _s1_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_read_T_21 = _s1_read_T_20 \| _s1_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_read_T_22 = _s1_read_T_21 \| _s1_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_read_T_23 = _s1_read_T_13 \| _s1_read_T_22; // @[package.scala:81:59] wire s1_read = _s1_read_T_6 \| _s1_read_T_23; // @[package.scala:81:59] wire _GEN_53 = s1_req_cmd == 5'h1; // @[DCache.scala:196:25] wire _s1_write_T; // @[Consts.scala:90:32] assign _s1_write_T = _GEN_53; // @[Consts.scala:90:32] wire _pstore1_rmw_T_25; // @[Consts.scala:90:32] assign _pstore1_rmw_T_25 = _GEN_53; // @[Consts.scala:90:32] wire _io_cpu_perf_canAcceptLoadThenLoad_T_26; // @[Consts.scala:90:32] assign _io_cpu_perf_canAcceptLoadThenLoad_T_26 = _GEN_53; // @[Consts.scala:90:32] wire _T_20 = s1_req_cmd == 5'h11; // @[DCache.scala:196:25] wire _s1_write_T_1; // @[Consts.scala:90:49] assign _s1_write_T_1 = _T_20; // @[Consts.scala:90:49] wire _s1_mask_T; // @[DCache.scala:327:32] assign _s1_mask_T = _T_20; // @[DCache.scala:327:32] wire _pstore1_rmw_T_26; // @[Consts.scala:90:49] assign _pstore1_rmw_T_26 = _T_20; // @[Consts.scala:90:49] wire _pstore1_rmw_T_48; // @[DCache.scala:1191:35] assign _pstore1_rmw_T_48 = _T_20; // @[DCache.scala:1191:35] wire _io_cpu_perf_canAcceptLoadThenLoad_T_27; // @[Consts.scala:90:49] assign _io_cpu_perf_canAcceptLoadThenLoad_T_27 = _T_20; // @[Consts.scala:90:49] wire _io_cpu_perf_canAcceptLoadThenLoad_T_49; // @[DCache.scala:1191:35] assign _io_cpu_perf_canAcceptLoadThenLoad_T_49 = _T_20; // @[DCache.scala:1191:35] wire _s1_write_T_2 = _s1_write_T \| _s1_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s1_write_T_4 = _s1_write_T_2 \| _s1_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s1_write_T_9 = _s1_write_T_5 \| _s1_write_T_6; // @[package.scala:16:47, :81:59] wire _s1_write_T_10 = _s1_write_T_9 \| _s1_write_T_7; // @[package.scala:16:47, :81:59] wire _s1_write_T_11 = _s1_write_T_10 \| _s1_write_T_8; // @[package.scala:16:47, :81:59] wire _s1_write_T_17 = _s1_write_T_12 \| _s1_write_T_13; // @[package.scala:16:47, :81:59] wire _s1_write_T_18 = _s1_write_T_17 \| _s1_write_T_14; // @[package.scala:16:47, :81:59] wire _s1_write_T_19 = _s1_write_T_18 \| _s1_write_T_15; // @[package.scala:16:47, :81:59] wire _s1_write_T_20 = _s1_write_T_19 \| _s1_write_T_16; // @[package.scala:16:47, :81:59] wire _s1_write_T_21 = _s1_write_T_11 \| _s1_write_T_20; // @[package.scala:81:59] wire s1_write = _s1_write_T_4 \| _s1_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s1_readwrite = s1_read \| s1_write; // @[DCache.scala:212:30] wire _s1_sfence_T = s1_req_cmd == 5'h14; // @[DCache.scala:196:25, :213:30] wire _GEN_54 = s1_req_cmd == 5'h15; // @[DCache.scala:196:25, :213:57] wire _s1_sfence_T_1; // @[DCache.scala:213:57] assign _s1_sfence_T_1 = _GEN_54; // @[DCache.scala:213:57] wire _tlb_io_sfence_bits_hv_T; // @[DCache.scala:283:39] assign _tlb_io_sfence_bits_hv_T = _GEN_54; // @[DCache.scala:213:57, :283:39] wire _s1_sfence_T_2 = _s1_sfence_T \| _s1_sfence_T_1; // @[DCache.scala:213:{30,43,57}] wire _GEN_55 = s1_req_cmd == 5'h16; // @[DCache.scala:196:25, :213:85] wire _s1_sfence_T_3; // @[DCache.scala:213:85] assign _s1_sfence_T_3 = _GEN_55; // @[DCache.scala:213:85] wire _tlb_io_sfence_bits_hg_T; // @[DCache.scala:284:39] assign _tlb_io_sfence_bits_hg_T = _GEN_55; // @[DCache.scala:213:85, :284:39] wire s1_sfence = _s1_sfence_T_2 \| _s1_sfence_T_3; // @[DCache.scala:213:{43,71,85}] wire _s1_flush_line_T = s1_req_cmd == 5'h5; // @[DCache.scala:196:25, :214:34] wire _s1_flush_line_T_1 = s1_req_size[0]; // @[DCache.scala:196:25, :214:64] wire _tlb_io_sfence_bits_rs1_T = s1_req_size[0]; // @[DCache.scala:196:25, :214:64, :279:40] wire s1_flush_line = _s1_flush_line_T & _s1_flush_line_T_1; // @[DCache.scala:214:{34,50,64}] reg s1_flush_valid; // @[DCache.scala:215:27] reg cached_grant_wait; // @[DCache.scala:223:34] reg resetting; // @[DCache.scala:224:26] assign metaArb_io_in_0_valid = resetting; // @[DCache.scala:135:28, :224:26] reg [8:0] flushCounter; // @[DCache.scala:225:29] reg release_ack_wait; // @[DCache.scala:226:33] reg [31:0] release_ack_addr; // @[DCache.scala:227:29] reg [3:0] release_state; // @[DCache.scala:228:30] reg [7:0] refill_way; // @[DCache.scala:229:23] assign metaArb_io_in_3_bits_way_en = refill_way; // @[DCache.scala:135:28, :229:23] assign dataArb_io_in_1_bits_way_en = refill_way; // @[DCache.scala:152:28, :229:23] wire _any_pstore_valid_T; // @[DCache.scala:508:36] wire any_pstore_valid; // @[DCache.scala:230:30] wire _T_114 = release_state == 4'h1; // @[package.scala:16:47] wire _inWriteback_T; // @[package.scala:16:47] assign _inWriteback_T = _T_114; // @[package.scala:16:47] wire _canAcceptCachedGrant_T; // @[package.scala:16:47] assign _canAcceptCachedGrant_T = _T_114; // @[package.scala:16:47] wire _inWriteback_T_1 = release_state == 4'h2; // @[package.scala:16:47] wire inWriteback = _inWriteback_T \| _inWriteback_T_1; // @[package.scala:16:47, :81:59] assign metaArb_io_in_4_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_5_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_6_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_7_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] wire _io_cpu_req_ready_T = ~(\|release_state); // @[DCache.scala:228:30, :233:38] wire _io_cpu_req_ready_T_1 = ~cached_grant_wait; // @[DCache.scala:223:34, :233:54] wire _io_cpu_req_ready_T_2 = _io_cpu_req_ready_T & _io_cpu_req_ready_T_1; // @[DCache.scala:233:{38,51,54}] wire _io_cpu_req_ready_T_3 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :233:76] wire _io_cpu_req_ready_T_4 = _io_cpu_req_ready_T_2 & _io_cpu_req_ready_T_3; // @[DCache.scala:233:{51,73,76}] reg uncachedInFlight_0; // @[DCache.scala:236:33] wire _s2_valid_cached_miss_T_2 = uncachedInFlight_0; // @[DCache.scala:236:33, :425:88] wire _s2_valid_uncached_pending_T_1 = uncachedInFlight_0; // @[DCache.scala:236:33, :430:92] wire _io_cpu_ordered_T_6 = uncachedInFlight_0; // @[DCache.scala:236:33, :929:142] wire _io_cpu_store_pending_T_24 = uncachedInFlight_0; // @[DCache.scala:236:33, :930:97] wire _clock_en_reg_T_22 = uncachedInFlight_0; // @[DCache.scala:236:33, :1072:50] reg [39:0] uncachedReqs_0_addr; // @[DCache.scala:237:25] wire [39:0] uncachedResp_addr = uncachedReqs_0_addr; // @[DCache.scala:237:25, :238:30] reg [7:0] uncachedReqs_0_tag; // @[DCache.scala:237:25] wire [7:0] uncachedResp_tag = uncachedReqs_0_tag; // @[DCache.scala:237:25, :238:30] reg [4:0] uncachedReqs_0_cmd; // @[DCache.scala:237:25] wire [4:0] uncachedResp_cmd = uncachedReqs_0_cmd; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_size; // @[DCache.scala:237:25] wire [1:0] uncachedResp_size = uncachedReqs_0_size; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_signed; // @[DCache.scala:237:25] wire uncachedResp_signed = uncachedReqs_0_signed; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_dprv; // @[DCache.scala:237:25] wire [1:0] uncachedResp_dprv = uncachedReqs_0_dprv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_dv; // @[DCache.scala:237:25] wire uncachedResp_dv = uncachedReqs_0_dv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_phys; // @[DCache.scala:237:25] wire uncachedResp_phys = uncachedReqs_0_phys; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_resp; // @[DCache.scala:237:25] wire uncachedResp_no_resp = uncachedReqs_0_no_resp; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_alloc; // @[DCache.scala:237:25] wire uncachedResp_no_alloc = uncachedReqs_0_no_alloc; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25] wire uncachedResp_no_xcpt = uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25, :238:30] reg [63:0] uncachedReqs_0_data; // @[DCache.scala:237:25] wire [63:0] uncachedResp_data = uncachedReqs_0_data; // @[DCache.scala:237:25, :238:30] reg [7:0] uncachedReqs_0_mask; // @[DCache.scala:237:25] wire [7:0] uncachedResp_mask = uncachedReqs_0_mask; // @[DCache.scala:237:25, :238:30] wire _GEN_56 = io_cpu_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _s0_read_T; // @[package.scala:16:47] assign _s0_read_T = _GEN_56; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T = _GEN_56; // @[package.scala:16:47] wire _s1_did_read_T; // @[package.scala:16:47] assign _s1_did_read_T = _GEN_56; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = io_cpu_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _s0_read_T_1; // @[package.scala:16:47] assign _s0_read_T_1 = _GEN_57; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_1 = _GEN_57; // @[package.scala:16:47] wire _s1_did_read_T_1; // @[package.scala:16:47] assign _s1_did_read_T_1 = _GEN_57; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_1 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = io_cpu_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _s0_read_T_2; // @[package.scala:16:47] assign _s0_read_T_2 = _GEN_58; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_2 = _GEN_58; // @[package.scala:16:47] wire _s1_did_read_T_2; // @[package.scala:16:47] assign _s1_did_read_T_2 = _GEN_58; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_2; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_2 = _GEN_58; // @[package.scala:16:47] wire _GEN_59 = io_cpu_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _s0_read_T_3; // @[package.scala:16:47] assign _s0_read_T_3 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_3 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:66] assign _dataArb_io_in_3_valid_T_28 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_3; // @[package.scala:16:47] assign _s1_did_read_T_3 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_28; // @[Consts.scala:90:66] assign _s1_did_read_T_28 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_3; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_3 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:66] assign _pstore_drain_opportunistic_T_28 = _GEN_59; // @[package.scala:16:47] wire _s0_read_T_4 = _s0_read_T \| _s0_read_T_1; // @[package.scala:16:47, :81:59] wire _s0_read_T_5 = _s0_read_T_4 \| _s0_read_T_2; // @[package.scala:16:47, :81:59] wire _s0_read_T_6 = _s0_read_T_5 \| _s0_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_60 = io_cpu_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _s0_read_T_7; // @[package.scala:16:47] assign _s0_read_T_7 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_7; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_7 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_30; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_30 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_7; // @[package.scala:16:47] assign _s1_did_read_T_7 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_30; // @[package.scala:16:47] assign _s1_did_read_T_30 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_7; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_7 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_30; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_30 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_cpu_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _s0_read_T_8; // @[package.scala:16:47] assign _s0_read_T_8 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_8 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_31 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_8; // @[package.scala:16:47] assign _s1_did_read_T_8 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_31; // @[package.scala:16:47] assign _s1_did_read_T_31 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_8; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_8 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_31; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_31 = _GEN_61; // @[package.scala:16:47] wire _GEN_62 = io_cpu_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _s0_read_T_9; // @[package.scala:16:47] assign _s0_read_T_9 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_9 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_32 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_9; // @[package.scala:16:47] assign _s1_did_read_T_9 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_32; // @[package.scala:16:47] assign _s1_did_read_T_32 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_9; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_9 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_32; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_32 = _GEN_62; // @[package.scala:16:47] wire _GEN_63 = io_cpu_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _s0_read_T_10; // @[package.scala:16:47] assign _s0_read_T_10 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_10 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_33 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_10; // @[package.scala:16:47] assign _s1_did_read_T_10 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_33; // @[package.scala:16:47] assign _s1_did_read_T_33 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_10; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_10 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_33; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_33 = _GEN_63; // @[package.scala:16:47] wire _s0_read_T_11 = _s0_read_T_7 \| _s0_read_T_8; // @[package.scala:16:47, :81:59] wire _s0_read_T_12 = _s0_read_T_11 \| _s0_read_T_9; // @[package.scala:16:47, :81:59] wire _s0_read_T_13 = _s0_read_T_12 \| _s0_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_64 = io_cpu_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _s0_read_T_14; // @[package.scala:16:47] assign _s0_read_T_14 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_14; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_14 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_37; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_37 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_14; // @[package.scala:16:47] assign _s1_did_read_T_14 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_37; // @[package.scala:16:47] assign _s1_did_read_T_37 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_14; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_14 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_37; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_37 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_cpu_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _s0_read_T_15; // @[package.scala:16:47] assign _s0_read_T_15 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_15 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_38 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_15; // @[package.scala:16:47] assign _s1_did_read_T_15 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_38; // @[package.scala:16:47] assign _s1_did_read_T_38 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_15; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_15 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_38; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_38 = _GEN_65; // @[package.scala:16:47] wire _GEN_66 = io_cpu_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _s0_read_T_16; // @[package.scala:16:47] assign _s0_read_T_16 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_16 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_39 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_16; // @[package.scala:16:47] assign _s1_did_read_T_16 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_39; // @[package.scala:16:47] assign _s1_did_read_T_39 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_16; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_16 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_39; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_39 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_cpu_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _s0_read_T_17; // @[package.scala:16:47] assign _s0_read_T_17 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_17 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_40 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_17; // @[package.scala:16:47] assign _s1_did_read_T_17 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_40; // @[package.scala:16:47] assign _s1_did_read_T_40 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_17; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_17 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_40; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_40 = _GEN_67; // @[package.scala:16:47] wire _GEN_68 = io_cpu_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _s0_read_T_18; // @[package.scala:16:47] assign _s0_read_T_18 = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_18 = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_41 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_18; // @[package.scala:16:47] assign _s1_did_read_T_18 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_41; // @[package.scala:16:47] assign _s1_did_read_T_41 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_18; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_18 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_41; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_41 = _GEN_68; // @[package.scala:16:47] wire _s0_read_T_19 = _s0_read_T_14 \| _s0_read_T_15; // @[package.scala:16:47, :81:59] wire _s0_read_T_20 = _s0_read_T_19 \| _s0_read_T_16; // @[package.scala:16:47, :81:59] wire _s0_read_T_21 = _s0_read_T_20 \| _s0_read_T_17; // @[package.scala:16:47, :81:59] wire _s0_read_T_22 = _s0_read_T_21 \| _s0_read_T_18; // @[package.scala:16:47, :81:59] wire _s0_read_T_23 = _s0_read_T_13 \| _s0_read_T_22; // @[package.scala:81:59] wire s0_read = _s0_read_T_6 \| _s0_read_T_23; // @[package.scala:81:59] wire _GEN_69 = io_cpu_req_bits_cmd_0 == 5'h1; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T = _GEN_69; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_25; // @[Consts.scala:90:32] assign _dataArb_io_in_3_valid_T_25 = _GEN_69; // @[package.scala:16:47] wire _s1_did_read_T_25; // @[Consts.scala:90:32] assign _s1_did_read_T_25 = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_25; // @[Consts.scala:90:32] assign _pstore_drain_opportunistic_T_25 = _GEN_69; // @[package.scala:16:47] wire _GEN_70 = io_cpu_req_bits_cmd_0 == 5'h3; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T_1 = _GEN_70; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T_1 = _GEN_70; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_2 = _dataArb_io_in_3_valid_res_T \| _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_res_T_3 = ~_dataArb_io_in_3_valid_res_T_2; // @[package.scala:81:59] wire dataArb_io_in_3_valid_res = _dataArb_io_in_3_valid_res_T_3; // @[DCache.scala:1185:{15,46}] wire _dataArb_io_in_3_valid_T_4 = _dataArb_io_in_3_valid_T \| _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_5 = _dataArb_io_in_3_valid_T_4 \| _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_6 = _dataArb_io_in_3_valid_T_5 \| _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_11 = _dataArb_io_in_3_valid_T_7 \| _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_12 = _dataArb_io_in_3_valid_T_11 \| _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_13 = _dataArb_io_in_3_valid_T_12 \| _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_19 = _dataArb_io_in_3_valid_T_14 \| _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_20 = _dataArb_io_in_3_valid_T_19 \| _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_21 = _dataArb_io_in_3_valid_T_20 \| _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_22 = _dataArb_io_in_3_valid_T_21 \| _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_23 = _dataArb_io_in_3_valid_T_13 \| _dataArb_io_in_3_valid_T_22; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_24 = _dataArb_io_in_3_valid_T_6 \| _dataArb_io_in_3_valid_T_23; // @[package.scala:81:59] wire _GEN_71 = io_cpu_req_bits_cmd_0 == 5'h11; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:49] assign _dataArb_io_in_3_valid_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:35] assign _dataArb_io_in_3_valid_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _s1_did_read_T_26; // @[Consts.scala:90:49] assign _s1_did_read_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _s1_did_read_T_48; // @[DCache.scala:1191:35] assign _s1_did_read_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:49] assign _pstore_drain_opportunistic_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:35] assign _pstore_drain_opportunistic_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _dataArb_io_in_3_valid_T_27 = _dataArb_io_in_3_valid_T_25 \| _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:{32,42,49}] wire _dataArb_io_in_3_valid_T_29 = _dataArb_io_in_3_valid_T_27 \| _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:{42,59,66}] wire _dataArb_io_in_3_valid_T_34 = _dataArb_io_in_3_valid_T_30 \| _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_35 = _dataArb_io_in_3_valid_T_34 \| _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_36 = _dataArb_io_in_3_valid_T_35 \| _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_42 = _dataArb_io_in_3_valid_T_37 \| _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_43 = _dataArb_io_in_3_valid_T_42 \| _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_44 = _dataArb_io_in_3_valid_T_43 \| _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_45 = _dataArb_io_in_3_valid_T_44 \| _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_46 = _dataArb_io_in_3_valid_T_36 \| _dataArb_io_in_3_valid_T_45; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_47 = _dataArb_io_in_3_valid_T_29 \| _dataArb_io_in_3_valid_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _dataArb_io_in_3_valid_T_50 = _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:{35,45}] wire _dataArb_io_in_3_valid_T_51 = _dataArb_io_in_3_valid_T_47 & _dataArb_io_in_3_valid_T_50; // @[DCache.scala:1191:{23,45}] wire _dataArb_io_in_3_valid_T_52 = _dataArb_io_in_3_valid_T_24 \| _dataArb_io_in_3_valid_T_51; // @[DCache.scala:1190:21, :1191:23] wire _dataArb_io_in_3_valid_T_53 = ~_dataArb_io_in_3_valid_T_52; // @[DCache.scala:1186:12, :1190:21] wire _dataArb_io_in_3_valid_T_54 = _dataArb_io_in_3_valid_T_53 \| dataArb_io_in_3_valid_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _dataArb_io_in_3_valid_T_56 = ~_dataArb_io_in_3_valid_T_55; // @[DCache.scala:1186:11] wire _dataArb_io_in_3_valid_T_57 = ~_dataArb_io_in_3_valid_T_54; // @[DCache.scala:1186:{11,28}] assign _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid_0 & dataArb_io_in_3_valid_res; // @[DCache.scala:101:7, :242:46, :1185:46] assign dataArb_io_in_3_valid = _dataArb_io_in_3_valid_T_58; // @[DCache.scala:152:28, :242:46] wire [27:0] _dataArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89] wire [27:0] _metaArb_io_in_1_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :454:58] wire [27:0] _metaArb_io_in_2_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :466:58] wire [27:0] _metaArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :745:58] wire [27:0] _metaArb_io_in_4_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :912:58] wire [27:0] _metaArb_io_in_5_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :1018:58] wire [11:0] _dataArb_io_in_3_bits_addr_T_1 = io_cpu_req_bits_addr_0[11:0]; // @[DCache.scala:101:7, :245:120] wire [39:0] _dataArb_io_in_3_bits_addr_T_2 = {_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:245:{36,89,120}] assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[11:0]; // @[DCache.scala:152:28, :245:{30,36}] wire _dataArb_io_in_3_bits_wordMask_mask_upper_T = io_cpu_req_bits_addr_0[3]; // @[DCache.scala:101:7, :250:43] wire _dataArb_io_in_3_bits_wordMask_mask_lower_T = io_cpu_req_bits_addr_0[3]; // @[DCache.scala:101:7, :250:43, :251:43] wire _dataArb_io_in_3_bits_wordMask_mask_upper_T_1 = _dataArb_io_in_3_bits_wordMask_mask_upper_T; // @[DCache.scala:250:{22,43}] wire dataArb_io_in_3_bits_wordMask_mask_upper = _dataArb_io_in_3_bits_wordMask_mask_upper_T_1; // @[DCache.scala:250:{22,57}] wire dataArb_io_in_3_bits_wordMask_mask_lower = ~_dataArb_io_in_3_bits_wordMask_mask_lower_T; // @[DCache.scala:251:{22,43}] wire [1:0] dataArb_io_in_3_bits_wordMask_mask = {dataArb_io_in_3_bits_wordMask_mask_upper, dataArb_io_in_3_bits_wordMask_mask_lower}; // @[DCache.scala:250:57, :251:22, :252:13] wire [3:0] _dataArb_io_in_3_bits_wordMask_T = {2{dataArb_io_in_3_bits_wordMask_mask}}; // @[DCache.scala:252:13, :254:9] wire [7:0] _dataArb_io_in_3_bits_wordMask_T_1 = {2{_dataArb_io_in_3_bits_wordMask_T}}; // @[DCache.scala:254:9] wire [15:0] _dataArb_io_in_3_bits_wordMask_T_2 = {2{_dataArb_io_in_3_bits_wordMask_T_1}}; // @[DCache.scala:254:9] assign dataArb_io_in_3_bits_wordMask = _dataArb_io_in_3_bits_wordMask_T_2[1:0]; // @[DCache.scala:152:28, :246:34, :254:9] wire _T_4 = ~dataArb_io_in_3_ready & s0_read; // @[DCache.scala:152:28, :258:{9,33}] wire _s1_did_read_T_4 = _s1_did_read_T \| _s1_did_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_5 = _s1_did_read_T_4 \| _s1_did_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_6 = _s1_did_read_T_5 \| _s1_did_read_T_3; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_11 = _s1_did_read_T_7 \| _s1_did_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_12 = _s1_did_read_T_11 \| _s1_did_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_13 = _s1_did_read_T_12 \| _s1_did_read_T_10; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_19 = _s1_did_read_T_14 \| _s1_did_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_20 = _s1_did_read_T_19 \| _s1_did_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_21 = _s1_did_read_T_20 \| _s1_did_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_22 = _s1_did_read_T_21 \| _s1_did_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_23 = _s1_did_read_T_13 \| _s1_did_read_T_22; // @[package.scala:81:59] wire _s1_did_read_T_24 = _s1_did_read_T_6 \| _s1_did_read_T_23; // @[package.scala:81:59] wire _s1_did_read_T_27 = _s1_did_read_T_25 \| _s1_did_read_T_26; // @[Consts.scala:90:{32,42,49}] wire _s1_did_read_T_29 = _s1_did_read_T_27 \| _s1_did_read_T_28; // @[Consts.scala:90:{42,59,66}] wire _s1_did_read_T_34 = _s1_did_read_T_30 \| _s1_did_read_T_31; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_35 = _s1_did_read_T_34 \| _s1_did_read_T_32; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_36 = _s1_did_read_T_35 \| _s1_did_read_T_33; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_42 = _s1_did_read_T_37 \| _s1_did_read_T_38; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_43 = _s1_did_read_T_42 \| _s1_did_read_T_39; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_44 = _s1_did_read_T_43 \| _s1_did_read_T_40; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_45 = _s1_did_read_T_44 \| _s1_did_read_T_41; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_46 = _s1_did_read_T_36 \| _s1_did_read_T_45; // @[package.scala:81:59] wire _s1_did_read_T_47 = _s1_did_read_T_29 \| _s1_did_read_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _s1_did_read_T_50 = _s1_did_read_T_48; // @[DCache.scala:1191:{35,45}] wire _s1_did_read_T_51 = _s1_did_read_T_47 & _s1_did_read_T_50; // @[DCache.scala:1191:{23,45}] wire _s1_did_read_T_52 = _s1_did_read_T_24 \| _s1_did_read_T_51; // @[DCache.scala:1190:21, :1191:23] wire _s1_did_read_T_53 = io_cpu_req_valid_0 & _s1_did_read_T_52; // @[DCache.scala:101:7, :259:75, :1190:21] wire _s1_did_read_T_54 = dataArb_io_in_3_ready & _s1_did_read_T_53; // @[DCache.scala:152:28, :259:{54,75}] reg s1_did_read; // @[DCache.scala:259:30] reg [1:0] s1_read_mask; // @[DCache.scala:260:31] assign _metaArb_io_in_7_bits_idx_T = _dataArb_io_in_3_bits_addr_T_2[11:6]; // @[DCache.scala:245:36, :263:58] assign metaArb_io_in_7_bits_idx = _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:135:28, :263:58] wire _s1_cmd_uses_tlb_T = s1_readwrite \| s1_flush_line; // @[DCache.scala:212:30, :214:50, :270:38] wire _s1_cmd_uses_tlb_T_1 = s1_req_cmd == 5'h17; // @[DCache.scala:196:25, :270:69] wire s1_cmd_uses_tlb = _s1_cmd_uses_tlb_T \| _s1_cmd_uses_tlb_T_1; // @[DCache.scala:270:{38,55,69}] wire _tlb_io_req_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :273:55] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[DCache.scala:182:25, :273:{52,55}] wire _tlb_io_req_valid_T_2 = _tlb_io_req_valid_T_1 & s1_cmd_uses_tlb; // @[DCache.scala:270:55, :273:{52,71}] wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_2; // @[DCache.scala:273:{40,71}] wire _T_10 = ~_tlb_io_req_ready & ~io_ptw_resp_valid_0 & ~io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :119:19, :275:{9,27,30,53,56}] wire _T_14 = s1_valid & s1_cmd_uses_tlb & _tlb_io_resp_miss; // @[DCache.scala:119:19, :182:25, :270:55, :276:{39,58}] wire _tlb_io_sfence_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :278:38] wire _tlb_io_sfence_valid_T_1 = s1_valid & _tlb_io_sfence_valid_T; // @[DCache.scala:182:25, :278:{35,38}] wire _tlb_io_sfence_valid_T_2 = _tlb_io_sfence_valid_T_1 & s1_sfence; // @[DCache.scala:213:71, :278:{35,54}] wire _tlb_io_sfence_bits_rs2_T = s1_req_size[1]; // @[DCache.scala:196:25, :280:40] wire [19:0] _s1_paddr_T = s1_req_addr[31:12]; // @[DCache.scala:196:25, :298:55] wire [19:0] _s1_paddr_T_1 = _tlb_io_resp_paddr[31:12]; // @[DCache.scala:119:19, :298:99] wire [19:0] _s1_paddr_T_2 = _s1_paddr_T_1; // @[DCache.scala:298:{25,99}] wire [31:0] s1_paddr = {_s1_paddr_T_2, _s1_paddr_T_3}; // @[DCache.scala:298:{21,25,125}] wire [2:0] _s1_victim_way_T; // @[package.scala:163:13] wire [2:0] s1_victim_way; // @[DCache.scala:299:27] assign rockettile_dcache_tag_array_MPORT_en = metaArb_io_out_valid & metaArb_io_out_bits_write; // @[DCache.scala:135:28, :310:27] assign wmask_0 = metaArb_io_out_bits_way_en[0]; // @[DCache.scala:135:28, :311:74] assign wmask_1 = metaArb_io_out_bits_way_en[1]; // @[DCache.scala:135:28, :311:74] assign wmask_2 = metaArb_io_out_bits_way_en[2]; // @[DCache.scala:135:28, :311:74] assign wmask_3 = metaArb_io_out_bits_way_en[3]; // @[DCache.scala:135:28, :311:74] assign wmask_4 = metaArb_io_out_bits_way_en[4]; // @[DCache.scala:135:28, :311:74] assign wmask_5 = metaArb_io_out_bits_way_en[5]; // @[DCache.scala:135:28, :311:74] assign wmask_6 = metaArb_io_out_bits_way_en[6]; // @[DCache.scala:135:28, :311:74] assign wmask_7 = metaArb_io_out_bits_way_en[7]; // @[DCache.scala:135:28, :311:74] wire _s1_meta_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43, :314:62] assign _s1_meta_T_1 = metaArb_io_out_valid & _s1_meta_T; // @[DCache.scala:135:28, :314:{59,62}] wire [1:0] _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_0_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_0_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T = _s1_meta_uncorrected_WIRE[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_0_tag = _s1_meta_uncorrected_T; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_1 = _s1_meta_uncorrected_WIRE[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_0_coh_state = _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_1_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_1_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_2 = _s1_meta_uncorrected_WIRE_1[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_1_tag = _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_3 = _s1_meta_uncorrected_WIRE_1[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_1_coh_state = _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_2_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_2_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_4 = _s1_meta_uncorrected_WIRE_2[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_2_tag = _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_5 = _s1_meta_uncorrected_WIRE_2[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_2_coh_state = _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_3_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_3_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_6 = _s1_meta_uncorrected_WIRE_3[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_3_tag = _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_7 = _s1_meta_uncorrected_WIRE_3[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_3_coh_state = _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_9; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_8; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_4_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_4_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_8 = _s1_meta_uncorrected_WIRE_4[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_4_tag = _s1_meta_uncorrected_T_8; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_9 = _s1_meta_uncorrected_WIRE_4[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_4_coh_state = _s1_meta_uncorrected_T_9; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_11; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_10; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_5_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_5_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_10 = _s1_meta_uncorrected_WIRE_5[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_5_tag = _s1_meta_uncorrected_T_10; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_11 = _s1_meta_uncorrected_WIRE_5[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_5_coh_state = _s1_meta_uncorrected_T_11; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_13; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_12; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_6_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_6_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_12 = _s1_meta_uncorrected_WIRE_6[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_6_tag = _s1_meta_uncorrected_T_12; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_13 = _s1_meta_uncorrected_WIRE_6[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_6_coh_state = _s1_meta_uncorrected_T_13; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_15; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_14; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_7_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_7_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_14 = _s1_meta_uncorrected_WIRE_7[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_7_tag = _s1_meta_uncorrected_T_14; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_15 = _s1_meta_uncorrected_WIRE_7[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_7_coh_state = _s1_meta_uncorrected_T_15; // @[DCache.scala:315:80] wire [19:0] s1_tag = s1_paddr[31:12]; // @[DCache.scala:298:21, :316:29] wire _s1_meta_hit_way_T = \|s1_meta_uncorrected_0_coh_state; // @[Metadata.scala:50:45] wire _GEN_72 = s1_meta_uncorrected_0_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_1; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_1 = _GEN_72; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T = _GEN_72; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_2 = _s1_meta_hit_way_T & _s1_meta_hit_way_T_1; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_3 = \|s1_meta_uncorrected_1_coh_state; // @[Metadata.scala:50:45] wire _GEN_73 = s1_meta_uncorrected_1_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_4; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_4 = _GEN_73; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_4; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_4 = _GEN_73; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_5 = _s1_meta_hit_way_T_3 & _s1_meta_hit_way_T_4; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_6 = \|s1_meta_uncorrected_2_coh_state; // @[Metadata.scala:50:45] wire _GEN_74 = s1_meta_uncorrected_2_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_7; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_7 = _GEN_74; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_8; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_8 = _GEN_74; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_8 = _s1_meta_hit_way_T_6 & _s1_meta_hit_way_T_7; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_9 = \|s1_meta_uncorrected_3_coh_state; // @[Metadata.scala:50:45] wire _GEN_75 = s1_meta_uncorrected_3_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_10; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_10 = _GEN_75; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_12; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_12 = _GEN_75; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_11 = _s1_meta_hit_way_T_9 & _s1_meta_hit_way_T_10; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_12 = \|s1_meta_uncorrected_4_coh_state; // @[Metadata.scala:50:45] wire _GEN_76 = s1_meta_uncorrected_4_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_13; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_13 = _GEN_76; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_16; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_16 = _GEN_76; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_14 = _s1_meta_hit_way_T_12 & _s1_meta_hit_way_T_13; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_15 = \|s1_meta_uncorrected_5_coh_state; // @[Metadata.scala:50:45] wire _GEN_77 = s1_meta_uncorrected_5_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_16; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_16 = _GEN_77; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_20; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_20 = _GEN_77; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_17 = _s1_meta_hit_way_T_15 & _s1_meta_hit_way_T_16; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_18 = \|s1_meta_uncorrected_6_coh_state; // @[Metadata.scala:50:45] wire _GEN_78 = s1_meta_uncorrected_6_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_19; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_19 = _GEN_78; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_24; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_24 = _GEN_78; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_20 = _s1_meta_hit_way_T_18 & _s1_meta_hit_way_T_19; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_21 = \|s1_meta_uncorrected_7_coh_state; // @[Metadata.scala:50:45] wire _GEN_79 = s1_meta_uncorrected_7_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_22; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_22 = _GEN_79; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_28; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_28 = _GEN_79; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_23 = _s1_meta_hit_way_T_21 & _s1_meta_hit_way_T_22; // @[Metadata.scala:50:45] wire [1:0] s1_meta_hit_way_lo_lo = {_s1_meta_hit_way_T_5, _s1_meta_hit_way_T_2}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_lo_hi = {_s1_meta_hit_way_T_11, _s1_meta_hit_way_T_8}; // @[package.scala:45:27] wire [3:0] s1_meta_hit_way_lo = {s1_meta_hit_way_lo_hi, s1_meta_hit_way_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_hi_lo = {_s1_meta_hit_way_T_17, _s1_meta_hit_way_T_14}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_hi_hi = {_s1_meta_hit_way_T_23, _s1_meta_hit_way_T_20}; // @[package.scala:45:27] wire [3:0] s1_meta_hit_way_hi = {s1_meta_hit_way_hi_hi, s1_meta_hit_way_hi_lo}; // @[package.scala:45:27] wire [7:0] s1_hit_way = {s1_meta_hit_way_hi, s1_meta_hit_way_lo}; // @[package.scala:45:27] wire _s1_meta_hit_state_T_1 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_2 = _s1_meta_hit_state_T & _s1_meta_hit_state_T_1; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_3 = _s1_meta_hit_state_T_2 ? s1_meta_uncorrected_0_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_5 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_6 = _s1_meta_hit_state_T_4 & _s1_meta_hit_state_T_5; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_7 = _s1_meta_hit_state_T_6 ? s1_meta_uncorrected_1_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_9 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_10 = _s1_meta_hit_state_T_8 & _s1_meta_hit_state_T_9; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_11 = _s1_meta_hit_state_T_10 ? s1_meta_uncorrected_2_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_13 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_14 = _s1_meta_hit_state_T_12 & _s1_meta_hit_state_T_13; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_15 = _s1_meta_hit_state_T_14 ? s1_meta_uncorrected_3_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_17 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_18 = _s1_meta_hit_state_T_16 & _s1_meta_hit_state_T_17; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_19 = _s1_meta_hit_state_T_18 ? s1_meta_uncorrected_4_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_21 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_22 = _s1_meta_hit_state_T_20 & _s1_meta_hit_state_T_21; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_23 = _s1_meta_hit_state_T_22 ? s1_meta_uncorrected_5_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_25 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_26 = _s1_meta_hit_state_T_24 & _s1_meta_hit_state_T_25; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_27 = _s1_meta_hit_state_T_26 ? s1_meta_uncorrected_6_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_29 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_30 = _s1_meta_hit_state_T_28 & _s1_meta_hit_state_T_29; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_31 = _s1_meta_hit_state_T_30 ? s1_meta_uncorrected_7_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire [1:0] _s1_meta_hit_state_T_32 = _s1_meta_hit_state_T_3 \| _s1_meta_hit_state_T_7; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_33 = _s1_meta_hit_state_T_32 \| _s1_meta_hit_state_T_11; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_34 = _s1_meta_hit_state_T_33 \| _s1_meta_hit_state_T_15; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_35 = _s1_meta_hit_state_T_34 \| _s1_meta_hit_state_T_19; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_36 = _s1_meta_hit_state_T_35 \| _s1_meta_hit_state_T_23; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_37 = _s1_meta_hit_state_T_36 \| _s1_meta_hit_state_T_27; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_38 = _s1_meta_hit_state_T_37 \| _s1_meta_hit_state_T_31; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_WIRE = _s1_meta_hit_state_T_38; // @[DCache.scala:320:{19,32}] wire [1:0] _s1_meta_hit_state_T_39; // @[DCache.scala:320:32] wire [1:0] s1_hit_state_state; // @[DCache.scala:320:32] assign _s1_meta_hit_state_T_39 = _s1_meta_hit_state_WIRE; // @[DCache.scala:320:32] assign s1_hit_state_state = _s1_meta_hit_state_T_39; // @[DCache.scala:320:32] wire [7:0] _s1_data_way_T = inWriteback ? releaseWay : s1_hit_way; // @[package.scala:45:27, :81:59] wire [8:0] s1_data_way; // @[DCache.scala:323:32] wire [7:0] _tl_d_data_encoded_T = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_22 = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_1 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_23 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_2 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_24 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_3 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_25 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_4 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_26 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_5 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_27 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_6 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_28 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_7 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_29 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_8 = nodeOut_d_bits_data[71:64]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_30 = nodeOut_d_bits_data[71:64]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_9 = nodeOut_d_bits_data[79:72]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_31 = nodeOut_d_bits_data[79:72]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_10 = nodeOut_d_bits_data[87:80]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_32 = nodeOut_d_bits_data[87:80]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_11 = nodeOut_d_bits_data[95:88]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_33 = nodeOut_d_bits_data[95:88]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_12 = nodeOut_d_bits_data[103:96]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_34 = nodeOut_d_bits_data[103:96]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_13 = nodeOut_d_bits_data[111:104]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_35 = nodeOut_d_bits_data[111:104]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_14 = nodeOut_d_bits_data[119:112]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_36 = nodeOut_d_bits_data[119:112]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_15 = nodeOut_d_bits_data[127:120]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_37 = nodeOut_d_bits_data[127:120]; // @[package.scala:211:50] wire [15:0] tl_d_data_encoded_lo_lo_lo = {_tl_d_data_encoded_T_1, _tl_d_data_encoded_T}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_lo_hi = {_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_lo = {tl_d_data_encoded_lo_lo_hi, tl_d_data_encoded_lo_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_lo_hi_lo = {_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi_hi = {_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_hi = {tl_d_data_encoded_lo_hi_hi, tl_d_data_encoded_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_lo = {tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo_lo = {_tl_d_data_encoded_T_9, _tl_d_data_encoded_T_8}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_lo_hi = {_tl_d_data_encoded_T_11, _tl_d_data_encoded_T_10}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_lo = {tl_d_data_encoded_hi_lo_hi, tl_d_data_encoded_hi_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_hi_lo = {_tl_d_data_encoded_T_13, _tl_d_data_encoded_T_12}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi_hi = {_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_hi = {tl_d_data_encoded_hi_hi_hi, tl_d_data_encoded_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_hi = {tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo}; // @[package.scala:45:27] wire [127:0] _tl_d_data_encoded_T_16 = {tl_d_data_encoded_hi, tl_d_data_encoded_lo}; // @[package.scala:45:27] wire [127:0] _tl_d_data_encoded_T_38; // @[package.scala:45:27] assign dataArb_io_in_1_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] assign dataArb_io_in_2_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] assign dataArb_io_in_3_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] wire [127:0] s1_all_data_ways_8 = tl_d_data_encoded; // @[DCache.scala:324:31, :325:33] wire [127:0] s1_all_data_ways_0; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_1; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_2; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_3; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_4; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_5; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_6; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_7; // @[DCache.scala:325:33] wire _s1_mask_xwr_upper_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_upper_T_1 = _s1_mask_xwr_upper_T; // @[AMOALU.scala:20:{22,27}] wire _s1_mask_xwr_upper_T_2 = \|s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire _s1_mask_xwr_upper_T_3 = _s1_mask_xwr_upper_T_2; // @[AMOALU.scala:20:{47,53}] wire s1_mask_xwr_upper = _s1_mask_xwr_upper_T_1 \| _s1_mask_xwr_upper_T_3; // @[AMOALU.scala:20:{22,42,47}] wire s1_mask_xwr_lower = ~_s1_mask_xwr_lower_T; // @[AMOALU.scala:21:{22,27}] wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper, s1_mask_xwr_lower}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_4 = s1_req_addr[1]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_1 = s1_req_addr[1]; // @[DCache.scala:196:25] wire [1:0] _s1_mask_xwr_upper_T_5 = _s1_mask_xwr_upper_T_4 ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_6 = s1_mask_xwr_size[1]; // @[AMOALU.scala:11:18, :20:53] wire [1:0] _s1_mask_xwr_upper_T_7 = {2{_s1_mask_xwr_upper_T_6}}; // @[AMOALU.scala:20:{47,53}] wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 \| _s1_mask_xwr_upper_T_7; // @[AMOALU.scala:20:{22,42,47}] wire [1:0] s1_mask_xwr_lower_1 = _s1_mask_xwr_lower_T_1 ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala:21:{22,27}, :22:16] wire [3:0] _s1_mask_xwr_T_1 = {s1_mask_xwr_upper_1, s1_mask_xwr_lower_1}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_8 = s1_req_addr[2]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_2 = s1_req_addr[2]; // @[DCache.scala:196:25] wire [3:0] _s1_mask_xwr_upper_T_9 = _s1_mask_xwr_upper_T_8 ? _s1_mask_xwr_T_1 : 4'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_10 = &s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire [3:0] _s1_mask_xwr_upper_T_11 = {4{_s1_mask_xwr_upper_T_10}}; // @[AMOALU.scala:20:{47,53}] wire [3:0] s1_mask_xwr_upper_2 = _s1_mask_xwr_upper_T_9 \| _s1_mask_xwr_upper_T_11; // @[AMOALU.scala:20:{22,42,47}] wire [3:0] s1_mask_xwr_lower_2 = _s1_mask_xwr_lower_T_2 ? 4'h0 : _s1_mask_xwr_T_1; // @[AMOALU.scala:21:{22,27}, :22:16] wire [7:0] s1_mask_xwr = {s1_mask_xwr_upper_2, s1_mask_xwr_lower_2}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire [7:0] s1_mask = _s1_mask_T ? io_cpu_s1_data_mask_0 : s1_mask_xwr; // @[DCache.scala:101:7, :327:{20,32}] wire _s2_valid_T = ~s1_sfence; // @[DCache.scala:213:71, :331:45] wire _s2_valid_T_1 = s1_valid_masked & _s2_valid_T; // @[DCache.scala:186:34, :331:{42,45}] reg s2_valid; // @[DCache.scala:331:25] wire [1:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ae_ld_0, io_cpu_s2_xcpt_ae_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_2 = {io_cpu_s2_xcpt_pf_ld_0, io_cpu_s2_xcpt_pf_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_3 = {io_cpu_s2_xcpt_ma_ld_0, io_cpu_s2_xcpt_ma_st_0}; // @[DCache.scala:101:7, :332:54] wire [3:0] s2_valid_no_xcpt_lo = {2'h0, _s2_valid_no_xcpt_T}; // @[DCache.scala:332:54] wire [3:0] s2_valid_no_xcpt_hi = {_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2}; // @[DCache.scala:332:54] wire [7:0] _s2_valid_no_xcpt_T_4 = {s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo}; // @[DCache.scala:332:54] wire _s2_valid_no_xcpt_T_5 = \|_s2_valid_no_xcpt_T_4; // @[DCache.scala:332:{54,61}] wire _s2_valid_no_xcpt_T_6 = ~_s2_valid_no_xcpt_T_5; // @[DCache.scala:332:{38,61}] wire s2_valid_no_xcpt = s2_valid & _s2_valid_no_xcpt_T_6; // @[DCache.scala:331:25, :332:{35,38}] reg s2_probe; // @[DCache.scala:333:25] wire _releaseInFlight_T = s1_probe \| s2_probe; // @[DCache.scala:183:25, :333:25, :334:34] wire _releaseInFlight_T_1 = \|release_state; // @[DCache.scala:228:30, :233:38, :334:63] wire releaseInFlight = _releaseInFlight_T \| _releaseInFlight_T_1; // @[DCache.scala:334:{34,46,63}] wire _s2_not_nacked_in_s1_T = ~s1_nack; // @[DCache.scala:185:28, :187:41, :335:37] reg s2_not_nacked_in_s1; // @[DCache.scala:335:36] wire s2_valid_not_nacked_in_s1 = s2_valid & s2_not_nacked_in_s1; // @[DCache.scala:331:25, :335:36, :336:44] wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala:332:35, :335:36, :337:42] wire s2_valid_not_killed = s2_valid_masked; // @[DCache.scala:337:42, :338:45] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :397:71] wire _s2_dont_nack_misc_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :441:43] reg [39:0] s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _putpartial_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_4 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_63 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_122 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_181 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_240 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_299 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_358 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_417 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_476 = s2_req_addr; // @[DCache.scala:339:19] reg [7:0] s2_req_tag; // @[DCache.scala:339:19] assign io_cpu_resp_bits_tag_0 = s2_req_tag; // @[DCache.scala:101:7, :339:19] reg [4:0] s2_req_cmd; // @[DCache.scala:339:19] assign io_cpu_resp_bits_cmd_0 = s2_req_cmd; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_size; // @[DCache.scala:339:19] assign io_cpu_resp_bits_size_0 = s2_req_size; // @[DCache.scala:101:7, :339:19] wire [1:0] size = s2_req_size; // @[DCache.scala:339:19] reg s2_req_signed; // @[DCache.scala:339:19] assign io_cpu_resp_bits_signed_0 = s2_req_signed; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_dprv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dprv_0 = s2_req_dprv; // @[DCache.scala:101:7, :339:19] reg s2_req_dv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dv_0 = s2_req_dv; // @[DCache.scala:101:7, :339:19] reg s2_req_phys; // @[DCache.scala:339:19] reg s2_req_no_resp; // @[DCache.scala:339:19] reg s2_req_no_alloc; // @[DCache.scala:339:19] reg s2_req_no_xcpt; // @[DCache.scala:339:19] reg [63:0] s2_req_data; // @[DCache.scala:339:19] reg [7:0] s2_req_mask; // @[DCache.scala:339:19] assign io_cpu_resp_bits_mask_0 = s2_req_mask; // @[DCache.scala:101:7, :339:19] wire _GEN_80 = s2_req_cmd == 5'h5; // @[DCache.scala:339:19, :340:37] wire _s2_cmd_flush_all_T; // @[DCache.scala:340:37] assign _s2_cmd_flush_all_T = _GEN_80; // @[DCache.scala:340:37] wire _s2_cmd_flush_line_T; // @[DCache.scala:341:38] assign _s2_cmd_flush_line_T = _GEN_80; // @[DCache.scala:340:37, :341:38] wire _s2_cmd_flush_all_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68] wire _s2_cmd_flush_line_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68, :341:68] wire _s2_cmd_flush_all_T_2 = ~_s2_cmd_flush_all_T_1; // @[DCache.scala:340:{56,68}] wire s2_cmd_flush_all = _s2_cmd_flush_all_T & _s2_cmd_flush_all_T_2; // @[DCache.scala:340:{37,53,56}] wire s2_cmd_flush_line = _s2_cmd_flush_line_T & _s2_cmd_flush_line_T_1; // @[DCache.scala:341:{38,54,68}] reg s2_tlb_xcpt_miss; // @[DCache.scala:342:24] reg [31:0] s2_tlb_xcpt_paddr; // @[DCache.scala:342:24] reg [39:0] s2_tlb_xcpt_gpa; // @[DCache.scala:342:24] assign io_cpu_s2_gpa_0 = s2_tlb_xcpt_gpa; // @[DCache.scala:101:7, :342:24] reg s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24] reg s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24] reg s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24] reg [1:0] s2_tlb_xcpt_size; // @[DCache.scala:342:24] reg [4:0] s2_tlb_xcpt_cmd; // @[DCache.scala:342:24] reg s2_pma_miss; // @[DCache.scala:343:19] reg [31:0] s2_pma_paddr; // @[DCache.scala:343:19] reg [39:0] s2_pma_gpa; // @[DCache.scala:343:19] reg s2_pma_pf_ld; // @[DCache.scala:343:19] reg s2_pma_pf_st; // @[DCache.scala:343:19] reg s2_pma_pf_inst; // @[DCache.scala:343:19] reg s2_pma_ae_ld; // @[DCache.scala:343:19] reg s2_pma_ae_st; // @[DCache.scala:343:19] reg s2_pma_ae_inst; // @[DCache.scala:343:19] reg s2_pma_ma_ld; // @[DCache.scala:343:19] reg s2_pma_ma_st; // @[DCache.scala:343:19] reg s2_pma_cacheable; // @[DCache.scala:343:19] reg s2_pma_must_alloc; // @[DCache.scala:343:19] reg s2_pma_prefetchable; // @[DCache.scala:343:19] reg [1:0] s2_pma_size; // @[DCache.scala:343:19] reg [4:0] s2_pma_cmd; // @[DCache.scala:343:19] reg [39:0] s2_uncached_resp_addr; // @[DCache.scala:344:34] wire _T_30 = s1_valid_not_nacked \| s1_flush_valid; // @[DCache.scala:187:38, :215:27, :345:29] wire _s2_vaddr_T; // @[DCache.scala:351:62] assign _s2_vaddr_T = _T_30; // @[DCache.scala:345:29, :351:62] wire _s1_meta_clk_en_T; // @[DCache.scala:357:44] assign _s1_meta_clk_en_T = _T_30; // @[DCache.scala:345:29, :357:44] wire _s2_hit_state_T; // @[DCache.scala:386:66] assign _s2_hit_state_T = _T_30; // @[DCache.scala:345:29, :386:66] wire _s2_victim_way_T; // @[DCache.scala:431:77] assign _s2_victim_way_T = _T_30; // @[DCache.scala:345:29, :431:77] reg [39:0] s2_vaddr_r; // @[DCache.scala:351:31] wire [27:0] _s2_vaddr_T_1 = s2_vaddr_r[39:12]; // @[DCache.scala:351:{31,81}] wire [11:0] _s2_vaddr_T_2 = s2_req_addr[11:0]; // @[DCache.scala:339:19, :351:103] wire [39:0] s2_vaddr = {_s2_vaddr_T_1, _s2_vaddr_T_2}; // @[DCache.scala:351:{21,81,103}] wire _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala:16:47] wire _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_81 = s2_req_cmd == 5'h6; // @[package.scala:16:47] wire _s2_read_T_2; // @[package.scala:16:47] assign _s2_read_T_2 = _GEN_81; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_81; // @[package.scala:16:47] wire _s2_lr_T; // @[DCache.scala:470:70] assign _s2_lr_T = _GEN_81; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:71] assign _metaArb_io_in_3_bits_data_c_cat_T_48 = _GEN_81; // @[package.scala:16:47] wire _GEN_82 = s2_req_cmd == 5'h7; // @[package.scala:16:47] wire _s2_read_T_3; // @[package.scala:16:47] assign _s2_read_T_3 = _GEN_82; // @[package.scala:16:47] wire _s2_write_T_3; // @[Consts.scala:90:66] assign _s2_write_T_3 = _GEN_82; // @[package.scala:16:47] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _GEN_82; // @[package.scala:16:47] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _GEN_82; // @[package.scala:16:47] wire _s2_sc_T; // @[DCache.scala:471:70] assign _s2_sc_T = _GEN_82; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_3 = _GEN_82; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_26 = _GEN_82; // @[package.scala:16:47] wire _io_cpu_store_pending_T_3; // @[Consts.scala:90:66] assign _io_cpu_store_pending_T_3 = _GEN_82; // @[package.scala:16:47] wire _s2_read_T_4 = _s2_read_T \| _s2_read_T_1; // @[package.scala:16:47, :81:59] wire _s2_read_T_5 = _s2_read_T_4 \| _s2_read_T_2; // @[package.scala:16:47, :81:59] wire _s2_read_T_6 = _s2_read_T_5 \| _s2_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_83 = s2_req_cmd == 5'h4; // @[package.scala:16:47] wire _s2_read_T_7; // @[package.scala:16:47] assign _s2_read_T_7 = _GEN_83; // @[package.scala:16:47] wire _s2_write_T_5; // @[package.scala:16:47] assign _s2_write_T_5 = _GEN_83; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_83; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_83; // @[package.scala:16:47] wire _atomics_T; // @[DCache.scala:587:81] assign _atomics_T = _GEN_83; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_5; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_5 = _GEN_83; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_28; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_28 = _GEN_83; // @[package.scala:16:47] wire _io_cpu_store_pending_T_5; // @[package.scala:16:47] assign _io_cpu_store_pending_T_5 = _GEN_83; // @[package.scala:16:47] wire _GEN_84 = s2_req_cmd == 5'h9; // @[package.scala:16:47] wire _s2_read_T_8; // @[package.scala:16:47] assign _s2_read_T_8 = _GEN_84; // @[package.scala:16:47] wire _s2_write_T_6; // @[package.scala:16:47] assign _s2_write_T_6 = _GEN_84; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_84; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_84; // @[package.scala:16:47] wire _atomics_T_2; // @[DCache.scala:587:81] assign _atomics_T_2 = _GEN_84; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_6 = _GEN_84; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_29 = _GEN_84; // @[package.scala:16:47] wire _io_cpu_store_pending_T_6; // @[package.scala:16:47] assign _io_cpu_store_pending_T_6 = _GEN_84; // @[package.scala:16:47] wire _GEN_85 = s2_req_cmd == 5'hA; // @[package.scala:16:47] wire _s2_read_T_9; // @[package.scala:16:47] assign _s2_read_T_9 = _GEN_85; // @[package.scala:16:47] wire _s2_write_T_7; // @[package.scala:16:47] assign _s2_write_T_7 = _GEN_85; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_85; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_85; // @[package.scala:16:47] wire _atomics_T_4; // @[DCache.scala:587:81] assign _atomics_T_4 = _GEN_85; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_7 = _GEN_85; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_30 = _GEN_85; // @[package.scala:16:47] wire _io_cpu_store_pending_T_7; // @[package.scala:16:47] assign _io_cpu_store_pending_T_7 = _GEN_85; // @[package.scala:16:47] wire _GEN_86 = s2_req_cmd == 5'hB; // @[package.scala:16:47] wire _s2_read_T_10; // @[package.scala:16:47] assign _s2_read_T_10 = _GEN_86; // @[package.scala:16:47] wire _s2_write_T_8; // @[package.scala:16:47] assign _s2_write_T_8 = _GEN_86; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_86; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_86; // @[package.scala:16:47] wire _atomics_T_6; // @[DCache.scala:587:81] assign _atomics_T_6 = _GEN_86; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_8 = _GEN_86; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_31 = _GEN_86; // @[package.scala:16:47] wire _io_cpu_store_pending_T_8; // @[package.scala:16:47] assign _io_cpu_store_pending_T_8 = _GEN_86; // @[package.scala:16:47] wire _s2_read_T_11 = _s2_read_T_7 \| _s2_read_T_8; // @[package.scala:16:47, :81:59] wire _s2_read_T_12 = _s2_read_T_11 \| _s2_read_T_9; // @[package.scala:16:47, :81:59] wire _s2_read_T_13 = _s2_read_T_12 \| _s2_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_87 = s2_req_cmd == 5'h8; // @[package.scala:16:47] wire _s2_read_T_14; // @[package.scala:16:47] assign _s2_read_T_14 = _GEN_87; // @[package.scala:16:47] wire _s2_write_T_12; // @[package.scala:16:47] assign _s2_write_T_12 = _GEN_87; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_87; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_87; // @[package.scala:16:47] wire _atomics_T_8; // @[DCache.scala:587:81] assign _atomics_T_8 = _GEN_87; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_12; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_12 = _GEN_87; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_35; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_35 = _GEN_87; // @[package.scala:16:47] wire _io_cpu_store_pending_T_12; // @[package.scala:16:47] assign _io_cpu_store_pending_T_12 = _GEN_87; // @[package.scala:16:47] wire _GEN_88 = s2_req_cmd == 5'hC; // @[package.scala:16:47] wire _s2_read_T_15; // @[package.scala:16:47] assign _s2_read_T_15 = _GEN_88; // @[package.scala:16:47] wire _s2_write_T_13; // @[package.scala:16:47] assign _s2_write_T_13 = _GEN_88; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_88; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_88; // @[package.scala:16:47] wire _atomics_T_10; // @[DCache.scala:587:81] assign _atomics_T_10 = _GEN_88; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_13 = _GEN_88; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_36 = _GEN_88; // @[package.scala:16:47] wire _io_cpu_store_pending_T_13; // @[package.scala:16:47] assign _io_cpu_store_pending_T_13 = _GEN_88; // @[package.scala:16:47] wire _GEN_89 = s2_req_cmd == 5'hD; // @[package.scala:16:47] wire _s2_read_T_16; // @[package.scala:16:47] assign _s2_read_T_16 = _GEN_89; // @[package.scala:16:47] wire _s2_write_T_14; // @[package.scala:16:47] assign _s2_write_T_14 = _GEN_89; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_89; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_89; // @[package.scala:16:47] wire _atomics_T_12; // @[DCache.scala:587:81] assign _atomics_T_12 = _GEN_89; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_14 = _GEN_89; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_37 = _GEN_89; // @[package.scala:16:47] wire _io_cpu_store_pending_T_14; // @[package.scala:16:47] assign _io_cpu_store_pending_T_14 = _GEN_89; // @[package.scala:16:47] wire _GEN_90 = s2_req_cmd == 5'hE; // @[package.scala:16:47] wire _s2_read_T_17; // @[package.scala:16:47] assign _s2_read_T_17 = _GEN_90; // @[package.scala:16:47] wire _s2_write_T_15; // @[package.scala:16:47] assign _s2_write_T_15 = _GEN_90; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_90; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_90; // @[package.scala:16:47] wire _atomics_T_14; // @[DCache.scala:587:81] assign _atomics_T_14 = _GEN_90; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_15 = _GEN_90; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_38 = _GEN_90; // @[package.scala:16:47] wire _io_cpu_store_pending_T_15; // @[package.scala:16:47] assign _io_cpu_store_pending_T_15 = _GEN_90; // @[package.scala:16:47] wire _GEN_91 = s2_req_cmd == 5'hF; // @[package.scala:16:47] wire _s2_read_T_18; // @[package.scala:16:47] assign _s2_read_T_18 = _GEN_91; // @[package.scala:16:47] wire _s2_write_T_16; // @[package.scala:16:47] assign _s2_write_T_16 = _GEN_91; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_91; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_91; // @[package.scala:16:47] wire _atomics_T_16; // @[DCache.scala:587:81] assign _atomics_T_16 = _GEN_91; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_16 = _GEN_91; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_39 = _GEN_91; // @[package.scala:16:47] wire _io_cpu_store_pending_T_16; // @[package.scala:16:47] assign _io_cpu_store_pending_T_16 = _GEN_91; // @[package.scala:16:47] wire _s2_read_T_19 = _s2_read_T_14 \| _s2_read_T_15; // @[package.scala:16:47, :81:59] wire _s2_read_T_20 = _s2_read_T_19 \| _s2_read_T_16; // @[package.scala:16:47, :81:59] wire _s2_read_T_21 = _s2_read_T_20 \| _s2_read_T_17; // @[package.scala:16:47, :81:59] wire _s2_read_T_22 = _s2_read_T_21 \| _s2_read_T_18; // @[package.scala:16:47, :81:59] wire _s2_read_T_23 = _s2_read_T_13 \| _s2_read_T_22; // @[package.scala:81:59] assign s2_read = _s2_read_T_6 \| _s2_read_T_23; // @[package.scala:81:59] assign io_cpu_resp_bits_has_data_0 = s2_read; // @[DCache.scala:101:7] wire _GEN_92 = s2_req_cmd == 5'h1; // @[DCache.scala:339:19] wire _s2_write_T; // @[Consts.scala:90:32] assign _s2_write_T = _GEN_92; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_92; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_92; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T = _GEN_92; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T_23; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T_23 = _GEN_92; // @[Consts.scala:90:32] wire _io_cpu_store_pending_T; // @[Consts.scala:90:32] assign _io_cpu_store_pending_T = _GEN_92; // @[Consts.scala:90:32] wire _GEN_93 = s2_req_cmd == 5'h11; // @[DCache.scala:339:19] wire _s2_write_T_1; // @[Consts.scala:90:49] assign _s2_write_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_93; // @[Consts.scala:90:49] wire _tl_out_a_bits_T_4; // @[DCache.scala:610:20] assign _tl_out_a_bits_T_4 = _GEN_93; // @[DCache.scala:610:20] wire _uncachedReqs_0_cmd_T; // @[DCache.scala:637:49] assign _uncachedReqs_0_cmd_T = _GEN_93; // @[DCache.scala:637:49] wire _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_24 = _GEN_93; // @[Consts.scala:90:49] wire _io_cpu_store_pending_T_1; // @[Consts.scala:90:49] assign _io_cpu_store_pending_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _s2_write_T_2 = _s2_write_T \| _s2_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s2_write_T_4 = _s2_write_T_2 \| _s2_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s2_write_T_9 = _s2_write_T_5 \| _s2_write_T_6; // @[package.scala:16:47, :81:59] wire _s2_write_T_10 = _s2_write_T_9 \| _s2_write_T_7; // @[package.scala:16:47, :81:59] wire _s2_write_T_11 = _s2_write_T_10 \| _s2_write_T_8; // @[package.scala:16:47, :81:59] wire _s2_write_T_17 = _s2_write_T_12 \| _s2_write_T_13; // @[package.scala:16:47, :81:59] wire _s2_write_T_18 = _s2_write_T_17 \| _s2_write_T_14; // @[package.scala:16:47, :81:59] wire _s2_write_T_19 = _s2_write_T_18 \| _s2_write_T_15; // @[package.scala:16:47, :81:59] wire _s2_write_T_20 = _s2_write_T_19 \| _s2_write_T_16; // @[package.scala:16:47, :81:59] wire _s2_write_T_21 = _s2_write_T_11 \| _s2_write_T_20; // @[package.scala:81:59] wire s2_write = _s2_write_T_4 \| _s2_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s2_readwrite = s2_read \| s2_write; // @[DCache.scala:354:30] reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43] wire s2_flush_valid = s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43, :363:51] wire s1_meta_clk_en = _s1_meta_clk_en_T \| s1_probe; // @[DCache.scala:183:25, :357:{44,62}] reg [21:0] s2_meta_corrected_r; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE = s2_meta_corrected_r; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_1; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_0_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_0_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T = _s2_meta_corrected_WIRE[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_0_tag = _s2_meta_corrected_T; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_1 = _s2_meta_corrected_WIRE[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_0_coh_state = _s2_meta_corrected_T_1; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_1; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_1 = s2_meta_corrected_r_1; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_3; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_2; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_1_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_1_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_2 = _s2_meta_corrected_WIRE_1[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_1_tag = _s2_meta_corrected_T_2; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_3 = _s2_meta_corrected_WIRE_1[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_1_coh_state = _s2_meta_corrected_T_3; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_2; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_2 = s2_meta_corrected_r_2; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_5; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_4; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_2_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_2_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_4 = _s2_meta_corrected_WIRE_2[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_2_tag = _s2_meta_corrected_T_4; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_5 = _s2_meta_corrected_WIRE_2[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_2_coh_state = _s2_meta_corrected_T_5; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_3; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_3 = s2_meta_corrected_r_3; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_7; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_6; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_3_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_3_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_6 = _s2_meta_corrected_WIRE_3[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_3_tag = _s2_meta_corrected_T_6; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_7 = _s2_meta_corrected_WIRE_3[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_3_coh_state = _s2_meta_corrected_T_7; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_4; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_4 = s2_meta_corrected_r_4; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_9; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_8; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_4_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_4_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_8 = _s2_meta_corrected_WIRE_4[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_4_tag = _s2_meta_corrected_T_8; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_9 = _s2_meta_corrected_WIRE_4[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_4_coh_state = _s2_meta_corrected_T_9; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_5; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_5 = s2_meta_corrected_r_5; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_11; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_10; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_5_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_5_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_10 = _s2_meta_corrected_WIRE_5[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_5_tag = _s2_meta_corrected_T_10; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_11 = _s2_meta_corrected_WIRE_5[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_5_coh_state = _s2_meta_corrected_T_11; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_6; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_6 = s2_meta_corrected_r_6; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_13; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_12; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_6_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_6_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_12 = _s2_meta_corrected_WIRE_6[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_6_tag = _s2_meta_corrected_T_12; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_13 = _s2_meta_corrected_WIRE_6[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_6_coh_state = _s2_meta_corrected_T_13; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_7; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_7 = s2_meta_corrected_r_7; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_15; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_14; // @[DCache.scala:361:99] wire [1:0] _s2_first_meta_corrected_T_8_coh_state = s2_meta_corrected_7_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_8_tag = s2_meta_corrected_7_tag; // @[Mux.scala:50:70] assign _s2_meta_corrected_T_14 = _s2_meta_corrected_WIRE_7[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_7_tag = _s2_meta_corrected_T_14; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_15 = _s2_meta_corrected_WIRE_7[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_7_coh_state = _s2_meta_corrected_T_15; // @[DCache.scala:361:99] wire _s2_data_en_T = s1_valid \| inWriteback; // @[package.scala:81:59] wire s2_data_en = _s2_data_en_T \| io_cpu_replay_next_0; // @[DCache.scala:101:7, :366:{23,38}] wire [1:0] _s2_data_word_en_T_1 = s1_did_read ? s1_read_mask : 2'h0; // @[DCache.scala:259:30, :260:31, :367:63] wire [1:0] s2_data_word_en = inWriteback ? 2'h3 : _s2_data_word_en_T_1; // @[package.scala:81:59] wire [63:0] s2_data_s1_way_words_0_0 = s1_all_data_ways_0[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_0_1 = s1_all_data_ways_0[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_1_0 = s1_all_data_ways_1[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_1_1 = s1_all_data_ways_1[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_2_0 = s1_all_data_ways_2[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_2_1 = s1_all_data_ways_2[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_3_0 = s1_all_data_ways_3[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_3_1 = s1_all_data_ways_3[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_4_0 = s1_all_data_ways_4[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_4_1 = s1_all_data_ways_4[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_5_0 = s1_all_data_ways_5[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_5_1 = s1_all_data_ways_5[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_6_0 = s1_all_data_ways_6[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_6_1 = s1_all_data_ways_6[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_7_0 = s1_all_data_ways_7[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_7_1 = s1_all_data_ways_7[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_8_0 = s1_all_data_ways_8[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_8_1 = s1_all_data_ways_8[127:64]; // @[package.scala:211:50] wire _s2_data_s1_word_en_T = ~io_cpu_replay_next_0; // @[DCache.scala:101:7, :377:28] wire _s2_data_s1_word_en_T_1 = uncachedResp_addr[3]; // @[package.scala:163:13] wire s1_uncached_data_word_word_idx = uncachedResp_addr[3]; // @[package.scala:163:13] wire s2_data_s1_word_en_shiftAmount = _s2_data_s1_word_en_T_1; // @[OneHot.scala:64:49] wire [1:0] _s2_data_s1_word_en_T_2 = 2'h1 << s2_data_s1_word_en_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _s2_data_s1_word_en_T_3 = _s2_data_s1_word_en_T_2; // @[OneHot.scala:65:{12,27}] wire [1:0] s2_data_s1_word_en = _s2_data_s1_word_en_T ? s2_data_word_en : _s2_data_s1_word_en_T_3; // @[OneHot.scala:65:27] wire _s2_data_T = s2_data_s1_word_en[0]; // @[DCache.scala:377:27, :379:39] wire [8:0] _s2_data_T_1 = _s2_data_T ? s1_data_way : 9'h0; // @[DCache.scala:323:32, :379:{28,39}] wire _s2_data_T_2 = _s2_data_T_1[0]; // @[Mux.scala:32:36] wire _s2_data_T_3 = _s2_data_T_1[1]; // @[Mux.scala:32:36] wire _s2_data_T_4 = _s2_data_T_1[2]; // @[Mux.scala:32:36] wire _s2_data_T_5 = _s2_data_T_1[3]; // @[Mux.scala:32:36] wire _s2_data_T_6 = _s2_data_T_1[4]; // @[Mux.scala:32:36] wire _s2_data_T_7 = _s2_data_T_1[5]; // @[Mux.scala:32:36] wire _s2_data_T_8 = _s2_data_T_1[6]; // @[Mux.scala:32:36] wire _s2_data_T_9 = _s2_data_T_1[7]; // @[Mux.scala:32:36] wire _s2_data_T_10 = _s2_data_T_1[8]; // @[Mux.scala:32:36] wire [63:0] _s2_data_T_11 = _s2_data_T_2 ? s2_data_s1_way_words_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_12 = _s2_data_T_3 ? s2_data_s1_way_words_1_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_13 = _s2_data_T_4 ? s2_data_s1_way_words_2_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_14 = _s2_data_T_5 ? s2_data_s1_way_words_3_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_15 = _s2_data_T_6 ? s2_data_s1_way_words_4_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_16 = _s2_data_T_7 ? s2_data_s1_way_words_5_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_17 = _s2_data_T_8 ? s2_data_s1_way_words_6_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_18 = _s2_data_T_9 ? s2_data_s1_way_words_7_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_19 = _s2_data_T_10 ? s2_data_s1_way_words_8_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_20 = _s2_data_T_11 \| _s2_data_T_12; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_21 = _s2_data_T_20 \| _s2_data_T_13; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_22 = _s2_data_T_21 \| _s2_data_T_14; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_23 = _s2_data_T_22 \| _s2_data_T_15; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_24 = _s2_data_T_23 \| _s2_data_T_16; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_25 = _s2_data_T_24 \| _s2_data_T_17; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_26 = _s2_data_T_25 \| _s2_data_T_18; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_27 = _s2_data_T_26 \| _s2_data_T_19; // @[Mux.scala:30:73] wire [63:0] _s2_data_WIRE = _s2_data_T_27; // @[Mux.scala:30:73] reg [63:0] s2_data_r; // @[DCache.scala:379:18] wire _s2_data_T_28 = s2_data_s1_word_en[1]; // @[DCache.scala:377:27, :379:39] wire [8:0] _s2_data_T_29 = _s2_data_T_28 ? s1_data_way : 9'h0; // @[DCache.scala:323:32, :379:{28,39}] wire _s2_data_T_30 = _s2_data_T_29[0]; // @[Mux.scala:32:36] wire _s2_data_T_31 = _s2_data_T_29[1]; // @[Mux.scala:32:36] wire _s2_data_T_32 = _s2_data_T_29[2]; // @[Mux.scala:32:36] wire _s2_data_T_33 = _s2_data_T_29[3]; // @[Mux.scala:32:36] wire _s2_data_T_34 = _s2_data_T_29[4]; // @[Mux.scala:32:36] wire _s2_data_T_35 = _s2_data_T_29[5]; // @[Mux.scala:32:36] wire _s2_data_T_36 = _s2_data_T_29[6]; // @[Mux.scala:32:36] wire _s2_data_T_37 = _s2_data_T_29[7]; // @[Mux.scala:32:36] wire _s2_data_T_38 = _s2_data_T_29[8]; // @[Mux.scala:32:36] wire [63:0] _s2_data_T_39 = _s2_data_T_30 ? s2_data_s1_way_words_0_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_40 = _s2_data_T_31 ? s2_data_s1_way_words_1_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_41 = _s2_data_T_32 ? s2_data_s1_way_words_2_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_42 = _s2_data_T_33 ? s2_data_s1_way_words_3_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_43 = _s2_data_T_34 ? s2_data_s1_way_words_4_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_44 = _s2_data_T_35 ? s2_data_s1_way_words_5_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_45 = _s2_data_T_36 ? s2_data_s1_way_words_6_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_46 = _s2_data_T_37 ? s2_data_s1_way_words_7_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_47 = _s2_data_T_38 ? s2_data_s1_way_words_8_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_48 = _s2_data_T_39 \| _s2_data_T_40; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_49 = _s2_data_T_48 \| _s2_data_T_41; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_50 = _s2_data_T_49 \| _s2_data_T_42; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_51 = _s2_data_T_50 \| _s2_data_T_43; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_52 = _s2_data_T_51 \| _s2_data_T_44; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_53 = _s2_data_T_52 \| _s2_data_T_45; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_54 = _s2_data_T_53 \| _s2_data_T_46; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_55 = _s2_data_T_54 \| _s2_data_T_47; // @[Mux.scala:30:73] wire [63:0] _s2_data_WIRE_1 = _s2_data_T_55; // @[Mux.scala:30:73] reg [63:0] s2_data_r_1; // @[DCache.scala:379:18] wire [127:0] s2_data = {s2_data_r_1, s2_data_r}; // @[package.scala:45:27] reg [7:0] s2_probe_way; // @[DCache.scala:383:31] reg [1:0] s2_probe_state_state; // @[DCache.scala:384:33] reg [7:0] s2_hit_way; // @[DCache.scala:385:29] reg [1:0] s2_hit_state_state; // @[DCache.scala:386:31] wire s2_hit_valid = \|s2_hit_state_state; // @[Metadata.scala:50:45] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_94 = s2_req_cmd == 5'h3; // @[DCache.scala:339:19] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_94; // @[Consts.scala:91:54] wire _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:91:54] assign _metaArb_io_in_3_bits_data_c_cat_T_46 = _GEN_94; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T = {r_c, s2_hit_state_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_25 = _r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_27 = {1'h0, _r_T_25}; // @[Misc.scala:35:36, :49:20] wire _r_T_28 = _r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_30 = _r_T_28 ? 2'h2 : _r_T_27; // @[Misc.scala:35:36, :49:20] wire _r_T_31 = _r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_33 = _r_T_31 ? 2'h1 : _r_T_30; // @[Misc.scala:35:36, :49:20] wire _r_T_34 = _r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_36 = _r_T_34 ? 2'h2 : _r_T_33; // @[Misc.scala:35:36, :49:20] wire _r_T_37 = _r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_39 = _r_T_37 ? 2'h0 : _r_T_36; // @[Misc.scala:35:36, :49:20] wire _r_T_40 = _r_T == 4'hE; // @[Misc.scala:49:20] wire _r_T_41 = _r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_42 = _r_T_40 ? 2'h3 : _r_T_39; // @[Misc.scala:35:36, :49:20] wire _r_T_43 = &_r_T; // @[Misc.scala:49:20] wire _r_T_44 = _r_T_43 \| _r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_45 = _r_T_43 ? 2'h3 : _r_T_42; // @[Misc.scala:35:36, :49:20] wire _r_T_46 = _r_T == 4'h6; // @[Misc.scala:49:20] wire _r_T_47 = _r_T_46 \| _r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_48 = _r_T_46 ? 2'h2 : _r_T_45; // @[Misc.scala:35:36, :49:20] wire _r_T_49 = _r_T == 4'h7; // @[Misc.scala:49:20] wire _r_T_50 = _r_T_49 \| _r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_51 = _r_T_49 ? 2'h3 : _r_T_48; // @[Misc.scala:35:36, :49:20] wire _r_T_52 = _r_T == 4'h1; // @[Misc.scala:49:20] wire _r_T_53 = _r_T_52 \| _r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_54 = _r_T_52 ? 2'h1 : _r_T_51; // @[Misc.scala:35:36, :49:20] wire _r_T_55 = _r_T == 4'h2; // @[Misc.scala:49:20] wire _r_T_56 = _r_T_55 \| _r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_57 = _r_T_55 ? 2'h2 : _r_T_54; // @[Misc.scala:35:36, :49:20] wire _r_T_58 = _r_T == 4'h3; // @[Misc.scala:49:20] wire s2_hit = _r_T_58 \| _r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] s2_grow_param = _r_T_58 ? 2'h3 : _r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] s2_new_hit_state_state = s2_grow_param; // @[Misc.scala:35:36] wire [1:0] metaArb_io_in_2_bits_data_meta_coh_state = s2_new_hit_state_state; // @[Metadata.scala:160:20] wire s2_word_idx = s2_req_addr[3]; // @[package.scala:163:13] wire _a_mask_T = s2_req_addr[3]; // @[package.scala:163:13] wire get_a_mask_sub_sub_sub_bit = s2_req_addr[3]; // @[package.scala:163:13] wire put_a_mask_sub_sub_sub_bit = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_1 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_2 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_3 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_4 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_5 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_6 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_7 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_8 = s2_req_addr[3]; // @[package.scala:163:13] wire [15:0] s2_data_corrected_lo_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_lo_lo = {s2_data_corrected_lo_lo_hi, s2_data_corrected_lo_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_lo_hi = {s2_data_corrected_lo_hi_hi, s2_data_corrected_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_corrected_lo = {s2_data_corrected_lo_hi, s2_data_corrected_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_lo_lo = s2_data[79:64]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_lo_lo = s2_data[79:64]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_lo_hi = s2_data[95:80]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_lo_hi = s2_data[95:80]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_hi_lo = {s2_data_corrected_hi_lo_hi, s2_data_corrected_hi_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_hi_lo = s2_data[111:96]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_hi_lo = s2_data[111:96]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_hi_hi = s2_data[127:112]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_hi_hi = s2_data[127:112]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_hi_hi = {s2_data_corrected_hi_hi_hi, s2_data_corrected_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_corrected_hi = {s2_data_corrected_hi_hi, s2_data_corrected_hi_lo}; // @[package.scala:45:27] assign s2_data_corrected = {s2_data_corrected_hi, s2_data_corrected_lo}; // @[package.scala:45:27] assign nodeOut_c_bits_data = s2_data_corrected; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_lo_lo = {s2_data_uncorrected_lo_lo_hi, s2_data_uncorrected_lo_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_lo_hi = {s2_data_uncorrected_lo_hi_hi, s2_data_uncorrected_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_uncorrected_lo = {s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_hi_lo = {s2_data_uncorrected_hi_lo_hi, s2_data_uncorrected_hi_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_hi_hi = {s2_data_uncorrected_hi_hi_hi, s2_data_uncorrected_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_uncorrected_hi = {s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo}; // @[package.scala:45:27] wire [127:0] s2_data_uncorrected = {s2_data_uncorrected_hi, s2_data_uncorrected_lo}; // @[package.scala:45:27] wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 & s2_hit; // @[Misc.scala:35:9] wire _s2_valid_hit_pre_data_ecc_and_waw_T = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala:354:30, :397:89, :418:89] wire s2_valid_hit_pre_data_ecc_and_waw = _s2_valid_hit_pre_data_ecc_and_waw_T; // @[DCache.scala:418:{89,105}] wire s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala:418:105, :420:69] wire s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_cmd_flush_line; // @[DCache.scala:341:54, :397:89, :419:75] wire _s2_victim_tag_T = s2_valid_flush_line; // @[DCache.scala:419:75, :433:47] wire s2_valid_hit = s2_valid_hit_pre_data_ecc; // @[DCache.scala:420:69, :422:48] wire _s2_valid_miss_T = s2_valid_masked & s2_readwrite; // @[DCache.scala:337:42, :354:30, :423:39] wire _s2_valid_miss_T_2 = _s2_valid_miss_T; // @[DCache.scala:423:{39,55}] wire _s2_valid_miss_T_3 = ~s2_hit; // @[Misc.scala:35:9] wire s2_valid_miss = _s2_valid_miss_T_2 & _s2_valid_miss_T_3; // @[DCache.scala:423:{55,73,76}] wire _s2_uncached_T = ~s2_pma_cacheable; // @[DCache.scala:343:19, :424:21] wire _s2_uncached_T_1 = ~s2_pma_must_alloc; // @[DCache.scala:343:19, :424:61] wire _s2_uncached_T_2 = s2_req_no_alloc & _s2_uncached_T_1; // @[DCache.scala:339:19, :424:{58,61}] wire _s2_uncached_T_3 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _s2_uncached_T_4 = _s2_uncached_T_2 & _s2_uncached_T_3; // @[DCache.scala:424:{58,80,83}] wire s2_uncached = _s2_uncached_T \| _s2_uncached_T_4; // @[DCache.scala:424:{21,39,80}] wire _s2_valid_cached_miss_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47] wire _s2_valid_cached_miss_T_1 = s2_valid_miss & _s2_valid_cached_miss_T; // @[DCache.scala:423:73, :425:{44,47}] wire _s2_valid_cached_miss_T_3 = ~_s2_valid_cached_miss_T_2; // @[DCache.scala:425:{63,88}] wire s2_valid_cached_miss = _s2_valid_cached_miss_T_1 & _s2_valid_cached_miss_T_3; // @[DCache.scala:425:{44,60,63}] wire _s2_want_victimize_T = s2_valid_cached_miss \| s2_valid_flush_line; // @[DCache.scala:419:75, :425:60, :427:77] wire _s2_want_victimize_T_1 = _s2_want_victimize_T; // @[DCache.scala:427:{77,100}] wire _s2_want_victimize_T_2 = _s2_want_victimize_T_1 \| s2_flush_valid; // @[DCache.scala:363:51, :427:{100,123}] wire s2_want_victimize = _s2_want_victimize_T_2; // @[DCache.scala:427:{52,123}] wire s2_victimize = s2_want_victimize; // @[DCache.scala:427:52, :429:40] wire _s2_cannot_victimize_T = ~s2_flush_valid; // @[DCache.scala:363:51, :428:29] wire _s2_valid_uncached_pending_T = s2_valid_miss & s2_uncached; // @[DCache.scala:423:73, :424:39, :430:49] wire _s2_valid_uncached_pending_T_2 = ~_s2_valid_uncached_pending_T_1; // @[DCache.scala:430:{67,92}] wire s2_valid_uncached_pending = _s2_valid_uncached_pending_T & _s2_valid_uncached_pending_T_2; // @[DCache.scala:430:{49,64,67}] reg [2:0] s2_victim_way_r; // @[DCache.scala:431:41] wire [7:0] s2_victim_way = 8'h1 << s2_victim_way_r; // @[OneHot.scala:58:35] assign s2_victim_or_hit_way = s2_hit_valid ? s2_hit_way : s2_victim_way; // @[OneHot.scala:58:35] assign metaArb_io_in_2_bits_way_en = s2_victim_or_hit_way; // @[DCache.scala:135:28, :432:33] wire [19:0] _s2_victim_tag_T_1 = s2_req_addr[31:12]; // @[DCache.scala:339:19, :433:82] wire _s2_victim_tag_T_2 = s2_victim_way[0]; // @[OneHot.scala:58:35] wire _s2_victim_state_T = s2_victim_way[0]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_3 = s2_victim_way[1]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_1 = s2_victim_way[1]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_4 = s2_victim_way[2]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_2 = s2_victim_way[2]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_5 = s2_victim_way[3]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_3 = s2_victim_way[3]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_6 = s2_victim_way[4]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_4 = s2_victim_way[4]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_7 = s2_victim_way[5]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_5 = s2_victim_way[5]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_8 = s2_victim_way[6]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_6 = s2_victim_way[6]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_9 = s2_victim_way[7]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_7 = s2_victim_way[7]; // @[OneHot.scala:58:35] wire [1:0] _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_10 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_11 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_12 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_13 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_14 = _s2_victim_tag_T_6 ? s2_meta_corrected_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_15 = _s2_victim_tag_T_7 ? s2_meta_corrected_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_16 = _s2_victim_tag_T_8 ? s2_meta_corrected_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_17 = _s2_victim_tag_T_9 ? s2_meta_corrected_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_18 = _s2_victim_tag_T_10 \| _s2_victim_tag_T_11; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_19 = _s2_victim_tag_T_18 \| _s2_victim_tag_T_12; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_20 = _s2_victim_tag_T_19 \| _s2_victim_tag_T_13; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_21 = _s2_victim_tag_T_20 \| _s2_victim_tag_T_14; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_22 = _s2_victim_tag_T_21 \| _s2_victim_tag_T_15; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_23 = _s2_victim_tag_T_22 \| _s2_victim_tag_T_16; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_24 = _s2_victim_tag_T_23 \| _s2_victim_tag_T_17; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_1 = _s2_victim_tag_T_24; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_WIRE_tag = _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_WIRE_coh_state = _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_25 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_26 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_27 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_28 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_29 = _s2_victim_tag_T_6 ? s2_meta_corrected_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_30 = _s2_victim_tag_T_7 ? s2_meta_corrected_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_31 = _s2_victim_tag_T_8 ? s2_meta_corrected_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_32 = _s2_victim_tag_T_9 ? s2_meta_corrected_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_33 = _s2_victim_tag_T_25 \| _s2_victim_tag_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_34 = _s2_victim_tag_T_33 \| _s2_victim_tag_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_35 = _s2_victim_tag_T_34 \| _s2_victim_tag_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_36 = _s2_victim_tag_T_35 \| _s2_victim_tag_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_37 = _s2_victim_tag_T_36 \| _s2_victim_tag_T_30; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_38 = _s2_victim_tag_T_37 \| _s2_victim_tag_T_31; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_39 = _s2_victim_tag_T_38 \| _s2_victim_tag_T_32; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_3 = _s2_victim_tag_T_39; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_2_state = _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73] wire [19:0] s2_victim_tag = _s2_victim_tag_T ? _s2_victim_tag_T_1 : _s2_victim_tag_WIRE_tag; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_WIRE_1; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_8 = _s2_victim_state_T ? s2_meta_corrected_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_9 = _s2_victim_state_T_1 ? s2_meta_corrected_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_10 = _s2_victim_state_T_2 ? s2_meta_corrected_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_11 = _s2_victim_state_T_3 ? s2_meta_corrected_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_12 = _s2_victim_state_T_4 ? s2_meta_corrected_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_13 = _s2_victim_state_T_5 ? s2_meta_corrected_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_14 = _s2_victim_state_T_6 ? s2_meta_corrected_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_15 = _s2_victim_state_T_7 ? s2_meta_corrected_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_16 = _s2_victim_state_T_8 \| _s2_victim_state_T_9; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_17 = _s2_victim_state_T_16 \| _s2_victim_state_T_10; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_18 = _s2_victim_state_T_17 \| _s2_victim_state_T_11; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_19 = _s2_victim_state_T_18 \| _s2_victim_state_T_12; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_20 = _s2_victim_state_T_19 \| _s2_victim_state_T_13; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_21 = _s2_victim_state_T_20 \| _s2_victim_state_T_14; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_22 = _s2_victim_state_T_21 \| _s2_victim_state_T_15; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_1 = _s2_victim_state_T_22; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_WIRE_tag = _s2_victim_state_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_coh_state = _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_23 = _s2_victim_state_T ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_24 = _s2_victim_state_T_1 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_25 = _s2_victim_state_T_2 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_26 = _s2_victim_state_T_3 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_27 = _s2_victim_state_T_4 ? s2_meta_corrected_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_28 = _s2_victim_state_T_5 ? s2_meta_corrected_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_29 = _s2_victim_state_T_6 ? s2_meta_corrected_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_30 = _s2_victim_state_T_7 ? s2_meta_corrected_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_31 = _s2_victim_state_T_23 \| _s2_victim_state_T_24; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_32 = _s2_victim_state_T_31 \| _s2_victim_state_T_25; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_33 = _s2_victim_state_T_32 \| _s2_victim_state_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_34 = _s2_victim_state_T_33 \| _s2_victim_state_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_35 = _s2_victim_state_T_34 \| _s2_victim_state_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_36 = _s2_victim_state_T_35 \| _s2_victim_state_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_37 = _s2_victim_state_T_36 \| _s2_victim_state_T_30; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_3 = _s2_victim_state_T_37; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_2_state = _s2_victim_state_WIRE_3; // @[Mux.scala:30:73] wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : _s2_victim_state_WIRE_coh_state; // @[Mux.scala:30:73] wire [3:0] _r_T_59 = {probe_bits_param, s2_probe_state_state}; // @[Metadata.scala:120:19] wire _r_T_72 = _r_T_59 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_74 = _r_T_72 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_76 = _r_T_59 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_78 = _r_T_76 ? 3'h2 : _r_T_74; // @[Misc.scala:38:36, :56:20] wire _r_T_80 = _r_T_59 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_82 = _r_T_80 ? 3'h1 : _r_T_78; // @[Misc.scala:38:36, :56:20] wire _r_T_84 = _r_T_59 == 4'hB; // @[Misc.scala:56:20] wire _r_T_85 = _r_T_84; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_86 = _r_T_84 ? 3'h1 : _r_T_82; // @[Misc.scala:38:36, :56:20] wire _r_T_88 = _r_T_59 == 4'h4; // @[Misc.scala:56:20] wire _r_T_89 = ~_r_T_88 & _r_T_85; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_90 = _r_T_88 ? 3'h5 : _r_T_86; // @[Misc.scala:38:36, :56:20] wire _r_T_92 = _r_T_59 == 4'h5; // @[Misc.scala:56:20] wire _r_T_93 = ~_r_T_92 & _r_T_89; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_94 = _r_T_92 ? 3'h4 : _r_T_90; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_95 = {1'h0, _r_T_92}; // @[Misc.scala:38:63, :56:20] wire _r_T_96 = _r_T_59 == 4'h6; // @[Misc.scala:56:20] wire _r_T_97 = ~_r_T_96 & _r_T_93; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_98 = _r_T_96 ? 3'h0 : _r_T_94; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_99 = _r_T_96 ? 2'h1 : _r_T_95; // @[Misc.scala:38:63, :56:20] wire _r_T_100 = _r_T_59 == 4'h7; // @[Misc.scala:56:20] wire _r_T_101 = _r_T_100 \| _r_T_97; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_102 = _r_T_100 ? 3'h0 : _r_T_98; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_103 = _r_T_100 ? 2'h1 : _r_T_99; // @[Misc.scala:38:63, :56:20] wire _r_T_104 = _r_T_59 == 4'h0; // @[Misc.scala:56:20] wire _r_T_105 = ~_r_T_104 & _r_T_101; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_106 = _r_T_104 ? 3'h5 : _r_T_102; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_107 = _r_T_104 ? 2'h0 : _r_T_103; // @[Misc.scala:38:63, :56:20] wire _r_T_108 = _r_T_59 == 4'h1; // @[Misc.scala:56:20] wire _r_T_109 = ~_r_T_108 & _r_T_105; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_110 = _r_T_108 ? 3'h4 : _r_T_106; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_111 = _r_T_108 ? 2'h1 : _r_T_107; // @[Misc.scala:38:63, :56:20] wire _r_T_112 = _r_T_59 == 4'h2; // @[Misc.scala:56:20] wire _r_T_113 = ~_r_T_112 & _r_T_109; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_114 = _r_T_112 ? 3'h3 : _r_T_110; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_115 = _r_T_112 ? 2'h2 : _r_T_111; // @[Misc.scala:38:63, :56:20] wire _r_T_116 = _r_T_59 == 4'h3; // @[Misc.scala:56:20] wire s2_prb_ack_data = _r_T_116 \| _r_T_113; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_report_param = _r_T_116 ? 3'h3 : _r_T_114; // @[Misc.scala:38:36, :56:20] wire [2:0] cleanReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [2:0] dirtyReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_116 ? 2'h2 : _r_T_115; // @[Misc.scala:38:63, :56:20] wire [1:0] probeNewCoh_state = r_3; // @[Misc.scala:38:63] wire [3:0] _r_T_123 = {2'h2, s2_victim_state_state}; // @[Metadata.scala:120:19] wire _r_T_136 = _r_T_123 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_138 = _r_T_136 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_140 = _r_T_123 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_142 = _r_T_140 ? 3'h2 : _r_T_138; // @[Misc.scala:38:36, :56:20] wire _r_T_144 = _r_T_123 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_146 = _r_T_144 ? 3'h1 : _r_T_142; // @[Misc.scala:38:36, :56:20] wire _r_T_148 = _r_T_123 == 4'hB; // @[Misc.scala:56:20] wire _r_T_149 = _r_T_148; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_150 = _r_T_148 ? 3'h1 : _r_T_146; // @[Misc.scala:38:36, :56:20] wire _r_T_152 = _r_T_123 == 4'h4; // @[Misc.scala:56:20] wire _r_T_153 = ~_r_T_152 & _r_T_149; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_154 = _r_T_152 ? 3'h5 : _r_T_150; // @[Misc.scala:38:36, :56:20] wire _r_T_156 = _r_T_123 == 4'h5; // @[Misc.scala:56:20] wire _r_T_157 = ~_r_T_156 & _r_T_153; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_158 = _r_T_156 ? 3'h4 : _r_T_154; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_159 = {1'h0, _r_T_156}; // @[Misc.scala:38:63, :56:20] wire _r_T_160 = _r_T_123 == 4'h6; // @[Misc.scala:56:20] wire _r_T_161 = ~_r_T_160 & _r_T_157; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_162 = _r_T_160 ? 3'h0 : _r_T_158; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_163 = _r_T_160 ? 2'h1 : _r_T_159; // @[Misc.scala:38:63, :56:20] wire _r_T_164 = _r_T_123 == 4'h7; // @[Misc.scala:56:20] wire _r_T_165 = _r_T_164 \| _r_T_161; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_166 = _r_T_164 ? 3'h0 : _r_T_162; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_167 = _r_T_164 ? 2'h1 : _r_T_163; // @[Misc.scala:38:63, :56:20] wire _r_T_168 = _r_T_123 == 4'h0; // @[Misc.scala:56:20] wire _r_T_169 = ~_r_T_168 & _r_T_165; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_170 = _r_T_168 ? 3'h5 : _r_T_166; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_171 = _r_T_168 ? 2'h0 : _r_T_167; // @[Misc.scala:38:63, :56:20] wire _r_T_172 = _r_T_123 == 4'h1; // @[Misc.scala:56:20] wire _r_T_173 = ~_r_T_172 & _r_T_169; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_174 = _r_T_172 ? 3'h4 : _r_T_170; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_175 = _r_T_172 ? 2'h1 : _r_T_171; // @[Misc.scala:38:63, :56:20] wire _r_T_176 = _r_T_123 == 4'h2; // @[Misc.scala:56:20] wire _r_T_177 = ~_r_T_176 & _r_T_173; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_178 = _r_T_176 ? 3'h3 : _r_T_174; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_179 = _r_T_176 ? 2'h2 : _r_T_175; // @[Misc.scala:38:63, :56:20] wire _r_T_180 = _r_T_123 == 4'h3; // @[Misc.scala:56:20] wire s2_victim_dirty = _r_T_180 \| _r_T_177; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_shrink_param = _r_T_180 ? 3'h3 : _r_T_178; // @[Misc.scala:38:36, :56:20] wire [2:0] nodeOut_c_bits_c_param = s2_shrink_param; // @[Misc.scala:38:36] wire [2:0] nodeOut_c_bits_c_1_param = s2_shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3_1 = _r_T_180 ? 2'h2 : _r_T_179; // @[Misc.scala:38:63, :56:20] wire [1:0] voluntaryNewCoh_state = r_3_1; // @[Misc.scala:38:63] wire _s2_update_meta_T = s2_hit_state_state == s2_new_hit_state_state; // @[Metadata.scala:46:46, :160:20] wire s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala:46:46, :47:40] wire s2_dont_nack_uncached = s2_valid_uncached_pending & tl_out_a_ready; // @[DCache.scala:159:22, :430:64, :440:57] wire _s2_dont_nack_misc_T_7 = ~s2_hit; // @[Misc.scala:35:9] wire _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala:339:19, :444:17] wire _s2_dont_nack_misc_T_11 = _s2_dont_nack_misc_T_10; // @[DCache.scala:443:55, :444:17] wire s2_dont_nack_misc = _s2_dont_nack_misc_T_1 & _s2_dont_nack_misc_T_11; // @[DCache.scala:441:{43,61}, :443:55] wire _io_cpu_s2_nack_T = ~s2_dont_nack_uncached; // @[DCache.scala:440:57, :445:41] wire _io_cpu_s2_nack_T_1 = s2_valid_no_xcpt & _io_cpu_s2_nack_T; // @[DCache.scala:332:35, :445:{38,41}] wire _io_cpu_s2_nack_T_2 = ~s2_dont_nack_misc; // @[DCache.scala:441:61, :445:67] wire _io_cpu_s2_nack_T_3 = _io_cpu_s2_nack_T_1 & _io_cpu_s2_nack_T_2; // @[DCache.scala:445:{38,64,67}] wire _io_cpu_s2_nack_T_4 = ~s2_valid_hit; // @[DCache.scala:422:48, :445:89] assign _io_cpu_s2_nack_T_5 = _io_cpu_s2_nack_T_3 & _io_cpu_s2_nack_T_4; // @[DCache.scala:445:{64,86,89}] assign io_cpu_s2_nack_0 = _io_cpu_s2_nack_T_5; // @[DCache.scala:101:7, :445:86] assign _metaArb_io_in_2_valid_T = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[Metadata.scala:47:40] wire _T_48 = io_cpu_s2_nack_0 \| _metaArb_io_in_2_valid_T; // @[DCache.scala:101:7, :446:24, :462:63] wire [1:0] _s2_first_meta_corrected_T_9_coh_state = _s2_first_meta_corrected_T_8_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_9_tag = _s2_first_meta_corrected_T_8_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_10_coh_state = _s2_first_meta_corrected_T_9_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_10_tag = _s2_first_meta_corrected_T_9_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_11_coh_state = _s2_first_meta_corrected_T_10_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_11_tag = _s2_first_meta_corrected_T_10_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_12_coh_state = _s2_first_meta_corrected_T_11_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_12_tag = _s2_first_meta_corrected_T_11_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_13_coh_state = _s2_first_meta_corrected_T_12_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_13_tag = _s2_first_meta_corrected_T_12_tag; // @[Mux.scala:50:70] wire [1:0] s2_first_meta_corrected_coh_state = _s2_first_meta_corrected_T_13_coh_state; // @[Mux.scala:50:70] wire [19:0] s2_first_meta_corrected_tag = _s2_first_meta_corrected_T_13_tag; // @[Mux.scala:50:70] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_state = s2_first_meta_corrected_coh_state; // @[Mux.scala:50:70] wire [19:0] metaArb_io_in_1_bits_data_new_meta_tag = s2_first_meta_corrected_tag; // @[Mux.scala:50:70] wire _metaArb_io_in_1_valid_T = s2_valid_masked \| s2_flush_valid_pre_tag_ecc; // @[DCache.scala:337:42, :355:43, :450:63] wire _metaArb_io_in_1_valid_T_1 = _metaArb_io_in_1_valid_T \| s2_probe; // @[DCache.scala:333:25, :450:{63,93}] wire [5:0] _metaArb_io_in_1_bits_idx_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _metaArb_io_in_6_bits_idx_T_1 = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _dataArb_io_in_2_bits_addr_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] assign _metaArb_io_in_4_bits_idx_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _metaArb_io_in_1_bits_idx_T_1 = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76] assign _metaArb_io_in_2_bits_idx_T = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76, :465:40] assign _metaArb_io_in_3_bits_idx_T = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76, :744:40] assign _metaArb_io_in_1_bits_idx_T_2 = s2_probe ? _metaArb_io_in_1_bits_idx_T : _metaArb_io_in_1_bits_idx_T_1; // @[DCache.scala:333:25, :453:{35,76}, :1200:47] assign metaArb_io_in_1_bits_idx = _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:135:28, :453:35] wire [11:0] _metaArb_io_in_1_bits_addr_T_1 = {_metaArb_io_in_1_bits_idx_T_2, 6'h0}; // @[DCache.scala:453:35, :454:98] assign _metaArb_io_in_1_bits_addr_T_2 = {_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1}; // @[DCache.scala:454:{36,58,98}] assign metaArb_io_in_1_bits_addr = _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:135:28, :454:36] assign _metaArb_io_in_1_bits_data_T = {metaArb_io_in_1_bits_data_new_meta_coh_state, metaArb_io_in_1_bits_data_new_meta_tag}; // @[DCache.scala:456:31, :458:14] assign metaArb_io_in_1_bits_data = _metaArb_io_in_1_bits_data_T; // @[DCache.scala:135:28, :458:14] assign metaArb_io_in_2_valid = _metaArb_io_in_2_valid_T; // @[DCache.scala:135:28, :462:63] assign metaArb_io_in_2_bits_idx = _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:135:28, :465:40] wire [11:0] _metaArb_io_in_2_bits_addr_T_1 = s2_vaddr[11:0]; // @[DCache.scala:351:21, :466:80] wire [11:0] _metaArb_io_in_3_bits_addr_T_1 = s2_vaddr[11:0]; // @[DCache.scala:351:21, :466:80, :745:80] assign _metaArb_io_in_2_bits_addr_T_2 = {_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1}; // @[DCache.scala:466:{36,58,80}] assign metaArb_io_in_2_bits_addr = _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:135:28, :466:36] wire [27:0] _metaArb_io_in_2_bits_data_T = s2_req_addr[39:12]; // @[DCache.scala:339:19, :467:68] wire [27:0] _metaArb_io_in_3_bits_data_T = s2_req_addr[39:12]; // @[DCache.scala:339:19, :467:68, :746:68] wire [19:0] metaArb_io_in_2_bits_data_meta_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data_meta_tag = _metaArb_io_in_2_bits_data_T[19:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_2_bits_data_T_1 = {metaArb_io_in_2_bits_data_meta_coh_state, metaArb_io_in_2_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data = _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:135:28, :467:97] wire s2_lr = _s2_lr_T; // @[DCache.scala:470:{56,70}] wire s2_sc = _s2_sc_T; // @[DCache.scala:471:{56,70}] wire io_cpu_resp_bits_data_doZero_2 = s2_sc; // @[DCache.scala:471:56] reg [6:0] lrscCount; // @[DCache.scala:472:26] wire lrscValid = \|(lrscCount[6:2]); // @[DCache.scala:472:26, :473:29] wire _lrscBackingOff_T = \|lrscCount; // @[DCache.scala:472:26, :474:34] wire _lrscBackingOff_T_1 = ~lrscValid; // @[DCache.scala:473:29, :474:43] wire lrscBackingOff = _lrscBackingOff_T & _lrscBackingOff_T_1; // @[DCache.scala:474:{34,40,43}] reg [33:0] lrscAddr; // @[DCache.scala:475:21] wire [33:0] _lrscAddrMatch_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49] wire [33:0] _lrscAddr_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :480:29] wire [33:0] _acquire_address_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :578:38] wire [33:0] _tl_out_a_bits_T_1 = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1210:39] wire [33:0] _io_errors_bus_bits_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1130:58] wire lrscAddrMatch = lrscAddr == _lrscAddrMatch_T; // @[DCache.scala:475:21, :476:{32,49}] wire _s2_sc_fail_T = lrscValid & lrscAddrMatch; // @[DCache.scala:473:29, :476:32, :477:41] wire _s2_sc_fail_T_1 = ~_s2_sc_fail_T; // @[DCache.scala:477:{29,41}] wire s2_sc_fail = s2_sc & _s2_sc_fail_T_1; // @[DCache.scala:471:56, :477:{26,29}] wire [6:0] _lrscCount_T = s2_hit ? 7'h4F : 7'h0; // @[Misc.scala:35:9] wire [7:0] _lrscCount_T_1 = {1'h0, lrscCount} - 8'h1; // @[DCache.scala:472:26, :482:51] wire [6:0] _lrscCount_T_2 = _lrscCount_T_1[6:0]; // @[DCache.scala:482:51] wire _s2_correct_T = ~any_pstore_valid; // @[DCache.scala:230:30, :487:37] wire _s2_correct_T_2 = any_pstore_valid \| s2_valid; // @[DCache.scala:230:30, :331:25, :487:84] reg s2_correct_REG; // @[DCache.scala:487:66] wire _s2_correct_T_3 = ~s2_correct_REG; // @[DCache.scala:487:{58,66}] wire _GEN_95 = s1_valid_not_nacked & s1_write; // @[DCache.scala:187:38, :492:63] wire _pstore1_cmd_T; // @[DCache.scala:492:63] assign _pstore1_cmd_T = _GEN_95; // @[DCache.scala:492:63] wire _pstore1_addr_T; // @[DCache.scala:493:62] assign _pstore1_addr_T = _GEN_95; // @[DCache.scala:492:63, :493:62] wire _pstore1_data_T; // @[DCache.scala:494:73] assign _pstore1_data_T = _GEN_95; // @[DCache.scala:492:63, :494:73] wire _pstore1_way_T; // @[DCache.scala:495:63] assign _pstore1_way_T = _GEN_95; // @[DCache.scala:492:63, :495:63] wire _pstore1_mask_T; // @[DCache.scala:496:61] assign _pstore1_mask_T = _GEN_95; // @[DCache.scala:492:63, :496:61] wire _pstore1_rmw_T_53; // @[DCache.scala:498:84] assign _pstore1_rmw_T_53 = _GEN_95; // @[DCache.scala:492:63, :498:84] reg [4:0] pstore1_cmd; // @[DCache.scala:492:30] reg [39:0] pstore1_addr; // @[DCache.scala:493:31] wire [39:0] _pstore2_addr_T = pstore1_addr; // @[DCache.scala:493:31, :524:35] reg [63:0] pstore1_data; // @[DCache.scala:494:31] assign io_cpu_resp_bits_store_data_0 = pstore1_data; // @[DCache.scala:101:7, :494:31] wire [63:0] _amoalu_io_rhs_T = pstore1_data; // @[DCache.scala:494:31, :986:37] reg [7:0] pstore1_way; // @[DCache.scala:495:30] wire [7:0] _pstore2_way_T = pstore1_way; // @[DCache.scala:495:30, :525:34] reg [7:0] pstore1_mask; // @[DCache.scala:496:31] wire [7:0] pstore2_storegen_mask_mergedMask = pstore1_mask; // @[DCache.scala:496:31, :533:37] wire [7:0] _amoalu_io_mask_T = pstore1_mask; // @[DCache.scala:496:31, :983:38] wire [63:0] pstore1_storegen_data; // @[DCache.scala:497:42] wire _pstore1_rmw_T_4 = _pstore1_rmw_T \| _pstore1_rmw_T_1; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_5 = _pstore1_rmw_T_4 \| _pstore1_rmw_T_2; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_6 = _pstore1_rmw_T_5 \| _pstore1_rmw_T_3; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_11 = _pstore1_rmw_T_7 \| _pstore1_rmw_T_8; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_12 = _pstore1_rmw_T_11 \| _pstore1_rmw_T_9; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_13 = _pstore1_rmw_T_12 \| _pstore1_rmw_T_10; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_19 = _pstore1_rmw_T_14 \| _pstore1_rmw_T_15; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_20 = _pstore1_rmw_T_19 \| _pstore1_rmw_T_16; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_21 = _pstore1_rmw_T_20 \| _pstore1_rmw_T_17; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_22 = _pstore1_rmw_T_21 \| _pstore1_rmw_T_18; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_23 = _pstore1_rmw_T_13 \| _pstore1_rmw_T_22; // @[package.scala:81:59] wire _pstore1_rmw_T_24 = _pstore1_rmw_T_6 \| _pstore1_rmw_T_23; // @[package.scala:81:59] wire _pstore1_rmw_T_27 = _pstore1_rmw_T_25 \| _pstore1_rmw_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore1_rmw_T_29 = _pstore1_rmw_T_27 \| _pstore1_rmw_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore1_rmw_T_34 = _pstore1_rmw_T_30 \| _pstore1_rmw_T_31; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_35 = _pstore1_rmw_T_34 \| _pstore1_rmw_T_32; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_36 = _pstore1_rmw_T_35 \| _pstore1_rmw_T_33; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_42 = _pstore1_rmw_T_37 \| _pstore1_rmw_T_38; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_43 = _pstore1_rmw_T_42 \| _pstore1_rmw_T_39; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_44 = _pstore1_rmw_T_43 \| _pstore1_rmw_T_40; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_45 = _pstore1_rmw_T_44 \| _pstore1_rmw_T_41; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_46 = _pstore1_rmw_T_36 \| _pstore1_rmw_T_45; // @[package.scala:81:59] wire _pstore1_rmw_T_47 = _pstore1_rmw_T_29 \| _pstore1_rmw_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore1_rmw_T_50 = _pstore1_rmw_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore1_rmw_T_51 = _pstore1_rmw_T_47 & _pstore1_rmw_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore1_rmw_T_52 = _pstore1_rmw_T_24 \| _pstore1_rmw_T_51; // @[DCache.scala:1190:21, :1191:23] reg pstore1_rmw_r; // @[DCache.scala:498:44] wire pstore1_rmw = pstore1_rmw_r; // @[DCache.scala:498:{32,44}] wire _pstore1_merge_likely_T = s2_valid_not_nacked_in_s1 & s2_write; // @[DCache.scala:336:44, :499:56] wire _GEN_96 = s2_valid_hit & s2_write; // @[DCache.scala:422:48, :490:46] wire _pstore1_merge_T; // @[DCache.scala:490:46] assign _pstore1_merge_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_valid_T; // @[DCache.scala:490:46] assign _pstore1_valid_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_held_T; // @[DCache.scala:490:46] assign _pstore1_held_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_merge_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_merge_T_2 = _pstore1_merge_T & _pstore1_merge_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_merge_T_4 = _pstore1_merge_T_2; // @[DCache.scala:490:58, :491:48] reg pstore2_valid; // @[DCache.scala:501:30] wire _pstore_drain_opportunistic_res_T_2 = _pstore_drain_opportunistic_res_T \| _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_res_T_3 = ~_pstore_drain_opportunistic_res_T_2; // @[package.scala:81:59] wire pstore_drain_opportunistic_res = _pstore_drain_opportunistic_res_T_3; // @[DCache.scala:1185:{15,46}] wire _pstore_drain_opportunistic_T_4 = _pstore_drain_opportunistic_T \| _pstore_drain_opportunistic_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_5 = _pstore_drain_opportunistic_T_4 \| _pstore_drain_opportunistic_T_2; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_6 = _pstore_drain_opportunistic_T_5 \| _pstore_drain_opportunistic_T_3; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_11 = _pstore_drain_opportunistic_T_7 \| _pstore_drain_opportunistic_T_8; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_12 = _pstore_drain_opportunistic_T_11 \| _pstore_drain_opportunistic_T_9; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_13 = _pstore_drain_opportunistic_T_12 \| _pstore_drain_opportunistic_T_10; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_19 = _pstore_drain_opportunistic_T_14 \| _pstore_drain_opportunistic_T_15; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_20 = _pstore_drain_opportunistic_T_19 \| _pstore_drain_opportunistic_T_16; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_21 = _pstore_drain_opportunistic_T_20 \| _pstore_drain_opportunistic_T_17; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_22 = _pstore_drain_opportunistic_T_21 \| _pstore_drain_opportunistic_T_18; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_23 = _pstore_drain_opportunistic_T_13 \| _pstore_drain_opportunistic_T_22; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_24 = _pstore_drain_opportunistic_T_6 \| _pstore_drain_opportunistic_T_23; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_27 = _pstore_drain_opportunistic_T_25 \| _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore_drain_opportunistic_T_29 = _pstore_drain_opportunistic_T_27 \| _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore_drain_opportunistic_T_34 = _pstore_drain_opportunistic_T_30 \| _pstore_drain_opportunistic_T_31; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_35 = _pstore_drain_opportunistic_T_34 \| _pstore_drain_opportunistic_T_32; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_36 = _pstore_drain_opportunistic_T_35 \| _pstore_drain_opportunistic_T_33; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_42 = _pstore_drain_opportunistic_T_37 \| _pstore_drain_opportunistic_T_38; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_43 = _pstore_drain_opportunistic_T_42 \| _pstore_drain_opportunistic_T_39; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_44 = _pstore_drain_opportunistic_T_43 \| _pstore_drain_opportunistic_T_40; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_45 = _pstore_drain_opportunistic_T_44 \| _pstore_drain_opportunistic_T_41; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_46 = _pstore_drain_opportunistic_T_36 \| _pstore_drain_opportunistic_T_45; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_47 = _pstore_drain_opportunistic_T_29 \| _pstore_drain_opportunistic_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore_drain_opportunistic_T_50 = _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore_drain_opportunistic_T_51 = _pstore_drain_opportunistic_T_47 & _pstore_drain_opportunistic_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore_drain_opportunistic_T_52 = _pstore_drain_opportunistic_T_24 \| _pstore_drain_opportunistic_T_51; // @[DCache.scala:1190:21, :1191:23] wire _pstore_drain_opportunistic_T_53 = ~_pstore_drain_opportunistic_T_52; // @[DCache.scala:1186:12, :1190:21] wire _pstore_drain_opportunistic_T_54 = _pstore_drain_opportunistic_T_53 \| pstore_drain_opportunistic_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _pstore_drain_opportunistic_T_56 = ~_pstore_drain_opportunistic_T_55; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_57 = ~_pstore_drain_opportunistic_T_54; // @[DCache.scala:1186:{11,28}] wire _pstore_drain_opportunistic_T_58 = io_cpu_req_valid_0 & pstore_drain_opportunistic_res; // @[DCache.scala:101:7, :502:55, :1185:46] wire _pstore_drain_opportunistic_T_59 = ~_pstore_drain_opportunistic_T_58; // @[DCache.scala:502:{36,55}] wire pstore_drain_opportunistic = _pstore_drain_opportunistic_T_59; // @[DCache.scala:502:{36,92}] reg pstore_drain_on_miss_REG; // @[DCache.scala:503:56] wire pstore_drain_on_miss = releaseInFlight \| pstore_drain_on_miss_REG; // @[DCache.scala:334:46, :503:{46,56}] reg pstore1_held; // @[DCache.scala:504:29] wire _GEN_97 = s2_valid & s2_write; // @[DCache.scala:331:25, :505:39] wire _pstore1_valid_likely_T; // @[DCache.scala:505:39] assign _pstore1_valid_likely_T = _GEN_97; // @[DCache.scala:505:39] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_1; // @[DCache.scala:1082:16] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = _GEN_97; // @[DCache.scala:505:39, :1082:16] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_1; // @[DCache.scala:1086:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = _GEN_97; // @[DCache.scala:505:39, :1086:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_4; // @[DCache.scala:1087:16] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = _GEN_97; // @[DCache.scala:505:39, :1087:16] wire _io_cpu_perf_canAcceptStoreThenLoad_T; // @[DCache.scala:1089:16] assign _io_cpu_perf_canAcceptStoreThenLoad_T = _GEN_97; // @[DCache.scala:505:39, :1089:16] wire _io_cpu_perf_canAcceptLoadThenLoad_T_55; // @[DCache.scala:1092:100] assign _io_cpu_perf_canAcceptLoadThenLoad_T_55 = _GEN_97; // @[DCache.scala:505:39, :1092:100] wire pstore1_valid_likely = _pstore1_valid_likely_T \| pstore1_held; // @[DCache.scala:504:29, :505:{39,51}] wire _pstore1_valid_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_valid_T_2 = _pstore1_valid_T & _pstore1_valid_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_valid_T_4 = _pstore1_valid_T_2; // @[DCache.scala:490:58, :491:48] wire pstore1_valid = _pstore1_valid_T_4 \| pstore1_held; // @[DCache.scala:491:48, :504:29, :507:38] wire _advance_pstore1_T = pstore1_valid; // @[DCache.scala:507:38, :522:40] assign _any_pstore_valid_T = pstore1_held \| pstore2_valid; // @[DCache.scala:501:30, :504:29, :508:36] assign any_pstore_valid = _any_pstore_valid_T; // @[DCache.scala:230:30, :508:36] wire _GEN_98 = pstore1_valid_likely & pstore2_valid; // @[DCache.scala:501:30, :505:51, :509:54] wire _pstore_drain_structural_T; // @[DCache.scala:509:54] assign _pstore_drain_structural_T = _GEN_98; // @[DCache.scala:509:54] wire _io_cpu_perf_canAcceptStoreThenLoad_T_6; // @[DCache.scala:1090:20] assign _io_cpu_perf_canAcceptStoreThenLoad_T_6 = _GEN_98; // @[DCache.scala:509:54, :1090:20] wire _GEN_99 = s1_valid & s1_write; // @[DCache.scala:182:25, :509:85] wire _pstore_drain_structural_T_1; // @[DCache.scala:509:85] assign _pstore_drain_structural_T_1 = _GEN_99; // @[DCache.scala:509:85] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T; // @[DCache.scala:1081:15] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T = _GEN_99; // @[DCache.scala:509:85, :1081:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T; // @[DCache.scala:1085:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T = _GEN_99; // @[DCache.scala:509:85, :1085:15] wire _io_cpu_perf_canAcceptStoreThenLoad_T_2; // @[DCache.scala:1089:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_2 = _GEN_99; // @[DCache.scala:509:85, :1089:57] wire _io_cpu_perf_canAcceptStoreThenLoad_T_7; // @[DCache.scala:1090:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_7 = _GEN_99; // @[DCache.scala:509:85, :1090:57] wire _io_cpu_perf_canAcceptLoadThenLoad_T; // @[DCache.scala:1092:52] assign _io_cpu_perf_canAcceptLoadThenLoad_T = _GEN_99; // @[DCache.scala:509:85, :1092:52] wire _pstore_drain_structural_T_2 = _pstore_drain_structural_T_1 \| pstore1_rmw; // @[DCache.scala:498:32, :509:{85,98}] wire pstore_drain_structural = _pstore_drain_structural_T & _pstore_drain_structural_T_2; // @[DCache.scala:509:{54,71,98}] wire _pstore_drain_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _dataArb_io_in_0_valid_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _T_57 = s2_valid_hit_pre_data_ecc & s2_write; // @[DCache.scala:420:69, :506:72] wire _pstore_drain_T_2; // @[DCache.scala:506:72] assign _pstore_drain_T_2 = _T_57; // @[DCache.scala:506:72] wire _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:72] assign _dataArb_io_in_0_valid_T_2 = _T_57; // @[DCache.scala:506:72] wire _pstore_drain_T_4 = _pstore_drain_T_2; // @[DCache.scala:506:{72,84}] wire _pstore_drain_T_5 = _pstore_drain_T_4 \| pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _pstore_drain_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _pstore_drain_T_7 = _pstore_drain_T_5 & _pstore_drain_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _pstore_drain_T_8 = _pstore_drain_T_7 \| pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _GEN_100 = pstore_drain_opportunistic \| pstore_drain_on_miss; // @[DCache.scala:502:92, :503:46, :518:107] wire _pstore_drain_T_9; // @[DCache.scala:518:107] assign _pstore_drain_T_9 = _GEN_100; // @[DCache.scala:518:107] wire _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:107] assign _dataArb_io_in_0_valid_T_9 = _GEN_100; // @[DCache.scala:518:107] wire _pstore_drain_T_10 = _pstore_drain_T_8 & _pstore_drain_T_9; // @[DCache.scala:518:{58,76,107}] wire _pstore_drain_T_11 = _pstore_drain_T_1 \| _pstore_drain_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign pstore_drain = _pstore_drain_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_bits_write = pstore_drain; // @[DCache.scala:152:28, :516:27] wire _pstore1_held_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_held_T_2 = _pstore1_held_T & _pstore1_held_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_held_T_4 = _pstore1_held_T_2; // @[DCache.scala:490:58, :491:48] wire _pstore1_held_T_6 = _pstore1_held_T_4; // @[DCache.scala:491:48, :521:35] wire _pstore1_held_T_7 = _pstore1_held_T_6 \| pstore1_held; // @[DCache.scala:504:29, :521:{35,54}] wire _pstore1_held_T_8 = _pstore1_held_T_7 & pstore2_valid; // @[DCache.scala:501:30, :521:{54,71}] wire _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala:516:27, :521:91] wire _pstore1_held_T_10 = _pstore1_held_T_8 & _pstore1_held_T_9; // @[DCache.scala:521:{71,88,91}] wire _advance_pstore1_T_1 = pstore2_valid == pstore_drain; // @[DCache.scala:501:30, :516:27, :522:79] wire advance_pstore1 = _advance_pstore1_T & _advance_pstore1_T_1; // @[DCache.scala:522:{40,61,79}] wire _pstore2_storegen_data_T_3 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_7 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_11 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_15 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_19 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_23 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_27 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_31 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_mask_T = advance_pstore1; // @[DCache.scala:522:61, :532:27] wire _pstore2_valid_T = ~pstore_drain; // @[DCache.scala:516:27, :521:91, :523:37] wire _pstore2_valid_T_1 = pstore2_valid & _pstore2_valid_T; // @[DCache.scala:501:30, :523:{34,37}] wire _pstore2_valid_T_2 = _pstore2_valid_T_1 \| advance_pstore1; // @[DCache.scala:522:61, :523:{34,51}] reg [39:0] pstore2_addr; // @[DCache.scala:524:31] reg [7:0] pstore2_way; // @[DCache.scala:525:30] wire [7:0] _pstore2_storegen_data_T = pstore1_storegen_data[7:0]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_1 = pstore1_mask[0]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_3 = pstore1_mask[0]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_4 = pstore1_storegen_data[15:8]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_5 = pstore1_mask[1]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_4 = pstore1_mask[1]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_1; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_8 = pstore1_storegen_data[23:16]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_9 = pstore1_mask[2]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_5 = pstore1_mask[2]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_2; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_12 = pstore1_storegen_data[31:24]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_13 = pstore1_mask[3]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_6 = pstore1_mask[3]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_3; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_16 = pstore1_storegen_data[39:32]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_17 = pstore1_mask[4]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_7 = pstore1_mask[4]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_4; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_20 = pstore1_storegen_data[47:40]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_21 = pstore1_mask[5]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_8 = pstore1_mask[5]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_5; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_24 = pstore1_storegen_data[55:48]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_25 = pstore1_mask[6]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_9 = pstore1_mask[6]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_6; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_28 = pstore1_storegen_data[63:56]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_29 = pstore1_mask[7]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_10 = pstore1_mask[7]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_7; // @[DCache.scala:528:22] wire [15:0] pstore2_storegen_data_lo_lo = {pstore2_storegen_data_r_1, pstore2_storegen_data_r}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_lo_hi = {pstore2_storegen_data_r_3, pstore2_storegen_data_r_2}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_lo = {pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_lo = {pstore2_storegen_data_r_5, pstore2_storegen_data_r_4}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_hi = {pstore2_storegen_data_r_7, pstore2_storegen_data_r_6}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_hi = {pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo}; // @[package.scala:45:27] wire [63:0] pstore2_storegen_data = {pstore2_storegen_data_hi, pstore2_storegen_data_lo}; // @[package.scala:45:27] reg [7:0] pstore2_storegen_mask; // @[DCache.scala:531:19] wire [7:0] _pstore2_storegen_mask_mask_T = ~pstore2_storegen_mask_mergedMask; // @[DCache.scala:533:37, :534:37] wire [7:0] _pstore2_storegen_mask_mask_T_1 = _pstore2_storegen_mask_mask_T; // @[DCache.scala:534:{19,37}] wire [7:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T_1; // @[DCache.scala:534:{15,19}] wire _dataArb_io_in_0_valid_T_4 = _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:{72,84}] wire _dataArb_io_in_0_valid_T_5 = _dataArb_io_in_0_valid_T_4 \| pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _dataArb_io_in_0_valid_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _dataArb_io_in_0_valid_T_7 = _dataArb_io_in_0_valid_T_5 & _dataArb_io_in_0_valid_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _dataArb_io_in_0_valid_T_8 = _dataArb_io_in_0_valid_T_7 \| pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _dataArb_io_in_0_valid_T_10 = _dataArb_io_in_0_valid_T_8 & _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:{58,76,107}] wire _dataArb_io_in_0_valid_T_11 = _dataArb_io_in_0_valid_T_1 \| _dataArb_io_in_0_valid_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign _dataArb_io_in_0_valid_T_12 = _dataArb_io_in_0_valid_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_valid = _dataArb_io_in_0_valid_T_12; // @[DCache.scala:152:28, :516:27] wire [39:0] _GEN_101 = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala:493:31, :501:30, :524:31, :549:36] wire [39:0] _dataArb_io_in_0_bits_addr_T; // @[DCache.scala:549:36] assign _dataArb_io_in_0_bits_addr_T = _GEN_101; // @[DCache.scala:549:36] wire [39:0] _dataArb_io_in_0_bits_wordMask_wordMask_T; // @[DCache.scala:554:32] assign _dataArb_io_in_0_bits_wordMask_wordMask_T = _GEN_101; // @[DCache.scala:549:36, :554:32] assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[11:0]; // @[DCache.scala:152:28, :549:{30,36}] assign _dataArb_io_in_0_bits_way_en_T = pstore2_valid ? pstore2_way : pstore1_way; // @[DCache.scala:495:30, :501:30, :525:30, :550:38] assign dataArb_io_in_0_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38] wire [63:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[package.scala:45:27] wire [127:0] _dataArb_io_in_0_bits_wdata_T_1 = {2{_dataArb_io_in_0_bits_wdata_T}}; // @[DCache.scala:551:{49,63}] wire [7:0] _dataArb_io_in_0_bits_wdata_T_2 = _dataArb_io_in_0_bits_wdata_T_1[7:0]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_3 = _dataArb_io_in_0_bits_wdata_T_1[15:8]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_4 = _dataArb_io_in_0_bits_wdata_T_1[23:16]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_5 = _dataArb_io_in_0_bits_wdata_T_1[31:24]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_6 = _dataArb_io_in_0_bits_wdata_T_1[39:32]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_7 = _dataArb_io_in_0_bits_wdata_T_1[47:40]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_8 = _dataArb_io_in_0_bits_wdata_T_1[55:48]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_9 = _dataArb_io_in_0_bits_wdata_T_1[63:56]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_10 = _dataArb_io_in_0_bits_wdata_T_1[71:64]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_11 = _dataArb_io_in_0_bits_wdata_T_1[79:72]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_12 = _dataArb_io_in_0_bits_wdata_T_1[87:80]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_13 = _dataArb_io_in_0_bits_wdata_T_1[95:88]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_14 = _dataArb_io_in_0_bits_wdata_T_1[103:96]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_15 = _dataArb_io_in_0_bits_wdata_T_1[111:104]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_16 = _dataArb_io_in_0_bits_wdata_T_1[119:112]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_17 = _dataArb_io_in_0_bits_wdata_T_1[127:120]; // @[package.scala:211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo_lo = {_dataArb_io_in_0_bits_wdata_T_3, _dataArb_io_in_0_bits_wdata_T_2}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo_hi = {_dataArb_io_in_0_bits_wdata_T_5, _dataArb_io_in_0_bits_wdata_T_4}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_lo_lo = {dataArb_io_in_0_bits_wdata_lo_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi_lo = {_dataArb_io_in_0_bits_wdata_T_7, _dataArb_io_in_0_bits_wdata_T_6}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi_hi = {_dataArb_io_in_0_bits_wdata_T_9, _dataArb_io_in_0_bits_wdata_T_8}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_lo_hi = {dataArb_io_in_0_bits_wdata_lo_hi_hi, dataArb_io_in_0_bits_wdata_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] dataArb_io_in_0_bits_wdata_lo = {dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo_lo = {_dataArb_io_in_0_bits_wdata_T_11, _dataArb_io_in_0_bits_wdata_T_10}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo_hi = {_dataArb_io_in_0_bits_wdata_T_13, _dataArb_io_in_0_bits_wdata_T_12}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_hi_lo = {dataArb_io_in_0_bits_wdata_hi_lo_hi, dataArb_io_in_0_bits_wdata_hi_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi_lo = {_dataArb_io_in_0_bits_wdata_T_15, _dataArb_io_in_0_bits_wdata_T_14}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi_hi = {_dataArb_io_in_0_bits_wdata_T_17, _dataArb_io_in_0_bits_wdata_T_16}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_hi_hi = {dataArb_io_in_0_bits_wdata_hi_hi_hi, dataArb_io_in_0_bits_wdata_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] dataArb_io_in_0_bits_wdata_hi = {dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_wdata_T_18 = {dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_wdata = _dataArb_io_in_0_bits_wdata_T_18; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T = _dataArb_io_in_0_bits_eccMask_T_17[0]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T_17[1]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T_17[2]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T_17[3]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T_17[4]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T_17[5]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T_17[6]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T_17[7]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = _dataArb_io_in_0_bits_wordMask_eccMask_T \| _dataArb_io_in_0_bits_wordMask_eccMask_T_1; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = _dataArb_io_in_0_bits_wordMask_eccMask_T_8 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_2; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = _dataArb_io_in_0_bits_wordMask_eccMask_T_9 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_3; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = _dataArb_io_in_0_bits_wordMask_eccMask_T_10 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_4; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = _dataArb_io_in_0_bits_wordMask_eccMask_T_11 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_5; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = _dataArb_io_in_0_bits_wordMask_eccMask_T_12 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_6; // @[package.scala:81:59] wire dataArb_io_in_0_bits_wordMask_eccMask = _dataArb_io_in_0_bits_wordMask_eccMask_T_13 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_7; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_wordMask_T_1 = _dataArb_io_in_0_bits_wordMask_wordMask_T[3]; // @[package.scala:163:13] wire [1:0] dataArb_io_in_0_bits_wordMask_wordMask = 2'h1 << _dataArb_io_in_0_bits_wordMask_wordMask_T_1; // @[OneHot.scala:58:35] wire _dataArb_io_in_0_bits_wordMask_T = dataArb_io_in_0_bits_wordMask_wordMask[0]; // @[OneHot.scala:58:35] wire _dataArb_io_in_0_bits_wordMask_T_1 = dataArb_io_in_0_bits_wordMask_wordMask[1]; // @[OneHot.scala:58:35] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_2 = {_dataArb_io_in_0_bits_wordMask_T_1, _dataArb_io_in_0_bits_wordMask_T}; // @[DCache.scala:555:20] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_3 = {2{dataArb_io_in_0_bits_wordMask_eccMask}}; // @[package.scala:81:59] assign _dataArb_io_in_0_bits_wordMask_T_4 = _dataArb_io_in_0_bits_wordMask_T_2 & _dataArb_io_in_0_bits_wordMask_T_3; // @[DCache.scala:555:{20,55,61}] assign dataArb_io_in_0_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_4; // @[DCache.scala:152:28, :555:55] wire [7:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? pstore2_storegen_mask : pstore1_mask; // @[DCache.scala:496:31, :501:30, :531:19, :557:47] wire _dataArb_io_in_0_bits_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T[0]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_9 = _dataArb_io_in_0_bits_eccMask_T_1; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T[1]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_10 = _dataArb_io_in_0_bits_eccMask_T_2; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T[2]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_11 = _dataArb_io_in_0_bits_eccMask_T_3; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T[3]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_12 = _dataArb_io_in_0_bits_eccMask_T_4; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T[4]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_13 = _dataArb_io_in_0_bits_eccMask_T_5; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T[5]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_14 = _dataArb_io_in_0_bits_eccMask_T_6; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T[6]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_15 = _dataArb_io_in_0_bits_eccMask_T_7; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_8 = _dataArb_io_in_0_bits_eccMask_T[7]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_16 = _dataArb_io_in_0_bits_eccMask_T_8; // @[package.scala:211:50] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_lo = {_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_hi = {_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_lo = {dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_lo = {_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_hi = {_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_hi = {dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_eccMask_T_17 = {dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [8:0] _s1_hazard_T = pstore1_addr[11:3]; // @[DCache.scala:493:31, :561:9] wire [8:0] _s1_hazard_T_1 = s1_vaddr[11:3]; // @[DCache.scala:197:21, :561:43] wire [8:0] _s1_hazard_T_63 = s1_vaddr[11:3]; // @[DCache.scala:197:21, :561:43] wire _s1_hazard_T_2 = _s1_hazard_T == _s1_hazard_T_1; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_11 = _s1_hazard_T_3; // @[package.scala:211:50] wire _s1_hazard_T_12 = _s1_hazard_T_4; // @[package.scala:211:50] wire _s1_hazard_T_13 = _s1_hazard_T_5; // @[package.scala:211:50] wire _s1_hazard_T_14 = _s1_hazard_T_6; // @[package.scala:211:50] wire _s1_hazard_T_15 = _s1_hazard_T_7; // @[package.scala:211:50] wire _s1_hazard_T_16 = _s1_hazard_T_8; // @[package.scala:211:50] wire _s1_hazard_T_17 = _s1_hazard_T_9; // @[package.scala:211:50] wire _s1_hazard_T_18 = _s1_hazard_T_10; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo = {_s1_hazard_T_12, _s1_hazard_T_11}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi = {_s1_hazard_T_14, _s1_hazard_T_13}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo = {s1_hazard_lo_hi, s1_hazard_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo = {_s1_hazard_T_16, _s1_hazard_T_15}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi = {_s1_hazard_T_18, _s1_hazard_T_17}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi = {s1_hazard_hi_hi, s1_hazard_hi_lo}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_19 = {s1_hazard_hi, s1_hazard_lo}; // @[package.scala:45:27] wire _s1_hazard_T_20 = _s1_hazard_T_19[0]; // @[package.scala:45:27] wire _s1_hazard_T_21 = _s1_hazard_T_19[1]; // @[package.scala:45:27] wire _s1_hazard_T_22 = _s1_hazard_T_19[2]; // @[package.scala:45:27] wire _s1_hazard_T_23 = _s1_hazard_T_19[3]; // @[package.scala:45:27] wire _s1_hazard_T_24 = _s1_hazard_T_19[4]; // @[package.scala:45:27] wire _s1_hazard_T_25 = _s1_hazard_T_19[5]; // @[package.scala:45:27] wire _s1_hazard_T_26 = _s1_hazard_T_19[6]; // @[package.scala:45:27] wire _s1_hazard_T_27 = _s1_hazard_T_19[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_1 = {_s1_hazard_T_21, _s1_hazard_T_20}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_1 = {_s1_hazard_T_23, _s1_hazard_T_22}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_1 = {s1_hazard_lo_hi_1, s1_hazard_lo_lo_1}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_1 = {_s1_hazard_T_25, _s1_hazard_T_24}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_1 = {_s1_hazard_T_27, _s1_hazard_T_26}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_1 = {s1_hazard_hi_hi_1, s1_hazard_hi_lo_1}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_28 = {s1_hazard_hi_1, s1_hazard_lo_1}; // @[DCache.scala:1182:52] wire _s1_hazard_T_29 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_91 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_37 = _s1_hazard_T_29; // @[package.scala:211:50] wire _s1_hazard_T_30 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_92 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_38 = _s1_hazard_T_30; // @[package.scala:211:50] wire _s1_hazard_T_31 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_93 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_39 = _s1_hazard_T_31; // @[package.scala:211:50] wire _s1_hazard_T_32 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_94 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_40 = _s1_hazard_T_32; // @[package.scala:211:50] wire _s1_hazard_T_33 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_95 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_41 = _s1_hazard_T_33; // @[package.scala:211:50] wire _s1_hazard_T_34 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_96 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_42 = _s1_hazard_T_34; // @[package.scala:211:50] wire _s1_hazard_T_35 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_97 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_43 = _s1_hazard_T_35; // @[package.scala:211:50] wire _s1_hazard_T_36 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_98 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_44 = _s1_hazard_T_36; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_2 = {_s1_hazard_T_38, _s1_hazard_T_37}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_2 = {_s1_hazard_T_40, _s1_hazard_T_39}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_2 = {s1_hazard_lo_hi_2, s1_hazard_lo_lo_2}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_2 = {_s1_hazard_T_42, _s1_hazard_T_41}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_2 = {_s1_hazard_T_44, _s1_hazard_T_43}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_2 = {s1_hazard_hi_hi_2, s1_hazard_hi_lo_2}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_45 = {s1_hazard_hi_2, s1_hazard_lo_2}; // @[package.scala:45:27] wire _s1_hazard_T_46 = _s1_hazard_T_45[0]; // @[package.scala:45:27] wire _s1_hazard_T_47 = _s1_hazard_T_45[1]; // @[package.scala:45:27] wire _s1_hazard_T_48 = _s1_hazard_T_45[2]; // @[package.scala:45:27] wire _s1_hazard_T_49 = _s1_hazard_T_45[3]; // @[package.scala:45:27] wire _s1_hazard_T_50 = _s1_hazard_T_45[4]; // @[package.scala:45:27] wire _s1_hazard_T_51 = _s1_hazard_T_45[5]; // @[package.scala:45:27] wire _s1_hazard_T_52 = _s1_hazard_T_45[6]; // @[package.scala:45:27] wire _s1_hazard_T_53 = _s1_hazard_T_45[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_3 = {_s1_hazard_T_47, _s1_hazard_T_46}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_3 = {_s1_hazard_T_49, _s1_hazard_T_48}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_3 = {s1_hazard_lo_hi_3, s1_hazard_lo_lo_3}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_3 = {_s1_hazard_T_51, _s1_hazard_T_50}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_3 = {_s1_hazard_T_53, _s1_hazard_T_52}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_3 = {s1_hazard_hi_hi_3, s1_hazard_hi_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_54 = {s1_hazard_hi_3, s1_hazard_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_55 = _s1_hazard_T_28 & _s1_hazard_T_54; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_56 = \|_s1_hazard_T_55; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_57 = pstore1_mask & s1_mask_xwr; // @[DCache.scala:496:31, :562:77] wire _s1_hazard_T_58 = \|_s1_hazard_T_57; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_59 = s1_write ? _s1_hazard_T_56 : _s1_hazard_T_58; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_60 = _s1_hazard_T_2 & _s1_hazard_T_59; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_61 = pstore1_valid_likely & _s1_hazard_T_60; // @[DCache.scala:505:51, :561:65, :564:27] wire [8:0] _s1_hazard_T_62 = pstore2_addr[11:3]; // @[DCache.scala:524:31, :561:9] wire _s1_hazard_T_64 = _s1_hazard_T_62 == _s1_hazard_T_63; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_65 = pstore2_storegen_mask[0]; // @[package.scala:211:50] wire _s1_hazard_T_73 = _s1_hazard_T_65; // @[package.scala:211:50] wire _s1_hazard_T_66 = pstore2_storegen_mask[1]; // @[package.scala:211:50] wire _s1_hazard_T_74 = _s1_hazard_T_66; // @[package.scala:211:50] wire _s1_hazard_T_67 = pstore2_storegen_mask[2]; // @[package.scala:211:50] wire _s1_hazard_T_75 = _s1_hazard_T_67; // @[package.scala:211:50] wire _s1_hazard_T_68 = pstore2_storegen_mask[3]; // @[package.scala:211:50] wire _s1_hazard_T_76 = _s1_hazard_T_68; // @[package.scala:211:50] wire _s1_hazard_T_69 = pstore2_storegen_mask[4]; // @[package.scala:211:50] wire _s1_hazard_T_77 = _s1_hazard_T_69; // @[package.scala:211:50] wire _s1_hazard_T_70 = pstore2_storegen_mask[5]; // @[package.scala:211:50] wire _s1_hazard_T_78 = _s1_hazard_T_70; // @[package.scala:211:50] wire _s1_hazard_T_71 = pstore2_storegen_mask[6]; // @[package.scala:211:50] wire _s1_hazard_T_79 = _s1_hazard_T_71; // @[package.scala:211:50] wire _s1_hazard_T_72 = pstore2_storegen_mask[7]; // @[package.scala:211:50] wire _s1_hazard_T_80 = _s1_hazard_T_72; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_4 = {_s1_hazard_T_74, _s1_hazard_T_73}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_4 = {_s1_hazard_T_76, _s1_hazard_T_75}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_4 = {s1_hazard_lo_hi_4, s1_hazard_lo_lo_4}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_4 = {_s1_hazard_T_78, _s1_hazard_T_77}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_4 = {_s1_hazard_T_80, _s1_hazard_T_79}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_4 = {s1_hazard_hi_hi_4, s1_hazard_hi_lo_4}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_81 = {s1_hazard_hi_4, s1_hazard_lo_4}; // @[package.scala:45:27] wire _s1_hazard_T_82 = _s1_hazard_T_81[0]; // @[package.scala:45:27] wire _s1_hazard_T_83 = _s1_hazard_T_81[1]; // @[package.scala:45:27] wire _s1_hazard_T_84 = _s1_hazard_T_81[2]; // @[package.scala:45:27] wire _s1_hazard_T_85 = _s1_hazard_T_81[3]; // @[package.scala:45:27] wire _s1_hazard_T_86 = _s1_hazard_T_81[4]; // @[package.scala:45:27] wire _s1_hazard_T_87 = _s1_hazard_T_81[5]; // @[package.scala:45:27] wire _s1_hazard_T_88 = _s1_hazard_T_81[6]; // @[package.scala:45:27] wire _s1_hazard_T_89 = _s1_hazard_T_81[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_5 = {_s1_hazard_T_83, _s1_hazard_T_82}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_5 = {_s1_hazard_T_85, _s1_hazard_T_84}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_5 = {s1_hazard_lo_hi_5, s1_hazard_lo_lo_5}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_5 = {_s1_hazard_T_87, _s1_hazard_T_86}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_5 = {_s1_hazard_T_89, _s1_hazard_T_88}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_5 = {s1_hazard_hi_hi_5, s1_hazard_hi_lo_5}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_90 = {s1_hazard_hi_5, s1_hazard_lo_5}; // @[DCache.scala:1182:52] wire _s1_hazard_T_99 = _s1_hazard_T_91; // @[package.scala:211:50] wire _s1_hazard_T_100 = _s1_hazard_T_92; // @[package.scala:211:50] wire _s1_hazard_T_101 = _s1_hazard_T_93; // @[package.scala:211:50] wire _s1_hazard_T_102 = _s1_hazard_T_94; // @[package.scala:211:50] wire _s1_hazard_T_103 = _s1_hazard_T_95; // @[package.scala:211:50] wire _s1_hazard_T_104 = _s1_hazard_T_96; // @[package.scala:211:50] wire _s1_hazard_T_105 = _s1_hazard_T_97; // @[package.scala:211:50] wire _s1_hazard_T_106 = _s1_hazard_T_98; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_6 = {_s1_hazard_T_100, _s1_hazard_T_99}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_6 = {_s1_hazard_T_102, _s1_hazard_T_101}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_6 = {s1_hazard_lo_hi_6, s1_hazard_lo_lo_6}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_6 = {_s1_hazard_T_104, _s1_hazard_T_103}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_6 = {_s1_hazard_T_106, _s1_hazard_T_105}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_6 = {s1_hazard_hi_hi_6, s1_hazard_hi_lo_6}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_107 = {s1_hazard_hi_6, s1_hazard_lo_6}; // @[package.scala:45:27] wire _s1_hazard_T_108 = _s1_hazard_T_107[0]; // @[package.scala:45:27] wire _s1_hazard_T_109 = _s1_hazard_T_107[1]; // @[package.scala:45:27] wire _s1_hazard_T_110 = _s1_hazard_T_107[2]; // @[package.scala:45:27] wire _s1_hazard_T_111 = _s1_hazard_T_107[3]; // @[package.scala:45:27] wire _s1_hazard_T_112 = _s1_hazard_T_107[4]; // @[package.scala:45:27] wire _s1_hazard_T_113 = _s1_hazard_T_107[5]; // @[package.scala:45:27] wire _s1_hazard_T_114 = _s1_hazard_T_107[6]; // @[package.scala:45:27] wire _s1_hazard_T_115 = _s1_hazard_T_107[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_7 = {_s1_hazard_T_109, _s1_hazard_T_108}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_7 = {_s1_hazard_T_111, _s1_hazard_T_110}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_7 = {s1_hazard_lo_hi_7, s1_hazard_lo_lo_7}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_7 = {_s1_hazard_T_113, _s1_hazard_T_112}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_7 = {_s1_hazard_T_115, _s1_hazard_T_114}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_7 = {s1_hazard_hi_hi_7, s1_hazard_hi_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_116 = {s1_hazard_hi_7, s1_hazard_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_117 = _s1_hazard_T_90 & _s1_hazard_T_116; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_118 = \|_s1_hazard_T_117; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_119 = pstore2_storegen_mask & s1_mask_xwr; // @[DCache.scala:531:19, :562:77] wire _s1_hazard_T_120 = \|_s1_hazard_T_119; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_121 = s1_write ? _s1_hazard_T_118 : _s1_hazard_T_120; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_122 = _s1_hazard_T_64 & _s1_hazard_T_121; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_123 = pstore2_valid & _s1_hazard_T_122; // @[DCache.scala:501:30, :561:65, :565:21] wire s1_hazard = _s1_hazard_T_61 \| _s1_hazard_T_123; // @[DCache.scala:564:{27,69}, :565:21] wire s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala:564:69, :566:31] wire _T_68 = s1_valid & s1_raw_hazard; // @[DCache.scala:182:25, :566:31, :571:18] reg io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:38] assign _io_cpu_s2_nack_cause_raw_T_3 = io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:{38,54}] assign io_cpu_s2_nack_cause_raw_0 = _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:101:7, :574:54] wire _a_source_T = ~uncachedInFlight_0; // @[DCache.scala:236:33, :577:34] wire [1:0] _a_source_T_1 = {_a_source_T, 1'h0}; // @[DCache.scala:577:{34,59}] wire _a_source_T_2 = _a_source_T_1[0]; // @[OneHot.scala:48:45] wire _a_source_T_3 = _a_source_T_1[1]; // @[OneHot.scala:48:45] wire a_source = ~_a_source_T_2; // @[OneHot.scala:48:45] wire get_source = a_source; // @[Mux.scala:50:70] wire put_source = a_source; // @[Mux.scala:50:70] wire putpartial_source = a_source; // @[Mux.scala:50:70] wire atomics_a_source = a_source; // @[Mux.scala:50:70] wire atomics_a_1_source = a_source; // @[Mux.scala:50:70] wire atomics_a_2_source = a_source; // @[Mux.scala:50:70] wire atomics_a_3_source = a_source; // @[Mux.scala:50:70] wire atomics_a_4_source = a_source; // @[Mux.scala:50:70] wire atomics_a_5_source = a_source; // @[Mux.scala:50:70] wire atomics_a_6_source = a_source; // @[Mux.scala:50:70] wire atomics_a_7_source = a_source; // @[Mux.scala:50:70] wire atomics_a_8_source = a_source; // @[Mux.scala:50:70] wire a_sel_shiftAmount = a_source; // @[OneHot.scala:64:49] wire [39:0] acquire_address = {_acquire_address_T, 6'h0}; // @[DCache.scala:578:{38,49}] wire [127:0] a_data = {2{pstore1_data}}; // @[DCache.scala:494:31, :581:20] wire [127:0] put_data = a_data; // @[Edges.scala:480:17] wire [127:0] putpartial_data = a_data; // @[Edges.scala:500:17] wire [127:0] atomics_a_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_1_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_2_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_3_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_4_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_5_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_6_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_7_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_8_data = a_data; // @[Edges.scala:517:17] wire [3:0] _a_mask_T_1 = {_a_mask_T, 3'h0}; // @[package.scala:163:13] wire [22:0] a_mask = {15'h0, pstore1_mask} << _a_mask_T_1; // @[DCache.scala:496:31, :582:{29,90}] wire [39:0] _GEN_102 = {s2_req_addr[39:14], s2_req_addr[13:0] ^ 14'h3000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_4; // @[Parameters.scala:137:31] assign _putpartial_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_103 = {s2_req_addr[39:17], s2_req_addr[16:0] ^ 17'h10000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31] assign _put_legal_T_63 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_63; // @[Parameters.scala:137:31] assign _putpartial_legal_T_63 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_35; // @[Parameters.scala:137:31] assign _atomics_legal_T_35 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_94; // @[Parameters.scala:137:31] assign _atomics_legal_T_94 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_153; // @[Parameters.scala:137:31] assign _atomics_legal_T_153 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_212; // @[Parameters.scala:137:31] assign _atomics_legal_T_212 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_271; // @[Parameters.scala:137:31] assign _atomics_legal_T_271 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_330; // @[Parameters.scala:137:31] assign _atomics_legal_T_330 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_389; // @[Parameters.scala:137:31] assign _atomics_legal_T_389 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_448; // @[Parameters.scala:137:31] assign _atomics_legal_T_448 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_507; // @[Parameters.scala:137:31] assign _atomics_legal_T_507 = _GEN_103; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_104 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_104; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_24; // @[Parameters.scala:137:31] assign _putpartial_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_105 = {s2_req_addr[39:28], s2_req_addr[27:0] ^ 28'h8000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_34; // @[Parameters.scala:137:31] assign _putpartial_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_39; // @[Parameters.scala:137:31] assign _putpartial_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_45; // @[Parameters.scala:137:31] assign _atomics_legal_T_45 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_104; // @[Parameters.scala:137:31] assign _atomics_legal_T_104 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_163; // @[Parameters.scala:137:31] assign _atomics_legal_T_163 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_222; // @[Parameters.scala:137:31] assign _atomics_legal_T_222 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_281; // @[Parameters.scala:137:31] assign _atomics_legal_T_281 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_340; // @[Parameters.scala:137:31] assign _atomics_legal_T_340 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_399; // @[Parameters.scala:137:31] assign _atomics_legal_T_399 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_458; // @[Parameters.scala:137:31] assign _atomics_legal_T_458 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_517; // @[Parameters.scala:137:31] assign _atomics_legal_T_517 = _GEN_105; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_106 = {s2_req_addr[39:29], s2_req_addr[28:0] ^ 29'h10000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_44; // @[Parameters.scala:137:31] assign _putpartial_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_201; // @[Parameters.scala:137:31] assign _atomics_legal_T_201 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_260; // @[Parameters.scala:137:31] assign _atomics_legal_T_260 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_319; // @[Parameters.scala:137:31] assign _atomics_legal_T_319 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_378; // @[Parameters.scala:137:31] assign _atomics_legal_T_378 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_437; // @[Parameters.scala:137:31] assign _atomics_legal_T_437 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_496; // @[Parameters.scala:137:31] assign _atomics_legal_T_496 = _GEN_106; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] assign io_cpu_s2_paddr_0 = s2_req_addr[31:0]; // @[DCache.scala:101:7, :339:19] wire [31:0] get_address = s2_req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = s2_req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] putpartial_address = s2_req_addr[31:0]; // @[Edges.scala:500:17] wire [31:0] atomics_a_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [39:0] _GEN_107 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ 32'h80000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_49; // @[Parameters.scala:137:31] assign _putpartial_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_50; // @[Parameters.scala:137:31] assign _atomics_legal_T_50 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_109; // @[Parameters.scala:137:31] assign _atomics_legal_T_109 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_168; // @[Parameters.scala:137:31] assign _atomics_legal_T_168 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_227; // @[Parameters.scala:137:31] assign _atomics_legal_T_227 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_286; // @[Parameters.scala:137:31] assign _atomics_legal_T_286 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_345; // @[Parameters.scala:137:31] assign _atomics_legal_T_345 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_404; // @[Parameters.scala:137:31] assign _atomics_legal_T_404 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_463; // @[Parameters.scala:137:31] assign _atomics_legal_T_463 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_522; // @[Parameters.scala:137:31] assign _atomics_legal_T_522 = _GEN_107; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_54 = _get_legal_T_18 \| _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_55 = _get_legal_T_54 \| _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_56 = _get_legal_T_55 \| _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_57 = _get_legal_T_56 \| _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_58 = _get_legal_T_57 \| _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_59 = _get_legal_T_58 \| _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 \| _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_62 \| _get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [15:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [15:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_108 = {2'h0, s2_req_size}; // @[Edges.scala:463:15] assign get_size = _GEN_108; // @[Edges.scala:460:17, :463:15] wire [3:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_108; // @[Misc.scala:202:34] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_108; // @[Edges.scala:463:15, :480:17] wire [3:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_108; // @[Misc.scala:202:34] wire [3:0] putpartial_size; // @[Edges.scala:500:17] assign putpartial_size = _GEN_108; // @[Edges.scala:463:15, :500:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_108; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_size = get_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_sub_1_2 = get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_sub_nbit = ~get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_sub_0_2 = get_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_sub_acc_T = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_0_1 = _get_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _get_a_mask_sub_sub_sub_acc_T_1 = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_1_1 = _get_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_word_bypass_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_2_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T_2 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_2_1 = get_a_mask_sub_sub_sub_1_1 \| _get_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_3_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_3 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_3_1 = get_a_mask_sub_sub_sub_1_1 \| _get_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = s2_req_addr[1]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_4_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_4 = get_a_mask_sub_size & get_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_4_1 = get_a_mask_sub_sub_2_1 \| _get_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_5_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_5 = get_a_mask_sub_size & get_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_5_1 = get_a_mask_sub_sub_2_1 \| _get_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_6_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_6 = get_a_mask_sub_size & get_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_6_1 = get_a_mask_sub_sub_3_1 \| _get_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_7_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_7 = get_a_mask_sub_size & get_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_7_1 = get_a_mask_sub_sub_3_1 \| _get_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = s2_req_addr[0]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 \| _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 \| _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_8 = get_a_mask_sub_4_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_8 = get_a_mask_size & get_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_8 = get_a_mask_sub_4_1 \| _get_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_9 = get_a_mask_sub_4_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_9 = get_a_mask_size & get_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_9 = get_a_mask_sub_4_1 \| _get_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_10 = get_a_mask_sub_5_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_10 = get_a_mask_size & get_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_10 = get_a_mask_sub_5_1 \| _get_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_11 = get_a_mask_sub_5_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_11 = get_a_mask_size & get_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_11 = get_a_mask_sub_5_1 \| _get_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_12 = get_a_mask_sub_6_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_12 = get_a_mask_size & get_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_12 = get_a_mask_sub_6_1 \| _get_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_13 = get_a_mask_sub_6_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_13 = get_a_mask_size & get_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_13 = get_a_mask_sub_6_1 \| _get_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_14 = get_a_mask_sub_7_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_14 = get_a_mask_size & get_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_14 = get_a_mask_sub_7_1 \| _get_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_15 = get_a_mask_sub_7_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_15 = get_a_mask_size & get_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_15 = get_a_mask_sub_7_1 \| _get_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_lo = {get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_lo_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_hi = {get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo_lo = {get_a_mask_acc_9, get_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_lo_hi = {get_a_mask_acc_11, get_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_lo = {get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_hi_lo = {get_a_mask_acc_13, get_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi_hi = {get_a_mask_acc_15, get_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_hi = {get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_109 = {s2_req_addr[39:21], s2_req_addr[20:0] ^ 21'h100000}; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_19; // @[Parameters.scala:137:31] assign _putpartial_legal_T_19 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_363; // @[Parameters.scala:137:31] assign _atomics_legal_T_363 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_422; // @[Parameters.scala:137:31] assign _atomics_legal_T_422 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_481; // @[Parameters.scala:137:31] assign _atomics_legal_T_481 = _GEN_109; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_110 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2010000}; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_29; // @[Parameters.scala:137:31] assign _putpartial_legal_T_29 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_309; // @[Parameters.scala:137:31] assign _atomics_legal_T_309 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_368; // @[Parameters.scala:137:31] assign _atomics_legal_T_368 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_427; // @[Parameters.scala:137:31] assign _atomics_legal_T_427 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_486; // @[Parameters.scala:137:31] assign _atomics_legal_T_486 = _GEN_110; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_54 = _put_legal_T_18 \| _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_55 = _put_legal_T_54 \| _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_56 = _put_legal_T_55 \| _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_57 = _put_legal_T_56 \| _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_58 = _put_legal_T_57 \| _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_59 = _put_legal_T_58 \| _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 \| _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46] wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_70 = _put_legal_T_69 \| _put_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26] wire [15:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [15:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_size = put_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_sub_1_2 = put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_sub_nbit = ~put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_sub_0_2 = put_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_sub_acc_T = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_0_1 = _put_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _put_a_mask_sub_sub_sub_acc_T_1 = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_1_1 = _put_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_2_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T_2 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_2_1 = put_a_mask_sub_sub_sub_1_1 \| _put_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_3_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_3 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_3_1 = put_a_mask_sub_sub_sub_1_1 \| _put_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_4_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_4 = put_a_mask_sub_size & put_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_4_1 = put_a_mask_sub_sub_2_1 \| _put_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_5_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_5 = put_a_mask_sub_size & put_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_5_1 = put_a_mask_sub_sub_2_1 \| _put_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_6_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_6 = put_a_mask_sub_size & put_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_6_1 = put_a_mask_sub_sub_3_1 \| _put_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_7_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_7 = put_a_mask_sub_size & put_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_7_1 = put_a_mask_sub_sub_3_1 \| _put_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 \| _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 \| _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_8 = put_a_mask_sub_4_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_8 = put_a_mask_size & put_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_8 = put_a_mask_sub_4_1 \| _put_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_9 = put_a_mask_sub_4_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_9 = put_a_mask_size & put_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_9 = put_a_mask_sub_4_1 \| _put_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_10 = put_a_mask_sub_5_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_10 = put_a_mask_size & put_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_10 = put_a_mask_sub_5_1 \| _put_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_11 = put_a_mask_sub_5_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_11 = put_a_mask_size & put_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_11 = put_a_mask_sub_5_1 \| _put_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_12 = put_a_mask_sub_6_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_12 = put_a_mask_size & put_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_12 = put_a_mask_sub_6_1 \| _put_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_13 = put_a_mask_sub_6_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_13 = put_a_mask_size & put_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_13 = put_a_mask_sub_6_1 \| _put_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_14 = put_a_mask_sub_7_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_14 = put_a_mask_size & put_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_14 = put_a_mask_sub_7_1 \| _put_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_15 = put_a_mask_sub_7_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_15 = put_a_mask_size & put_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_15 = put_a_mask_sub_7_1 \| _put_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_lo = {put_a_mask_lo_lo_hi, put_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_lo_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_hi = {put_a_mask_lo_hi_hi, put_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo_lo = {put_a_mask_acc_9, put_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_lo_hi = {put_a_mask_acc_11, put_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_lo = {put_a_mask_hi_lo_hi, put_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_hi_lo = {put_a_mask_acc_13, put_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi_hi = {put_a_mask_acc_15, put_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_hi = {put_a_mask_hi_hi_hi, put_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _putpartial_legal_T_5 = {1'h0, _putpartial_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_6 = _putpartial_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_7 = _putpartial_legal_T_6; // @[Parameters.scala:137:46] wire _putpartial_legal_T_8 = _putpartial_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_9 = _putpartial_legal_T_8; // @[Parameters.scala:684:54] wire _putpartial_legal_T_69 = _putpartial_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _putpartial_legal_T_15 = {1'h0, _putpartial_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_16 = _putpartial_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_17 = _putpartial_legal_T_16; // @[Parameters.scala:137:46] wire _putpartial_legal_T_18 = _putpartial_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_20 = {1'h0, _putpartial_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_21 = _putpartial_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_22 = _putpartial_legal_T_21; // @[Parameters.scala:137:46] wire _putpartial_legal_T_23 = _putpartial_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_25 = {1'h0, _putpartial_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_26 = _putpartial_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_27 = _putpartial_legal_T_26; // @[Parameters.scala:137:46] wire _putpartial_legal_T_28 = _putpartial_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_30 = {1'h0, _putpartial_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_31 = _putpartial_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_32 = _putpartial_legal_T_31; // @[Parameters.scala:137:46] wire _putpartial_legal_T_33 = _putpartial_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_35 = {1'h0, _putpartial_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_36 = _putpartial_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_37 = _putpartial_legal_T_36; // @[Parameters.scala:137:46] wire _putpartial_legal_T_38 = _putpartial_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_40 = {1'h0, _putpartial_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_41 = _putpartial_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_42 = _putpartial_legal_T_41; // @[Parameters.scala:137:46] wire _putpartial_legal_T_43 = _putpartial_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_45 = {1'h0, _putpartial_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_46 = _putpartial_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_47 = _putpartial_legal_T_46; // @[Parameters.scala:137:46] wire _putpartial_legal_T_48 = _putpartial_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_50 = {1'h0, _putpartial_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_51 = _putpartial_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_52 = _putpartial_legal_T_51; // @[Parameters.scala:137:46] wire _putpartial_legal_T_53 = _putpartial_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_54 = _putpartial_legal_T_18 \| _putpartial_legal_T_23; // @[Parameters.scala:685:42] wire _putpartial_legal_T_55 = _putpartial_legal_T_54 \| _putpartial_legal_T_28; // @[Parameters.scala:685:42] wire _putpartial_legal_T_56 = _putpartial_legal_T_55 \| _putpartial_legal_T_33; // @[Parameters.scala:685:42] wire _putpartial_legal_T_57 = _putpartial_legal_T_56 \| _putpartial_legal_T_38; // @[Parameters.scala:685:42] wire _putpartial_legal_T_58 = _putpartial_legal_T_57 \| _putpartial_legal_T_43; // @[Parameters.scala:685:42] wire _putpartial_legal_T_59 = _putpartial_legal_T_58 \| _putpartial_legal_T_48; // @[Parameters.scala:685:42] wire _putpartial_legal_T_60 = _putpartial_legal_T_59 \| _putpartial_legal_T_53; // @[Parameters.scala:685:42] wire _putpartial_legal_T_61 = _putpartial_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _putpartial_legal_T_64 = {1'h0, _putpartial_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_65 = _putpartial_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_66 = _putpartial_legal_T_65; // @[Parameters.scala:137:46] wire _putpartial_legal_T_67 = _putpartial_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_70 = _putpartial_legal_T_69 \| _putpartial_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire putpartial_legal = _putpartial_legal_T_70; // @[Parameters.scala:686:26] wire [15:0] putpartial_mask; // @[Edges.scala:500:17] assign putpartial_mask = a_mask[15:0]; // @[Edges.scala:500:17, :508:15] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_111 = {s2_req_addr[39:28], s2_req_addr[27:0] ^ 28'hC000000}; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_255; // @[Parameters.scala:137:31] assign _atomics_legal_T_255 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_314; // @[Parameters.scala:137:31] assign _atomics_legal_T_314 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_373; // @[Parameters.scala:137:31] assign _atomics_legal_T_373 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_432; // @[Parameters.scala:137:31] assign _atomics_legal_T_432 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_491; // @[Parameters.scala:137:31] assign _atomics_legal_T_491 = _GEN_111; // @[Parameters.scala:137:31] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_29 = _atomics_legal_T_8 \| _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_30 = _atomics_legal_T_29 \| _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_31 = _atomics_legal_T_30 \| _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_32 = _atomics_legal_T_31 \| _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_33 = _atomics_legal_T_32; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_57 = _atomics_legal_T_33; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_36 = {1'h0, _atomics_legal_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_38 = _atomics_legal_T_37; // @[Parameters.scala:137:46] wire _atomics_legal_T_39 = _atomics_legal_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_46 = {1'h0, _atomics_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_47 = _atomics_legal_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_48 = _atomics_legal_T_47; // @[Parameters.scala:137:46] wire _atomics_legal_T_49 = _atomics_legal_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_51 = {1'h0, _atomics_legal_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_52 = _atomics_legal_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_53 = _atomics_legal_T_52; // @[Parameters.scala:137:46] wire _atomics_legal_T_54 = _atomics_legal_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_55 = _atomics_legal_T_49 \| _atomics_legal_T_54; // @[Parameters.scala:685:42] wire _atomics_legal_T_56 = _atomics_legal_T_55; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_58 = _atomics_legal_T_57; // @[Parameters.scala:686:26] wire atomics_legal = _atomics_legal_T_58 \| _atomics_legal_T_56; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [15:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size = atomics_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit = ~atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1 = _atomics_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1 = atomics_a_mask_sub_sub_sub_1_1 \| _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1 = atomics_a_mask_sub_sub_sub_1_1 \| _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size & atomics_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1 = atomics_a_mask_sub_sub_2_1 \| _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size & atomics_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1 = atomics_a_mask_sub_sub_2_1 \| _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size & atomics_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1 = atomics_a_mask_sub_sub_3_1 \| _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size & atomics_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1 = atomics_a_mask_sub_sub_3_1 \| _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_4_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_4_1 \| _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_4_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_4_1 \| _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_5_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_5_1 \| _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_5_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_5_1 \| _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_6_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_6_1 \| _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_6_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_6_1 \| _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_7_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_7_1 \| _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_7_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_7_1 \| _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo = {atomics_a_mask_lo_lo_hi, atomics_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi = {atomics_a_mask_lo_hi_hi, atomics_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo = {atomics_a_mask_hi_lo_hi, atomics_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi = {atomics_a_mask_hi_hi_hi, atomics_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_88 = _atomics_legal_T_67 \| _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_89 = _atomics_legal_T_88 \| _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_90 = _atomics_legal_T_89 \| _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_91 = _atomics_legal_T_90 \| _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_92 = _atomics_legal_T_91; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_116 = _atomics_legal_T_92; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_95 = {1'h0, _atomics_legal_T_94}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_96 = _atomics_legal_T_95 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_97 = _atomics_legal_T_96; // @[Parameters.scala:137:46] wire _atomics_legal_T_98 = _atomics_legal_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_105 = {1'h0, _atomics_legal_T_104}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_106 = _atomics_legal_T_105 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_107 = _atomics_legal_T_106; // @[Parameters.scala:137:46] wire _atomics_legal_T_108 = _atomics_legal_T_107 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_110 = {1'h0, _atomics_legal_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_111 = _atomics_legal_T_110 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_112 = _atomics_legal_T_111; // @[Parameters.scala:137:46] wire _atomics_legal_T_113 = _atomics_legal_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_114 = _atomics_legal_T_108 \| _atomics_legal_T_113; // @[Parameters.scala:685:42] wire _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_117 = _atomics_legal_T_116; // @[Parameters.scala:686:26] wire atomics_legal_1 = _atomics_legal_T_117 \| _atomics_legal_T_115; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [15:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_1 = atomics_a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 \| _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 \| _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_1 = atomics_a_mask_sub_sub_2_1_1 \| _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_1 = atomics_a_mask_sub_sub_2_1_1 \| _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_1 = atomics_a_mask_sub_sub_3_1_1 \| _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_1 = atomics_a_mask_sub_sub_3_1_1 \| _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_1 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_1 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_1 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_1 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_1 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_1 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_1 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_1 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_1 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_4_1_1 \| _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_1 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_4_1_1 \| _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_1 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_5_1_1 \| _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_1 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_5_1_1 \| _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_1 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_6_1_1 \| _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_1 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_6_1_1 \| _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_1 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_7_1_1 \| _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_1 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_7_1_1 \| _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_1 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_1 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_lo_lo_hi_1, atomics_a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_1 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_1 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_lo_hi_hi_1, atomics_a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_1 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_1 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_hi_lo_hi_1, atomics_a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_1 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_1 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_hi_hi_hi_1, atomics_a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_126 \| _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 \| _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 \| _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 \| _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_175 = _atomics_legal_T_151; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_154 = {1'h0, _atomics_legal_T_153}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_155 = _atomics_legal_T_154 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_156 = _atomics_legal_T_155; // @[Parameters.scala:137:46] wire _atomics_legal_T_157 = _atomics_legal_T_156 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_164 = {1'h0, _atomics_legal_T_163}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_165 = _atomics_legal_T_164 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_166 = _atomics_legal_T_165; // @[Parameters.scala:137:46] wire _atomics_legal_T_167 = _atomics_legal_T_166 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_169 = {1'h0, _atomics_legal_T_168}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_170 = _atomics_legal_T_169 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_171 = _atomics_legal_T_170; // @[Parameters.scala:137:46] wire _atomics_legal_T_172 = _atomics_legal_T_171 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_173 = _atomics_legal_T_167 \| _atomics_legal_T_172; // @[Parameters.scala:685:42] wire _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_176 = _atomics_legal_T_175; // @[Parameters.scala:686:26] wire atomics_legal_2 = _atomics_legal_T_176 \| _atomics_legal_T_174; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [15:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_2 = atomics_a_mask_sizeOH_2[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 \| _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 \| _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_4_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_2 = atomics_a_mask_sub_sub_2_1_2 \| _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_5_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_2 = atomics_a_mask_sub_sub_2_1_2 \| _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_6_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_2 = atomics_a_mask_sub_sub_3_1_2 \| _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_7_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_2 = atomics_a_mask_sub_sub_3_1_2 \| _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_2 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_2 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_2 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_2 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_2 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_2 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_2 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_2 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_2 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_4_1_2 \| _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_2 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_4_1_2 \| _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_2 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_5_1_2 \| _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_2 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_5_1_2 \| _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_2 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_6_1_2 \| _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_2 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_6_1_2 \| _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_2 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_7_1_2 \| _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_2 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_7_1_2 \| _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_2 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_2 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_lo_lo_hi_2, atomics_a_mask_lo_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_2 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_2 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_lo_hi_hi_2, atomics_a_mask_lo_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_2 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_2 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_hi_lo_hi_2, atomics_a_mask_hi_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_2 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_2 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_hi_hi_hi_2, atomics_a_mask_hi_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_202 = {1'h0, _atomics_legal_T_201}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_203 = _atomics_legal_T_202 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_204 = _atomics_legal_T_203; // @[Parameters.scala:137:46] wire _atomics_legal_T_205 = _atomics_legal_T_204 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_206 = _atomics_legal_T_185 \| _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206 \| _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_208 = _atomics_legal_T_207 \| _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_209 = _atomics_legal_T_208 \| _atomics_legal_T_205; // @[Parameters.scala:685:42] wire _atomics_legal_T_210 = _atomics_legal_T_209; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_234 = _atomics_legal_T_210; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_213 = {1'h0, _atomics_legal_T_212}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_214 = _atomics_legal_T_213 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_215 = _atomics_legal_T_214; // @[Parameters.scala:137:46] wire _atomics_legal_T_216 = _atomics_legal_T_215 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_223 = {1'h0, _atomics_legal_T_222}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_224 = _atomics_legal_T_223 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_225 = _atomics_legal_T_224; // @[Parameters.scala:137:46] wire _atomics_legal_T_226 = _atomics_legal_T_225 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_228 = {1'h0, _atomics_legal_T_227}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_229 = _atomics_legal_T_228 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_230 = _atomics_legal_T_229; // @[Parameters.scala:137:46] wire _atomics_legal_T_231 = _atomics_legal_T_230 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_232 = _atomics_legal_T_226 \| _atomics_legal_T_231; // @[Parameters.scala:685:42] wire _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_235 = _atomics_legal_T_234; // @[Parameters.scala:686:26] wire atomics_legal_3 = _atomics_legal_T_235 \| _atomics_legal_T_233; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [15:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_3 = atomics_a_mask_sizeOH_3[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 \| _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 \| _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_4_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_3 = atomics_a_mask_sub_sub_2_1_3 \| _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_5_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_3 = atomics_a_mask_sub_sub_2_1_3 \| _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_6_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_3 = atomics_a_mask_sub_sub_3_1_3 \| _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_7_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_3 = atomics_a_mask_sub_sub_3_1_3 \| _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_3 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_3 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_3 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_3 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_3 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_3 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_3 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_3 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_3 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_4_1_3 \| _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_3 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_4_1_3 \| _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_3 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_5_1_3 \| _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_3 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_5_1_3 \| _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_3 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_6_1_3 \| _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_3 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_6_1_3 \| _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_3 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_7_1_3 \| _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_3 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_7_1_3 \| _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_3 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_3 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_lo_lo_hi_3, atomics_a_mask_lo_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_3 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_3 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_lo_hi_hi_3, atomics_a_mask_lo_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_3 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_3 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_hi_lo_hi_3, atomics_a_mask_hi_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_3 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_3 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_hi_hi_hi_3, atomics_a_mask_hi_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_256 = {1'h0, _atomics_legal_T_255}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_257 = _atomics_legal_T_256 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_258 = _atomics_legal_T_257; // @[Parameters.scala:137:46] wire _atomics_legal_T_259 = _atomics_legal_T_258 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_261 = {1'h0, _atomics_legal_T_260}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_262 = _atomics_legal_T_261 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_263 = _atomics_legal_T_262; // @[Parameters.scala:137:46] wire _atomics_legal_T_264 = _atomics_legal_T_263 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_265 = _atomics_legal_T_244 \| _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_266 = _atomics_legal_T_265 \| _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_267 = _atomics_legal_T_266 \| _atomics_legal_T_259; // @[Parameters.scala:685:42] wire _atomics_legal_T_268 = _atomics_legal_T_267 \| _atomics_legal_T_264; // @[Parameters.scala:685:42] wire _atomics_legal_T_269 = _atomics_legal_T_268; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_293 = _atomics_legal_T_269; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_272 = {1'h0, _atomics_legal_T_271}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_273 = _atomics_legal_T_272 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_274 = _atomics_legal_T_273; // @[Parameters.scala:137:46] wire _atomics_legal_T_275 = _atomics_legal_T_274 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_282 = {1'h0, _atomics_legal_T_281}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_283 = _atomics_legal_T_282 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_284 = _atomics_legal_T_283; // @[Parameters.scala:137:46] wire _atomics_legal_T_285 = _atomics_legal_T_284 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_287 = {1'h0, _atomics_legal_T_286}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_288 = _atomics_legal_T_287 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_289 = _atomics_legal_T_288; // @[Parameters.scala:137:46] wire _atomics_legal_T_290 = _atomics_legal_T_289 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_291 = _atomics_legal_T_285 \| _atomics_legal_T_290; // @[Parameters.scala:685:42] wire _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_294 = _atomics_legal_T_293; // @[Parameters.scala:686:26] wire atomics_legal_4 = _atomics_legal_T_294 \| _atomics_legal_T_292; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [15:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_4 = atomics_a_mask_sizeOH_4[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_18 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 \| _atomics_a_mask_sub_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_19 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 \| _atomics_a_mask_sub_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_36 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_4_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_4 = atomics_a_mask_sub_sub_2_1_4 \| _atomics_a_mask_sub_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_37 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_5_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_4 = atomics_a_mask_sub_sub_2_1_4 \| _atomics_a_mask_sub_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_38 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_6_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_4 = atomics_a_mask_sub_sub_3_1_4 \| _atomics_a_mask_sub_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_39 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_7_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_4 = atomics_a_mask_sub_sub_3_1_4 \| _atomics_a_mask_sub_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_4 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_4 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_4 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_4 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_4 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_4 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_4 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_4 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_72 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_72 = atomics_a_mask_size_4 & atomics_a_mask_eq_72; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_72 = atomics_a_mask_sub_4_1_4 \| _atomics_a_mask_acc_T_72; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_73 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_73 = atomics_a_mask_size_4 & atomics_a_mask_eq_73; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_73 = atomics_a_mask_sub_4_1_4 \| _atomics_a_mask_acc_T_73; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_74 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_74 = atomics_a_mask_size_4 & atomics_a_mask_eq_74; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_74 = atomics_a_mask_sub_5_1_4 \| _atomics_a_mask_acc_T_74; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_75 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_75 = atomics_a_mask_size_4 & atomics_a_mask_eq_75; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_75 = atomics_a_mask_sub_5_1_4 \| _atomics_a_mask_acc_T_75; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_76 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_76 = atomics_a_mask_size_4 & atomics_a_mask_eq_76; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_76 = atomics_a_mask_sub_6_1_4 \| _atomics_a_mask_acc_T_76; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_77 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_77 = atomics_a_mask_size_4 & atomics_a_mask_eq_77; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_77 = atomics_a_mask_sub_6_1_4 \| _atomics_a_mask_acc_T_77; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_78 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_78 = atomics_a_mask_size_4 & atomics_a_mask_eq_78; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_78 = atomics_a_mask_sub_7_1_4 \| _atomics_a_mask_acc_T_78; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_79 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_79 = atomics_a_mask_size_4 & atomics_a_mask_eq_79; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_79 = atomics_a_mask_sub_7_1_4 \| _atomics_a_mask_acc_T_79; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_4 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_4 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_lo_lo_hi_4, atomics_a_mask_lo_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_4 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_4 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_lo_hi_hi_4, atomics_a_mask_lo_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_4 = {atomics_a_mask_acc_73, atomics_a_mask_acc_72}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_4 = {atomics_a_mask_acc_75, atomics_a_mask_acc_74}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_hi_lo_hi_4, atomics_a_mask_hi_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_4 = {atomics_a_mask_acc_77, atomics_a_mask_acc_76}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_4 = {atomics_a_mask_acc_79, atomics_a_mask_acc_78}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_hi_hi_hi_4, atomics_a_mask_hi_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_310 = {1'h0, _atomics_legal_T_309}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_311 = _atomics_legal_T_310 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_312 = _atomics_legal_T_311; // @[Parameters.scala:137:46] wire _atomics_legal_T_313 = _atomics_legal_T_312 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_315 = {1'h0, _atomics_legal_T_314}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_316 = _atomics_legal_T_315 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_317 = _atomics_legal_T_316; // @[Parameters.scala:137:46] wire _atomics_legal_T_318 = _atomics_legal_T_317 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_320 = {1'h0, _atomics_legal_T_319}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_321 = _atomics_legal_T_320 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_322 = _atomics_legal_T_321; // @[Parameters.scala:137:46] wire _atomics_legal_T_323 = _atomics_legal_T_322 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_324 = _atomics_legal_T_303 \| _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_325 = _atomics_legal_T_324 \| _atomics_legal_T_313; // @[Parameters.scala:685:42] wire _atomics_legal_T_326 = _atomics_legal_T_325 \| _atomics_legal_T_318; // @[Parameters.scala:685:42] wire _atomics_legal_T_327 = _atomics_legal_T_326 \| _atomics_legal_T_323; // @[Parameters.scala:685:42] wire _atomics_legal_T_328 = _atomics_legal_T_327; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_352 = _atomics_legal_T_328; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_331 = {1'h0, _atomics_legal_T_330}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_332 = _atomics_legal_T_331 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_333 = _atomics_legal_T_332; // @[Parameters.scala:137:46] wire _atomics_legal_T_334 = _atomics_legal_T_333 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_341 = {1'h0, _atomics_legal_T_340}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_342 = _atomics_legal_T_341 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_343 = _atomics_legal_T_342; // @[Parameters.scala:137:46] wire _atomics_legal_T_344 = _atomics_legal_T_343 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_346 = {1'h0, _atomics_legal_T_345}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_347 = _atomics_legal_T_346 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_348 = _atomics_legal_T_347; // @[Parameters.scala:137:46] wire _atomics_legal_T_349 = _atomics_legal_T_348 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_350 = _atomics_legal_T_344 \| _atomics_legal_T_349; // @[Parameters.scala:685:42] wire _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_353 = _atomics_legal_T_352; // @[Parameters.scala:686:26] wire atomics_legal_5 = _atomics_legal_T_353 \| _atomics_legal_T_351; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [15:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_5 = atomics_a_mask_sizeOH_5[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_20 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_21 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_22 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 \| _atomics_a_mask_sub_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_23 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 \| _atomics_a_mask_sub_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_40 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_41 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_42 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_43 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_44 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_4_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_5 = atomics_a_mask_sub_sub_2_1_5 \| _atomics_a_mask_sub_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_45 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_5_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_5 = atomics_a_mask_sub_sub_2_1_5 \| _atomics_a_mask_sub_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_46 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_6_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_5 = atomics_a_mask_sub_sub_3_1_5 \| _atomics_a_mask_sub_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_47 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_7_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_5 = atomics_a_mask_sub_sub_3_1_5 \| _atomics_a_mask_sub_acc_T_47; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_80 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_80 = atomics_a_mask_size_5 & atomics_a_mask_eq_80; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_80 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_80; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_81 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_81 = atomics_a_mask_size_5 & atomics_a_mask_eq_81; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_81 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_81; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_82 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_82 = atomics_a_mask_size_5 & atomics_a_mask_eq_82; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_82 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_82; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_83 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_83 = atomics_a_mask_size_5 & atomics_a_mask_eq_83; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_83 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_83; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_84 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_84 = atomics_a_mask_size_5 & atomics_a_mask_eq_84; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_84 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_84; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_85 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_85 = atomics_a_mask_size_5 & atomics_a_mask_eq_85; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_85 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_85; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_86 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_86 = atomics_a_mask_size_5 & atomics_a_mask_eq_86; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_86 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_86; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_87 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_87 = atomics_a_mask_size_5 & atomics_a_mask_eq_87; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_87 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_87; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_88 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_88 = atomics_a_mask_size_5 & atomics_a_mask_eq_88; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_88 = atomics_a_mask_sub_4_1_5 \| _atomics_a_mask_acc_T_88; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_89 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_89 = atomics_a_mask_size_5 & atomics_a_mask_eq_89; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_89 = atomics_a_mask_sub_4_1_5 \| _atomics_a_mask_acc_T_89; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_90 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_90 = atomics_a_mask_size_5 & atomics_a_mask_eq_90; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_90 = atomics_a_mask_sub_5_1_5 \| _atomics_a_mask_acc_T_90; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_91 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_91 = atomics_a_mask_size_5 & atomics_a_mask_eq_91; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_91 = atomics_a_mask_sub_5_1_5 \| _atomics_a_mask_acc_T_91; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_92 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_92 = atomics_a_mask_size_5 & atomics_a_mask_eq_92; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_92 = atomics_a_mask_sub_6_1_5 \| _atomics_a_mask_acc_T_92; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_93 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_93 = atomics_a_mask_size_5 & atomics_a_mask_eq_93; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_93 = atomics_a_mask_sub_6_1_5 \| _atomics_a_mask_acc_T_93; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_94 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_94 = atomics_a_mask_size_5 & atomics_a_mask_eq_94; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_94 = atomics_a_mask_sub_7_1_5 \| _atomics_a_mask_acc_T_94; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_95 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_95 = atomics_a_mask_size_5 & atomics_a_mask_eq_95; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_95 = atomics_a_mask_sub_7_1_5 \| _atomics_a_mask_acc_T_95; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_5 = {atomics_a_mask_acc_81, atomics_a_mask_acc_80}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_5 = {atomics_a_mask_acc_83, atomics_a_mask_acc_82}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_lo_lo_hi_5, atomics_a_mask_lo_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_5 = {atomics_a_mask_acc_85, atomics_a_mask_acc_84}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_5 = {atomics_a_mask_acc_87, atomics_a_mask_acc_86}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_lo_hi_hi_5, atomics_a_mask_lo_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_5 = {atomics_a_mask_acc_89, atomics_a_mask_acc_88}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_5 = {atomics_a_mask_acc_91, atomics_a_mask_acc_90}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_hi_lo_hi_5, atomics_a_mask_hi_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_5 = {atomics_a_mask_acc_93, atomics_a_mask_acc_92}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_5 = {atomics_a_mask_acc_95, atomics_a_mask_acc_94}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_hi_hi_hi_5, atomics_a_mask_hi_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_364 = {1'h0, _atomics_legal_T_363}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_365 = _atomics_legal_T_364 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_366 = _atomics_legal_T_365; // @[Parameters.scala:137:46] wire _atomics_legal_T_367 = _atomics_legal_T_366 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_369 = {1'h0, _atomics_legal_T_368}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_370 = _atomics_legal_T_369 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_371 = _atomics_legal_T_370; // @[Parameters.scala:137:46] wire _atomics_legal_T_372 = _atomics_legal_T_371 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_374 = {1'h0, _atomics_legal_T_373}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_375 = _atomics_legal_T_374 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_376 = _atomics_legal_T_375; // @[Parameters.scala:137:46] wire _atomics_legal_T_377 = _atomics_legal_T_376 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_379 = {1'h0, _atomics_legal_T_378}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_380 = _atomics_legal_T_379 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_381 = _atomics_legal_T_380; // @[Parameters.scala:137:46] wire _atomics_legal_T_382 = _atomics_legal_T_381 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_383 = _atomics_legal_T_362 \| _atomics_legal_T_367; // @[Parameters.scala:685:42] wire _atomics_legal_T_384 = _atomics_legal_T_383 \| _atomics_legal_T_372; // @[Parameters.scala:685:42] wire _atomics_legal_T_385 = _atomics_legal_T_384 \| _atomics_legal_T_377; // @[Parameters.scala:685:42] wire _atomics_legal_T_386 = _atomics_legal_T_385 \| _atomics_legal_T_382; // @[Parameters.scala:685:42] wire _atomics_legal_T_387 = _atomics_legal_T_386; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_411 = _atomics_legal_T_387; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_390 = {1'h0, _atomics_legal_T_389}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_391 = _atomics_legal_T_390 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_392 = _atomics_legal_T_391; // @[Parameters.scala:137:46] wire _atomics_legal_T_393 = _atomics_legal_T_392 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_400 = {1'h0, _atomics_legal_T_399}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_401 = _atomics_legal_T_400 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_402 = _atomics_legal_T_401; // @[Parameters.scala:137:46] wire _atomics_legal_T_403 = _atomics_legal_T_402 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_405 = {1'h0, _atomics_legal_T_404}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_406 = _atomics_legal_T_405 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_407 = _atomics_legal_T_406; // @[Parameters.scala:137:46] wire _atomics_legal_T_408 = _atomics_legal_T_407 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_409 = _atomics_legal_T_403 \| _atomics_legal_T_408; // @[Parameters.scala:685:42] wire _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_412 = _atomics_legal_T_411; // @[Parameters.scala:686:26] wire atomics_legal_6 = _atomics_legal_T_412 \| _atomics_legal_T_410; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [15:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_6 = atomics_a_mask_sizeOH_6[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_24 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_25 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_26 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 \| _atomics_a_mask_sub_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_27 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 \| _atomics_a_mask_sub_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_48 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_49 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_50 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_51 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_52 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_4_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_6 = atomics_a_mask_sub_sub_2_1_6 \| _atomics_a_mask_sub_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_53 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_5_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_6 = atomics_a_mask_sub_sub_2_1_6 \| _atomics_a_mask_sub_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_54 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_6_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_6 = atomics_a_mask_sub_sub_3_1_6 \| _atomics_a_mask_sub_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_55 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_7_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_6 = atomics_a_mask_sub_sub_3_1_6 \| _atomics_a_mask_sub_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_96 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_96 = atomics_a_mask_size_6 & atomics_a_mask_eq_96; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_96 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_96; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_97 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_97 = atomics_a_mask_size_6 & atomics_a_mask_eq_97; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_97 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_97; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_98 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_98 = atomics_a_mask_size_6 & atomics_a_mask_eq_98; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_98 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_98; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_99 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_99 = atomics_a_mask_size_6 & atomics_a_mask_eq_99; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_99 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_99; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_100 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_100 = atomics_a_mask_size_6 & atomics_a_mask_eq_100; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_100 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_100; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_101 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_101 = atomics_a_mask_size_6 & atomics_a_mask_eq_101; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_101 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_101; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_102 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_102 = atomics_a_mask_size_6 & atomics_a_mask_eq_102; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_102 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_102; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_103 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_103 = atomics_a_mask_size_6 & atomics_a_mask_eq_103; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_103 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_103; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_104 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_104 = atomics_a_mask_size_6 & atomics_a_mask_eq_104; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_104 = atomics_a_mask_sub_4_1_6 \| _atomics_a_mask_acc_T_104; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_105 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_105 = atomics_a_mask_size_6 & atomics_a_mask_eq_105; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_105 = atomics_a_mask_sub_4_1_6 \| _atomics_a_mask_acc_T_105; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_106 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_106 = atomics_a_mask_size_6 & atomics_a_mask_eq_106; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_106 = atomics_a_mask_sub_5_1_6 \| _atomics_a_mask_acc_T_106; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_107 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_107 = atomics_a_mask_size_6 & atomics_a_mask_eq_107; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_107 = atomics_a_mask_sub_5_1_6 \| _atomics_a_mask_acc_T_107; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_108 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_108 = atomics_a_mask_size_6 & atomics_a_mask_eq_108; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_108 = atomics_a_mask_sub_6_1_6 \| _atomics_a_mask_acc_T_108; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_109 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_109 = atomics_a_mask_size_6 & atomics_a_mask_eq_109; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_109 = atomics_a_mask_sub_6_1_6 \| _atomics_a_mask_acc_T_109; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_110 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_110 = atomics_a_mask_size_6 & atomics_a_mask_eq_110; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_110 = atomics_a_mask_sub_7_1_6 \| _atomics_a_mask_acc_T_110; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_111 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_111 = atomics_a_mask_size_6 & atomics_a_mask_eq_111; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_111 = atomics_a_mask_sub_7_1_6 \| _atomics_a_mask_acc_T_111; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_6 = {atomics_a_mask_acc_97, atomics_a_mask_acc_96}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_6 = {atomics_a_mask_acc_99, atomics_a_mask_acc_98}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_lo_lo_hi_6, atomics_a_mask_lo_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_6 = {atomics_a_mask_acc_101, atomics_a_mask_acc_100}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_6 = {atomics_a_mask_acc_103, atomics_a_mask_acc_102}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_lo_hi_hi_6, atomics_a_mask_lo_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_6 = {atomics_a_mask_acc_105, atomics_a_mask_acc_104}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_6 = {atomics_a_mask_acc_107, atomics_a_mask_acc_106}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_hi_lo_hi_6, atomics_a_mask_hi_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_6 = {atomics_a_mask_acc_109, atomics_a_mask_acc_108}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_6 = {atomics_a_mask_acc_111, atomics_a_mask_acc_110}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_hi_hi_hi_6, atomics_a_mask_hi_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_418 = {1'h0, _atomics_legal_T_417}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_419 = _atomics_legal_T_418 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_420 = _atomics_legal_T_419; // @[Parameters.scala:137:46] wire _atomics_legal_T_421 = _atomics_legal_T_420 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_423 = {1'h0, _atomics_legal_T_422}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_424 = _atomics_legal_T_423 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_425 = _atomics_legal_T_424; // @[Parameters.scala:137:46] wire _atomics_legal_T_426 = _atomics_legal_T_425 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_428 = {1'h0, _atomics_legal_T_427}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_429 = _atomics_legal_T_428 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_430 = _atomics_legal_T_429; // @[Parameters.scala:137:46] wire _atomics_legal_T_431 = _atomics_legal_T_430 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_433 = {1'h0, _atomics_legal_T_432}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_434 = _atomics_legal_T_433 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_435 = _atomics_legal_T_434; // @[Parameters.scala:137:46] wire _atomics_legal_T_436 = _atomics_legal_T_435 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_438 = {1'h0, _atomics_legal_T_437}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_440 = _atomics_legal_T_439; // @[Parameters.scala:137:46] wire _atomics_legal_T_441 = _atomics_legal_T_440 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_442 = _atomics_legal_T_421 \| _atomics_legal_T_426; // @[Parameters.scala:685:42] wire _atomics_legal_T_443 = _atomics_legal_T_442 \| _atomics_legal_T_431; // @[Parameters.scala:685:42] wire _atomics_legal_T_444 = _atomics_legal_T_443 \| _atomics_legal_T_436; // @[Parameters.scala:685:42] wire _atomics_legal_T_445 = _atomics_legal_T_444 \| _atomics_legal_T_441; // @[Parameters.scala:685:42] wire _atomics_legal_T_446 = _atomics_legal_T_445; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_470 = _atomics_legal_T_446; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_449 = {1'h0, _atomics_legal_T_448}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_450 = _atomics_legal_T_449 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_451 = _atomics_legal_T_450; // @[Parameters.scala:137:46] wire _atomics_legal_T_452 = _atomics_legal_T_451 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_459 = {1'h0, _atomics_legal_T_458}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_460 = _atomics_legal_T_459 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_461 = _atomics_legal_T_460; // @[Parameters.scala:137:46] wire _atomics_legal_T_462 = _atomics_legal_T_461 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_464 = {1'h0, _atomics_legal_T_463}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_465 = _atomics_legal_T_464 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_466 = _atomics_legal_T_465; // @[Parameters.scala:137:46] wire _atomics_legal_T_467 = _atomics_legal_T_466 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_468 = _atomics_legal_T_462 \| _atomics_legal_T_467; // @[Parameters.scala:685:42] wire _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_471 = _atomics_legal_T_470; // @[Parameters.scala:686:26] wire atomics_legal_7 = _atomics_legal_T_471 \| _atomics_legal_T_469; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [15:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_7 = atomics_a_mask_sizeOH_7[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_28 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_29 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_30 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 \| _atomics_a_mask_sub_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_31 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 \| _atomics_a_mask_sub_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_56 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_57 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_58 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_59 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_60 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_4_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_7 = atomics_a_mask_sub_sub_2_1_7 \| _atomics_a_mask_sub_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_61 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_5_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_7 = atomics_a_mask_sub_sub_2_1_7 \| _atomics_a_mask_sub_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_62 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_6_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_7 = atomics_a_mask_sub_sub_3_1_7 \| _atomics_a_mask_sub_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_63 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_7_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_7 = atomics_a_mask_sub_sub_3_1_7 \| _atomics_a_mask_sub_acc_T_63; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_112 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_112 = atomics_a_mask_size_7 & atomics_a_mask_eq_112; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_112 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_112; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_113 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_113 = atomics_a_mask_size_7 & atomics_a_mask_eq_113; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_113 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_113; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_114 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_114 = atomics_a_mask_size_7 & atomics_a_mask_eq_114; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_114 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_114; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_115 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_115 = atomics_a_mask_size_7 & atomics_a_mask_eq_115; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_115 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_115; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_116 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_116 = atomics_a_mask_size_7 & atomics_a_mask_eq_116; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_116 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_116; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_117 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_117 = atomics_a_mask_size_7 & atomics_a_mask_eq_117; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_117 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_117; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_118 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_118 = atomics_a_mask_size_7 & atomics_a_mask_eq_118; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_118 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_118; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_119 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_119 = atomics_a_mask_size_7 & atomics_a_mask_eq_119; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_119 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_119; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_120 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_120 = atomics_a_mask_size_7 & atomics_a_mask_eq_120; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_120 = atomics_a_mask_sub_4_1_7 \| _atomics_a_mask_acc_T_120; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_121 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_121 = atomics_a_mask_size_7 & atomics_a_mask_eq_121; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_121 = atomics_a_mask_sub_4_1_7 \| _atomics_a_mask_acc_T_121; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_122 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_122 = atomics_a_mask_size_7 & atomics_a_mask_eq_122; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_122 = atomics_a_mask_sub_5_1_7 \| _atomics_a_mask_acc_T_122; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_123 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_123 = atomics_a_mask_size_7 & atomics_a_mask_eq_123; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_123 = atomics_a_mask_sub_5_1_7 \| _atomics_a_mask_acc_T_123; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_124 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_124 = atomics_a_mask_size_7 & atomics_a_mask_eq_124; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_124 = atomics_a_mask_sub_6_1_7 \| _atomics_a_mask_acc_T_124; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_125 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_125 = atomics_a_mask_size_7 & atomics_a_mask_eq_125; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_125 = atomics_a_mask_sub_6_1_7 \| _atomics_a_mask_acc_T_125; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_126 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_126 = atomics_a_mask_size_7 & atomics_a_mask_eq_126; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_126 = atomics_a_mask_sub_7_1_7 \| _atomics_a_mask_acc_T_126; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_127 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_127 = atomics_a_mask_size_7 & atomics_a_mask_eq_127; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_127 = atomics_a_mask_sub_7_1_7 \| _atomics_a_mask_acc_T_127; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_7 = {atomics_a_mask_acc_113, atomics_a_mask_acc_112}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_7 = {atomics_a_mask_acc_115, atomics_a_mask_acc_114}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_lo_lo_hi_7, atomics_a_mask_lo_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_7 = {atomics_a_mask_acc_117, atomics_a_mask_acc_116}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_7 = {atomics_a_mask_acc_119, atomics_a_mask_acc_118}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_lo_hi_hi_7, atomics_a_mask_lo_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_7 = {atomics_a_mask_acc_121, atomics_a_mask_acc_120}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_7 = {atomics_a_mask_acc_123, atomics_a_mask_acc_122}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_hi_lo_hi_7, atomics_a_mask_hi_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_7 = {atomics_a_mask_acc_125, atomics_a_mask_acc_124}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_7 = {atomics_a_mask_acc_127, atomics_a_mask_acc_126}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_hi_hi_hi_7, atomics_a_mask_hi_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_477 = {1'h0, _atomics_legal_T_476}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_478 = _atomics_legal_T_477 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_479 = _atomics_legal_T_478; // @[Parameters.scala:137:46] wire _atomics_legal_T_480 = _atomics_legal_T_479 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_482 = {1'h0, _atomics_legal_T_481}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_483 = _atomics_legal_T_482 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_484 = _atomics_legal_T_483; // @[Parameters.scala:137:46] wire _atomics_legal_T_485 = _atomics_legal_T_484 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_487 = {1'h0, _atomics_legal_T_486}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_488 = _atomics_legal_T_487 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_489 = _atomics_legal_T_488; // @[Parameters.scala:137:46] wire _atomics_legal_T_490 = _atomics_legal_T_489 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_492 = {1'h0, _atomics_legal_T_491}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_493 = _atomics_legal_T_492 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_494 = _atomics_legal_T_493; // @[Parameters.scala:137:46] wire _atomics_legal_T_495 = _atomics_legal_T_494 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_497 = {1'h0, _atomics_legal_T_496}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_498 = _atomics_legal_T_497 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_499 = _atomics_legal_T_498; // @[Parameters.scala:137:46] wire _atomics_legal_T_500 = _atomics_legal_T_499 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_501 = _atomics_legal_T_480 \| _atomics_legal_T_485; // @[Parameters.scala:685:42] wire _atomics_legal_T_502 = _atomics_legal_T_501 \| _atomics_legal_T_490; // @[Parameters.scala:685:42] wire _atomics_legal_T_503 = _atomics_legal_T_502 \| _atomics_legal_T_495; // @[Parameters.scala:685:42] wire _atomics_legal_T_504 = _atomics_legal_T_503 \| _atomics_legal_T_500; // @[Parameters.scala:685:42] wire _atomics_legal_T_505 = _atomics_legal_T_504; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_529 = _atomics_legal_T_505; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_508 = {1'h0, _atomics_legal_T_507}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_509 = _atomics_legal_T_508 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_510 = _atomics_legal_T_509; // @[Parameters.scala:137:46] wire _atomics_legal_T_511 = _atomics_legal_T_510 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_518 = {1'h0, _atomics_legal_T_517}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_519 = _atomics_legal_T_518 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_520 = _atomics_legal_T_519; // @[Parameters.scala:137:46] wire _atomics_legal_T_521 = _atomics_legal_T_520 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_523 = {1'h0, _atomics_legal_T_522}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_524 = _atomics_legal_T_523 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_525 = _atomics_legal_T_524; // @[Parameters.scala:137:46] wire _atomics_legal_T_526 = _atomics_legal_T_525 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_527 = _atomics_legal_T_521 \| _atomics_legal_T_526; // @[Parameters.scala:685:42] wire _atomics_legal_T_528 = _atomics_legal_T_527; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_530 = _atomics_legal_T_529; // @[Parameters.scala:686:26] wire atomics_legal_8 = _atomics_legal_T_530 \| _atomics_legal_T_528; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [15:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_8 = atomics_a_mask_sizeOH_8[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_32 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_33 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_34 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 \| _atomics_a_mask_sub_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_35 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 \| _atomics_a_mask_sub_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_64 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_65 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_66 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_67 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_68 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_4_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_8 = atomics_a_mask_sub_sub_2_1_8 \| _atomics_a_mask_sub_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_69 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_5_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_8 = atomics_a_mask_sub_sub_2_1_8 \| _atomics_a_mask_sub_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_70 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_6_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_8 = atomics_a_mask_sub_sub_3_1_8 \| _atomics_a_mask_sub_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_71 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_7_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_8 = atomics_a_mask_sub_sub_3_1_8 \| _atomics_a_mask_sub_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_128 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_128 = atomics_a_mask_size_8 & atomics_a_mask_eq_128; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_128 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_128; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_129 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_129 = atomics_a_mask_size_8 & atomics_a_mask_eq_129; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_129 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_129; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_130 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_130 = atomics_a_mask_size_8 & atomics_a_mask_eq_130; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_130 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_130; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_131 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_131 = atomics_a_mask_size_8 & atomics_a_mask_eq_131; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_131 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_131; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_132 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_132 = atomics_a_mask_size_8 & atomics_a_mask_eq_132; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_132 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_132; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_133 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_133 = atomics_a_mask_size_8 & atomics_a_mask_eq_133; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_133 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_133; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_134 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_134 = atomics_a_mask_size_8 & atomics_a_mask_eq_134; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_134 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_134; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_135 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_135 = atomics_a_mask_size_8 & atomics_a_mask_eq_135; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_135 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_135; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_136 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_136 = atomics_a_mask_size_8 & atomics_a_mask_eq_136; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_136 = atomics_a_mask_sub_4_1_8 \| _atomics_a_mask_acc_T_136; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_137 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_137 = atomics_a_mask_size_8 & atomics_a_mask_eq_137; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_137 = atomics_a_mask_sub_4_1_8 \| _atomics_a_mask_acc_T_137; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_138 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_138 = atomics_a_mask_size_8 & atomics_a_mask_eq_138; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_138 = atomics_a_mask_sub_5_1_8 \| _atomics_a_mask_acc_T_138; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_139 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_139 = atomics_a_mask_size_8 & atomics_a_mask_eq_139; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_139 = atomics_a_mask_sub_5_1_8 \| _atomics_a_mask_acc_T_139; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_140 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_140 = atomics_a_mask_size_8 & atomics_a_mask_eq_140; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_140 = atomics_a_mask_sub_6_1_8 \| _atomics_a_mask_acc_T_140; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_141 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_141 = atomics_a_mask_size_8 & atomics_a_mask_eq_141; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_141 = atomics_a_mask_sub_6_1_8 \| _atomics_a_mask_acc_T_141; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_142 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_142 = atomics_a_mask_size_8 & atomics_a_mask_eq_142; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_142 = atomics_a_mask_sub_7_1_8 \| _atomics_a_mask_acc_T_142; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_143 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_143 = atomics_a_mask_size_8 & atomics_a_mask_eq_143; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_143 = atomics_a_mask_sub_7_1_8 \| _atomics_a_mask_acc_T_143; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_8 = {atomics_a_mask_acc_129, atomics_a_mask_acc_128}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_8 = {atomics_a_mask_acc_131, atomics_a_mask_acc_130}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_lo_lo_hi_8, atomics_a_mask_lo_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_8 = {atomics_a_mask_acc_133, atomics_a_mask_acc_132}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_8 = {atomics_a_mask_acc_135, atomics_a_mask_acc_134}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_lo_hi_hi_8, atomics_a_mask_lo_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_8 = {atomics_a_mask_acc_137, atomics_a_mask_acc_136}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_8 = {atomics_a_mask_acc_139, atomics_a_mask_acc_138}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_hi_lo_hi_8, atomics_a_mask_hi_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_8 = {atomics_a_mask_acc_141, atomics_a_mask_acc_140}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_8 = {atomics_a_mask_acc_143, atomics_a_mask_acc_142}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_hi_hi_hi_8, atomics_a_mask_hi_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [2:0] _GEN_112 = _atomics_T ? 3'h3 : 3'h0; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_opcode; // @[DCache.scala:587:81] assign _atomics_T_1_opcode = _GEN_112; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_param; // @[DCache.scala:587:81] assign _atomics_T_1_param = _GEN_112; // @[DCache.scala:587:81] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire _atomics_T_1_source = _atomics_T & atomics_a_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [15:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 16'h0; // @[Edges.scala:534:17] wire [127:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 128'h0; // @[Edges.scala:534:17] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire _atomics_T_3_source = _atomics_T_2 ? atomics_a_1_source : _atomics_T_1_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire _atomics_T_5_source = _atomics_T_4 ? atomics_a_2_source : _atomics_T_3_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire _atomics_T_7_source = _atomics_T_6 ? atomics_a_3_source : _atomics_T_5_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire _atomics_T_9_source = _atomics_T_8 ? atomics_a_4_source : _atomics_T_7_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire _atomics_T_11_source = _atomics_T_10 ? atomics_a_5_source : _atomics_T_9_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire _atomics_T_13_source = _atomics_T_12 ? atomics_a_6_source : _atomics_T_11_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire _atomics_T_15_source = _atomics_T_14 ? atomics_a_7_source : _atomics_T_13_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[DCache.scala:587:81] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[DCache.scala:587:81] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire atomics_source = _atomics_T_16 ? atomics_a_8_source : _atomics_T_15_source; // @[Edges.scala:517:17] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [15:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [127:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17] wire [39:0] _tl_out_a_valid_T_1 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ release_ack_addr}; // @[DCache.scala:227:29, :339:19, :606:43] wire [14:0] _tl_out_a_valid_T_2 = _tl_out_a_valid_T_1[20:6]; // @[DCache.scala:606:{43,62}] wire _tl_out_a_valid_T_3 = _tl_out_a_valid_T_2 == 15'h0; // @[DCache.scala:582:29, :606:{62,118}] wire _tl_out_a_valid_T_4 = release_ack_wait & _tl_out_a_valid_T_3; // @[DCache.scala:226:33, :606:{27,118}] wire _tl_out_a_valid_T_5 = ~_tl_out_a_valid_T_4; // @[DCache.scala:606:{8,27}] wire _tl_out_a_valid_T_6 = s2_valid_cached_miss & _tl_out_a_valid_T_5; // @[DCache.scala:425:60, :605:29, :606:8] wire _tl_out_a_valid_T_7 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47] wire _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[Misc.scala:38:9] wire _tl_out_a_valid_T_11 = _tl_out_a_valid_T_10; // @[DCache.scala:607:{88,91}] wire _tl_out_a_valid_T_12 = _tl_out_a_valid_T_6 & _tl_out_a_valid_T_11; // @[DCache.scala:605:29, :606:127, :607:88] wire _tl_out_a_valid_T_13 = s2_valid_uncached_pending \| _tl_out_a_valid_T_12; // @[DCache.scala:430:64, :604:32, :606:127] assign _tl_out_a_valid_T_14 = _tl_out_a_valid_T_13; // @[DCache.scala:603:37, :604:32] assign tl_out_a_valid = _tl_out_a_valid_T_14; // @[DCache.scala:159:22, :603:37] wire _tl_out_a_bits_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47, :608:24] wire [39:0] _tl_out_a_bits_T_2 = {_tl_out_a_bits_T_1, 6'h0}; // @[DCache.scala:1210:{39,60}] wire [39:0] _tl_out_a_bits_legal_T_1 = _tl_out_a_bits_T_2; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_2 = {1'h0, _tl_out_a_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_3 = _tl_out_a_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_4 = _tl_out_a_bits_legal_T_3; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_5 = _tl_out_a_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _tl_out_a_bits_legal_T_6 = {_tl_out_a_bits_T_2[39:17], _tl_out_a_bits_T_2[16:0] ^ 17'h10000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_7 = {1'h0, _tl_out_a_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_8 = _tl_out_a_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_9 = _tl_out_a_bits_legal_T_8; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_10 = _tl_out_a_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _tl_out_a_bits_legal_T_11 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'hC000000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_12 = {1'h0, _tl_out_a_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_13 = _tl_out_a_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_14 = _tl_out_a_bits_legal_T_13; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_15 = _tl_out_a_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _tl_out_a_bits_legal_T_16 = _tl_out_a_bits_legal_T_5 \| _tl_out_a_bits_legal_T_10; // @[Parameters.scala:685:42] wire _tl_out_a_bits_legal_T_17 = _tl_out_a_bits_legal_T_16 \| _tl_out_a_bits_legal_T_15; // @[Parameters.scala:685:42] wire [39:0] _tl_out_a_bits_legal_T_21 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'h8000000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_22 = {1'h0, _tl_out_a_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_23 = _tl_out_a_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_24 = _tl_out_a_bits_legal_T_23; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_25 = _tl_out_a_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] tl_out_a_bits_a_address = _tl_out_a_bits_T_2[31:0]; // @[Edges.scala:346:17] wire [39:0] _tl_out_a_bits_legal_T_26 = {_tl_out_a_bits_T_2[39:32], tl_out_a_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [40:0] _tl_out_a_bits_legal_T_27 = {1'h0, _tl_out_a_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_28 = _tl_out_a_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_29 = _tl_out_a_bits_legal_T_28; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_30 = _tl_out_a_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _tl_out_a_bits_legal_T_31 = _tl_out_a_bits_legal_T_25 \| _tl_out_a_bits_legal_T_30; // @[Parameters.scala:685:42] wire _tl_out_a_bits_legal_T_32 = _tl_out_a_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire tl_out_a_bits_legal = _tl_out_a_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] wire [2:0] tl_out_a_bits_a_param; // @[Edges.scala:346:17] assign tl_out_a_bits_a_param = {1'h0, s2_grow_param}; // @[Misc.scala:35:36] wire tl_out_a_bits_a_mask_sub_sub_sub_bit = _tl_out_a_bits_T_2[3]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_sub_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_sub_sub_nbit = ~tl_out_a_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_sub_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_sub_bit = _tl_out_a_bits_T_2[2]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_sub_nbit = ~tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T = tl_out_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T_1 = tl_out_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_sub_2_2 = tl_out_a_bits_a_mask_sub_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T_2 = tl_out_a_bits_a_mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_sub_3_2 = tl_out_a_bits_a_mask_sub_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T_3 = tl_out_a_bits_a_mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_bit = _tl_out_a_bits_T_2[1]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_nbit = ~tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_2_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_3_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_4_2 = tl_out_a_bits_a_mask_sub_sub_2_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_5_2 = tl_out_a_bits_a_mask_sub_sub_2_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_6_2 = tl_out_a_bits_a_mask_sub_sub_3_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_7_2 = tl_out_a_bits_a_mask_sub_sub_3_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_bit = _tl_out_a_bits_T_2[0]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_nbit = ~tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_eq = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T = tl_out_a_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_1 = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_1 = tl_out_a_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_2 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_2 = tl_out_a_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_3 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_3 = tl_out_a_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_4 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_4 = tl_out_a_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_5 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_5 = tl_out_a_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_6 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_6 = tl_out_a_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_7 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_7 = tl_out_a_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_8 = tl_out_a_bits_a_mask_sub_4_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_8 = tl_out_a_bits_a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_9 = tl_out_a_bits_a_mask_sub_4_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_9 = tl_out_a_bits_a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_10 = tl_out_a_bits_a_mask_sub_5_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_10 = tl_out_a_bits_a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_11 = tl_out_a_bits_a_mask_sub_5_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_11 = tl_out_a_bits_a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_12 = tl_out_a_bits_a_mask_sub_6_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_12 = tl_out_a_bits_a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_13 = tl_out_a_bits_a_mask_sub_6_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_13 = tl_out_a_bits_a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_14 = tl_out_a_bits_a_mask_sub_7_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_14 = tl_out_a_bits_a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_15 = tl_out_a_bits_a_mask_sub_7_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_15 = tl_out_a_bits_a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _tl_out_a_bits_T_3 = ~s2_write; // @[DCache.scala:609:9] wire _tl_out_a_bits_T_5 = ~s2_read; // @[DCache.scala:611:9] wire [2:0] _tl_out_a_bits_T_6_opcode = _tl_out_a_bits_T_5 ? 3'h0 : atomics_opcode; // @[DCache.scala:587:81, :611:{8,9}] wire [2:0] _tl_out_a_bits_T_6_param = _tl_out_a_bits_T_5 ? 3'h0 : atomics_param; // @[DCache.scala:587:81, :611:{8,9}] wire [3:0] _tl_out_a_bits_T_6_size = _tl_out_a_bits_T_5 ? put_size : atomics_size; // @[Edges.scala:480:17] wire _tl_out_a_bits_T_6_source = _tl_out_a_bits_T_5 ? put_source : atomics_source; // @[Edges.scala:480:17] wire [31:0] _tl_out_a_bits_T_6_address = _tl_out_a_bits_T_5 ? put_address : atomics_address; // @[Edges.scala:480:17] wire [15:0] _tl_out_a_bits_T_6_mask = _tl_out_a_bits_T_5 ? put_mask : atomics_mask; // @[Edges.scala:480:17] wire [127:0] _tl_out_a_bits_T_6_data = _tl_out_a_bits_T_5 ? put_data : atomics_data; // @[Edges.scala:480:17] wire [2:0] _tl_out_a_bits_T_7_opcode = _tl_out_a_bits_T_4 ? 3'h1 : _tl_out_a_bits_T_6_opcode; // @[DCache.scala:610:{8,20}, :611:8] wire [2:0] _tl_out_a_bits_T_7_param = _tl_out_a_bits_T_4 ? 3'h0 : _tl_out_a_bits_T_6_param; // @[DCache.scala:610:{8,20}, :611:8] wire [3:0] _tl_out_a_bits_T_7_size = _tl_out_a_bits_T_4 ? putpartial_size : _tl_out_a_bits_T_6_size; // @[Edges.scala:500:17] wire _tl_out_a_bits_T_7_source = _tl_out_a_bits_T_4 ? putpartial_source : _tl_out_a_bits_T_6_source; // @[Edges.scala:500:17] wire [31:0] _tl_out_a_bits_T_7_address = _tl_out_a_bits_T_4 ? putpartial_address : _tl_out_a_bits_T_6_address; // @[Edges.scala:500:17] wire [15:0] _tl_out_a_bits_T_7_mask = _tl_out_a_bits_T_4 ? putpartial_mask : _tl_out_a_bits_T_6_mask; // @[Edges.scala:500:17] wire [127:0] _tl_out_a_bits_T_7_data = _tl_out_a_bits_T_4 ? putpartial_data : _tl_out_a_bits_T_6_data; // @[Edges.scala:500:17] wire [2:0] _tl_out_a_bits_T_8_opcode = _tl_out_a_bits_T_3 ? 3'h4 : _tl_out_a_bits_T_7_opcode; // @[DCache.scala:609:{8,9}, :610:8] wire [2:0] _tl_out_a_bits_T_8_param = _tl_out_a_bits_T_3 ? 3'h0 : _tl_out_a_bits_T_7_param; // @[DCache.scala:609:{8,9}, :610:8] wire [3:0] _tl_out_a_bits_T_8_size = _tl_out_a_bits_T_3 ? get_size : _tl_out_a_bits_T_7_size; // @[Edges.scala:460:17] wire _tl_out_a_bits_T_8_source = _tl_out_a_bits_T_3 ? get_source : _tl_out_a_bits_T_7_source; // @[Edges.scala:460:17] wire [31:0] _tl_out_a_bits_T_8_address = _tl_out_a_bits_T_3 ? get_address : _tl_out_a_bits_T_7_address; // @[Edges.scala:460:17] wire [15:0] _tl_out_a_bits_T_8_mask = _tl_out_a_bits_T_3 ? get_mask : _tl_out_a_bits_T_7_mask; // @[Edges.scala:460:17] wire [127:0] _tl_out_a_bits_T_8_data = _tl_out_a_bits_T_3 ? 128'h0 : _tl_out_a_bits_T_7_data; // @[DCache.scala:609:{8,9}, :610:8] assign _tl_out_a_bits_T_9_opcode = _tl_out_a_bits_T ? 3'h6 : _tl_out_a_bits_T_8_opcode; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_param = _tl_out_a_bits_T ? tl_out_a_bits_a_param : _tl_out_a_bits_T_8_param; // @[Edges.scala:346:17] assign _tl_out_a_bits_T_9_size = _tl_out_a_bits_T ? 4'h6 : _tl_out_a_bits_T_8_size; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_source = ~_tl_out_a_bits_T & _tl_out_a_bits_T_8_source; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_address = _tl_out_a_bits_T ? tl_out_a_bits_a_address : _tl_out_a_bits_T_8_address; // @[Edges.scala:346:17] assign _tl_out_a_bits_T_9_mask = _tl_out_a_bits_T ? 16'hFFFF : _tl_out_a_bits_T_8_mask; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_data = _tl_out_a_bits_T ? 128'h0 : _tl_out_a_bits_T_8_data; // @[DCache.scala:608:{23,24}, :609:8] assign tl_out_a_bits_opcode = _tl_out_a_bits_T_9_opcode; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_param = _tl_out_a_bits_T_9_param; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_size = _tl_out_a_bits_T_9_size; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_source = _tl_out_a_bits_T_9_source; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_address = _tl_out_a_bits_T_9_address; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_mask = _tl_out_a_bits_T_9_mask; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_data = _tl_out_a_bits_T_9_data; // @[DCache.scala:159:22, :608:23] wire [1:0] _a_sel_T = 2'h1 << a_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _a_sel_T_1 = _a_sel_T; // @[OneHot.scala:65:{12,27}] wire a_sel = _a_sel_T_1[1]; // @[OneHot.scala:65:27] wire _io_cpu_perf_acquire_T = tl_out_a_ready & tl_out_a_valid; // @[Decoupled.scala:51:35] wire [4:0] _uncachedReqs_0_cmd_T_1 = {_uncachedReqs_0_cmd_T, 4'h1}; // @[DCache.scala:637:{37,49}] wire [4:0] _uncachedReqs_0_cmd_T_2 = s2_write ? _uncachedReqs_0_cmd_T_1 : 5'h0; // @[DCache.scala:637:{23,37}] wire _T_90 = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire _io_cpu_replay_next_T; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T = _T_90; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_near_end_of_refill_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_blocked_near_end_of_refill_T = _T_90; // @[Decoupled.scala:51:35] wire _io_errors_bus_valid_T; // @[Decoupled.scala:51:35] assign _io_errors_bus_valid_T = _T_90; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire r_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] r_counter; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_last = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = d_last & _T_90; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T = d_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_address_inc = {r_4, 4'h0}; // @[Edges.scala:234:25, :269:29] wire grantIsUncachedData = nodeOut_d_bits_opcode == 3'h1; // @[package.scala:16:47] wire grantIsUncached = grantIsUncachedData \| nodeOut_d_bits_opcode == 3'h0 \| nodeOut_d_bits_opcode == 3'h2; // @[package.scala:16:47, :81:59] wire _tl_d_data_encoded_T_17 = io_ptw_customCSRs_csrs_0_value_0[9]; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_18 = ~_tl_d_data_encoded_T_17; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_19 = nodeOut_d_bits_corrupt & _tl_d_data_encoded_T_18; // @[DCache.scala:663:{77,80}] wire _tl_d_data_encoded_T_20 = ~grantIsUncached; // @[package.scala:81:59] wire _tl_d_data_encoded_T_21 = _tl_d_data_encoded_T_19 & _tl_d_data_encoded_T_20; // @[DCache.scala:663:{77,126,129}] wire [15:0] tl_d_data_encoded_lo_lo_lo_1 = {_tl_d_data_encoded_T_23, _tl_d_data_encoded_T_22}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_lo_hi_1 = {_tl_d_data_encoded_T_25, _tl_d_data_encoded_T_24}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_lo_1 = {tl_d_data_encoded_lo_lo_hi_1, tl_d_data_encoded_lo_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_lo_hi_lo_1 = {_tl_d_data_encoded_T_27, _tl_d_data_encoded_T_26}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi_hi_1 = {_tl_d_data_encoded_T_29, _tl_d_data_encoded_T_28}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_hi_1 = {tl_d_data_encoded_lo_hi_hi_1, tl_d_data_encoded_lo_hi_lo_1}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_lo_1 = {tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo_lo_1 = {_tl_d_data_encoded_T_31, _tl_d_data_encoded_T_30}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_lo_hi_1 = {_tl_d_data_encoded_T_33, _tl_d_data_encoded_T_32}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_lo_1 = {tl_d_data_encoded_hi_lo_hi_1, tl_d_data_encoded_hi_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_hi_lo_1 = {_tl_d_data_encoded_T_35, _tl_d_data_encoded_T_34}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi_hi_1 = {_tl_d_data_encoded_T_37, _tl_d_data_encoded_T_36}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_hi_1 = {tl_d_data_encoded_hi_hi_hi_1, tl_d_data_encoded_hi_hi_lo_1}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_hi_1 = {tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1}; // @[package.scala:45:27] assign _tl_d_data_encoded_T_38 = {tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1}; // @[package.scala:45:27] assign tl_d_data_encoded = _tl_d_data_encoded_T_38; // @[package.scala:45:27] wire _grantIsCached_T = nodeOut_d_bits_opcode == 3'h4; // @[package.scala:16:47] wire _GEN_113 = nodeOut_d_bits_opcode == 3'h5; // @[package.scala:16:47] wire _grantIsCached_T_1; // @[package.scala:16:47] assign _grantIsCached_T_1 = _GEN_113; // @[package.scala:16:47] wire grantIsRefill; // @[DCache.scala:666:29] assign grantIsRefill = _GEN_113; // @[package.scala:16:47] wire grantIsCached = _grantIsCached_T \| _grantIsCached_T_1; // @[package.scala:16:47, :81:59] wire grantIsVoluntary = nodeOut_d_bits_opcode == 3'h6; // @[DCache.scala:665:32] reg grantInProgress; // @[DCache.scala:667:32] reg [2:0] blockProbeAfterGrantCount; // @[DCache.scala:668:42] wire [3:0] _blockProbeAfterGrantCount_T = {1'h0, blockProbeAfterGrantCount} - 4'h1; // @[DCache.scala:668:42, :669:99] wire [2:0] _blockProbeAfterGrantCount_T_1 = _blockProbeAfterGrantCount_T[2:0]; // @[DCache.scala:669:99] wire _T_115 = release_state == 4'h6; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_1; // @[package.scala:16:47] assign _canAcceptCachedGrant_T_1 = _T_115; // @[package.scala:16:47] wire _metaArb_io_in_4_valid_T; // @[package.scala:16:47] assign _metaArb_io_in_4_valid_T = _T_115; // @[package.scala:16:47] wire _T_119 = release_state == 4'h9; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_2; // @[package.scala:16:47] assign _canAcceptCachedGrant_T_2 = _T_119; // @[package.scala:16:47] wire _nodeOut_c_valid_T_1; // @[DCache.scala:810:91] assign _nodeOut_c_valid_T_1 = _T_119; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_3 = _canAcceptCachedGrant_T \| _canAcceptCachedGrant_T_1; // @[package.scala:16:47, :81:59] wire _canAcceptCachedGrant_T_4 = _canAcceptCachedGrant_T_3 \| _canAcceptCachedGrant_T_2; // @[package.scala:16:47, :81:59] wire canAcceptCachedGrant = ~_canAcceptCachedGrant_T_4; // @[package.scala:81:59] wire _nodeOut_d_ready_T = ~d_first; // @[Edges.scala:231:25] wire _nodeOut_d_ready_T_1 = _nodeOut_d_ready_T \| nodeOut_e_ready; // @[DCache.scala:671:{41,50}] wire _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :671:{50,69}] wire _nodeOut_d_ready_T_3 = ~grantIsCached \| _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [1:0] _uncachedRespIdxOH_T = 2'h1 << uncachedRespIdxOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _uncachedRespIdxOH_T_1 = _uncachedRespIdxOH_T; // @[OneHot.scala:65:{12,27}] wire uncachedRespIdxOH = _uncachedRespIdxOH_T_1[1]; // @[OneHot.scala:65:27] wire _uncachedResp_T = uncachedRespIdxOH; // @[Mux.scala:32:36] wire _GEN_114 = _T_90 & grantIsCached; // @[Decoupled.scala:51:35] assign replace = _GEN_114 & d_last; // @[Replacement.scala:37:29, :38:11] wire _T_82 = uncachedRespIdxOH & d_last; // @[Edges.scala:232:33] assign s1_data_way = ~_T_90 \| grantIsCached \| ~(grantIsUncached & grantIsUncachedData) ? {1'h0, _s1_data_way_T} : 9'h100; // @[Decoupled.scala:51:35] wire [27:0] _s2_req_addr_dontCareBits_T = s1_paddr[31:4]; // @[DCache.scala:298:21, :701:41] wire [31:0] s2_req_addr_dontCareBits = {_s2_req_addr_dontCareBits_T, 4'h0}; // @[DCache.scala:701:{41,55}] wire [3:0] _s2_req_addr_T = uncachedResp_addr[3:0]; // @[DCache.scala:238:30, :702:45] wire [31:0] _s2_req_addr_T_1 = {s2_req_addr_dontCareBits[31:4], s2_req_addr_dontCareBits[3:0] \| _s2_req_addr_T}; // @[DCache.scala:701:55, :702:{26,45}] wire _nodeOut_e_valid_T = nodeOut_d_valid & d_first; // @[Edges.scala:231:25] wire _nodeOut_e_valid_T_1 = _nodeOut_e_valid_T & grantIsCached; // @[package.scala:81:59] wire _nodeOut_e_valid_T_2 = _nodeOut_e_valid_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :714:{47,64}] assign nodeOut_e_bits_sink = nodeOut_e_bits_e_sink; // @[Edges.scala:451:17] wire _dataArb_io_in_1_valid_T = nodeOut_d_valid & grantIsRefill; // @[DCache.scala:666:29, :721:44] wire _dataArb_io_in_1_valid_T_1 = _dataArb_io_in_1_valid_T & canAcceptCachedGrant; // @[DCache.scala:670:30, :721:{44,61}] wire _T_98 = grantIsRefill & ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :666:29, :722:{23,26}] assign nodeOut_e_valid = ~_T_98 & _nodeOut_e_valid_T_2; // @[DCache.scala:714:{18,64}, :722:{23,51}, :723:20] wire [33:0] _dataArb_io_in_1_bits_addr_T = s2_vaddr[39:6]; // @[DCache.scala:351:21, :728:46] wire [39:0] _dataArb_io_in_1_bits_addr_T_1 = {_dataArb_io_in_1_bits_addr_T, 6'h0}; // @[DCache.scala:728:{46,57}] wire [39:0] _dataArb_io_in_1_bits_addr_T_2 = {_dataArb_io_in_1_bits_addr_T_1[39:12], _dataArb_io_in_1_bits_addr_T_1[11:0] \| d_address_inc}; // @[Edges.scala:269:29] assign dataArb_io_in_1_bits_addr = _dataArb_io_in_1_bits_addr_T_2[11:0]; // @[DCache.scala:152:28, :728:{32,67}] wire _metaArb_io_in_3_valid_T = grantIsCached & d_done; // @[package.scala:81:59] wire _metaArb_io_in_3_valid_T_1 = ~nodeOut_d_bits_denied; // @[DCache.scala:741:56] assign _metaArb_io_in_3_valid_T_2 = _metaArb_io_in_3_valid_T & _metaArb_io_in_3_valid_T_1; // @[DCache.scala:741:{43,53,56}] assign metaArb_io_in_3_valid = _metaArb_io_in_3_valid_T_2; // @[DCache.scala:135:28, :741:53] assign metaArb_io_in_3_bits_idx = _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:135:28, :744:40] assign _metaArb_io_in_3_bits_addr_T_2 = {_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:745:{36,58,80}] assign metaArb_io_in_3_bits_addr = _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:135:28, :745:36] wire _metaArb_io_in_3_bits_data_c_cat_T_2 = _metaArb_io_in_3_bits_data_c_cat_T \| _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_4 = _metaArb_io_in_3_bits_data_c_cat_T_2 \| _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_9 = _metaArb_io_in_3_bits_data_c_cat_T_5 \| _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_10 = _metaArb_io_in_3_bits_data_c_cat_T_9 \| _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_11 = _metaArb_io_in_3_bits_data_c_cat_T_10 \| _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_17 = _metaArb_io_in_3_bits_data_c_cat_T_12 \| _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_18 = _metaArb_io_in_3_bits_data_c_cat_T_17 \| _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_19 = _metaArb_io_in_3_bits_data_c_cat_T_18 \| _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_20 = _metaArb_io_in_3_bits_data_c_cat_T_19 \| _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_21 = _metaArb_io_in_3_bits_data_c_cat_T_11 \| _metaArb_io_in_3_bits_data_c_cat_T_20; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_22 = _metaArb_io_in_3_bits_data_c_cat_T_4 \| _metaArb_io_in_3_bits_data_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_25 = _metaArb_io_in_3_bits_data_c_cat_T_23 \| _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_27 = _metaArb_io_in_3_bits_data_c_cat_T_25 \| _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_32 = _metaArb_io_in_3_bits_data_c_cat_T_28 \| _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_33 = _metaArb_io_in_3_bits_data_c_cat_T_32 \| _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_34 = _metaArb_io_in_3_bits_data_c_cat_T_33 \| _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_40 = _metaArb_io_in_3_bits_data_c_cat_T_35 \| _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_41 = _metaArb_io_in_3_bits_data_c_cat_T_40 \| _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_42 = _metaArb_io_in_3_bits_data_c_cat_T_41 \| _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_43 = _metaArb_io_in_3_bits_data_c_cat_T_42 \| _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_44 = _metaArb_io_in_3_bits_data_c_cat_T_34 \| _metaArb_io_in_3_bits_data_c_cat_T_43; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_45 = _metaArb_io_in_3_bits_data_c_cat_T_27 \| _metaArb_io_in_3_bits_data_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_47 = _metaArb_io_in_3_bits_data_c_cat_T_45 \| _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _metaArb_io_in_3_bits_data_c_cat_T_49 = _metaArb_io_in_3_bits_data_c_cat_T_47 \| _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] metaArb_io_in_3_bits_data_c = {_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _metaArb_io_in_3_bits_data_T_1 = {metaArb_io_in_3_bits_data_c, nodeOut_d_bits_param}; // @[Metadata.scala:29:18, :84:18] wire _metaArb_io_in_3_bits_data_T_10 = _metaArb_io_in_3_bits_data_T_1 == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_11 = {1'h0, _metaArb_io_in_3_bits_data_T_10}; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_12 = _metaArb_io_in_3_bits_data_T_1 == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_13 = _metaArb_io_in_3_bits_data_T_12 ? 2'h2 : _metaArb_io_in_3_bits_data_T_11; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_14 = _metaArb_io_in_3_bits_data_T_1 == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_15 = _metaArb_io_in_3_bits_data_T_14 ? 2'h2 : _metaArb_io_in_3_bits_data_T_13; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_16 = _metaArb_io_in_3_bits_data_T_1 == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_17 = _metaArb_io_in_3_bits_data_T_16 ? 2'h3 : _metaArb_io_in_3_bits_data_T_15; // @[Metadata.scala:84:38] wire [1:0] metaArb_io_in_3_bits_data_meta_state = _metaArb_io_in_3_bits_data_T_17; // @[Metadata.scala:84:38, :160:20] wire [1:0] metaArb_io_in_3_bits_data_meta_1_coh_state = metaArb_io_in_3_bits_data_meta_state; // @[Metadata.scala:160:20] wire [19:0] metaArb_io_in_3_bits_data_meta_1_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data_meta_1_tag = _metaArb_io_in_3_bits_data_T[19:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_3_bits_data_T_18 = {metaArb_io_in_3_bits_data_meta_1_coh_state, metaArb_io_in_3_bits_data_meta_1_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data = _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:135:28, :746:134] reg blockUncachedGrant; // @[DCache.scala:750:33] wire _T_100 = grantIsUncachedData & (blockUncachedGrant \| s1_valid); // @[package.scala:16:47] assign nodeOut_d_ready = ~(_T_100 \| _T_98) & _nodeOut_d_ready_T_3; // @[DCache.scala:671:{18,24}, :722:{23,51}, :724:20, :752:{31,68}, :753:22] assign io_cpu_req_ready_0 = _T_100 ? ~(nodeOut_d_valid \| _T_10 \| ~metaArb_io_in_7_ready \| _T_4) & _io_cpu_req_ready_T_4 : ~(_T_10 \| ~metaArb_io_in_7_ready \| _T_4) & _io_cpu_req_ready_T_4; // @[DCache.scala:101:7, :135:28, :195:9, :233:{20,73}, :258:{33,45,64}, :267:{34,53}, :275:{27,53,79,98}, :752:{31,68}, :755:29, :756:26] wire _GEN_115 = _T_100 & nodeOut_d_valid; // @[DCache.scala:721:26, :752:{31,68}, :755:29, :757:32] assign dataArb_io_in_1_valid = _GEN_115 \| _dataArb_io_in_1_valid_T_1; // @[DCache.scala:152:28, :721:{26,61}, :752:68, :755:29, :757:32] assign dataArb_io_in_1_bits_write = ~_T_100 \| ~nodeOut_d_valid; // @[DCache.scala:152:28, :727:33, :752:{31,68}, :755:29, :758:37] wire _blockUncachedGrant_T = ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :722:26, :759:31] wire _block_probe_for_core_progress_T = \|blockProbeAfterGrantCount; // @[DCache.scala:668:42, :669:35, :766:65] wire block_probe_for_core_progress = _block_probe_for_core_progress_T \| lrscValid; // @[DCache.scala:473:29, :766:{65,71}] wire [31:0] _block_probe_for_pending_release_ack_T = nodeOut_b_bits_address ^ release_ack_addr; // @[DCache.scala:227:29, :767:88] wire [14:0] _block_probe_for_pending_release_ack_T_1 = _block_probe_for_pending_release_ack_T[20:6]; // @[DCache.scala:767:{88,107}] wire _block_probe_for_pending_release_ack_T_2 = _block_probe_for_pending_release_ack_T_1 == 15'h0; // @[DCache.scala:582:29, :767:{107,163}] wire block_probe_for_pending_release_ack = release_ack_wait & _block_probe_for_pending_release_ack_T_2; // @[DCache.scala:226:33, :767:{62,163}] wire _block_probe_for_ordering_T = releaseInFlight \| block_probe_for_pending_release_ack; // @[DCache.scala:334:46, :767:62, :768:50] wire block_probe_for_ordering = _block_probe_for_ordering_T \| grantInProgress; // @[DCache.scala:667:32, :768:{50,89}] wire _metaArb_io_in_6_valid_T = ~block_probe_for_core_progress; // @[DCache.scala:766:71, :769:48] wire _metaArb_io_in_6_valid_T_1 = _metaArb_io_in_6_valid_T \| lrscBackingOff; // @[DCache.scala:474:40, :769:{48,79}] wire _metaArb_io_in_6_valid_T_2 = nodeOut_b_valid & _metaArb_io_in_6_valid_T_1; // @[DCache.scala:769:{44,79}] wire _nodeOut_b_ready_T = block_probe_for_core_progress \| block_probe_for_ordering; // @[DCache.scala:766:71, :768:89, :770:79] wire _nodeOut_b_ready_T_1 = _nodeOut_b_ready_T \| s1_valid; // @[DCache.scala:182:25, :770:{79,107}] wire _nodeOut_b_ready_T_2 = _nodeOut_b_ready_T_1 \| s2_valid; // @[DCache.scala:331:25, :770:{107,119}] wire _nodeOut_b_ready_T_3 = ~_nodeOut_b_ready_T_2; // @[DCache.scala:770:{47,119}] assign _nodeOut_b_ready_T_4 = metaArb_io_in_6_ready & _nodeOut_b_ready_T_3; // @[DCache.scala:135:28, :770:{44,47}] assign nodeOut_b_ready = _nodeOut_b_ready_T_4; // @[DCache.scala:770:44] wire [5:0] _metaArb_io_in_6_bits_idx_T = nodeOut_b_bits_address[11:6]; // @[DCache.scala:1200:47] wire [7:0] _metaArb_io_in_6_bits_addr_T = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58] wire [7:0] _metaArb_io_in_6_bits_addr_T_2 = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58, :844:62] wire [39:0] _metaArb_io_in_6_bits_addr_T_1 = {_metaArb_io_in_6_bits_addr_T, nodeOut_b_bits_address}; // @[DCache.scala:773:{36,58}] assign _s1_victim_way_T = lfsr[2:0]; // @[PRNG.scala:95:17] assign s1_victim_way = _s1_victim_way_T; // @[package.scala:163:13] wire _T_134 = nodeOut_c_ready & nodeOut_c_valid; // @[Decoupled.scala:51:35] wire _releaseRejected_T; // @[Decoupled.scala:51:35] assign _releaseRejected_T = _T_134; // @[Decoupled.scala:51:35] wire _io_cpu_perf_release_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_release_T = _T_134; // @[Decoupled.scala:51:35] wire [26:0] _GEN_116 = 27'hFFF << nodeOut_c_bits_size; // @[package.scala:243:71] wire [26:0] _r_beats1_decode_T_3; // @[package.scala:243:71] assign _r_beats1_decode_T_3 = _GEN_116; // @[package.scala:243:71] wire [26:0] _io_cpu_perf_release_beats1_decode_T; // @[package.scala:243:71] assign _io_cpu_perf_release_beats1_decode_T = _GEN_116; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_4 = _r_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_5 = ~_r_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode_1 = _r_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire r_beats1_opdata_1 = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36] wire io_cpu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36] wire [7:0] r_beats1_1 = r_beats1_opdata_1 ? r_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] r_counter_1; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T_1 = {1'h0, r_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1_1 = _r_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first = r_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T_2 = r_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_3 = r_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_last = _r_last_T_2 \| _r_last_T_3; // @[Edges.scala:232:{25,33,43}] wire releaseDone = c_last & _T_134; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T_1 = ~r_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_count = r_beats1_1 & _r_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T_1 = c_first ? r_beats1_1 : r_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _releaseRejected_T_2; // @[DCache.scala:803:44] wire releaseRejected; // @[DCache.scala:800:29] wire _s1_release_data_valid_T = dataArb_io_in_2_ready & _dataArb_io_in_2_valid_T_1; // @[Decoupled.scala:51:35] reg s1_release_data_valid; // @[DCache.scala:801:38] wire _s2_release_data_valid_T = ~releaseRejected; // @[DCache.scala:800:29, :802:64] wire _s2_release_data_valid_T_1 = s1_release_data_valid & _s2_release_data_valid_T; // @[DCache.scala:801:38, :802:{61,64}] reg s2_release_data_valid; // @[DCache.scala:802:38] wire _nodeOut_c_valid_T_3 = s2_release_data_valid; // @[DCache.scala:802:38, :810:44] wire _releaseRejected_T_1 = ~_releaseRejected_T; // @[Decoupled.scala:51:35] assign _releaseRejected_T_2 = s2_release_data_valid & _releaseRejected_T_1; // @[DCache.scala:802:38, :803:{44,47}] assign releaseRejected = _releaseRejected_T_2; // @[DCache.scala:800:29, :803:44] wire [8:0] _releaseDataBeat_T = {1'h0, c_count}; // @[Edges.scala:234:25] wire [1:0] _releaseDataBeat_T_1 = {1'h0, s2_release_data_valid}; // @[DCache.scala:802:38, :804:98] wire [2:0] _releaseDataBeat_T_2 = {2'h0, s1_release_data_valid} + {1'h0, _releaseDataBeat_T_1}; // @[DCache.scala:801:38, :804:{93,98}] wire [1:0] _releaseDataBeat_T_3 = _releaseDataBeat_T_2[1:0]; // @[DCache.scala:804:93] wire [1:0] _releaseDataBeat_T_4 = releaseRejected ? 2'h0 : _releaseDataBeat_T_3; // @[DCache.scala:800:29, :804:{48,93}] wire [9:0] _releaseDataBeat_T_5 = {1'h0, _releaseDataBeat_T} + {8'h0, _releaseDataBeat_T_4}; // @[DCache.scala:804:{28,43,48}] wire [8:0] releaseDataBeat = _releaseDataBeat_T_5[8:0]; // @[DCache.scala:804:43] wire _nodeOut_c_valid_T_4 = c_first & release_ack_wait; // @[Edges.scala:231:25] wire _nodeOut_c_valid_T_5 = ~_nodeOut_c_valid_T_4; // @[DCache.scala:810:{120,130}] wire _nodeOut_c_valid_T_6 = _nodeOut_c_valid_T_3 & _nodeOut_c_valid_T_5; // @[DCache.scala:810:{44,117,120}] wire [1:0] newCoh_state; // @[DCache.scala:812:27] wire [1:0] metaArb_io_in_4_bits_data_meta_coh_state = newCoh_state; // @[HellaCache.scala:305:20] wire _release_state_T_8 = s2_valid_flush_line \| s2_flush_valid; // @[DCache.scala:363:51, :419:75, :817:34, :820:151] wire _discard_line_T = s2_req_size[1]; // @[DCache.scala:339:19, :818:60] wire _discard_line_T_1 = s2_valid_flush_line & _discard_line_T; // @[DCache.scala:419:75, :818:{46,60}] wire _discard_line_T_3 = s2_flush_valid & _discard_line_T_2; // @[DCache.scala:363:51, :818:{82,102}] wire discard_line = _discard_line_T_1 \| _discard_line_T_3; // @[DCache.scala:818:{46,64,82}] wire _release_state_T = ~discard_line; // @[DCache.scala:818:64, :819:47] wire _release_state_T_1 = s2_victim_dirty & _release_state_T; // @[Misc.scala:38:9] wire _release_state_T_3 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47, :820:57] wire _release_state_T_6 = \|s2_victim_state_state; // @[Metadata.scala:50:45] wire _release_state_T_9 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _release_state_T_10 = s2_readwrite & _release_state_T_9; // @[DCache.scala:354:30, :820:{185,188}] wire _release_state_T_11 = _release_state_T_8 \| _release_state_T_10; // @[DCache.scala:820:{151,169,185}] wire [3:0] _release_state_T_14 = _release_state_T_1 ? 4'h1 : 4'h6; // @[DCache.scala:819:{27,44}] wire [5:0] _probe_bits_T_1 = s2_req_addr[11:6]; // @[DCache.scala:339:19, :822:76] wire [25:0] _probe_bits_T_2 = {s2_victim_tag, _probe_bits_T_1}; // @[DCache.scala:433:26, :822:{49,76}] wire [31:0] _probe_bits_T_3 = {_probe_bits_T_2, 6'h0}; // @[DCache.scala:822:{49,96}] wire [31:0] probe_bits_res_address = _probe_bits_T_3; // @[DCache.scala:822:96, :1202:19] wire probeNack; // @[DCache.scala:825:34] wire [3:0] _release_state_T_15 = {1'h0, releaseDone, 2'h3}; // @[Edges.scala:233:22] wire _probeNack_T = ~releaseDone; // @[Edges.scala:233:22] assign probeNack = s2_prb_ack_data \| (\|s2_probe_state_state) \| _probeNack_T; // @[Misc.scala:38:9] wire [3:0] _release_state_T_16 = releaseDone ? 4'h0 : 4'h5; // @[Edges.scala:233:22] assign s1_nack = s2_probe ? probeNack \| _T_68 \| _T_48 \| _T_14 : _T_68 \| _T_48 \| _T_14; // @[DCache.scala:185:28, :276:{39,58,79}, :288:{75,85}, :333:25, :446:{24,82,92}, :571:{18,36,46}, :824:21, :825:34, :839:{24,34}] wire _T_110 = release_state == 4'h4; // @[DCache.scala:228:30, :841:25] assign metaArb_io_in_6_valid = _T_110 \| _metaArb_io_in_6_valid_T_2; // @[DCache.scala:135:28, :769:{26,44}, :841:{25,44}, :842:30] assign metaArb_io_in_6_bits_idx = _T_110 ? _metaArb_io_in_6_bits_idx_T_1 : _metaArb_io_in_6_bits_idx_T; // @[DCache.scala:135:28, :772:29, :841:{25,44}, :843:33, :1200:47] wire [39:0] _metaArb_io_in_6_bits_addr_T_3 = {_metaArb_io_in_6_bits_addr_T_2, probe_bits_address}; // @[DCache.scala:184:29, :844:{40,62}] assign metaArb_io_in_6_bits_addr = _T_110 ? _metaArb_io_in_6_bits_addr_T_3 : _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:135:28, :773:{30,36}, :841:{25,44}, :844:{34,40}] wire _T_111 = release_state == 4'h5; // @[DCache.scala:228:30, :850:25] wire _T_112 = release_state == 4'h3; // @[DCache.scala:228:30, :854:25] assign nodeOut_c_valid = _T_112 \| _T_111 \| s2_probe & ~s2_prb_ack_data \| _nodeOut_c_valid_T_6; // @[Misc.scala:38:9] wire _GEN_117 = _T_112 \| ~(~s2_probe \| s2_prb_ack_data \| ~(\|s2_probe_state_state)); // @[Misc.scala:38:9] wire _T_118 = _T_114 \| _T_115 \| _T_119; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_opcode = _T_118 ? {2'h3, ~_T_119} : {2'h2, _inWriteback_T_1}; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_param = _T_118 ? (_T_119 ? nodeOut_c_bits_c_param : nodeOut_c_bits_c_1_param) : _inWriteback_T_1 ? dirtyReleaseMessage_param : _GEN_117 ? cleanReleaseMessage_param : 3'h5; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_size = _T_118 ? 4'h6 : _inWriteback_T_1 ? dirtyReleaseMessage_size : _GEN_117 ? cleanReleaseMessage_size : nackResponseMessage_size; // @[package.scala:16:47, :81:59] assign newCoh_state = _T_118 ? voluntaryNewCoh_state : probeNewCoh_state; // @[package.scala:81:59] assign releaseWay = _T_118 ? s2_victim_or_hit_way : s2_probe_way; // @[package.scala:81:59] wire _dataArb_io_in_2_valid_T = releaseDataBeat < 9'h4; // @[DCache.scala:804:43, :900:60] assign _dataArb_io_in_2_valid_T_1 = inWriteback & _dataArb_io_in_2_valid_T; // @[package.scala:81:59] assign dataArb_io_in_2_valid = _dataArb_io_in_2_valid_T_1; // @[DCache.scala:152:28, :900:41] wire [11:0] _dataArb_io_in_2_bits_addr_T_1 = {_dataArb_io_in_2_bits_addr_T, 6'h0}; // @[DCache.scala:903:55, :1200:47] wire [1:0] _dataArb_io_in_2_bits_addr_T_2 = releaseDataBeat[1:0]; // @[DCache.scala:804:43, :903:90] wire [5:0] _dataArb_io_in_2_bits_addr_T_3 = {_dataArb_io_in_2_bits_addr_T_2, 4'h0}; // @[DCache.scala:903:{90,117}] assign _dataArb_io_in_2_bits_addr_T_4 = {_dataArb_io_in_2_bits_addr_T_1[11:6], _dataArb_io_in_2_bits_addr_T_1[5:0] \| _dataArb_io_in_2_bits_addr_T_3}; // @[DCache.scala:903:{55,72,117}] assign dataArb_io_in_2_bits_addr = _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:152:28, :903:72] wire _metaArb_io_in_4_valid_T_1 = release_state == 4'h7; // @[package.scala:16:47] assign _metaArb_io_in_4_valid_T_2 = _metaArb_io_in_4_valid_T \| _metaArb_io_in_4_valid_T_1; // @[package.scala:16:47, :81:59] assign metaArb_io_in_4_valid = _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59] assign metaArb_io_in_4_bits_idx = _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:135:28, :1200:47] wire [11:0] _metaArb_io_in_4_bits_addr_T_1 = probe_bits_address[11:0]; // @[DCache.scala:184:29, :912:90] assign _metaArb_io_in_4_bits_addr_T_2 = {_metaArb_io_in_4_bits_addr_T, _metaArb_io_in_4_bits_addr_T_1}; // @[DCache.scala:912:{36,58,90}] assign metaArb_io_in_4_bits_addr = _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:135:28, :912:36] wire [19:0] _metaArb_io_in_4_bits_data_T = nodeOut_c_bits_address[31:12]; // @[DCache.scala:913:78] wire [19:0] metaArb_io_in_4_bits_data_meta_tag = _metaArb_io_in_4_bits_data_T; // @[HellaCache.scala:305:20] assign _metaArb_io_in_4_bits_data_T_1 = {metaArb_io_in_4_bits_data_meta_coh_state, metaArb_io_in_4_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_4_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_5_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_6_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_7_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] wire _io_cpu_s2_uncached_T = ~s2_hit; // @[Misc.scala:35:9] assign _io_cpu_s2_uncached_T_1 = s2_uncached & _io_cpu_s2_uncached_T; // @[DCache.scala:424:39, :920:{37,40}] assign io_cpu_s2_uncached_0 = _io_cpu_s2_uncached_T_1; // @[DCache.scala:101:7, :920:37] wire _io_cpu_ordered_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35] wire _io_cpu_ordered_T_1 = s1_valid & _io_cpu_ordered_T; // @[DCache.scala:182:25, :929:{32,35}] wire _io_cpu_ordered_T_2 = ~s2_req_no_xcpt; // @[DCache.scala:339:19, :929:72] wire _io_cpu_ordered_T_3 = s2_valid & _io_cpu_ordered_T_2; // @[DCache.scala:331:25, :929:{69,72}] wire _io_cpu_ordered_T_4 = _io_cpu_ordered_T_1 \| _io_cpu_ordered_T_3; // @[DCache.scala:929:{32,57,69}] wire _io_cpu_ordered_T_5 = _io_cpu_ordered_T_4 \| cached_grant_wait; // @[DCache.scala:223:34, :929:{57,94}] wire _io_cpu_ordered_T_7 = _io_cpu_ordered_T_5 \| _io_cpu_ordered_T_6; // @[DCache.scala:929:{94,115,142}] assign _io_cpu_ordered_T_8 = ~_io_cpu_ordered_T_7; // @[DCache.scala:929:{21,115}] assign io_cpu_ordered_0 = _io_cpu_ordered_T_8; // @[DCache.scala:101:7, :929:21] wire _io_cpu_store_pending_T_2 = _io_cpu_store_pending_T \| _io_cpu_store_pending_T_1; // @[Consts.scala:90:{32,42,49}] wire _io_cpu_store_pending_T_4 = _io_cpu_store_pending_T_2 \| _io_cpu_store_pending_T_3; // @[Consts.scala:90:{42,59,66}] wire _io_cpu_store_pending_T_9 = _io_cpu_store_pending_T_5 \| _io_cpu_store_pending_T_6; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_10 = _io_cpu_store_pending_T_9 \| _io_cpu_store_pending_T_7; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_11 = _io_cpu_store_pending_T_10 \| _io_cpu_store_pending_T_8; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_17 = _io_cpu_store_pending_T_12 \| _io_cpu_store_pending_T_13; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_18 = _io_cpu_store_pending_T_17 \| _io_cpu_store_pending_T_14; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_19 = _io_cpu_store_pending_T_18 \| _io_cpu_store_pending_T_15; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_20 = _io_cpu_store_pending_T_19 \| _io_cpu_store_pending_T_16; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_21 = _io_cpu_store_pending_T_11 \| _io_cpu_store_pending_T_20; // @[package.scala:81:59] wire _io_cpu_store_pending_T_22 = _io_cpu_store_pending_T_4 \| _io_cpu_store_pending_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _io_cpu_store_pending_T_23 = cached_grant_wait & _io_cpu_store_pending_T_22; // @[DCache.scala:223:34, :930:46] assign _io_cpu_store_pending_T_25 = _io_cpu_store_pending_T_23 \| _io_cpu_store_pending_T_24; // @[DCache.scala:930:{46,70,97}] assign io_cpu_store_pending_0 = _io_cpu_store_pending_T_25; // @[DCache.scala:101:7, :930:70] wire _s1_xcpt_valid_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35, :932:43] wire _s1_xcpt_valid_T_1 = _tlb_io_req_valid_T_3 & _s1_xcpt_valid_T; // @[DCache.scala:273:40, :932:{40,43}] wire _s1_xcpt_valid_T_2 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :932:68] wire s1_xcpt_valid = _s1_xcpt_valid_T_1 & _s1_xcpt_valid_T_2; // @[DCache.scala:932:{40,65,68}] reg io_cpu_s2_xcpt_REG; // @[DCache.scala:933:32] wire _io_cpu_s2_xcpt_T_miss = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_miss; // @[DCache.scala:342:24, :933:{24,32}] wire [31:0] _io_cpu_s2_xcpt_T_paddr = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_paddr : 32'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [39:0] _io_cpu_s2_xcpt_T_gpa = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_gpa : 40'h0; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_pf_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_ae_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_cacheable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_must_alloc = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_prefetchable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24, :933:{24,32}] wire [1:0] _io_cpu_s2_xcpt_T_size = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_size : 2'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [4:0] _io_cpu_s2_xcpt_T_cmd = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_cmd : 5'h0; // @[DCache.scala:342:24, :933:{24,32}] assign io_cpu_s2_xcpt_pf_ld_0 = _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_pf_st_0 = _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_ld_0 = _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_st_0 = _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_ld_0 = _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_st_0 = _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:101:7, :933:24] wire _s1_uncached_data_word_T = s1_uncached_data_word_word_idx; // @[package.scala:39:86, :163:13] wire [63:0] s1_uncached_data_word_words_0 = nodeOut_d_bits_data[63:0]; // @[package.scala:211:50] wire [63:0] s1_uncached_data_word_words_1 = nodeOut_d_bits_data[127:64]; // @[package.scala:211:50] wire [63:0] s1_uncached_data_word = _s1_uncached_data_word_T ? s1_uncached_data_word_words_1 : s1_uncached_data_word_words_0; // @[package.scala:39:{76,86}, :211:50] reg [63:0] s2_uncached_data_word; // @[DCache.scala:947:40] reg doUncachedResp; // @[DCache.scala:948:31] assign io_cpu_resp_bits_replay_0 = doUncachedResp; // @[DCache.scala:101:7, :948:31] wire _io_cpu_resp_valid_T = s2_valid_hit_pre_data_ecc \| doUncachedResp; // @[DCache.scala:420:69, :948:31, :949:51] assign _io_cpu_resp_valid_T_2 = _io_cpu_resp_valid_T; // @[DCache.scala:949:{51,70}] assign io_cpu_resp_valid_0 = _io_cpu_resp_valid_T_2; // @[DCache.scala:101:7, :949:70] wire _io_cpu_replay_next_T_1 = _io_cpu_replay_next_T & grantIsUncachedData; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T_3 = _io_cpu_replay_next_T_1; // @[DCache.scala:950:{39,62}] assign io_cpu_replay_next_0 = _io_cpu_replay_next_T_3; // @[DCache.scala:101:7, :950:62]
Generate the Verilog code corresponding to the following Chisel files. File HellaCacheArbiter.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat,log2Up} import org.chipsalliance.cde.config.Parameters class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module { val io = IO(new Bundle { val requestor = Flipped(Vec(n, new HellaCacheIO)) val mem = new HellaCacheIO }) if (n == 1) { io.mem <> io.requestor.head } else { val s1_id = Reg(UInt()) val s2_id = RegNext(s1_id) io.mem.keep_clock_enabled := io.requestor.map(_.keep_clock_enabled).reduce(_\|\|_) io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_\|\|_) io.requestor(0).req.ready := io.mem.req.ready for (i <- 1 until n) io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid for (i <- n-1 to 0 by -1) { val req = io.requestor(i).req def connect_s0() = { io.mem.req.bits := req.bits io.mem.req.bits.tag := Cat(req.bits.tag, i.U(log2Up(n).W)) s1_id := i.U } def connect_s1() = { io.mem.s1_kill := io.requestor(i).s1_kill io.mem.s1_data := io.requestor(i).s1_data } def connect_s2() = { io.mem.s2_kill := io.requestor(i).s2_kill } if (i == n-1) { connect_s0() connect_s1() connect_s2() } else { when (req.valid) { connect_s0() } when (s1_id === i.U) { connect_s1() } when (s2_id === i.U) { connect_s2() } } } io.mem.uncached_resp.foreach(_.ready := false.B) for (i <- 0 until n) { val resp = io.requestor(i).resp val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === i.U resp.valid := io.mem.resp.valid && tag_hit io.requestor(i).s2_xcpt := io.mem.s2_xcpt io.requestor(i).s2_gpa := io.mem.s2_gpa io.requestor(i).s2_gpa_is_pte := io.mem.s2_gpa_is_pte io.requestor(i).ordered := io.mem.ordered io.requestor(i).store_pending := io.mem.store_pending io.requestor(i).perf := io.mem.perf io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === i.U io.requestor(i).s2_nack_cause_raw := io.mem.s2_nack_cause_raw io.requestor(i).s2_uncached := io.mem.s2_uncached io.requestor(i).s2_paddr := io.mem.s2_paddr io.requestor(i).clock_enabled := io.mem.clock_enabled resp.bits := io.mem.resp.bits resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n) io.requestor(i).replay_next := io.mem.replay_next io.requestor(i).uncached_resp.map { uncached_resp => val uncached_tag_hit = io.mem.uncached_resp.get.bits.tag(log2Up(n)-1,0) === i.U uncached_resp.valid := io.mem.uncached_resp.get.valid && uncached_tag_hit when (uncached_resp.ready && uncached_tag_hit) { io.mem.uncached_resp.get.ready := true.B } uncached_resp.bits := io.mem.uncached_resp.get.bits uncached_resp.bits.tag := io.mem.uncached_resp.get.bits.tag >> log2Up(n) } } } }	module HellaCacheArbiter( // @[HellaCacheArbiter.scala:10:7] input clock, // @[HellaCacheArbiter.scala:10:7] input reset, // @[HellaCacheArbiter.scala:10:7] output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_0_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_0_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_valid, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_1_s1_data_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_1_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_1_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_1_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_2_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_2_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_requestor_2_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_2_req_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_2_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_s1_kill, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_2_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_2_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_2_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_2_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_2_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_2_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_2_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_2_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_2_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_keep_clock_enabled, // @[HellaCacheArbiter.scala:12:14] input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_mem_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_phys, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_mem_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_uncached, // @[HellaCacheArbiter.scala:12:14] input [31:0] io_mem_s2_paddr, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_mem_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] input io_mem_replay_next, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_s2_gpa, // @[HellaCacheArbiter.scala:12:14] input io_mem_ordered, // @[HellaCacheArbiter.scala:12:14] input io_mem_store_pending, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_acquire, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_release, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_grant, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_blocked, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_mem_keep_clock_enabled // @[HellaCacheArbiter.scala:12:14] ); wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_s1_data_mask_0 = io_requestor_1_s1_data_mask; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_valid_0 = io_requestor_2_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_2_req_bits_addr_0 = io_requestor_2_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_req_bits_tag_0 = io_requestor_2_req_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_2_req_bits_cmd_0 = io_requestor_2_req_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_2_req_bits_size_0 = io_requestor_2_req_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_signed_0 = io_requestor_2_req_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_2_req_bits_dprv_0 = io_requestor_2_req_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_dv_0 = io_requestor_2_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_no_resp_0 = io_requestor_2_req_bits_no_resp; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s1_kill_0 = io_requestor_2_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_s1_data_data_0 = io_requestor_2_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_keep_clock_enabled_0 = io_requestor_2_keep_clock_enabled; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[HellaCacheArbiter.scala:10:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[HellaCacheArbiter.scala:10:7] wire io_mem_ordered_0 = io_mem_ordered; // @[HellaCacheArbiter.scala:10:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[HellaCacheArbiter.scala:10:7] wire [9:0] _io_mem_req_bits_tag_T_2 = 10'h0; // @[HellaCacheArbiter.scala:34:35] wire [1:0] io_requestor_0_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :51:21] wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [9:0] _io_mem_req_bits_tag_T_1 = 10'h1; // @[HellaCacheArbiter.scala:34:35] wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_size = 2'h0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_dprv = 2'h0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_req_bits_tag = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_req_bits_tag = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_req_bits_addr = 40'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire io_requestor_0_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_mem_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_dv = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s1_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_keep_clock_enabled_T = 1'h0; // @[HellaCacheArbiter.scala:23:81] wire io_mem_req_bits_phys_0 = io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64] wire _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_requestor_2_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64] wire _io_requestor_2_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_2_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_mem_keep_clock_enabled_T_1 = io_requestor_2_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7, :23:81] wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_req_valid_T_1; // @[HellaCacheArbiter.scala:25:63] wire io_requestor_0_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_0_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_1_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_2_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_2_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_2_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_2_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_2_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_2_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] reg [1:0] s1_id; // @[HellaCacheArbiter.scala:20:20] reg [1:0] s2_id; // @[HellaCacheArbiter.scala:21:24] assign io_mem_keep_clock_enabled_0 = _io_mem_keep_clock_enabled_T_1; // @[HellaCacheArbiter.scala:10:7, :23:81] wire _io_mem_req_valid_T = io_requestor_0_req_valid_0 \| io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63] assign _io_mem_req_valid_T_1 = _io_mem_req_valid_T \| io_requestor_2_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63] assign io_mem_req_valid_0 = _io_mem_req_valid_T_1; // @[HellaCacheArbiter.scala:10:7, :25:63] wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}] assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64] wire _io_requestor_2_req_ready_T = ~io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] assign _io_requestor_2_req_ready_T_1 = io_requestor_1_req_ready_0 & _io_requestor_2_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}] assign io_requestor_2_req_ready_0 = _io_requestor_2_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64] wire [9:0] _io_mem_req_bits_tag_T = {io_requestor_2_req_bits_tag_0, 2'h2}; // @[HellaCacheArbiter.scala:10:7, :34:35] wire _T = s1_id == 2'h1; // @[HellaCacheArbiter.scala:20:20, :51:21] wire _io_requestor_1_s2_nack_T = s2_id == 2'h1; // @[HellaCacheArbiter.scala:21:24, :51:21, :52:21, :68:58] assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_valid_0 ? 40'h0 : io_requestor_2_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] assign io_mem_req_bits_cmd_0 = io_requestor_0_req_valid_0 \| io_requestor_1_req_valid_0 ? 5'h0 : io_requestor_2_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_size_0 = io_requestor_0_req_valid_0 ? 2'h3 : io_requestor_1_req_valid_0 ? 2'h0 : io_requestor_2_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] assign io_mem_req_bits_signed_0 = ~io_requestor_0_req_valid_0 & ~io_requestor_1_req_valid_0 & io_requestor_2_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_dprv_0 = io_requestor_0_req_valid_0 ? 2'h1 : io_requestor_1_req_valid_0 ? 2'h0 : io_requestor_2_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26, :51:21] assign io_mem_req_bits_dv_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_dv_0 : ~io_requestor_1_req_valid_0 & io_requestor_2_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_no_resp_0 = ~io_requestor_0_req_valid_0 & ~io_requestor_1_req_valid_0 & io_requestor_2_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? 8'h0 : io_requestor_1_req_valid_0 ? 8'h1 : _io_mem_req_bits_tag_T[7:0]; // @[HellaCacheArbiter.scala:10:7, :34:{29,35}, :50:26] wire _T_2 = s1_id == 2'h0; // @[HellaCacheArbiter.scala:20:20, :51:21] assign io_mem_s1_kill_0 = _T_2 ? io_requestor_0_s1_kill_0 : ~_T & io_requestor_2_s1_kill_0; // @[HellaCacheArbiter.scala:10:7, :38:24, :51:{21,30}] assign io_mem_s1_data_data_0 = _T_2 ? 64'h0 : _T ? io_requestor_1_s1_data_data_0 : io_requestor_2_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7, :39:24, :51:{21,30}] assign io_mem_s1_data_mask_0 = _T_2 \| ~_T ? 8'h0 : io_requestor_1_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7, :38:24, :39:24, :51:{21,30}] wire _io_requestor_0_s2_nack_T = s2_id == 2'h0; // @[HellaCacheArbiter.scala:21:24, :52:21, :68:58] wire [1:0] _tag_hit_T = io_mem_resp_bits_tag_0[1:0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire [1:0] _tag_hit_T_1 = io_mem_resp_bits_tag_0[1:0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire [1:0] _tag_hit_T_2 = io_mem_resp_bits_tag_0[1:0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire tag_hit = _tag_hit_T == 2'h0; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] wire [5:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:2]; // @[HellaCacheArbiter.scala:10:7, :74:45] wire [5:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:2]; // @[HellaCacheArbiter.scala:10:7, :74:45] wire [5:0] _io_requestor_2_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:2]; // @[HellaCacheArbiter.scala:10:7, :74:45] assign io_requestor_0_resp_bits_tag_0 = {2'h0, _io_requestor_0_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] wire tag_hit_1 = _tag_hit_T_1 == 2'h1; // @[HellaCacheArbiter.scala:51:21, :60:{41,57}] assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] assign io_requestor_1_resp_bits_tag_0 = {2'h0, _io_requestor_1_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] wire tag_hit_2 = _tag_hit_T_2 == 2'h2; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_2_resp_valid_T = io_mem_resp_valid_0 & tag_hit_2; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_2_resp_valid_0 = _io_requestor_2_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] wire _io_requestor_2_s2_nack_T = s2_id == 2'h2; // @[HellaCacheArbiter.scala:21:24, :68:58] assign _io_requestor_2_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_2_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_2_s2_nack_0 = _io_requestor_2_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] assign io_requestor_2_resp_bits_tag_0 = {2'h0, _io_requestor_2_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] always @(posedge clock) begin // @[HellaCacheArbiter.scala:10:7] s1_id <= io_requestor_0_req_valid_0 ? 2'h0 : io_requestor_1_req_valid_0 ? 2'h1 : 2'h2; // @[HellaCacheArbiter.scala:10:7, :20:20, :35:15, :50:26, :51:21] s2_id <= s1_id; // @[HellaCacheArbiter.scala:20:20, :21:24] always @(posedge) assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack_cause_raw = io_requestor_0_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_uncached = io_requestor_0_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_paddr = io_requestor_0_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_cmd = io_requestor_0_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_signed = io_requestor_0_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_mask = io_requestor_0_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_replay = io_requestor_0_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_store_data = io_requestor_0_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_replay_next = io_requestor_0_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_gpa = io_requestor_0_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_release = io_requestor_0_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_tlbMiss = io_requestor_0_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_blocked = io_requestor_0_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenLoad = io_requestor_0_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenRMW = io_requestor_0_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptLoadThenLoad = io_requestor_0_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterLoad = io_requestor_0_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterStore = io_requestor_0_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack_cause_raw = io_requestor_1_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_uncached = io_requestor_1_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_paddr = io_requestor_1_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_addr = io_requestor_1_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_cmd = io_requestor_1_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_signed = io_requestor_1_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dprv = io_requestor_1_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dv = io_requestor_1_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_mask = io_requestor_1_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_replay = io_requestor_1_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_word_bypass = io_requestor_1_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_raw = io_requestor_1_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_store_data = io_requestor_1_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_replay_next = io_requestor_1_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_ld = io_requestor_1_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_st = io_requestor_1_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_ld = io_requestor_1_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_st = io_requestor_1_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_ld = io_requestor_1_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_st = io_requestor_1_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_gpa = io_requestor_1_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_release = io_requestor_1_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_tlbMiss = io_requestor_1_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_blocked = io_requestor_1_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenLoad = io_requestor_1_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenRMW = io_requestor_1_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptLoadThenLoad = io_requestor_1_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterLoad = io_requestor_1_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterStore = io_requestor_1_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_req_ready = io_requestor_2_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_nack = io_requestor_2_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_nack_cause_raw = io_requestor_2_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_uncached = io_requestor_2_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_paddr = io_requestor_2_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_valid = io_requestor_2_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_addr = io_requestor_2_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_tag = io_requestor_2_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_cmd = io_requestor_2_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_size = io_requestor_2_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_signed = io_requestor_2_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_dprv = io_requestor_2_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_dv = io_requestor_2_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_data = io_requestor_2_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_mask = io_requestor_2_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_replay = io_requestor_2_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_has_data = io_requestor_2_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_data_word_bypass = io_requestor_2_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_data_raw = io_requestor_2_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_store_data = io_requestor_2_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_replay_next = io_requestor_2_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ma_ld = io_requestor_2_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ma_st = io_requestor_2_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_pf_ld = io_requestor_2_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_pf_st = io_requestor_2_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ae_ld = io_requestor_2_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ae_st = io_requestor_2_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_gpa = io_requestor_2_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_ordered = io_requestor_2_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_store_pending = io_requestor_2_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_acquire = io_requestor_2_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_release = io_requestor_2_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_grant = io_requestor_2_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_tlbMiss = io_requestor_2_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_blocked = io_requestor_2_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_canAcceptStoreThenLoad = io_requestor_2_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_canAcceptStoreThenRMW = io_requestor_2_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_canAcceptLoadThenLoad = io_requestor_2_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_storeBufferEmptyAfterLoad = io_requestor_2_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_storeBufferEmptyAfterStore = io_requestor_2_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_cmd = io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_size = io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_signed = io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dprv = io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_phys = io_mem_req_bits_phys_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_no_resp = io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_mask = io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_keep_clock_enabled = io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }

module rockettile_icache_tag_array_0( // @[DescribedSRAM.scala:17:26] input [5:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [167:0] RW0_wdata, output [167:0] RW0_rdata, input [7:0] RW0_wmask ); rockettile_icache_tag_array_ext rockettile_icache_tag_array_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[DescribedSRAM.scala:17:26] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_309( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready || !io.in.bits.head || at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready || !io.in.bits.head || at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) && (vcalloc_q.io.enq.ready || !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }

module IngressUnit_51( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_10, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_11, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_12, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_13, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_14, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_15, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_16, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_17, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_18, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_19, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_20, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_10, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_11, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_14, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_15, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_18, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_19, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_20, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_21, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [5:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_10; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_11; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_12; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_13; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_14; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_15; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_16; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_17; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_18; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_19; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_20; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_21; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 6'h28; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 6'h2B; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 6'h2E; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 6'h31; // @[IngressUnit.scala:30:72] wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid || io.clear || io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 || rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_||_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_||_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_||_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready || agen_ready || dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }

module IssueSlot_53( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File dcache.scala: //****************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc, Transpose} class BoomWritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new WritebackReq(edge.bundle))) val meta_read = Decoupled(new L1MetaReadReq) val resp = Output(Bool()) val idx = Output(Valid(UInt())) val data_req = Decoupled(new L1DataReadReq) val data_resp = Input(UInt(encRowBits.W)) val mem_grant = Input(Bool()) val release = Decoupled(new TLBundleC(edge.bundle)) val lsu_release = Decoupled(new TLBundleC(edge.bundle)) }) val req = Reg(new WritebackReq(edge.bundle)) val s_invalid :: s_fill_buffer :: s_lsu_release :: s_active :: s_grant :: Nil = Enum(5) val state = RegInit(s_invalid) val r1_data_req_fired = RegInit(false.B) val r2_data_req_fired = RegInit(false.B) val r1_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W)) val r2_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W)) val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W)) val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release) val wb_buffer = Reg(Vec(refillCycles, UInt(encRowBits.W))) val acked = RegInit(false.B) io.idx.valid := state =/= s_invalid io.idx.bits := req.idx io.release.valid := false.B io.release.bits := DontCare io.req.ready := false.B io.meta_read.valid := false.B io.meta_read.bits := DontCare io.data_req.valid := false.B io.data_req.bits := DontCare io.resp := false.B io.lsu_release.valid := false.B io.lsu_release.bits := DontCare val r_address = Cat(req.tag, req.idx) << blockOffBits val id = cfg.nMSHRs val probeResponse = edge.ProbeAck( fromSource = id.U, toAddress = r_address, lgSize = lgCacheBlockBytes.U, reportPermissions = req.param, data = wb_buffer(data_req_cnt)) val voluntaryRelease = edge.Release( fromSource = id.U, toAddress = r_address, lgSize = lgCacheBlockBytes.U, shrinkPermissions = req.param, data = wb_buffer(data_req_cnt))._2 when (state === s_invalid) { io.req.ready := true.B when (io.req.fire) { state := s_fill_buffer data_req_cnt := 0.U req := io.req.bits acked := false.B } } .elsewhen (state === s_fill_buffer) { io.meta_read.valid := data_req_cnt < refillCycles.U io.meta_read.bits.idx := req.idx io.meta_read.bits.tag := req.tag io.data_req.valid := data_req_cnt < refillCycles.U io.data_req.bits.way_en := req.way_en io.data_req.bits.addr := (if(refillCycles > 1) Cat(req.idx, data_req_cnt(log2Up(refillCycles)-1,0)) else req.idx) << rowOffBits r1_data_req_fired := false.B r1_data_req_cnt := 0.U r2_data_req_fired := r1_data_req_fired r2_data_req_cnt := r1_data_req_cnt when (io.data_req.fire && io.meta_read.fire) { r1_data_req_fired := true.B r1_data_req_cnt := data_req_cnt data_req_cnt := data_req_cnt + 1.U } when (r2_data_req_fired) { wb_buffer(r2_data_req_cnt) := io.data_resp when (r2_data_req_cnt === (refillCycles-1).U) { io.resp := true.B state := s_lsu_release data_req_cnt := 0.U } } } .elsewhen (state === s_lsu_release) { io.lsu_release.valid := true.B io.lsu_release.bits := probeResponse when (io.lsu_release.fire) { state := s_active } } .elsewhen (state === s_active) { io.release.valid := data_req_cnt < refillCycles.U io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse) when (io.mem_grant) { acked := true.B } when (io.release.fire) { data_req_cnt := data_req_cnt + 1.U } when ((data_req_cnt === (refillCycles-1).U) && io.release.fire) { state := Mux(req.voluntary, s_grant, s_invalid) } } .elsewhen (state === s_grant) { when (io.mem_grant) { acked := true.B } when (acked) { state := s_invalid } } } class BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new TLBundleB(edge.bundle))) val rep = Decoupled(new TLBundleC(edge.bundle)) val meta_read = Decoupled(new L1MetaReadReq) val meta_write = Decoupled(new L1MetaWriteReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val way_en = Input(UInt(nWays.W)) val wb_rdy = Input(Bool()) // Is writeback unit currently busy? If so need to retry meta read when its done val mshr_rdy = Input(Bool()) // Is MSHR ready for this request to proceed? val mshr_wb_rdy = Output(Bool()) // Should we block MSHR writebacks while we finish our own? val block_state = Input(new ClientMetadata()) val lsu_release = Decoupled(new TLBundleC(edge.bundle)) val state = Output(Valid(UInt(coreMaxAddrBits.W))) }) val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_mshr_resp :: s_lsu_release :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: s_meta_write_resp :: Nil) = Enum(11) val state = RegInit(s_invalid) val req = Reg(new TLBundleB(edge.bundle)) val req_idx = req.address(idxMSB, idxLSB) val req_tag = req.address >> untagBits val way_en = Reg(UInt()) val tag_matches = way_en.orR val old_coh = Reg(new ClientMetadata) val miss_coh = ClientMetadata.onReset val reply_coh = Mux(tag_matches, old_coh, miss_coh) val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param) io.state.valid := state =/= s_invalid io.state.bits := req.address io.req.ready := state === s_invalid io.rep.valid := state === s_release io.rep.bits := edge.ProbeAck(req, report_param) assert(!io.rep.valid || !edge.hasData(io.rep.bits), "ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it") io.meta_read.valid := state === s_meta_read io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := ~(0.U(nWays.W)) io.meta_write.valid := state === s_meta_write io.meta_write.bits.way_en := way_en io.meta_write.bits.idx := req_idx io.meta_write.bits.tag := req_tag io.meta_write.bits.data.tag := req_tag io.meta_write.bits.data.coh := new_coh io.wb_req.valid := state === s_writeback_req io.wb_req.bits.source := req.source io.wb_req.bits.idx := req_idx io.wb_req.bits.tag := req_tag io.wb_req.bits.param := report_param io.wb_req.bits.way_en := way_en io.wb_req.bits.voluntary := false.B io.mshr_wb_rdy := !state.isOneOf(s_release, s_writeback_req, s_writeback_resp, s_meta_write, s_meta_write_resp) io.lsu_release.valid := state === s_lsu_release io.lsu_release.bits := edge.ProbeAck(req, report_param) // state === s_invalid when (state === s_invalid) { when (io.req.fire) { state := s_meta_read req := io.req.bits } } .elsewhen (state === s_meta_read) { when (io.meta_read.fire) { state := s_meta_resp } } .elsewhen (state === s_meta_resp) { // we need to wait one cycle for the metadata to be read from the array state := s_mshr_req } .elsewhen (state === s_mshr_req) { old_coh := io.block_state way_en := io.way_en // if the read didn't go through, we need to retry state := Mux(io.mshr_rdy && io.wb_rdy, s_mshr_resp, s_meta_read) } .elsewhen (state === s_mshr_resp) { state := Mux(tag_matches && is_dirty, s_writeback_req, s_lsu_release) } .elsewhen (state === s_lsu_release) { when (io.lsu_release.fire) { state := s_release } } .elsewhen (state === s_release) { when (io.rep.ready) { state := Mux(tag_matches, s_meta_write, s_invalid) } } .elsewhen (state === s_writeback_req) { when (io.wb_req.fire) { state := s_writeback_resp } } .elsewhen (state === s_writeback_resp) { // wait for the writeback request to finish before updating the metadata when (io.wb_req.ready) { state := s_meta_write } } .elsewhen (state === s_meta_write) { when (io.meta_write.fire) { state := s_meta_write_resp } } .elsewhen (state === s_meta_write_resp) { state := s_invalid } } class BoomL1MetaReadReq(implicit p: Parameters) extends BoomBundle()(p) { val req = Vec(memWidth, new L1MetaReadReq) } class BoomL1DataReadReq(implicit p: Parameters) extends BoomBundle()(p) { val req = Vec(memWidth, new L1DataReadReq) val valid = Vec(memWidth, Bool()) } abstract class AbstractBoomDataArray(implicit p: Parameters) extends BoomModule with HasL1HellaCacheParameters { val io = IO(new BoomBundle { val read = Input(Vec(memWidth, Valid(new L1DataReadReq))) val write = Input(Valid(new L1DataWriteReq)) val resp = Output(Vec(memWidth, Vec(nWays, Bits(encRowBits.W)))) val nacks = Output(Vec(memWidth, Bool())) }) def pipeMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) } class BoomDuplicatedDataArray(implicit p: Parameters) extends AbstractBoomDataArray { val waddr = io.write.bits.addr >> rowOffBits for (j <- 0 until memWidth) { val raddr = io.read(j).bits.addr >> rowOffBits for (w <- 0 until nWays) { val array = DescribedSRAM( name = s"array_${w}_${j}", desc = "Non-blocking DCache Data Array", size = nSets * refillCycles, data = Vec(rowWords, Bits(encDataBits.W)) ) when (io.write.bits.way_en(w) && io.write.valid) { val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))) array.write(waddr, data, io.write.bits.wmask.asBools) } io.resp(j)(w) := RegNext(array.read(raddr, io.read(j).bits.way_en(w) && io.read(j).valid).asUInt) } io.nacks(j) := false.B } } class BoomBankedDataArray(implicit p: Parameters) extends AbstractBoomDataArray { val nBanks = boomParams.numDCacheBanks val bankSize = nSets * refillCycles / nBanks require (nBanks >= memWidth) require (bankSize > 0) val bankBits = log2Ceil(nBanks) val bankOffBits = log2Ceil(rowWords) + log2Ceil(wordBytes) val bidxBits = log2Ceil(bankSize) val bidxOffBits = bankOffBits + bankBits //---------------------------------------------------------------------------------------------------- val s0_rbanks = if (nBanks > 1) VecInit(io.read.map(r => (r.bits.addr >> bankOffBits)(bankBits-1,0))) else VecInit(0.U) val s0_wbank = if (nBanks > 1) (io.write.bits.addr >> bankOffBits)(bankBits-1,0) else 0.U val s0_ridxs = VecInit(io.read.map(r => (r.bits.addr >> bidxOffBits)(bidxBits-1,0))) val s0_widx = (io.write.bits.addr >> bidxOffBits)(bidxBits-1,0) val s0_read_valids = VecInit(io.read.map(_.valid)) val s0_bank_conflicts = pipeMap(w => (0 until w).foldLeft(false.B)((c,i) => c || io.read(i).valid && s0_rbanks(i) === s0_rbanks(w))) val s0_do_bank_read = s0_read_valids zip s0_bank_conflicts map {case (v,c) => v && !c} val s0_bank_read_gnts = Transpose(VecInit(s0_rbanks zip s0_do_bank_read map {case (b,d) => VecInit((UIntToOH(b) & Fill(nBanks,d)).asBools)})) val s0_bank_write_gnt = (UIntToOH(s0_wbank) & Fill(nBanks, io.write.valid)).asBools //---------------------------------------------------------------------------------------------------- val s1_rbanks = RegNext(s0_rbanks) val s1_ridxs = RegNext(s0_ridxs) val s1_read_valids = RegNext(s0_read_valids) val s1_pipe_selection = pipeMap(i => VecInit(PriorityEncoderOH(pipeMap(j => if (j < i) s1_read_valids(j) && s1_rbanks(j) === s1_rbanks(i) else if (j == i) true.B else false.B)))) val s1_ridx_match = pipeMap(i => pipeMap(j => if (j < i) s1_ridxs(j) === s1_ridxs(i) else if (j == i) true.B else false.B)) val s1_nacks = pipeMap(w => s1_read_valids(w) && (s1_pipe_selection(w).asUInt & ~s1_ridx_match(w).asUInt).orR) val s1_bank_selection = pipeMap(w => Mux1H(s1_pipe_selection(w), s1_rbanks)) //---------------------------------------------------------------------------------------------------- val s2_bank_selection = RegNext(s1_bank_selection) val s2_nacks = RegNext(s1_nacks) for (w <- 0 until nWays) { val s2_bank_reads = Reg(Vec(nBanks, Bits(encRowBits.W))) for (b <- 0 until nBanks) { val array = DescribedSRAM( name = s"array_${w}_${b}", desc = "Non-blocking DCache Data Array", size = bankSize, data = Vec(rowWords, Bits(encDataBits.W)) ) val ridx = Mux1H(s0_bank_read_gnts(b), s0_ridxs) val way_en = Mux1H(s0_bank_read_gnts(b), io.read.map(_.bits.way_en)) s2_bank_reads(b) := array.read(ridx, way_en(w) && s0_bank_read_gnts(b).reduce(_||_)).asUInt when (io.write.bits.way_en(w) && s0_bank_write_gnt(b)) { val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))) array.write(s0_widx, data, io.write.bits.wmask.asBools) } } for (i <- 0 until memWidth) { io.resp(i)(w) := s2_bank_reads(s2_bank_selection(i)) } } io.nacks := s2_nacks } /** * Top level class wrapping a non-blocking dcache. * * @param hartid hardware thread for the cache */ class BoomNonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule { private val tileParams = p(TileKey) protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${staticIdForMetadataUseOnly} DCache", sourceId = IdRange(0, 1 max (cfg.nMSHRs + 1)), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${staticIdForMetadataUseOnly} DCache MMIO", sourceId = IdRange(cfg.nMSHRs + 1, cfg.nMSHRs + 1 + cfg.nMMIOs), requestFifo = true)) val node = TLClientNode(Seq(TLMasterPortParameters.v1( cacheClientParameters ++ mmioClientParameters, minLatency = 1))) lazy val module = new BoomNonBlockingDCacheModule(this) def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class BoomDCacheBundle(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { val lsu = Flipped(new LSUDMemIO) } class BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters with HasBoomCoreParameters { implicit val edge = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new BoomDCacheBundle) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees ${m.nodePath.map(_.name)}") } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val t_replay :: t_probe :: t_wb :: t_mshr_meta_read :: t_lsu :: t_prefetch :: Nil = Enum(6) val wb = Module(new BoomWritebackUnit) val prober = Module(new BoomProbeUnit) val mshrs = Module(new BoomMSHRFile) mshrs.io.clear_all := io.lsu.force_order mshrs.io.brupdate := io.lsu.brupdate mshrs.io.exception := io.lsu.exception mshrs.io.rob_pnr_idx := io.lsu.rob_pnr_idx mshrs.io.rob_head_idx := io.lsu.rob_head_idx // tags def onReset = L1Metadata(0.U, ClientMetadata.onReset) val meta = Seq.fill(memWidth) { Module(new L1MetadataArray(onReset _)) } val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2)) // 0 goes to MSHR refills, 1 goes to prober val metaReadArb = Module(new Arbiter(new BoomL1MetaReadReq, 6)) // 0 goes to MSHR replays, 1 goes to prober, 2 goes to wb, 3 goes to MSHR meta read, // 4 goes to pipeline, 5 goes to prefetcher metaReadArb.io.in := DontCare for (w <- 0 until memWidth) { meta(w).io.write.valid := metaWriteArb.io.out.fire meta(w).io.write.bits := metaWriteArb.io.out.bits meta(w).io.read.valid := metaReadArb.io.out.valid meta(w).io.read.bits := metaReadArb.io.out.bits.req(w) } metaReadArb.io.out.ready := meta.map(_.io.read.ready).reduce(_||_) metaWriteArb.io.out.ready := meta.map(_.io.write.ready).reduce(_||_) // data val data = Module(if (boomParams.numDCacheBanks == 1) new BoomDuplicatedDataArray else new BoomBankedDataArray) val dataWriteArb = Module(new Arbiter(new L1DataWriteReq, 2)) // 0 goes to pipeline, 1 goes to MSHR refills val dataReadArb = Module(new Arbiter(new BoomL1DataReadReq, 3)) // 0 goes to MSHR replays, 1 goes to wb, 2 goes to pipeline dataReadArb.io.in := DontCare for (w <- 0 until memWidth) { data.io.read(w).valid := dataReadArb.io.out.bits.valid(w) && dataReadArb.io.out.valid data.io.read(w).bits := dataReadArb.io.out.bits.req(w) } dataReadArb.io.out.ready := true.B data.io.write.valid := dataWriteArb.io.out.fire data.io.write.bits := dataWriteArb.io.out.bits dataWriteArb.io.out.ready := true.B // ------------ // New requests io.lsu.req.ready := metaReadArb.io.in(4).ready && dataReadArb.io.in(2).ready metaReadArb.io.in(4).valid := io.lsu.req.valid dataReadArb.io.in(2).valid := io.lsu.req.valid for (w <- 0 until memWidth) { // Tag read for new requests metaReadArb.io.in(4).bits.req(w).idx := io.lsu.req.bits(w).bits.addr >> blockOffBits metaReadArb.io.in(4).bits.req(w).way_en := DontCare metaReadArb.io.in(4).bits.req(w).tag := DontCare // Data read for new requests dataReadArb.io.in(2).bits.valid(w) := io.lsu.req.bits(w).valid dataReadArb.io.in(2).bits.req(w).addr := io.lsu.req.bits(w).bits.addr dataReadArb.io.in(2).bits.req(w).way_en := ~0.U(nWays.W) } // ------------ // MSHR Replays val replay_req = Wire(Vec(memWidth, new BoomDCacheReq)) replay_req := DontCare replay_req(0).uop := mshrs.io.replay.bits.uop replay_req(0).addr := mshrs.io.replay.bits.addr replay_req(0).data := mshrs.io.replay.bits.data replay_req(0).is_hella := mshrs.io.replay.bits.is_hella mshrs.io.replay.ready := metaReadArb.io.in(0).ready && dataReadArb.io.in(0).ready // Tag read for MSHR replays // We don't actually need to read the metadata, for replays we already know our way metaReadArb.io.in(0).valid := mshrs.io.replay.valid metaReadArb.io.in(0).bits.req(0).idx := mshrs.io.replay.bits.addr >> blockOffBits metaReadArb.io.in(0).bits.req(0).way_en := DontCare metaReadArb.io.in(0).bits.req(0).tag := DontCare // Data read for MSHR replays dataReadArb.io.in(0).valid := mshrs.io.replay.valid dataReadArb.io.in(0).bits.req(0).addr := mshrs.io.replay.bits.addr dataReadArb.io.in(0).bits.req(0).way_en := mshrs.io.replay.bits.way_en dataReadArb.io.in(0).bits.valid := widthMap(w => (w == 0).B) // ----------- // MSHR Meta read val mshr_read_req = Wire(Vec(memWidth, new BoomDCacheReq)) mshr_read_req := DontCare mshr_read_req(0).uop := NullMicroOp mshr_read_req(0).addr := Cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx) << blockOffBits mshr_read_req(0).data := DontCare mshr_read_req(0).is_hella := false.B metaReadArb.io.in(3).valid := mshrs.io.meta_read.valid metaReadArb.io.in(3).bits.req(0) := mshrs.io.meta_read.bits mshrs.io.meta_read.ready := metaReadArb.io.in(3).ready // ----------- // Write-backs val wb_fire = wb.io.meta_read.fire && wb.io.data_req.fire val wb_req = Wire(Vec(memWidth, new BoomDCacheReq)) wb_req := DontCare wb_req(0).uop := NullMicroOp wb_req(0).addr := Cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr) wb_req(0).data := DontCare wb_req(0).is_hella := false.B // Couple the two decoupled interfaces of the WBUnit's meta_read and data_read // Tag read for write-back metaReadArb.io.in(2).valid := wb.io.meta_read.valid metaReadArb.io.in(2).bits.req(0) := wb.io.meta_read.bits wb.io.meta_read.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready // Data read for write-back dataReadArb.io.in(1).valid := wb.io.data_req.valid dataReadArb.io.in(1).bits.req(0) := wb.io.data_req.bits dataReadArb.io.in(1).bits.valid := widthMap(w => (w == 0).B) wb.io.data_req.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire)) // ------- // Prober val prober_fire = prober.io.meta_read.fire val prober_req = Wire(Vec(memWidth, new BoomDCacheReq)) prober_req := DontCare prober_req(0).uop := NullMicroOp prober_req(0).addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << blockOffBits prober_req(0).data := DontCare prober_req(0).is_hella := false.B // Tag read for prober metaReadArb.io.in(1).valid := prober.io.meta_read.valid metaReadArb.io.in(1).bits.req(0) := prober.io.meta_read.bits prober.io.meta_read.ready := metaReadArb.io.in(1).ready // Prober does not need to read data array // ------- // Prefetcher val prefetch_fire = mshrs.io.prefetch.fire val prefetch_req = Wire(Vec(memWidth, new BoomDCacheReq)) prefetch_req := DontCare prefetch_req(0) := mshrs.io.prefetch.bits // Tag read for prefetch metaReadArb.io.in(5).valid := mshrs.io.prefetch.valid metaReadArb.io.in(5).bits.req(0).idx := mshrs.io.prefetch.bits.addr >> blockOffBits metaReadArb.io.in(5).bits.req(0).way_en := DontCare metaReadArb.io.in(5).bits.req(0).tag := DontCare mshrs.io.prefetch.ready := metaReadArb.io.in(5).ready // Prefetch does not need to read data array val s0_valid = Mux(io.lsu.req.fire, VecInit(io.lsu.req.bits.map(_.valid)), Mux(mshrs.io.replay.fire || wb_fire || prober_fire || prefetch_fire || mshrs.io.meta_read.fire, VecInit(1.U(memWidth.W).asBools), VecInit(0.U(memWidth.W).asBools))) val s0_req = Mux(io.lsu.req.fire , VecInit(io.lsu.req.bits.map(_.bits)), Mux(wb_fire , wb_req, Mux(prober_fire , prober_req, Mux(prefetch_fire , prefetch_req, Mux(mshrs.io.meta_read.fire, mshr_read_req , replay_req))))) val s0_type = Mux(io.lsu.req.fire , t_lsu, Mux(wb_fire , t_wb, Mux(prober_fire , t_probe, Mux(prefetch_fire , t_prefetch, Mux(mshrs.io.meta_read.fire, t_mshr_meta_read , t_replay))))) // Does this request need to send a response or nack val s0_send_resp_or_nack = Mux(io.lsu.req.fire, s0_valid, VecInit(Mux(mshrs.io.replay.fire && isRead(mshrs.io.replay.bits.uop.mem_cmd), 1.U(memWidth.W), 0.U(memWidth.W)).asBools)) val s1_req = RegNext(s0_req) for (w <- 0 until memWidth) s1_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s0_req(w).uop) val s2_store_failed = Wire(Bool()) val s1_valid = widthMap(w => RegNext(s0_valid(w) && !IsKilledByBranch(io.lsu.brupdate, s0_req(w).uop) && !(io.lsu.exception && s0_req(w).uop.uses_ldq) && !(s2_store_failed && io.lsu.req.fire && s0_req(w).uop.uses_stq), init=false.B)) for (w <- 0 until memWidth) assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid))) val s1_addr = s1_req.map(_.addr) val s1_nack = s1_addr.map(a => a(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready) val s1_send_resp_or_nack = RegNext(s0_send_resp_or_nack) val s1_type = RegNext(s0_type) val s1_mshr_meta_read_way_en = RegNext(mshrs.io.meta_read.bits.way_en) val s1_replay_way_en = RegNext(mshrs.io.replay.bits.way_en) // For replays, the metadata isn't written yet val s1_wb_way_en = RegNext(wb.io.data_req.bits.way_en) // tag check def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f)) val s1_tag_eq_way = widthMap(i => wayMap((w: Int) => meta(i).io.resp(w).tag === (s1_addr(i) >> untagBits)).asUInt) val s1_tag_match_way = widthMap(i => Mux(s1_type === t_replay, s1_replay_way_en, Mux(s1_type === t_wb, s1_wb_way_en, Mux(s1_type === t_mshr_meta_read, s1_mshr_meta_read_way_en, wayMap((w: Int) => s1_tag_eq_way(i)(w) && meta(i).io.resp(w).coh.isValid()).asUInt)))) val s1_wb_idx_matches = widthMap(i => (s1_addr(i)(untagBits-1,blockOffBits) === wb.io.idx.bits) && wb.io.idx.valid) val s2_req = RegNext(s1_req) val s2_type = RegNext(s1_type) val s2_valid = widthMap(w => RegNext(s1_valid(w) && !io.lsu.s1_kill(w) && !IsKilledByBranch(io.lsu.brupdate, s1_req(w).uop) && !(io.lsu.exception && s1_req(w).uop.uses_ldq) && !(s2_store_failed && (s1_type === t_lsu) && s1_req(w).uop.uses_stq))) for (w <- 0 until memWidth) s2_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s1_req(w).uop) val s2_tag_match_way = RegNext(s1_tag_match_way) val s2_tag_match = s2_tag_match_way.map(_.orR) val s2_hit_state = widthMap(i => Mux1H(s2_tag_match_way(i), wayMap((w: Int) => RegNext(meta(i).io.resp(w).coh)))) val s2_has_permission = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._1) val s2_new_hit_state = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._3) val s2_hit = widthMap(w => (s2_tag_match(w) && s2_has_permission(w) && s2_hit_state(w) === s2_new_hit_state(w) && !mshrs.io.block_hit(w)) || s2_type.isOneOf(t_replay, t_wb)) val s2_nack = Wire(Vec(memWidth, Bool())) assert(!(s2_type === t_replay && !s2_hit(0)), "Replays should always hit") assert(!(s2_type === t_wb && !s2_hit(0)), "Writeback should always see data hit") val s2_wb_idx_matches = RegNext(s1_wb_idx_matches) // lr/sc val debug_sc_fail_addr = RegInit(0.U) val debug_sc_fail_cnt = RegInit(0.U(8.W)) val lrsc_count = RegInit(0.U(log2Ceil(lrscCycles).W)) val lrsc_valid = lrsc_count > lrscBackoff.U val lrsc_addr = Reg(UInt()) val s2_lr = s2_req(0).uop.mem_cmd === M_XLR && (!RegNext(s1_nack(0)) || s2_type === t_replay) val s2_sc = s2_req(0).uop.mem_cmd === M_XSC && (!RegNext(s1_nack(0)) || s2_type === t_replay) val s2_lrsc_addr_match = widthMap(w => lrsc_valid && lrsc_addr === (s2_req(w).addr >> blockOffBits)) val s2_sc_fail = s2_sc && !s2_lrsc_addr_match(0) when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U } when (s2_valid(0) && ((s2_type === t_lsu && s2_hit(0) && !s2_nack(0)) || (s2_type === t_replay && s2_req(0).uop.mem_cmd =/= M_FLUSH_ALL))) { when (s2_lr) { lrsc_count := (lrscCycles - 1).U lrsc_addr := s2_req(0).addr >> blockOffBits } when (lrsc_count > 0.U) { lrsc_count := 0.U } } for (w <- 0 until memWidth) { when (s2_valid(w) && s2_type === t_lsu && !s2_hit(w) && !(s2_has_permission(w) && s2_tag_match(w)) && s2_lrsc_addr_match(w) && !s2_nack(w)) { lrsc_count := 0.U } } when (s2_valid(0)) { when (s2_req(0).addr === debug_sc_fail_addr) { when (s2_sc_fail) { debug_sc_fail_cnt := debug_sc_fail_cnt + 1.U } .elsewhen (s2_sc) { debug_sc_fail_cnt := 0.U } } .otherwise { when (s2_sc_fail) { debug_sc_fail_addr := s2_req(0).addr debug_sc_fail_cnt := 1.U } } } assert(debug_sc_fail_cnt < 100.U, "L1DCache failed too many SCs in a row") val s2_data = Wire(Vec(memWidth, Vec(nWays, UInt(encRowBits.W)))) for (i <- 0 until memWidth) { for (w <- 0 until nWays) { s2_data(i)(w) := data.io.resp(i)(w) } } val s2_data_muxed = widthMap(w => Mux1H(s2_tag_match_way(w), s2_data(w))) val s2_word_idx = widthMap(w => if (rowWords == 1) 0.U else s2_req(w).addr(log2Up(rowWords*wordBytes)-1, log2Up(wordBytes))) // replacement policy val replacer = cacheParams.replacement val s1_replaced_way_en = UIntToOH(replacer.way) val s2_replaced_way_en = UIntToOH(RegNext(replacer.way)) val s2_repl_meta = widthMap(i => Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegNext(meta(i).io.resp(w))).toSeq)) // nack because of incoming probe val s2_nack_hit = RegNext(VecInit(s1_nack)) // Nack when we hit something currently being evicted val s2_nack_victim = widthMap(w => s2_valid(w) && s2_hit(w) && mshrs.io.secondary_miss(w)) // MSHRs not ready for request val s2_nack_miss = widthMap(w => s2_valid(w) && !s2_hit(w) && !mshrs.io.req(w).ready) // Bank conflict on data arrays val s2_nack_data = widthMap(w => data.io.nacks(w)) // Can't allocate MSHR for same set currently being written back val s2_nack_wb = widthMap(w => s2_valid(w) && !s2_hit(w) && s2_wb_idx_matches(w)) s2_nack := widthMap(w => (s2_nack_miss(w) || s2_nack_hit(w) || s2_nack_victim(w) || s2_nack_data(w) || s2_nack_wb(w)) && s2_type =/= t_replay) val s2_send_resp = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && !s2_nack(w) && (s2_hit(w) || (mshrs.io.req(w).fire && isWrite(s2_req(w).uop.mem_cmd) && !isRead(s2_req(w).uop.mem_cmd))))) val s2_send_nack = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && s2_nack(w))) for (w <- 0 until memWidth) assert(!(s2_send_resp(w) && s2_send_nack(w))) // hits always send a response // If MSHR is not available, LSU has to replay this request later // If MSHR is available and this is only a store(not a amo), we don't need to wait for resp later s2_store_failed := s2_valid(0) && s2_nack(0) && s2_send_nack(0) && s2_req(0).uop.uses_stq // Miss handling for (w <- 0 until memWidth) { mshrs.io.req(w).valid := s2_valid(w) && !s2_hit(w) && !s2_nack_hit(w) && !s2_nack_victim(w) && !s2_nack_data(w) && !s2_nack_wb(w) && s2_type.isOneOf(t_lsu, t_prefetch) && !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) && !(io.lsu.exception && s2_req(w).uop.uses_ldq) && (isPrefetch(s2_req(w).uop.mem_cmd) || isRead(s2_req(w).uop.mem_cmd) || isWrite(s2_req(w).uop.mem_cmd)) assert(!(mshrs.io.req(w).valid && s2_type === t_replay), "Replays should not need to go back into MSHRs") mshrs.io.req(w).bits := DontCare mshrs.io.req(w).bits.uop := s2_req(w).uop mshrs.io.req(w).bits.uop.br_mask := GetNewBrMask(io.lsu.brupdate, s2_req(w).uop) mshrs.io.req(w).bits.addr := s2_req(w).addr mshrs.io.req(w).bits.tag_match := s2_tag_match(w) mshrs.io.req(w).bits.old_meta := Mux(s2_tag_match(w), L1Metadata(s2_repl_meta(w).tag, s2_hit_state(w)), s2_repl_meta(w)) mshrs.io.req(w).bits.way_en := Mux(s2_tag_match(w), s2_tag_match_way(w), s2_replaced_way_en) mshrs.io.req(w).bits.data := s2_req(w).data mshrs.io.req(w).bits.is_hella := s2_req(w).is_hella mshrs.io.req_is_probe(w) := s2_type === t_probe && s2_valid(w) } mshrs.io.meta_resp.valid := !s2_nack_hit(0) || prober.io.mshr_wb_rdy mshrs.io.meta_resp.bits := Mux1H(s2_tag_match_way(0), RegNext(meta(0).io.resp)) when (mshrs.io.req.map(_.fire).reduce(_||_)) { replacer.miss } tl_out.a <> mshrs.io.mem_acquire // probes and releases prober.io.req.valid := tl_out.b.valid && !lrsc_valid tl_out.b.ready := prober.io.req.ready && !lrsc_valid prober.io.req.bits := tl_out.b.bits prober.io.way_en := s2_tag_match_way(0) prober.io.block_state := s2_hit_state(0) metaWriteArb.io.in(1) <> prober.io.meta_write prober.io.mshr_rdy := mshrs.io.probe_rdy prober.io.wb_rdy := (prober.io.meta_write.bits.idx =/= wb.io.idx.bits) || !wb.io.idx.valid mshrs.io.prober_state := prober.io.state // refills when (tl_out.d.bits.source === cfg.nMSHRs.U) { // This should be ReleaseAck tl_out.d.ready := true.B mshrs.io.mem_grant.valid := false.B mshrs.io.mem_grant.bits := DontCare } .otherwise { // This should be GrantData mshrs.io.mem_grant <> tl_out.d } dataWriteArb.io.in(1) <> mshrs.io.refill metaWriteArb.io.in(0) <> mshrs.io.meta_write tl_out.e <> mshrs.io.mem_finish // writebacks val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle), 2)) // 0 goes to prober, 1 goes to MSHR evictions wbArb.io.in(0) <> prober.io.wb_req wbArb.io.in(1) <> mshrs.io.wb_req wb.io.req <> wbArb.io.out wb.io.data_resp := s2_data_muxed(0) mshrs.io.wb_resp := wb.io.resp wb.io.mem_grant := tl_out.d.fire && tl_out.d.bits.source === cfg.nMSHRs.U val lsu_release_arb = Module(new Arbiter(new TLBundleC(edge.bundle), 2)) io.lsu.release <> lsu_release_arb.io.out lsu_release_arb.io.in(0) <> wb.io.lsu_release lsu_release_arb.io.in(1) <> prober.io.lsu_release TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep) io.lsu.perf.release := edge.done(tl_out.c) io.lsu.perf.acquire := edge.done(tl_out.a) // load data gen val s2_data_word_prebypass = widthMap(w => s2_data_muxed(w) >> Cat(s2_word_idx(w), 0.U(log2Ceil(coreDataBits).W))) val s2_data_word = Wire(Vec(memWidth, UInt())) val loadgen = (0 until memWidth).map { w => new LoadGen(s2_req(w).uop.mem_size, s2_req(w).uop.mem_signed, s2_req(w).addr, s2_data_word(w), s2_sc && (w == 0).B, wordBytes) } // Mux between cache responses and uncache responses val cache_resp = Wire(Vec(memWidth, Valid(new BoomDCacheResp))) for (w <- 0 until memWidth) { cache_resp(w).valid := s2_valid(w) && s2_send_resp(w) cache_resp(w).bits.uop := s2_req(w).uop cache_resp(w).bits.data := loadgen(w).data | s2_sc_fail cache_resp(w).bits.is_hella := s2_req(w).is_hella } val uncache_resp = Wire(Valid(new BoomDCacheResp)) uncache_resp.bits := mshrs.io.resp.bits uncache_resp.valid := mshrs.io.resp.valid mshrs.io.resp.ready := !(cache_resp.map(_.valid).reduce(_&&_)) // We can backpressure the MSHRs, but not cache hits val resp = WireInit(cache_resp) var uncache_responding = false.B for (w <- 0 until memWidth) { val uncache_respond = !cache_resp(w).valid && !uncache_responding when (uncache_respond) { resp(w) := uncache_resp } uncache_responding = uncache_responding || uncache_respond } for (w <- 0 until memWidth) { io.lsu.resp(w).valid := resp(w).valid && !(io.lsu.exception && resp(w).bits.uop.uses_ldq) && !IsKilledByBranch(io.lsu.brupdate, resp(w).bits.uop) io.lsu.resp(w).bits := UpdateBrMask(io.lsu.brupdate, resp(w).bits) io.lsu.nack(w).valid := s2_valid(w) && s2_send_nack(w) && !(io.lsu.exception && s2_req(w).uop.uses_ldq) && !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) io.lsu.nack(w).bits := UpdateBrMask(io.lsu.brupdate, s2_req(w)) assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu)) } // Store/amo hits val s3_req = RegNext(s2_req(0)) val s3_valid = RegNext(s2_valid(0) && s2_hit(0) && isWrite(s2_req(0).uop.mem_cmd) && !s2_sc_fail && !(s2_send_nack(0) && s2_nack(0))) for (w <- 1 until memWidth) { assert(!(s2_valid(w) && s2_hit(w) && isWrite(s2_req(w).uop.mem_cmd) && !s2_sc_fail && !(s2_send_nack(w) && s2_nack(w))), "Store must go through 0th pipe in L1D") } // For bypassing val s4_req = RegNext(s3_req) val s4_valid = RegNext(s3_valid) val s5_req = RegNext(s4_req) val s5_valid = RegNext(s4_valid) val s3_bypass = widthMap(w => s3_valid && ((s2_req(w).addr >> wordOffBits) === (s3_req.addr >> wordOffBits))) val s4_bypass = widthMap(w => s4_valid && ((s2_req(w).addr >> wordOffBits) === (s4_req.addr >> wordOffBits))) val s5_bypass = widthMap(w => s5_valid && ((s2_req(w).addr >> wordOffBits) === (s5_req.addr >> wordOffBits))) // Store -> Load bypassing for (w <- 0 until memWidth) { s2_data_word(w) := Mux(s3_bypass(w), s3_req.data, Mux(s4_bypass(w), s4_req.data, Mux(s5_bypass(w), s5_req.data, s2_data_word_prebypass(w)))) } val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := new StoreGen(s2_req(0).uop.mem_size, s2_req(0).addr, 0.U, xLen/8).mask amoalu.io.cmd := s2_req(0).uop.mem_cmd amoalu.io.lhs := s2_data_word(0) amoalu.io.rhs := s2_req(0).data s3_req.data := amoalu.io.out val s3_way = RegNext(s2_tag_match_way(0)) dataWriteArb.io.in(0).valid := s3_valid dataWriteArb.io.in(0).bits.addr := s3_req.addr dataWriteArb.io.in(0).bits.wmask := UIntToOH(s3_req.addr.extract(rowOffBits-1,offsetlsb)) dataWriteArb.io.in(0).bits.data := Fill(rowWords, s3_req.data) dataWriteArb.io.in(0).bits.way_en := s3_way io.lsu.ordered := mshrs.io.fence_rdy && !s1_valid.reduce(_||_) && !s2_valid.reduce(_||_) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module BoomWritebackUnit( // @[dcache.scala:24:7] input clock, // @[dcache.scala:24:7] input reset, // @[dcache.scala:24:7] output io_req_ready, // @[dcache.scala:25:14] input io_req_valid, // @[dcache.scala:25:14] input [19:0] io_req_bits_tag, // @[dcache.scala:25:14] input [5:0] io_req_bits_idx, // @[dcache.scala:25:14] input [1:0] io_req_bits_source, // @[dcache.scala:25:14] input [2:0] io_req_bits_param, // @[dcache.scala:25:14] input [3:0] io_req_bits_way_en, // @[dcache.scala:25:14] input io_req_bits_voluntary, // @[dcache.scala:25:14] input io_meta_read_ready, // @[dcache.scala:25:14] output io_meta_read_valid, // @[dcache.scala:25:14] output [5:0] io_meta_read_bits_idx, // @[dcache.scala:25:14] output [19:0] io_meta_read_bits_tag, // @[dcache.scala:25:14] output io_resp, // @[dcache.scala:25:14] output io_idx_valid, // @[dcache.scala:25:14] output [5:0] io_idx_bits, // @[dcache.scala:25:14] input io_data_req_ready, // @[dcache.scala:25:14] output io_data_req_valid, // @[dcache.scala:25:14] output [3:0] io_data_req_bits_way_en, // @[dcache.scala:25:14] output [11:0] io_data_req_bits_addr, // @[dcache.scala:25:14] input [63:0] io_data_resp, // @[dcache.scala:25:14] input io_mem_grant, // @[dcache.scala:25:14] input io_release_ready, // @[dcache.scala:25:14] output io_release_valid, // @[dcache.scala:25:14] output [2:0] io_release_bits_opcode, // @[dcache.scala:25:14] output [2:0] io_release_bits_param, // @[dcache.scala:25:14] output [31:0] io_release_bits_address, // @[dcache.scala:25:14] output [63:0] io_release_bits_data, // @[dcache.scala:25:14] input io_lsu_release_ready, // @[dcache.scala:25:14] output io_lsu_release_valid, // @[dcache.scala:25:14] output [2:0] io_lsu_release_bits_param, // @[dcache.scala:25:14] output [31:0] io_lsu_release_bits_address, // @[dcache.scala:25:14] output [63:0] io_lsu_release_bits_data // @[dcache.scala:25:14] ); reg [2:0] state; // @[dcache.scala:39:22] wire io_req_valid_0 = io_req_valid; // @[dcache.scala:24:7] wire [19:0] io_req_bits_tag_0 = io_req_bits_tag; // @[dcache.scala:24:7] wire [5:0] io_req_bits_idx_0 = io_req_bits_idx; // @[dcache.scala:24:7] wire [1:0] io_req_bits_source_0 = io_req_bits_source; // @[dcache.scala:24:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[dcache.scala:24:7] wire [3:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[dcache.scala:24:7] wire io_req_bits_voluntary_0 = io_req_bits_voluntary; // @[dcache.scala:24:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[dcache.scala:24:7] wire io_data_req_ready_0 = io_data_req_ready; // @[dcache.scala:24:7] wire [63:0] io_data_resp_0 = io_data_resp; // @[dcache.scala:24:7] wire io_mem_grant_0 = io_mem_grant; // @[dcache.scala:24:7] wire io_release_ready_0 = io_release_ready; // @[dcache.scala:24:7] wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:24:7] wire [26:0] _r_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _r_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [8:0] r_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire _voluntaryRelease_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _voluntaryRelease_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire [2:0] voluntaryRelease_opcode = 3'h7; // @[Edges.scala:396:17] wire [2:0] io_lsu_release_bits_opcode = 3'h5; // @[dcache.scala:24:7] wire [2:0] probeResponse_opcode = 3'h5; // @[Edges.scala:433:17] wire io_release_bits_corrupt = 1'h0; // @[dcache.scala:24:7] wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:24:7] wire probeResponse_corrupt = 1'h0; // @[Edges.scala:433:17] wire _voluntaryRelease_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _voluntaryRelease_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _voluntaryRelease_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire voluntaryRelease_corrupt = 1'h0; // @[Edges.scala:396:17] wire _io_release_bits_T_corrupt = 1'h0; // @[dcache.scala:124:27] wire [1:0] io_release_bits_source = 2'h2; // @[dcache.scala:24:7] wire [1:0] io_lsu_release_bits_source = 2'h2; // @[dcache.scala:24:7] wire [1:0] probeResponse_source = 2'h2; // @[Edges.scala:433:17] wire [1:0] voluntaryRelease_source = 2'h2; // @[Edges.scala:396:17] wire [1:0] _io_release_bits_T_source = 2'h2; // @[dcache.scala:124:27] wire [3:0] io_release_bits_size = 4'h6; // @[dcache.scala:24:7] wire [3:0] io_lsu_release_bits_size = 4'h6; // @[dcache.scala:24:7] wire [3:0] probeResponse_size = 4'h6; // @[Edges.scala:433:17] wire [3:0] voluntaryRelease_size = 4'h6; // @[Edges.scala:396:17] wire [3:0] _io_release_bits_T_size = 4'h6; // @[dcache.scala:124:27] wire [3:0] io_meta_read_bits_way_en = 4'h0; // @[dcache.scala:24:7] wire io_req_ready_0 = ~(|state); // @[dcache.scala:24:7, :39:22, :49:31, :80:15] wire _io_idx_valid_T; // @[dcache.scala:49:31] wire [11:0] _io_data_req_bits_addr_T_2; // @[dcache.scala:97:43] wire [2:0] _io_release_bits_T_opcode; // @[dcache.scala:124:27] wire [2:0] _io_release_bits_T_param; // @[dcache.scala:124:27] wire [31:0] _io_release_bits_T_address; // @[dcache.scala:124:27] wire [63:0] _io_release_bits_T_data; // @[dcache.scala:124:27] wire [2:0] probeResponse_param; // @[Edges.scala:433:17] wire [31:0] probeResponse_address; // @[Edges.scala:433:17] wire [63:0] probeResponse_data; // @[Edges.scala:433:17] wire [5:0] io_meta_read_bits_idx_0; // @[dcache.scala:24:7] wire [19:0] io_meta_read_bits_tag_0; // @[dcache.scala:24:7] wire io_meta_read_valid_0; // @[dcache.scala:24:7] wire io_idx_valid_0; // @[dcache.scala:24:7] wire [5:0] io_idx_bits_0; // @[dcache.scala:24:7] wire [3:0] io_data_req_bits_way_en_0; // @[dcache.scala:24:7] wire [11:0] io_data_req_bits_addr_0; // @[dcache.scala:24:7] wire io_data_req_valid_0; // @[dcache.scala:24:7] wire [2:0] io_release_bits_opcode_0; // @[dcache.scala:24:7] wire [2:0] io_release_bits_param_0; // @[dcache.scala:24:7] wire [31:0] io_release_bits_address_0; // @[dcache.scala:24:7] wire [63:0] io_release_bits_data_0; // @[dcache.scala:24:7] wire io_release_valid_0; // @[dcache.scala:24:7] wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:24:7] wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:24:7] wire [63:0] io_lsu_release_bits_data_0; // @[dcache.scala:24:7] wire io_lsu_release_valid_0; // @[dcache.scala:24:7] wire io_resp_0; // @[dcache.scala:24:7] reg [19:0] req_tag; // @[dcache.scala:37:16] assign io_meta_read_bits_tag_0 = req_tag; // @[dcache.scala:24:7, :37:16] reg [5:0] req_idx; // @[dcache.scala:37:16] assign io_meta_read_bits_idx_0 = req_idx; // @[dcache.scala:24:7, :37:16] assign io_idx_bits_0 = req_idx; // @[dcache.scala:24:7, :37:16] reg [1:0] req_source; // @[dcache.scala:37:16] reg [2:0] req_param; // @[dcache.scala:37:16] assign probeResponse_param = req_param; // @[Edges.scala:433:17] wire [2:0] voluntaryRelease_param = req_param; // @[Edges.scala:396:17] reg [3:0] req_way_en; // @[dcache.scala:37:16] assign io_data_req_bits_way_en_0 = req_way_en; // @[dcache.scala:24:7, :37:16] reg req_voluntary; // @[dcache.scala:37:16] reg r1_data_req_fired; // @[dcache.scala:40:34] reg r2_data_req_fired; // @[dcache.scala:41:34] reg [3:0] r1_data_req_cnt; // @[dcache.scala:42:28] reg [3:0] r2_data_req_cnt; // @[dcache.scala:43:28] reg [3:0] data_req_cnt; // @[dcache.scala:44:29] wire _T_14 = io_release_ready_0 & io_release_valid_0; // @[Decoupled.scala:51:35] wire r_beats1_opdata = io_release_bits_opcode_0[0]; // @[Edges.scala:102:36] wire [8:0] r_beats1 = r_beats1_opdata ? 9'h7 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire last_beat = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire all_beats_done = last_beat & _T_14; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] beat_count = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [63:0] wb_buffer_0; // @[dcache.scala:46:22] reg [63:0] wb_buffer_1; // @[dcache.scala:46:22] reg [63:0] wb_buffer_2; // @[dcache.scala:46:22] reg [63:0] wb_buffer_3; // @[dcache.scala:46:22] reg [63:0] wb_buffer_4; // @[dcache.scala:46:22] reg [63:0] wb_buffer_5; // @[dcache.scala:46:22] reg [63:0] wb_buffer_6; // @[dcache.scala:46:22] reg [63:0] wb_buffer_7; // @[dcache.scala:46:22] reg acked; // @[dcache.scala:47:22] assign _io_idx_valid_T = |state; // @[dcache.scala:39:22, :49:31] assign io_idx_valid_0 = _io_idx_valid_T; // @[dcache.scala:24:7, :49:31] wire [25:0] _r_address_T = {req_tag, req_idx}; // @[dcache.scala:37:16, :63:22] wire [31:0] r_address = {_r_address_T, 6'h0}; // @[dcache.scala:63:{22,41}] assign probeResponse_address = r_address; // @[Edges.scala:433:17] wire [31:0] _voluntaryRelease_legal_T_1 = r_address; // @[Parameters.scala:137:31] wire [31:0] voluntaryRelease_address = r_address; // @[Edges.scala:396:17] wire [2:0] _probeResponse_T = data_req_cnt[2:0]; // @[dcache.scala:44:29] wire [2:0] _voluntaryRelease_T = data_req_cnt[2:0]; // @[dcache.scala:44:29] wire [2:0] _io_data_req_bits_addr_T = data_req_cnt[2:0]; // @[dcache.scala:44:29, :96:56] assign io_lsu_release_bits_param_0 = probeResponse_param; // @[Edges.scala:433:17] assign io_lsu_release_bits_address_0 = probeResponse_address; // @[Edges.scala:433:17] assign io_lsu_release_bits_data_0 = probeResponse_data; // @[Edges.scala:433:17] wire [7:0][63:0] _GEN = {{wb_buffer_7}, {wb_buffer_6}, {wb_buffer_5}, {wb_buffer_4}, {wb_buffer_3}, {wb_buffer_2}, {wb_buffer_1}, {wb_buffer_0}}; // @[Edges.scala:441:15] assign probeResponse_data = _GEN[_probeResponse_T]; // @[Edges.scala:433:17, :441:15] wire [32:0] _voluntaryRelease_legal_T_2 = {1'h0, _voluntaryRelease_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_3 = _voluntaryRelease_legal_T_2 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_4 = _voluntaryRelease_legal_T_3; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_5 = _voluntaryRelease_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _voluntaryRelease_legal_T_6 = {r_address[31:17], r_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] _voluntaryRelease_legal_T_7 = {1'h0, _voluntaryRelease_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_8 = _voluntaryRelease_legal_T_7 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_9 = _voluntaryRelease_legal_T_8; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_10 = _voluntaryRelease_legal_T_9 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _voluntaryRelease_legal_T_11 = {r_address[31:28], r_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] _voluntaryRelease_legal_T_12 = {1'h0, _voluntaryRelease_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_13 = _voluntaryRelease_legal_T_12 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_14 = _voluntaryRelease_legal_T_13; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_15 = _voluntaryRelease_legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _voluntaryRelease_legal_T_16 = _voluntaryRelease_legal_T_5 | _voluntaryRelease_legal_T_10; // @[Parameters.scala:685:42] wire _voluntaryRelease_legal_T_17 = _voluntaryRelease_legal_T_16 | _voluntaryRelease_legal_T_15; // @[Parameters.scala:685:42] wire [31:0] _voluntaryRelease_legal_T_21 = {r_address[31:28], r_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] _voluntaryRelease_legal_T_22 = {1'h0, _voluntaryRelease_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_23 = _voluntaryRelease_legal_T_22 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_24 = _voluntaryRelease_legal_T_23; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_25 = _voluntaryRelease_legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _voluntaryRelease_legal_T_26 = r_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _voluntaryRelease_legal_T_27 = {1'h0, _voluntaryRelease_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [32:0] _voluntaryRelease_legal_T_28 = _voluntaryRelease_legal_T_27 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _voluntaryRelease_legal_T_29 = _voluntaryRelease_legal_T_28; // @[Parameters.scala:137:46] wire _voluntaryRelease_legal_T_30 = _voluntaryRelease_legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _voluntaryRelease_legal_T_31 = _voluntaryRelease_legal_T_25 | _voluntaryRelease_legal_T_30; // @[Parameters.scala:685:42] wire _voluntaryRelease_legal_T_32 = _voluntaryRelease_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire voluntaryRelease_legal = _voluntaryRelease_legal_T_32; // @[Parameters.scala:684:54, :686:26] wire [63:0] voluntaryRelease_data; // @[Edges.scala:396:17] assign voluntaryRelease_data = _GEN[_voluntaryRelease_T]; // @[Edges.scala:396:17, :404:15, :441:15] wire _T_3 = state == 3'h1; // @[dcache.scala:39:22, :88:22] wire _io_meta_read_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40] assign io_meta_read_valid_0 = (|state) & _T_3 & _io_meta_read_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :54:22, :80:30, :88:{22,41}, :89:{24,40}] wire _io_data_req_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40, :93:39] assign io_data_req_valid_0 = (|state) & _T_3 & _io_data_req_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :56:22, :80:30, :88:{22,41}, :93:{23,39}] wire [8:0] _io_data_req_bits_addr_T_1 = {req_idx, _io_data_req_bits_addr_T}; // @[dcache.scala:37:16, :96:{34,56}] assign _io_data_req_bits_addr_T_2 = {_io_data_req_bits_addr_T_1, 3'h0}; // @[dcache.scala:96:34, :97:43] assign io_data_req_bits_addr_0 = _io_data_req_bits_addr_T_2; // @[dcache.scala:24:7, :97:43] wire [4:0] _GEN_0 = {1'h0, data_req_cnt} + 5'h1; // @[dcache.scala:44:29, :106:36] wire [4:0] _data_req_cnt_T; // @[dcache.scala:106:36] assign _data_req_cnt_T = _GEN_0; // @[dcache.scala:106:36] wire [4:0] _data_req_cnt_T_2; // @[dcache.scala:130:36] assign _data_req_cnt_T_2 = _GEN_0; // @[dcache.scala:106:36, :130:36] wire [3:0] _data_req_cnt_T_1 = _data_req_cnt_T[3:0]; // @[dcache.scala:106:36] wire _T_8 = r2_data_req_cnt == 4'h7; // @[dcache.scala:43:28, :110:29] assign io_resp_0 = (|state) & _T_3 & r2_data_req_fired & _T_8; // @[dcache.scala:24:7, :39:22, :41:34, :49:31, :58:22, :80:30, :88:{22,41}, :108:30, :110:{29,53}] wire _T_9 = state == 3'h2; // @[dcache.scala:39:22, :116:22] assign io_lsu_release_valid_0 = ~(~(|state) | _T_3) & _T_9; // @[dcache.scala:24:7, :39:22, :49:31, :59:24, :80:{15,30}, :88:{22,41}, :116:{22,41}] wire _T_11 = state == 3'h3; // @[dcache.scala:39:22, :122:22] wire _io_release_valid_T = ~(data_req_cnt[3]); // @[dcache.scala:44:29, :89:40, :123:38] wire _GEN_1 = _T_3 | _T_9; // @[dcache.scala:51:22, :88:{22,41}, :116:{22,41}, :122:36] assign io_release_valid_0 = ~(~(|state) | _GEN_1) & _T_11 & _io_release_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :51:22, :80:{15,30}, :88:41, :116:41, :122:{22,36}, :123:{22,38}] assign _io_release_bits_T_opcode = {1'h1, req_voluntary, 1'h1}; // @[dcache.scala:37:16, :124:27] assign _io_release_bits_T_param = req_voluntary ? voluntaryRelease_param : probeResponse_param; // @[Edges.scala:396:17, :433:17] assign _io_release_bits_T_address = req_voluntary ? voluntaryRelease_address : probeResponse_address; // @[Edges.scala:396:17, :433:17] assign _io_release_bits_T_data = req_voluntary ? voluntaryRelease_data : probeResponse_data; // @[Edges.scala:396:17, :433:17] assign io_release_bits_opcode_0 = _io_release_bits_T_opcode; // @[dcache.scala:24:7, :124:27] assign io_release_bits_param_0 = _io_release_bits_T_param; // @[dcache.scala:24:7, :124:27] assign io_release_bits_address_0 = _io_release_bits_T_address; // @[dcache.scala:24:7, :124:27] assign io_release_bits_data_0 = _io_release_bits_T_data; // @[dcache.scala:24:7, :124:27] wire [3:0] _data_req_cnt_T_3 = _data_req_cnt_T_2[3:0]; // @[dcache.scala:130:36] wire [2:0] _state_T = {req_voluntary, 2'h0}; // @[dcache.scala:37:16, :133:19] wire _T_16 = state == 3'h4; // @[dcache.scala:39:22, :135:22] wire _T_2 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_2 = (|state) & _T_3; // @[dcache.scala:39:22, :41:34, :49:31, :80:30, :88:{22,41}] wire _T_6 = io_data_req_ready_0 & io_data_req_valid_0 & io_meta_read_ready_0 & io_meta_read_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[dcache.scala:24:7] if (~(|state) & _T_2) begin // @[Decoupled.scala:51:35] req_tag <= io_req_bits_tag_0; // @[dcache.scala:24:7, :37:16] req_idx <= io_req_bits_idx_0; // @[dcache.scala:24:7, :37:16] req_source <= io_req_bits_source_0; // @[dcache.scala:24:7, :37:16] req_param <= io_req_bits_param_0; // @[dcache.scala:24:7, :37:16] req_way_en <= io_req_bits_way_en_0; // @[dcache.scala:24:7, :37:16] req_voluntary <= io_req_bits_voluntary_0; // @[dcache.scala:24:7, :37:16] end if (_GEN_2) begin // @[dcache.scala:41:34, :43:28, :80:30, :88:41] r1_data_req_cnt <= _T_6 ? data_req_cnt : 4'h0; // @[Decoupled.scala:51:35] r2_data_req_cnt <= r1_data_req_cnt; // @[dcache.scala:42:28, :43:28] end if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h0) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_0 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h1) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_1 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h2) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_2 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h3) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_3 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h4) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_4 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h5) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_5 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h6) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_6 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if ((|state) & _T_3 & r2_data_req_fired & (&(r2_data_req_cnt[2:0]))) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34] wb_buffer_7 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22] if (reset) begin // @[dcache.scala:24:7] state <= 3'h0; // @[dcache.scala:39:22] r1_data_req_fired <= 1'h0; // @[dcache.scala:40:34] r2_data_req_fired <= 1'h0; // @[dcache.scala:41:34] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] r_counter <= 9'h0; // @[Edges.scala:229:27] acked <= 1'h0; // @[dcache.scala:47:22] end else begin // @[dcache.scala:24:7] if (|state) begin // @[dcache.scala:39:22, :49:31] if (_T_3) begin // @[dcache.scala:88:22] if (r2_data_req_fired & _T_8) begin // @[dcache.scala:39:22, :41:34, :108:30, :110:{29,53}, :112:15] state <= 3'h2; // @[dcache.scala:39:22] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] end else if (_T_6) // @[Decoupled.scala:51:35] data_req_cnt <= _data_req_cnt_T_1; // @[dcache.scala:44:29, :106:36] end else begin // @[dcache.scala:88:22] if (_T_9) begin // @[dcache.scala:116:22] if (io_lsu_release_ready_0 & io_lsu_release_valid_0) // @[Decoupled.scala:51:35] state <= 3'h3; // @[dcache.scala:39:22] end else if (_T_11) begin // @[dcache.scala:122:22] if (data_req_cnt == 4'h7 & _T_14) // @[Decoupled.scala:51:35] state <= _state_T; // @[dcache.scala:39:22, :133:19] end else if (_T_16 & acked) // @[dcache.scala:39:22, :47:22, :135:{22,35}, :139:18, :140:13] state <= 3'h0; // @[dcache.scala:39:22] if (_T_9 | ~(_T_11 & _T_14)) begin // @[Decoupled.scala:51:35] end else // @[dcache.scala:44:29, :116:41, :122:36] data_req_cnt <= _data_req_cnt_T_3; // @[dcache.scala:44:29, :130:36] end if (~_GEN_1) // @[dcache.scala:51:22, :88:41, :116:41, :122:36] acked <= _T_11 ? io_mem_grant_0 | acked : _T_16 & io_mem_grant_0 | acked; // @[dcache.scala:24:7, :47:22, :122:{22,36}, :126:25, :127:13, :135:{22,35}, :136:25, :137:13] end else begin // @[dcache.scala:49:31] if (_T_2) begin // @[Decoupled.scala:51:35] state <= 3'h1; // @[dcache.scala:39:22] data_req_cnt <= 4'h0; // @[dcache.scala:44:29] end acked <= ~_T_2 & acked; // @[Decoupled.scala:51:35] end if (_GEN_2) begin // @[dcache.scala:41:34, :80:30, :88:41] r1_data_req_fired <= _T_6; // @[Decoupled.scala:51:35] r2_data_req_fired <= r1_data_req_fired; // @[dcache.scala:40:34, :41:34] end if (_T_14) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] end always @(posedge) assign io_req_ready = io_req_ready_0; // @[dcache.scala:24:7] assign io_meta_read_valid = io_meta_read_valid_0; // @[dcache.scala:24:7] assign io_meta_read_bits_idx = io_meta_read_bits_idx_0; // @[dcache.scala:24:7] assign io_meta_read_bits_tag = io_meta_read_bits_tag_0; // @[dcache.scala:24:7] assign io_resp = io_resp_0; // @[dcache.scala:24:7] assign io_idx_valid = io_idx_valid_0; // @[dcache.scala:24:7] assign io_idx_bits = io_idx_bits_0; // @[dcache.scala:24:7] assign io_data_req_valid = io_data_req_valid_0; // @[dcache.scala:24:7] assign io_data_req_bits_way_en = io_data_req_bits_way_en_0; // @[dcache.scala:24:7] assign io_data_req_bits_addr = io_data_req_bits_addr_0; // @[dcache.scala:24:7] assign io_release_valid = io_release_valid_0; // @[dcache.scala:24:7] assign io_release_bits_opcode = io_release_bits_opcode_0; // @[dcache.scala:24:7] assign io_release_bits_param = io_release_bits_param_0; // @[dcache.scala:24:7] assign io_release_bits_address = io_release_bits_address_0; // @[dcache.scala:24:7] assign io_release_bits_data = io_release_bits_data_0; // @[dcache.scala:24:7] assign io_lsu_release_valid = io_lsu_release_valid_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_param = io_lsu_release_bits_param_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_address = io_lsu_release_bits_address_0; // @[dcache.scala:24:7] assign io_lsu_release_bits_data = io_lsu_release_bits_data_0; // @[dcache.scala:24:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_470( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tilelink.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLMasterToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2)) a.io.protocol <> io.tilelink.a io.tilelink.b <> b.io.protocol c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol e.io.protocol <> io.tilelink.e io.flits.a <> a.io.flit b.io.flit <> io.flits.b io.flits.c <> c.io.flit d.io.flit <> io.flits.d io.flits.e <> e.io.flit } class TLMasterACDToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) a.io.protocol <> io.tilelink.a c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol io.flits.a <> a.io.flit io.flits.c <> c.io.flit d.io.flit <> io.flits.d } class TLMasterBEToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0)) io.tilelink.b <> b.io.protocol e.io.protocol <> io.tilelink.e b.io.flit <> io.flits.b io.flits.e <> e.io.flit } class TLSlaveToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val b = Decoupled(new IngressFlit(flitWidth)) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) io.tilelink.a <> a.io.protocol b.io.protocol <> io.tilelink.b io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d io.tilelink.e <> e.io.protocol a.io.flit <> io.flits.a io.flits.b <> b.io.flit c.io.flit <> io.flits.c io.flits.d <> d.io.flit e.io.flit <> io.flits.e } class TLSlaveACDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart)) io.tilelink.a <> a.io.protocol io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d a.io.flit <> io.flits.a c.io.flit <> io.flits.c io.flits.d <> d.io.flit } class TLSlaveBEToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val b = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) b.io.protocol <> io.tilelink.b io.tilelink.e <> e.io.protocol io.flits.b <> b.io.flit e.io.flit <> io.flits.e } class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle { val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) }) val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) }) } trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper { def edgesIn: Seq[TLEdge] def edgesOut: Seq[TLEdge] def edgeInNodes: Seq[Int] def edgeOutNodes: Seq[Int] require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size) def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle)) def genBundle = new TLBundle(wideBundle) def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut) } object TLConnect { def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = { l.valid := r.valid r.ready := l.ready l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll } } // BEGIN: TileLinkProtocolParams case class TileLinkABCDEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int] ) extends TileLinkProtocolParams { // END: TileLinkProtocolParams val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten val nVirtualNetworks = 5 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A (if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B (if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D (if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { edgesIn.zipWithIndex.map { case (e,i) => val nif_master = Module(new TLMasterToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 3 + edgesIn.size * 2 + egressOffset, minPayloadWidth )) nif_master.io.tilelink := DontCare nif_master.io.tilelink.a.valid := false.B nif_master.io.tilelink.c.valid := false.B nif_master.io.tilelink.e.valid := false.B TLConnect(nif_master.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master.io.tilelink.b) TLConnect(nif_master.io.tilelink.c, protocol.in(i).c) TLConnect(nif_master.io.tilelink.e, protocol.in(i).e) } ingresses(i * 3 + 0).flit <> nif_master.io.flits.a ingresses(i * 3 + 1).flit <> nif_master.io.flits.c ingresses(i * 3 + 2).flit <> nif_master.io.flits.e nif_master.io.flits.b <> egresses(i * 2 + 0).flit nif_master.io.flits.d <> egresses(i * 2 + 1).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave = Module(new TLSlaveToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 2 + egressOffset, minPayloadWidth )) nif_slave.io.tilelink := DontCare nif_slave.io.tilelink.b.valid := false.B nif_slave.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a) TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b) TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c) TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e) } ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit } } } } } case class TileLinkACDProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val nVirtualNetworks = 3 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A (if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_acd = Module(new TLMasterACDToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 2 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_acd.io.tilelink := DontCare nif_master_acd.io.tilelink.a.valid := false.B nif_master_acd.io.tilelink.c.valid := false.B nif_master_acd.io.tilelink.e.valid := false.B TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c) } ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_acd = Module(new TLSlaveACDToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_acd.io.tilelink := DontCare nif_slave_acd.io.tilelink.b.valid := false.B nif_slave_acd.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a) TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c) } ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit } }} } } case class TileLinkBEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val nVirtualNetworks = 2 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B (if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_be = Module(new TLMasterBEToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 1 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_be.io.tilelink := DontCare nif_master_be.io.tilelink.a.valid := false.B nif_master_be.io.tilelink.c.valid := false.B nif_master_be.io.tilelink.e.valid := false.B if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b) TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e) } ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_be = Module(new TLSlaveBEToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_be.io.tilelink := DontCare nif_slave_be.io.tilelink.b.valid := false.B nif_slave_be.io.tilelink.d.valid := false.B if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e) TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b) } ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit } }} } } abstract class TLNoCLike(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") // TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers port.managers map { manager => manager.v1copy(fifoId = None) } } ) } ) } abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) { val edgesIn: Seq[TLEdge] val edgesOut: Seq[TLEdge] val nodeMapping: DiplomaticNetworkNodeMapping val nocName: String lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name))) lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name))) lazy val edgeInNodes = nodeMapping.getNodesIn(inNames) lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames) def printNodeMappings() { println(s"Constellation: TLNoC $nocName inwards mapping:") for ((n, i) <- inNames zip edgeInNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } println(s"Constellation: TLNoC $nocName outwards mapping:") for ((n, i) <- outNames zip edgeOutNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } } } trait TLNoCParams // Instantiates a private TLNoC. Replaces the TLXbar // BEGIN: TLNoCParams case class SimpleTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, nocParams: NoCParams = NoCParams(), ) extends TLNoCParams class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { // END: TLNoCParams override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val noc = Module(new ProtocolNoC(ProtocolNoCParams( params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC), Seq(protocolParams), inlineNoC = inlineNoC ))) noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } } case class SplitACDxBETLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, acdNoCParams: NoCParams = NoCParams(), beNoCParams: NoCParams = NoCParams(), beDivision: Int = 2 ) extends TLNoCParams class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val acdProtocolParams = TileLinkACDProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val beProtocolParams = TileLinkBEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC), Seq(acdProtocolParams), inlineNoC = inlineNoC ))) val be_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC), Seq(beProtocolParams), widthDivision = params.beDivision, inlineNoC = inlineNoC ))) acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } }} be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.b <> r.b l.e <> r.e } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.b <> r.b l.e <> r.e } }} } } case class GlobalTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping ) extends TLNoCParams // Maps this interconnect onto a global NoC class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike { lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) printNodeMappings() val io_global = IO(Flipped(protocolParams.genIO())) io_global match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } }

module TLMasterToNoC_2( // @[Tilelink.scala:37:7] input clock, // @[Tilelink.scala:37:7] input reset, // @[Tilelink.scala:37:7] output io_tilelink_a_ready, // @[Tilelink.scala:44:14] input io_tilelink_a_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:44:14] input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_d_ready, // @[Tilelink.scala:44:14] output io_tilelink_d_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_d_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_sink, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:44:14] input io_flits_a_ready, // @[Tilelink.scala:44:14] output io_flits_a_valid, // @[Tilelink.scala:44:14] output io_flits_a_bits_head, // @[Tilelink.scala:44:14] output io_flits_a_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:44:14] output [3:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_b_ready, // @[Tilelink.scala:44:14] input io_flits_b_valid, // @[Tilelink.scala:44:14] input io_flits_b_bits_head, // @[Tilelink.scala:44:14] input io_flits_b_bits_tail, // @[Tilelink.scala:44:14] output io_flits_d_ready, // @[Tilelink.scala:44:14] input io_flits_d_valid, // @[Tilelink.scala:44:14] input io_flits_d_bits_head, // @[Tilelink.scala:44:14] input io_flits_d_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_d_bits_payload // @[Tilelink.scala:44:14] ); TLAToNoC_2 a ( // @[Tilelink.scala:54:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:54:17] TLBFromNoC b ( // @[Tilelink.scala:55:17] .clock (clock), .reset (reset), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail) ); // @[Tilelink.scala:55:17] TLDFromNoC d ( // @[Tilelink.scala:57:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:68:14] ); // @[Tilelink.scala:57:17] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RegisterFile.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import freechips.rocketchip.util._ import saturn.common._ class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { val io = IO(new ArbiterIO(new VectorReadReq, n)) val arb = Module(new RRArbiter(new VectorReadReq, n)) io <> arb.io val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) //assert(PopCount(oldest_oh) <= 1.U) when (oldest_oh.orR) { io.chosen := VecInit(oldest_oh).asUInt io.out.valid := true.B io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) for (i <- 0 until n) { io.in(i).ready := oldest_oh(i) && io.out.ready } } } class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Vec(n, Flipped(new VectorReadIO)) val out = Vec(banks, new VectorReadIO) }) val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } for (i <- 0 until banks) { io.out(i).req <> arbs(i).io.out } val bankOffset = log2Ceil(banks) for (i <- 0 until n) { val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) for (j <- 0 until banks) { arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest } io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) } } class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val read = Vec(reads, Flipped(new VectorReadIO)) val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) val write = Input(Valid(new VectorWrite(dLen))) val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) }) val ll_write_valid = RegInit(false.B) val ll_write_bits = Reg(new VectorWrite(dLen)) val vrf = Mem(rows, Vec(dLen, Bool())) val v0_mask = Mem(maskRows, Vec(dLen, Bool())) for (read <- io.read) { read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) read.resp := DontCare when (read.req.valid) { read.resp := vrf.read(read.req.bits.eg).asUInt } } for (mask_read <- io.mask_read) { mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) mask_read.resp := DontCare when (mask_read.req.valid) { mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt } } val write = WireInit(io.write) io.ll_write.ready := false.B if (vParams.vrfHiccupBuffer) { when (!io.write.valid) { // drain hiccup buffer write.valid := ll_write_valid || io.ll_write.valid write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) ll_write_valid := false.B when (io.ll_write.valid && ll_write_valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } .elsewhen (!ll_write_valid) { // fill hiccup buffer when (io.ll_write.valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } } else { when (!io.write.valid) { io.ll_write.ready := true.B write.valid := io.ll_write.valid write.bits := io.ll_write.bits } } when (write.valid) { vrf.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) when (write.bits.eg < maskRows.U) { v0_mask.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) } } } class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val nBanks = vParams.vrfBanking // Support 1, 2, and 4 banks for the VRF require(nBanks == 1 || nBanks == 2 || nBanks == 4) val io = IO(new Bundle { val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) }) val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } reads.zipWithIndex.foreach { case (rc, i) => val xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.read(i) <> xbar.io.out(j) } xbar.io.in <> io.read(i) } maskReads.zipWithIndex.foreach { case (rc, i) => val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.mask_read(i) <> mask_xbar.io.out(j) } mask_xbar.io.in <> io.mask_read(i) } io.ll_writes.foreach(_.ready := false.B) vrf.zipWithIndex.foreach { case (rf, i) => val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) val bank_write_valid = bank_match.orR rf.io.write.valid := bank_write_valid rf.io.write.bits.data := bank_write_data rf.io.write.bits.mask := bank_write_mask rf.io.write.bits.eg := bank_write_eg >> vrfBankBits when (bank_write_valid) { PopCount(bank_match) === 1.U } val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) rf.io.ll_write <> ll_arb.io.out io.ll_writes.zipWithIndex.foreach { case (w, j) => ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits ll_arb.io.in(j).bits.data := w.bits.data ll_arb.io.in(j).bits.mask := w.bits.mask when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { w.ready := true.B } } } }

module RegisterReadXbar_3( // @[RegisterFile.scala:27:7] input clock, // @[RegisterFile.scala:27:7] output io_in_0_req_ready, // @[RegisterFile.scala:28:14] input io_in_0_req_valid, // @[RegisterFile.scala:28:14] input io_in_0_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_0_resp, // @[RegisterFile.scala:28:14] output io_in_1_req_ready, // @[RegisterFile.scala:28:14] input io_in_1_req_valid, // @[RegisterFile.scala:28:14] input io_in_1_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_1_resp, // @[RegisterFile.scala:28:14] output io_in_2_req_ready, // @[RegisterFile.scala:28:14] input io_in_2_req_valid, // @[RegisterFile.scala:28:14] input io_in_2_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_2_resp, // @[RegisterFile.scala:28:14] output io_in_3_req_ready, // @[RegisterFile.scala:28:14] input io_in_3_req_valid, // @[RegisterFile.scala:28:14] input io_in_3_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_3_resp, // @[RegisterFile.scala:28:14] output io_in_4_req_ready, // @[RegisterFile.scala:28:14] input io_in_4_req_valid, // @[RegisterFile.scala:28:14] input [4:0] io_in_4_req_bits_eg, // @[RegisterFile.scala:28:14] output [63:0] io_in_4_resp, // @[RegisterFile.scala:28:14] input io_out_0_req_ready, // @[RegisterFile.scala:28:14] output [4:0] io_out_0_req_bits_eg, // @[RegisterFile.scala:28:14] input [63:0] io_out_0_resp, // @[RegisterFile.scala:28:14] input io_out_1_req_ready, // @[RegisterFile.scala:28:14] output [4:0] io_out_1_req_bits_eg, // @[RegisterFile.scala:28:14] input [63:0] io_out_1_resp // @[RegisterFile.scala:28:14] ); wire _arbs_1_io_in_4_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_4_ready; // @[RegisterFile.scala:33:38] wire [4:0] arbs_1_io_in_4_bits_eg = {1'h0, io_in_4_req_bits_eg[4:1]}; // @[RegisterFile.scala:44:{32,56}] OldestRRArbiter_6 arbs_0 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (io_in_0_req_ready), .io_in_0_valid (io_in_0_req_valid), .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (io_in_1_req_ready), .io_in_1_valid (io_in_1_req_valid), .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (io_in_2_req_ready), .io_in_2_valid (io_in_2_req_valid), .io_in_2_bits_oldest (io_in_2_req_bits_oldest), .io_in_3_ready (io_in_3_req_ready), .io_in_3_valid (io_in_3_req_valid), .io_in_3_bits_oldest (io_in_3_req_bits_oldest), .io_in_4_ready (_arbs_0_io_in_4_ready), .io_in_4_valid (io_in_4_req_valid & ~(io_in_4_req_bits_eg[0])), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_4_bits_eg (arbs_1_io_in_4_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_0_req_ready), .io_out_bits_eg (io_out_0_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter_6 arbs_1 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (/* unused */), .io_in_0_valid (1'h0), .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (/* unused */), .io_in_1_valid (1'h0), .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (/* unused */), .io_in_2_valid (1'h0), .io_in_2_bits_oldest (io_in_2_req_bits_oldest), .io_in_3_ready (/* unused */), .io_in_3_valid (1'h0), .io_in_3_bits_oldest (io_in_3_req_bits_oldest), .io_in_4_ready (_arbs_1_io_in_4_ready), .io_in_4_valid (io_in_4_req_valid & io_in_4_req_bits_eg[0]), // @[RegisterFile.scala:41:82, :43:52] .io_in_4_bits_eg (arbs_1_io_in_4_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_1_req_ready), .io_out_bits_eg (io_out_1_req_bits_eg) ); // @[RegisterFile.scala:33:38] assign io_in_0_resp = io_out_0_resp; // @[RegisterFile.scala:27:7] assign io_in_1_resp = io_out_0_resp; // @[RegisterFile.scala:27:7] assign io_in_2_resp = io_out_0_resp; // @[RegisterFile.scala:27:7] assign io_in_3_resp = io_out_0_resp; // @[RegisterFile.scala:27:7] assign io_in_4_req_ready = ~(io_in_4_req_bits_eg[0]) & _arbs_0_io_in_4_ready | io_in_4_req_bits_eg[0] & _arbs_1_io_in_4_ready; // @[Mux.scala:30:73] assign io_in_4_resp = (io_in_4_req_bits_eg[0] ? 64'h0 : io_out_0_resp) | (io_in_4_req_bits_eg[0] ? io_out_1_resp : 64'h0); // @[Mux.scala:30:73] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_314( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_58 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w4_d3_i0_29( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_277 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_278 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_279 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_280 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File DivSqrtRecFN_small.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2017 SiFive, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of SiFive nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ /* s = sigWidth c_i = newBit Division: width of a is (s+2) Normal ------ (qi + ci * 2^(-i))*b <= a q0 = 0 r0 = a q(i+1) = qi + ci*2^(-i) ri = a - qi*b r(i+1) = a - q(i+1)*b = a - qi*b - ci*2^(-i)*b r(i+1) = ri - ci*2^(-i)*b ci = ri >= 2^(-i)*b summary_i = ri != 0 i = 0 to s+1 (s+1)th bit plus summary_(i+1) gives enough information for rounding If (a < b), then we need to calculate (s+2)th bit and summary_(i+1) because we need s bits ignoring the leading zero. (This is skipCycle2 part of Hauser's code.) Hauser ------ sig_i = qi rem_i = 2^(i-2)*ri cycle_i = s+3-i sig_0 = 0 rem_0 = a/4 cycle_0 = s+3 bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits) sig(i+1) = sig(i) + ci*bit_i rem(i+1) = 2rem_i - ci*b/2 ci = 2rem_i >= b/2 bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits) cycle(i+1) = cycle_i-1 summary_1 = a <> b summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0 Proof: 2^i*r(i+1) = 2^i*ri - ci*b. Qed ci = 2^i*ri >= b. Qed summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0 Now, note that all of ck's cannot be 0, since that means a is 0. So when you traverse through a chain of 0 ck's, from the end, eventually, you reach a non-zero cj. That is exactly the value of ri as the reminder remains the same. When all ck's are 0 except c0 (which must be 1) then summary_1 is set correctly according to r1 = a-b != 0. So summary(i+1) is always set correctly according to r(i+1) Square root: width of a is (s+1) Normal ------ (xi + ci*2^(-i))^2 <= a xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a x0 = 0 x(i+1) = xi + ci*2^(-i) ri = a - xi^2 r(i+1) = a - x(i+1)^2 = a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i))) = ri - ci*2^(-i)*(2xi+ci*2^(-i)) = ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1 ci = ri >= 2^(-i)*(2xi + 2^(-i)) summary_i = ri != 0 i = 0 to s+1 For odd expression, do 2 steps initially. (s+1)th bit plus summary_(i+1) gives enough information for rounding. Hauser ------ sig_i = xi rem_i = ri*2^(i-1) cycle_i = s+2-i bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation) sig_0 = 0 rem_0 = a/2 cycle_0 = s+2 bit_0 = 1 (= 2^s in terms of bit representation) sig(i+1) = sig_i + ci * bit_i rem(i+1) = 2rem_i - ci*(2sig_i + bit_i) ci = 2*sig_i + bit_i <= 2*rem_i bit_i = 2^(cycle_i-2) (in terms of bit representation) cycle(i+1) = cycle_i-1 summary_1 = a - (2^s) (in terms of bit representation) summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0 Proof: ci = 2*sig_i + bit_i <= 2*rem_i ci = 2xi + 2^(-i) <= ri*2^i. Qed sig(i+1) = sig_i + ci * bit_i x(i+1) = xi + ci*2^(-i). Qed rem(i+1) = 2rem_i - ci*(2sig_i + bit_i) r(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i)) r(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed Same argument as before for summary. ------------------------------ Note that all registers are updated normally until cycle == 2. At cycle == 2, rem is not updated, but all other registers are updated normally. But, cycle == 1 does not read rem to calculate anything (note that final summary is calculated using the values at cycle = 2). */ package hardfloat import chisel3._ import chisel3.util._ import consts._ /*---------------------------------------------------------------------------- | Computes a division or square root for floating-point in recoded form. | Multiple clock cycles are needed for each division or square-root operation, | except possibly in special cases. *----------------------------------------------------------------------------*/ class DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /*-------------------------------------------------------------------- *--------------------------------------------------------------------*/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val roundingMode = Input(UInt(3.W)) /*-------------------------------------------------------------------- *--------------------------------------------------------------------*/ val rawOutValid_div = Output(Bool()) val rawOutValid_sqrt = Output(Bool()) val roundingModeOut = Output(UInt(3.W)) val invalidExc = Output(Bool()) val infiniteExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W)) val inReady = RegInit(true.B) // <-> (cycleNum <= 1) val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1) val sqrtOp_Z = Reg(Bool()) val majorExc_Z = Reg(Bool()) //*** REDUCE 3 BITS TO 2-BIT CODE: val isNaN_Z = Reg(Bool()) val isInf_Z = Reg(Bool()) val isZero_Z = Reg(Bool()) val sign_Z = Reg(Bool()) val sExp_Z = Reg(SInt((expWidth + 2).W)) val fractB_Z = Reg(UInt(sigWidth.W)) val roundingMode_Z = Reg(UInt(3.W)) /*------------------------------------------------------------------------ | (The most-significant and least-significant bits of 'rem_Z' are needed | only for square roots.) *------------------------------------------------------------------------*/ val rem_Z = Reg(UInt((sigWidth + 2).W)) val notZeroRem_Z = Reg(Bool()) val sigX_Z = Reg(UInt((sigWidth + 2).W)) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val rawA_S = io.a val rawB_S = io.b //*** IMPROVE THESE: val notSigNaNIn_invalidExc_S_div = (rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf) val notSigNaNIn_invalidExc_S_sqrt = ! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign val majorExc_S = Mux(io.sqrtOp, isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt, isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) || notSigNaNIn_invalidExc_S_div || (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero) ) val isNaN_S = Mux(io.sqrtOp, rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt, rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div ) val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero) val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf) val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign) val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) val sExpQuot_S_div = rawA_S.sExp +& Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt //*** IS THIS OPTIMAL?: val sSatExpQuot_S_div = Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div), 6.U, sExpQuot_S_div(expWidth + 1, expWidth - 2) ), sExpQuot_S_div(expWidth - 3, 0) ).asSInt val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0) val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val idle = cycleNum === 0.U val entering = inReady && io.inValid val entering_normalCase = entering && normalCase_S val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B when (! idle || entering) { def computeCycleNum(f: UInt => UInt): UInt = { Mux(entering & ! normalCase_S, f(1.U), 0.U) | Mux(entering_normalCase, Mux(io.sqrtOp, Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)), f((sigWidth + 2).U) ), 0.U ) | Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) | Mux(skipCycle2, f(1.U), 0.U) } inReady := computeCycleNum(_ <= 1.U).asBool rawOutValid := computeCycleNum(_ === 1.U).asBool cycleNum := computeCycleNum(x => x) } io.inReady := inReady /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ when (entering) { sqrtOp_Z := io.sqrtOp majorExc_Z := majorExc_S isNaN_Z := isNaN_S isInf_Z := isInf_S isZero_Z := isZero_S sign_Z := sign_S sExp_Z := Mux(io.sqrtOp, (rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S, sSatExpQuot_S_div ) roundingMode_Z := io.roundingMode } when (entering || ! inReady && sqrtOp_Z) { fractB_Z := Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) | Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) | Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) | Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) | Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U) } /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val rem = Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) | Mux(inReady && oddSqrt_S, Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U, rawA_S.sig(sigWidth - 3, 0)<<3 ), 0.U ) | Mux(! inReady, rem_Z<<1, 0.U) val bitMask = (1.U<<cycleNum)>>2 val trialTerm = Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) | Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) | Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) | Mux(! inReady, fractB_Z, 0.U) | Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) | Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U) val trialRem = rem.zext -& trialTerm.zext val newBit = (0.S <= trialRem) val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0) val rem2 = nextRem_Z<<1 val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth)) val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U) val trialRem2 = Mux(newBit, (trialRem<<1) - trialTerm2_newBit1.zext, (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) val newBit2 = (0.S <= trialRem2) val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z) val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z) processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) || processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) || !(processTwoBits && newBit2) && nextNotZeroRem_Z val nextRem_Z_2 = Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) | Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) | Mux(!processTwoBits, nextRem_Z, 0.U) when (entering || ! inReady) { notZeroRem_Z := nextNotZeroRem_Z_2 rem_Z := nextRem_Z_2 sigX_Z := Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) | Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) | Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) | Mux(! inReady, sigX_Z, 0.U) | Mux(! inReady && newBit, bitMask, 0.U) | Mux(processTwoBits && newBit2, bitMask>>1, 0.U) } /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ io.rawOutValid_div := rawOutValid && ! sqrtOp_Z io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z io.roundingModeOut := roundingMode_Z io.invalidExc := majorExc_Z && isNaN_Z io.infiniteExc := majorExc_Z && ! isNaN_Z io.rawOut.isNaN := isNaN_Z io.rawOut.isInf := isInf_Z io.rawOut.isZero := isZero_Z io.rawOut.sign := sign_Z io.rawOut.sExp := sExp_Z io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z } /*---------------------------------------------------------------------------- *----------------------------------------------------------------------------*/ class DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /*-------------------------------------------------------------------- *--------------------------------------------------------------------*/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) /*-------------------------------------------------------------------- *--------------------------------------------------------------------*/ val rawOutValid_div = Output(Bool()) val rawOutValid_sqrt = Output(Bool()) val roundingModeOut = Output(UInt(3.W)) val invalidExc = Output(Bool()) val infiniteExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val divSqrtRawFN = Module(new DivSqrtRawFN_small(expWidth, sigWidth, options)) io.inReady := divSqrtRawFN.io.inReady divSqrtRawFN.io.inValid := io.inValid divSqrtRawFN.io.sqrtOp := io.sqrtOp divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) divSqrtRawFN.io.roundingMode := io.roundingMode io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt io.roundingModeOut := divSqrtRawFN.io.roundingModeOut io.invalidExc := divSqrtRawFN.io.invalidExc io.infiniteExc := divSqrtRawFN.io.infiniteExc io.rawOut := divSqrtRawFN.io.rawOut } /*---------------------------------------------------------------------------- *----------------------------------------------------------------------------*/ class DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int) extends Module { override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { /*-------------------------------------------------------------------- *--------------------------------------------------------------------*/ val inReady = Output(Bool()) val inValid = Input(Bool()) val sqrtOp = Input(Bool()) val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) /*-------------------------------------------------------------------- *--------------------------------------------------------------------*/ val outValid_div = Output(Bool()) val outValid_sqrt = Output(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val divSqrtRecFNToRaw = Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options)) io.inReady := divSqrtRecFNToRaw.io.inReady divSqrtRecFNToRaw.io.inValid := io.inValid divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp divSqrtRecFNToRaw.io.a := io.a divSqrtRecFNToRaw.io.b := io.b divSqrtRecFNToRaw.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module DivSqrtRecFM_small_e8_s24_2( // @[DivSqrtRecFN_small.scala:468:5] input clock, // @[DivSqrtRecFN_small.scala:468:5] input reset, // @[DivSqrtRecFN_small.scala:468:5] output io_inReady, // @[DivSqrtRecFN_small.scala:472:16] input io_inValid, // @[DivSqrtRecFN_small.scala:472:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:472:16] input [32:0] io_a, // @[DivSqrtRecFN_small.scala:472:16] input [32:0] io_b, // @[DivSqrtRecFN_small.scala:472:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:472:16] output io_outValid_div, // @[DivSqrtRecFN_small.scala:472:16] output io_outValid_sqrt, // @[DivSqrtRecFN_small.scala:472:16] output [32:0] io_out, // @[DivSqrtRecFN_small.scala:472:16] output [4:0] io_exceptionFlags // @[DivSqrtRecFN_small.scala:472:16] ); wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_invalidExc; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_infiniteExc; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_isNaN; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_isInf; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_isZero; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_sign; // @[DivSqrtRecFN_small.scala:493:15] wire [9:0] _divSqrtRecFNToRaw_io_rawOut_sExp; // @[DivSqrtRecFN_small.scala:493:15] wire [26:0] _divSqrtRecFNToRaw_io_rawOut_sig; // @[DivSqrtRecFN_small.scala:493:15] wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:468:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:468:5] wire [32:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:468:5] wire [32:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:468:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:468:5] wire io_detectTininess = 1'h1; // @[DivSqrtRecFN_small.scala:468:5, :472:16, :508:15] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5] wire io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5] wire io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5] wire [32:0] io_out_0; // @[DivSqrtRecFN_small.scala:468:5] wire [4:0] io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5] DivSqrtRecFMToRaw_small_e8_s24_2 divSqrtRecFNToRaw ( // @[DivSqrtRecFN_small.scala:493:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:468:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:468:5] .io_a (io_a_0), // @[DivSqrtRecFN_small.scala:468:5] .io_b (io_b_0), // @[DivSqrtRecFN_small.scala:468:5] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:468:5] .io_rawOutValid_div (io_outValid_div_0), .io_rawOutValid_sqrt (io_outValid_sqrt_0), .io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut), .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc), .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc), .io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN), .io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf), .io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero), .io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign), .io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp), .io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig) ); // @[DivSqrtRecFN_small.scala:493:15] RoundRawFNToRecFN_e8_s24_5 roundRawFNToRecFN ( // @[DivSqrtRecFN_small.scala:508:15] .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc), // @[DivSqrtRecFN_small.scala:493:15] .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc), // @[DivSqrtRecFN_small.scala:493:15] .io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN), // @[DivSqrtRecFN_small.scala:493:15] .io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf), // @[DivSqrtRecFN_small.scala:493:15] .io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero), // @[DivSqrtRecFN_small.scala:493:15] .io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign), // @[DivSqrtRecFN_small.scala:493:15] .io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp), // @[DivSqrtRecFN_small.scala:493:15] .io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig), // @[DivSqrtRecFN_small.scala:493:15] .io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut), // @[DivSqrtRecFN_small.scala:493:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[DivSqrtRecFN_small.scala:508:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_outValid_div = io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_outValid_sqrt = io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_out = io_out_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_332( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_130( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1)) }) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf || io.b.isInf val notNaN_isZeroOut = io.a.isZero || io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN || io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulRawFN_14( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_14 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn || noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }

module TLNoC_router_2ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_2 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_2_flit_ready (auto_routers_ingress_nodes_in_2_flit_ready), .auto_ingress_nodes_in_2_flit_valid (auto_routers_ingress_nodes_in_2_flit_valid), .auto_ingress_nodes_in_2_flit_bits_head (auto_routers_ingress_nodes_in_2_flit_bits_head), .auto_ingress_nodes_in_2_flit_bits_payload (auto_routers_ingress_nodes_in_2_flit_bits_payload), .auto_ingress_nodes_in_2_flit_bits_egress_id (auto_routers_ingress_nodes_in_2_flit_bits_egress_id), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule

Generate the Verilog code corresponding to the following Chisel files. File rename-busytable.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Rename BusyTable //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util._ import boom.v3.common._ import boom.v3.util._ import org.chipsalliance.cde.config.Parameters class BusyResp extends Bundle { val prs1_busy = Bool() val prs2_busy = Bool() val prs3_busy = Bool() } class RenameBusyTable( val plWidth: Int, val numPregs: Int, val numWbPorts: Int, val bypass: Boolean, val float: Boolean) (implicit p: Parameters) extends BoomModule { val pregSz = log2Ceil(numPregs) val io = IO(new BoomBundle()(p) { val ren_uops = Input(Vec(plWidth, new MicroOp)) val busy_resps = Output(Vec(plWidth, new BusyResp)) val rebusy_reqs = Input(Vec(plWidth, Bool())) val wb_pdsts = Input(Vec(numWbPorts, UInt(pregSz.W))) val wb_valids = Input(Vec(numWbPorts, Bool())) val debug = new Bundle { val busytable = Output(Bits(numPregs.W)) } }) val busy_table = RegInit(0.U(numPregs.W)) // Unbusy written back registers. val busy_table_wb = busy_table & ~(io.wb_pdsts zip io.wb_valids) .map {case (pdst, valid) => UIntToOH(pdst) & Fill(numPregs, valid.asUInt)}.reduce(_|_) // Rebusy newly allocated registers. val busy_table_next = busy_table_wb | (io.ren_uops zip io.rebusy_reqs) .map {case (uop, req) => UIntToOH(uop.pdst) & Fill(numPregs, req.asUInt)}.reduce(_|_) busy_table := busy_table_next // Read the busy table. for (i <- 0 until plWidth) { val prs1_was_bypassed = (0 until i).map(j => io.ren_uops(i).lrs1 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_) val prs2_was_bypassed = (0 until i).map(j => io.ren_uops(i).lrs2 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_) val prs3_was_bypassed = (0 until i).map(j => io.ren_uops(i).lrs3 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_) io.busy_resps(i).prs1_busy := busy_table(io.ren_uops(i).prs1) || prs1_was_bypassed && bypass.B io.busy_resps(i).prs2_busy := busy_table(io.ren_uops(i).prs2) || prs2_was_bypassed && bypass.B io.busy_resps(i).prs3_busy := busy_table(io.ren_uops(i).prs3) || prs3_was_bypassed && bypass.B if (!float) io.busy_resps(i).prs3_busy := false.B } io.debug.busytable := busy_table }

module RenameBusyTable_2( // @[rename-busytable.scala:27:7] input clock, // @[rename-busytable.scala:27:7] input reset, // @[rename-busytable.scala:27:7] input [6:0] io_ren_uops_0_uopc, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_0_inst, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_0_debug_inst, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_rvc, // @[rename-busytable.scala:37:14] input [39:0] io_ren_uops_0_debug_pc, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_0_iq_type, // @[rename-busytable.scala:37:14] input [9:0] io_ren_uops_0_fu_code, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_0_ctrl_br_type, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_ctrl_op1_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_0_ctrl_op2_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_0_ctrl_imm_sel, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_ctrl_op_fcn, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ctrl_fcn_dw, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_0_ctrl_csr_cmd, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ctrl_is_load, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ctrl_is_sta, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ctrl_is_std, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_iw_state, // @[rename-busytable.scala:37:14] input io_ren_uops_0_iw_p1_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_0_iw_p2_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_br, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_jalr, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_jal, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_sfb, // @[rename-busytable.scala:37:14] input [15:0] io_ren_uops_0_br_mask, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_0_br_tag, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_ftq_idx, // @[rename-busytable.scala:37:14] input io_ren_uops_0_edge_inst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_0_pc_lob, // @[rename-busytable.scala:37:14] input io_ren_uops_0_taken, // @[rename-busytable.scala:37:14] input [19:0] io_ren_uops_0_imm_packed, // @[rename-busytable.scala:37:14] input [11:0] io_ren_uops_0_csr_addr, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_0_rob_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_ldq_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_stq_idx, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_rxq_idx, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_0_pdst, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_0_prs1, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_0_prs2, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_ppred, // @[rename-busytable.scala:37:14] input io_ren_uops_0_prs1_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_0_prs2_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ppred_busy, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_0_stale_pdst, // @[rename-busytable.scala:37:14] input io_ren_uops_0_exception, // @[rename-busytable.scala:37:14] input [63:0] io_ren_uops_0_exc_cause, // @[rename-busytable.scala:37:14] input io_ren_uops_0_bypassable, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_0_mem_cmd, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_mem_size, // @[rename-busytable.scala:37:14] input io_ren_uops_0_mem_signed, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_fence, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_fencei, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_amo, // @[rename-busytable.scala:37:14] input io_ren_uops_0_uses_ldq, // @[rename-busytable.scala:37:14] input io_ren_uops_0_uses_stq, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_sys_pc2epc, // @[rename-busytable.scala:37:14] input io_ren_uops_0_is_unique, // @[rename-busytable.scala:37:14] input io_ren_uops_0_flush_on_commit, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ldst_is_rs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_0_ldst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_0_lrs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_0_lrs2, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_0_lrs3, // @[rename-busytable.scala:37:14] input io_ren_uops_0_ldst_val, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_dst_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_lrs1_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_lrs2_rtype, // @[rename-busytable.scala:37:14] input io_ren_uops_0_frs3_en, // @[rename-busytable.scala:37:14] input io_ren_uops_0_fp_val, // @[rename-busytable.scala:37:14] input io_ren_uops_0_fp_single, // @[rename-busytable.scala:37:14] input io_ren_uops_0_xcpt_pf_if, // @[rename-busytable.scala:37:14] input io_ren_uops_0_xcpt_ae_if, // @[rename-busytable.scala:37:14] input io_ren_uops_0_xcpt_ma_if, // @[rename-busytable.scala:37:14] input io_ren_uops_0_bp_debug_if, // @[rename-busytable.scala:37:14] input io_ren_uops_0_bp_xcpt_if, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_debug_fsrc, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_0_debug_tsrc, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_uopc, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_1_inst, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_1_debug_inst, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_rvc, // @[rename-busytable.scala:37:14] input [39:0] io_ren_uops_1_debug_pc, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_1_iq_type, // @[rename-busytable.scala:37:14] input [9:0] io_ren_uops_1_fu_code, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_1_ctrl_br_type, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_ctrl_op1_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_1_ctrl_op2_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_1_ctrl_imm_sel, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_ctrl_op_fcn, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ctrl_fcn_dw, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_1_ctrl_csr_cmd, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ctrl_is_load, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ctrl_is_sta, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ctrl_is_std, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_iw_state, // @[rename-busytable.scala:37:14] input io_ren_uops_1_iw_p1_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_1_iw_p2_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_br, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_jalr, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_jal, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_sfb, // @[rename-busytable.scala:37:14] input [15:0] io_ren_uops_1_br_mask, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_1_br_tag, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_ftq_idx, // @[rename-busytable.scala:37:14] input io_ren_uops_1_edge_inst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_1_pc_lob, // @[rename-busytable.scala:37:14] input io_ren_uops_1_taken, // @[rename-busytable.scala:37:14] input [19:0] io_ren_uops_1_imm_packed, // @[rename-busytable.scala:37:14] input [11:0] io_ren_uops_1_csr_addr, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_rob_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_ldq_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_stq_idx, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_rxq_idx, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_pdst, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_prs1, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_prs2, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_ppred, // @[rename-busytable.scala:37:14] input io_ren_uops_1_prs1_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_1_prs2_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ppred_busy, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_1_stale_pdst, // @[rename-busytable.scala:37:14] input io_ren_uops_1_exception, // @[rename-busytable.scala:37:14] input [63:0] io_ren_uops_1_exc_cause, // @[rename-busytable.scala:37:14] input io_ren_uops_1_bypassable, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_1_mem_cmd, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_mem_size, // @[rename-busytable.scala:37:14] input io_ren_uops_1_mem_signed, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_fence, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_fencei, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_amo, // @[rename-busytable.scala:37:14] input io_ren_uops_1_uses_ldq, // @[rename-busytable.scala:37:14] input io_ren_uops_1_uses_stq, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_sys_pc2epc, // @[rename-busytable.scala:37:14] input io_ren_uops_1_is_unique, // @[rename-busytable.scala:37:14] input io_ren_uops_1_flush_on_commit, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ldst_is_rs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_1_ldst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_1_lrs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_1_lrs2, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_1_lrs3, // @[rename-busytable.scala:37:14] input io_ren_uops_1_ldst_val, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_dst_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_lrs1_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_lrs2_rtype, // @[rename-busytable.scala:37:14] input io_ren_uops_1_frs3_en, // @[rename-busytable.scala:37:14] input io_ren_uops_1_fp_val, // @[rename-busytable.scala:37:14] input io_ren_uops_1_fp_single, // @[rename-busytable.scala:37:14] input io_ren_uops_1_xcpt_pf_if, // @[rename-busytable.scala:37:14] input io_ren_uops_1_xcpt_ae_if, // @[rename-busytable.scala:37:14] input io_ren_uops_1_xcpt_ma_if, // @[rename-busytable.scala:37:14] input io_ren_uops_1_bp_debug_if, // @[rename-busytable.scala:37:14] input io_ren_uops_1_bp_xcpt_if, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_debug_fsrc, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_1_debug_tsrc, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_uopc, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_2_inst, // @[rename-busytable.scala:37:14] input [31:0] io_ren_uops_2_debug_inst, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_rvc, // @[rename-busytable.scala:37:14] input [39:0] io_ren_uops_2_debug_pc, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_2_iq_type, // @[rename-busytable.scala:37:14] input [9:0] io_ren_uops_2_fu_code, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_2_ctrl_br_type, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_ctrl_op1_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_2_ctrl_op2_sel, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_2_ctrl_imm_sel, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_ctrl_op_fcn, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ctrl_fcn_dw, // @[rename-busytable.scala:37:14] input [2:0] io_ren_uops_2_ctrl_csr_cmd, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ctrl_is_load, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ctrl_is_sta, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ctrl_is_std, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_iw_state, // @[rename-busytable.scala:37:14] input io_ren_uops_2_iw_p1_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_2_iw_p2_poisoned, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_br, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_jalr, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_jal, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_sfb, // @[rename-busytable.scala:37:14] input [15:0] io_ren_uops_2_br_mask, // @[rename-busytable.scala:37:14] input [3:0] io_ren_uops_2_br_tag, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_ftq_idx, // @[rename-busytable.scala:37:14] input io_ren_uops_2_edge_inst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_2_pc_lob, // @[rename-busytable.scala:37:14] input io_ren_uops_2_taken, // @[rename-busytable.scala:37:14] input [19:0] io_ren_uops_2_imm_packed, // @[rename-busytable.scala:37:14] input [11:0] io_ren_uops_2_csr_addr, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_rob_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_ldq_idx, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_stq_idx, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_rxq_idx, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_pdst, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_prs1, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_prs2, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_ppred, // @[rename-busytable.scala:37:14] input io_ren_uops_2_prs1_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_2_prs2_busy, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ppred_busy, // @[rename-busytable.scala:37:14] input [6:0] io_ren_uops_2_stale_pdst, // @[rename-busytable.scala:37:14] input io_ren_uops_2_exception, // @[rename-busytable.scala:37:14] input [63:0] io_ren_uops_2_exc_cause, // @[rename-busytable.scala:37:14] input io_ren_uops_2_bypassable, // @[rename-busytable.scala:37:14] input [4:0] io_ren_uops_2_mem_cmd, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_mem_size, // @[rename-busytable.scala:37:14] input io_ren_uops_2_mem_signed, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_fence, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_fencei, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_amo, // @[rename-busytable.scala:37:14] input io_ren_uops_2_uses_ldq, // @[rename-busytable.scala:37:14] input io_ren_uops_2_uses_stq, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_sys_pc2epc, // @[rename-busytable.scala:37:14] input io_ren_uops_2_is_unique, // @[rename-busytable.scala:37:14] input io_ren_uops_2_flush_on_commit, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ldst_is_rs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_2_ldst, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_2_lrs1, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_2_lrs2, // @[rename-busytable.scala:37:14] input [5:0] io_ren_uops_2_lrs3, // @[rename-busytable.scala:37:14] input io_ren_uops_2_ldst_val, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_dst_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_lrs1_rtype, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_lrs2_rtype, // @[rename-busytable.scala:37:14] input io_ren_uops_2_frs3_en, // @[rename-busytable.scala:37:14] input io_ren_uops_2_fp_val, // @[rename-busytable.scala:37:14] input io_ren_uops_2_fp_single, // @[rename-busytable.scala:37:14] input io_ren_uops_2_xcpt_pf_if, // @[rename-busytable.scala:37:14] input io_ren_uops_2_xcpt_ae_if, // @[rename-busytable.scala:37:14] input io_ren_uops_2_xcpt_ma_if, // @[rename-busytable.scala:37:14] input io_ren_uops_2_bp_debug_if, // @[rename-busytable.scala:37:14] input io_ren_uops_2_bp_xcpt_if, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_debug_fsrc, // @[rename-busytable.scala:37:14] input [1:0] io_ren_uops_2_debug_tsrc, // @[rename-busytable.scala:37:14] output io_busy_resps_0_prs1_busy, // @[rename-busytable.scala:37:14] output io_busy_resps_0_prs2_busy, // @[rename-busytable.scala:37:14] output io_busy_resps_1_prs1_busy, // @[rename-busytable.scala:37:14] output io_busy_resps_1_prs2_busy, // @[rename-busytable.scala:37:14] output io_busy_resps_2_prs1_busy, // @[rename-busytable.scala:37:14] output io_busy_resps_2_prs2_busy, // @[rename-busytable.scala:37:14] input io_rebusy_reqs_0, // @[rename-busytable.scala:37:14] input io_rebusy_reqs_1, // @[rename-busytable.scala:37:14] input io_rebusy_reqs_2, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_0, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_1, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_2, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_3, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_4, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_5, // @[rename-busytable.scala:37:14] input [6:0] io_wb_pdsts_6, // @[rename-busytable.scala:37:14] input io_wb_valids_0, // @[rename-busytable.scala:37:14] input io_wb_valids_1, // @[rename-busytable.scala:37:14] input io_wb_valids_2, // @[rename-busytable.scala:37:14] input io_wb_valids_3, // @[rename-busytable.scala:37:14] input io_wb_valids_4, // @[rename-busytable.scala:37:14] input io_wb_valids_5, // @[rename-busytable.scala:37:14] input io_wb_valids_6, // @[rename-busytable.scala:37:14] output [99:0] io_debug_busytable // @[rename-busytable.scala:37:14] ); wire [6:0] io_ren_uops_0_uopc_0 = io_ren_uops_0_uopc; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_0_inst_0 = io_ren_uops_0_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_0_debug_inst_0 = io_ren_uops_0_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_rvc_0 = io_ren_uops_0_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_0_debug_pc_0 = io_ren_uops_0_debug_pc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_iq_type_0 = io_ren_uops_0_iq_type; // @[rename-busytable.scala:27:7] wire [9:0] io_ren_uops_0_fu_code_0 = io_ren_uops_0_fu_code; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_ctrl_br_type_0 = io_ren_uops_0_ctrl_br_type; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_ctrl_op1_sel_0 = io_ren_uops_0_ctrl_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_ctrl_op2_sel_0 = io_ren_uops_0_ctrl_op2_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_ctrl_imm_sel_0 = io_ren_uops_0_ctrl_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ctrl_op_fcn_0 = io_ren_uops_0_ctrl_op_fcn; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ctrl_fcn_dw_0 = io_ren_uops_0_ctrl_fcn_dw; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_ctrl_csr_cmd_0 = io_ren_uops_0_ctrl_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ctrl_is_load_0 = io_ren_uops_0_ctrl_is_load; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ctrl_is_sta_0 = io_ren_uops_0_ctrl_is_sta; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ctrl_is_std_0 = io_ren_uops_0_ctrl_is_std; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_iw_state_0 = io_ren_uops_0_iw_state; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p1_poisoned_0 = io_ren_uops_0_iw_p1_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p2_poisoned_0 = io_ren_uops_0_iw_p2_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_br_0 = io_ren_uops_0_is_br; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_jalr_0 = io_ren_uops_0_is_jalr; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_jal_0 = io_ren_uops_0_is_jal; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sfb_0 = io_ren_uops_0_is_sfb; // @[rename-busytable.scala:27:7] wire [15:0] io_ren_uops_0_br_mask_0 = io_ren_uops_0_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_br_tag_0 = io_ren_uops_0_br_tag; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ftq_idx_0 = io_ren_uops_0_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_edge_inst_0 = io_ren_uops_0_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_pc_lob_0 = io_ren_uops_0_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_taken_0 = io_ren_uops_0_taken; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_0_imm_packed_0 = io_ren_uops_0_imm_packed; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_0_csr_addr_0 = io_ren_uops_0_csr_addr; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_rob_idx_0 = io_ren_uops_0_rob_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ldq_idx_0 = io_ren_uops_0_ldq_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_stq_idx_0 = io_ren_uops_0_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_rxq_idx_0 = io_ren_uops_0_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_pdst_0 = io_ren_uops_0_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs1_0 = io_ren_uops_0_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs2_0 = io_ren_uops_0_prs2; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ppred_0 = io_ren_uops_0_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs1_busy_0 = io_ren_uops_0_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs2_busy_0 = io_ren_uops_0_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ppred_busy_0 = io_ren_uops_0_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_stale_pdst_0 = io_ren_uops_0_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_exception_0 = io_ren_uops_0_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_0_exc_cause_0 = io_ren_uops_0_exc_cause; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bypassable_0 = io_ren_uops_0_bypassable; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_mem_cmd_0 = io_ren_uops_0_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_mem_size_0 = io_ren_uops_0_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_mem_signed_0 = io_ren_uops_0_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_fence_0 = io_ren_uops_0_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_fencei_0 = io_ren_uops_0_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_amo_0 = io_ren_uops_0_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_uses_ldq_0 = io_ren_uops_0_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_uses_stq_0 = io_ren_uops_0_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sys_pc2epc_0 = io_ren_uops_0_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_unique_0 = io_ren_uops_0_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_flush_on_commit_0 = io_ren_uops_0_flush_on_commit; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ldst_is_rs1_0 = io_ren_uops_0_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_ldst_0 = io_ren_uops_0_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs1_0 = io_ren_uops_0_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs2_0 = io_ren_uops_0_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs3_0 = io_ren_uops_0_lrs3; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ldst_val_0 = io_ren_uops_0_ldst_val; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_dst_rtype_0 = io_ren_uops_0_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_lrs1_rtype_0 = io_ren_uops_0_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_lrs2_rtype_0 = io_ren_uops_0_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_frs3_en_0 = io_ren_uops_0_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_val_0 = io_ren_uops_0_fp_val; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_single_0 = io_ren_uops_0_fp_single; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_pf_if_0 = io_ren_uops_0_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_ae_if_0 = io_ren_uops_0_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_ma_if_0 = io_ren_uops_0_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bp_debug_if_0 = io_ren_uops_0_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bp_xcpt_if_0 = io_ren_uops_0_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_debug_fsrc_0 = io_ren_uops_0_debug_fsrc; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_debug_tsrc_0 = io_ren_uops_0_debug_tsrc; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_uopc_0 = io_ren_uops_1_uopc; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_1_inst_0 = io_ren_uops_1_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_1_debug_inst_0 = io_ren_uops_1_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_rvc_0 = io_ren_uops_1_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_1_debug_pc_0 = io_ren_uops_1_debug_pc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_iq_type_0 = io_ren_uops_1_iq_type; // @[rename-busytable.scala:27:7] wire [9:0] io_ren_uops_1_fu_code_0 = io_ren_uops_1_fu_code; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_ctrl_br_type_0 = io_ren_uops_1_ctrl_br_type; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_ctrl_op1_sel_0 = io_ren_uops_1_ctrl_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_ctrl_op2_sel_0 = io_ren_uops_1_ctrl_op2_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_ctrl_imm_sel_0 = io_ren_uops_1_ctrl_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ctrl_op_fcn_0 = io_ren_uops_1_ctrl_op_fcn; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ctrl_fcn_dw_0 = io_ren_uops_1_ctrl_fcn_dw; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_ctrl_csr_cmd_0 = io_ren_uops_1_ctrl_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ctrl_is_load_0 = io_ren_uops_1_ctrl_is_load; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ctrl_is_sta_0 = io_ren_uops_1_ctrl_is_sta; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ctrl_is_std_0 = io_ren_uops_1_ctrl_is_std; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_iw_state_0 = io_ren_uops_1_iw_state; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p1_poisoned_0 = io_ren_uops_1_iw_p1_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p2_poisoned_0 = io_ren_uops_1_iw_p2_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_br_0 = io_ren_uops_1_is_br; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_jalr_0 = io_ren_uops_1_is_jalr; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_jal_0 = io_ren_uops_1_is_jal; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sfb_0 = io_ren_uops_1_is_sfb; // @[rename-busytable.scala:27:7] wire [15:0] io_ren_uops_1_br_mask_0 = io_ren_uops_1_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_br_tag_0 = io_ren_uops_1_br_tag; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ftq_idx_0 = io_ren_uops_1_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_edge_inst_0 = io_ren_uops_1_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_pc_lob_0 = io_ren_uops_1_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_taken_0 = io_ren_uops_1_taken; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_1_imm_packed_0 = io_ren_uops_1_imm_packed; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_1_csr_addr_0 = io_ren_uops_1_csr_addr; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_rob_idx_0 = io_ren_uops_1_rob_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ldq_idx_0 = io_ren_uops_1_ldq_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_stq_idx_0 = io_ren_uops_1_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_rxq_idx_0 = io_ren_uops_1_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_pdst_0 = io_ren_uops_1_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs1_0 = io_ren_uops_1_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs2_0 = io_ren_uops_1_prs2; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ppred_0 = io_ren_uops_1_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs1_busy_0 = io_ren_uops_1_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs2_busy_0 = io_ren_uops_1_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ppred_busy_0 = io_ren_uops_1_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_stale_pdst_0 = io_ren_uops_1_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_exception_0 = io_ren_uops_1_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_1_exc_cause_0 = io_ren_uops_1_exc_cause; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bypassable_0 = io_ren_uops_1_bypassable; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_mem_cmd_0 = io_ren_uops_1_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_mem_size_0 = io_ren_uops_1_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_mem_signed_0 = io_ren_uops_1_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_fence_0 = io_ren_uops_1_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_fencei_0 = io_ren_uops_1_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_amo_0 = io_ren_uops_1_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_uses_ldq_0 = io_ren_uops_1_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_uses_stq_0 = io_ren_uops_1_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sys_pc2epc_0 = io_ren_uops_1_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_unique_0 = io_ren_uops_1_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_flush_on_commit_0 = io_ren_uops_1_flush_on_commit; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ldst_is_rs1_0 = io_ren_uops_1_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_ldst_0 = io_ren_uops_1_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs1_0 = io_ren_uops_1_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs2_0 = io_ren_uops_1_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs3_0 = io_ren_uops_1_lrs3; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ldst_val_0 = io_ren_uops_1_ldst_val; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_dst_rtype_0 = io_ren_uops_1_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_lrs1_rtype_0 = io_ren_uops_1_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_lrs2_rtype_0 = io_ren_uops_1_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_frs3_en_0 = io_ren_uops_1_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_val_0 = io_ren_uops_1_fp_val; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_single_0 = io_ren_uops_1_fp_single; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_pf_if_0 = io_ren_uops_1_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_ae_if_0 = io_ren_uops_1_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_ma_if_0 = io_ren_uops_1_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bp_debug_if_0 = io_ren_uops_1_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bp_xcpt_if_0 = io_ren_uops_1_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_debug_fsrc_0 = io_ren_uops_1_debug_fsrc; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_debug_tsrc_0 = io_ren_uops_1_debug_tsrc; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_uopc_0 = io_ren_uops_2_uopc; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_2_inst_0 = io_ren_uops_2_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_2_debug_inst_0 = io_ren_uops_2_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_rvc_0 = io_ren_uops_2_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_2_debug_pc_0 = io_ren_uops_2_debug_pc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_2_iq_type_0 = io_ren_uops_2_iq_type; // @[rename-busytable.scala:27:7] wire [9:0] io_ren_uops_2_fu_code_0 = io_ren_uops_2_fu_code; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_2_ctrl_br_type_0 = io_ren_uops_2_ctrl_br_type; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_ctrl_op1_sel_0 = io_ren_uops_2_ctrl_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_2_ctrl_op2_sel_0 = io_ren_uops_2_ctrl_op2_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_2_ctrl_imm_sel_0 = io_ren_uops_2_ctrl_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_ctrl_op_fcn_0 = io_ren_uops_2_ctrl_op_fcn; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ctrl_fcn_dw_0 = io_ren_uops_2_ctrl_fcn_dw; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_2_ctrl_csr_cmd_0 = io_ren_uops_2_ctrl_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ctrl_is_load_0 = io_ren_uops_2_ctrl_is_load; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ctrl_is_sta_0 = io_ren_uops_2_ctrl_is_sta; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ctrl_is_std_0 = io_ren_uops_2_ctrl_is_std; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_iw_state_0 = io_ren_uops_2_iw_state; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_iw_p1_poisoned_0 = io_ren_uops_2_iw_p1_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_iw_p2_poisoned_0 = io_ren_uops_2_iw_p2_poisoned; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_br_0 = io_ren_uops_2_is_br; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_jalr_0 = io_ren_uops_2_is_jalr; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_jal_0 = io_ren_uops_2_is_jal; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_sfb_0 = io_ren_uops_2_is_sfb; // @[rename-busytable.scala:27:7] wire [15:0] io_ren_uops_2_br_mask_0 = io_ren_uops_2_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_2_br_tag_0 = io_ren_uops_2_br_tag; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_ftq_idx_0 = io_ren_uops_2_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_edge_inst_0 = io_ren_uops_2_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_2_pc_lob_0 = io_ren_uops_2_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_taken_0 = io_ren_uops_2_taken; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_2_imm_packed_0 = io_ren_uops_2_imm_packed; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_2_csr_addr_0 = io_ren_uops_2_csr_addr; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_rob_idx_0 = io_ren_uops_2_rob_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_ldq_idx_0 = io_ren_uops_2_ldq_idx; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_stq_idx_0 = io_ren_uops_2_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_rxq_idx_0 = io_ren_uops_2_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_pdst_0 = io_ren_uops_2_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_prs1_0 = io_ren_uops_2_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_prs2_0 = io_ren_uops_2_prs2; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_ppred_0 = io_ren_uops_2_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_prs1_busy_0 = io_ren_uops_2_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_prs2_busy_0 = io_ren_uops_2_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ppred_busy_0 = io_ren_uops_2_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_2_stale_pdst_0 = io_ren_uops_2_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_exception_0 = io_ren_uops_2_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_2_exc_cause_0 = io_ren_uops_2_exc_cause; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_bypassable_0 = io_ren_uops_2_bypassable; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_2_mem_cmd_0 = io_ren_uops_2_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_mem_size_0 = io_ren_uops_2_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_mem_signed_0 = io_ren_uops_2_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_fence_0 = io_ren_uops_2_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_fencei_0 = io_ren_uops_2_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_amo_0 = io_ren_uops_2_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_uses_ldq_0 = io_ren_uops_2_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_uses_stq_0 = io_ren_uops_2_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_sys_pc2epc_0 = io_ren_uops_2_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_is_unique_0 = io_ren_uops_2_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_flush_on_commit_0 = io_ren_uops_2_flush_on_commit; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ldst_is_rs1_0 = io_ren_uops_2_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_2_ldst_0 = io_ren_uops_2_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_2_lrs1_0 = io_ren_uops_2_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_2_lrs2_0 = io_ren_uops_2_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_2_lrs3_0 = io_ren_uops_2_lrs3; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_ldst_val_0 = io_ren_uops_2_ldst_val; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_dst_rtype_0 = io_ren_uops_2_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_lrs1_rtype_0 = io_ren_uops_2_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_lrs2_rtype_0 = io_ren_uops_2_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_frs3_en_0 = io_ren_uops_2_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_fp_val_0 = io_ren_uops_2_fp_val; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_fp_single_0 = io_ren_uops_2_fp_single; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_xcpt_pf_if_0 = io_ren_uops_2_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_xcpt_ae_if_0 = io_ren_uops_2_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_xcpt_ma_if_0 = io_ren_uops_2_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_bp_debug_if_0 = io_ren_uops_2_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_bp_xcpt_if_0 = io_ren_uops_2_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_debug_fsrc_0 = io_ren_uops_2_debug_fsrc; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_2_debug_tsrc_0 = io_ren_uops_2_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_0_0 = io_rebusy_reqs_0; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_1_0 = io_rebusy_reqs_1; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_2_0 = io_rebusy_reqs_2; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_0_0 = io_wb_pdsts_0; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_1_0 = io_wb_pdsts_1; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_2_0 = io_wb_pdsts_2; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_3_0 = io_wb_pdsts_3; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_4_0 = io_wb_pdsts_4; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_5_0 = io_wb_pdsts_5; // @[rename-busytable.scala:27:7] wire [6:0] io_wb_pdsts_6_0 = io_wb_pdsts_6; // @[rename-busytable.scala:27:7] wire io_wb_valids_0_0 = io_wb_valids_0; // @[rename-busytable.scala:27:7] wire io_wb_valids_1_0 = io_wb_valids_1; // @[rename-busytable.scala:27:7] wire io_wb_valids_2_0 = io_wb_valids_2; // @[rename-busytable.scala:27:7] wire io_wb_valids_3_0 = io_wb_valids_3; // @[rename-busytable.scala:27:7] wire io_wb_valids_4_0 = io_wb_valids_4; // @[rename-busytable.scala:27:7] wire io_wb_valids_5_0 = io_wb_valids_5; // @[rename-busytable.scala:27:7] wire io_wb_valids_6_0 = io_wb_valids_6; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_ren_uops_2_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_busy_resps_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_busy_resps_2_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire _io_busy_resps_0_prs1_busy_T_2 = 1'h0; // @[rename-busytable.scala:67:88] wire _io_busy_resps_0_prs2_busy_T_2 = 1'h0; // @[rename-busytable.scala:68:88] wire _io_busy_resps_0_prs3_busy_T_2 = 1'h0; // @[rename-busytable.scala:69:88] wire _io_busy_resps_1_prs1_busy_T_2 = 1'h0; // @[rename-busytable.scala:67:88] wire _io_busy_resps_1_prs2_busy_T_2 = 1'h0; // @[rename-busytable.scala:68:88] wire _io_busy_resps_1_prs3_busy_T_2 = 1'h0; // @[rename-busytable.scala:69:88] wire _io_busy_resps_2_prs1_busy_T_2 = 1'h0; // @[rename-busytable.scala:67:88] wire _io_busy_resps_2_prs2_busy_T_2 = 1'h0; // @[rename-busytable.scala:68:88] wire _io_busy_resps_2_prs3_busy_T_2 = 1'h0; // @[rename-busytable.scala:69:88] wire [6:0] io_ren_uops_0_prs3 = 7'h0; // @[rename-busytable.scala:27:7, :37:14] wire [6:0] io_ren_uops_1_prs3 = 7'h0; // @[rename-busytable.scala:27:7, :37:14] wire [6:0] io_ren_uops_2_prs3 = 7'h0; // @[rename-busytable.scala:27:7, :37:14] wire _io_busy_resps_0_prs1_busy_T_3; // @[rename-busytable.scala:67:67] wire _io_busy_resps_0_prs2_busy_T_3; // @[rename-busytable.scala:68:67] wire _io_busy_resps_1_prs1_busy_T_3; // @[rename-busytable.scala:67:67] wire _io_busy_resps_1_prs2_busy_T_3; // @[rename-busytable.scala:68:67] wire _io_busy_resps_2_prs1_busy_T_3; // @[rename-busytable.scala:67:67] wire _io_busy_resps_2_prs2_busy_T_3; // @[rename-busytable.scala:68:67] wire io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_2_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_2_prs2_busy_0; // @[rename-busytable.scala:27:7] wire [99:0] io_debug_busytable_0; // @[rename-busytable.scala:27:7] reg [99:0] busy_table; // @[rename-busytable.scala:48:27] assign io_debug_busytable_0 = busy_table; // @[rename-busytable.scala:27:7, :48:27] wire [99:0] _io_busy_resps_0_prs3_busy_T = busy_table; // @[rename-busytable.scala:48:27, :69:45] wire [99:0] _io_busy_resps_1_prs3_busy_T = busy_table; // @[rename-busytable.scala:48:27, :69:45] wire [99:0] _io_busy_resps_2_prs3_busy_T = busy_table; // @[rename-busytable.scala:48:27, :69:45] wire [127:0] _busy_table_wb_T = 128'h1 << io_wb_pdsts_0_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_1 = {100{io_wb_valids_0_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_2 = {28'h0, _busy_table_wb_T[99:0] & _busy_table_wb_T_1}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_3 = 128'h1 << io_wb_pdsts_1_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_4 = {100{io_wb_valids_1_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_5 = {28'h0, _busy_table_wb_T_3[99:0] & _busy_table_wb_T_4}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_6 = 128'h1 << io_wb_pdsts_2_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_7 = {100{io_wb_valids_2_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_8 = {28'h0, _busy_table_wb_T_6[99:0] & _busy_table_wb_T_7}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_9 = 128'h1 << io_wb_pdsts_3_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_10 = {100{io_wb_valids_3_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_11 = {28'h0, _busy_table_wb_T_9[99:0] & _busy_table_wb_T_10}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_12 = 128'h1 << io_wb_pdsts_4_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_13 = {100{io_wb_valids_4_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_14 = {28'h0, _busy_table_wb_T_12[99:0] & _busy_table_wb_T_13}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_15 = 128'h1 << io_wb_pdsts_5_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_16 = {100{io_wb_valids_5_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_17 = {28'h0, _busy_table_wb_T_15[99:0] & _busy_table_wb_T_16}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_18 = 128'h1 << io_wb_pdsts_6_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_wb_T_19 = {100{io_wb_valids_6_0}}; // @[rename-busytable.scala:27:7, :51:54] wire [127:0] _busy_table_wb_T_20 = {28'h0, _busy_table_wb_T_18[99:0] & _busy_table_wb_T_19}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_21 = _busy_table_wb_T_2 | _busy_table_wb_T_5; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_22 = _busy_table_wb_T_21 | _busy_table_wb_T_8; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_23 = _busy_table_wb_T_22 | _busy_table_wb_T_11; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_24 = _busy_table_wb_T_23 | _busy_table_wb_T_14; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_25 = _busy_table_wb_T_24 | _busy_table_wb_T_17; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_26 = _busy_table_wb_T_25 | _busy_table_wb_T_20; // @[rename-busytable.scala:51:{48,88}] wire [127:0] _busy_table_wb_T_27 = ~_busy_table_wb_T_26; // @[rename-busytable.scala:50:36, :51:88] wire [127:0] busy_table_wb = {28'h0, _busy_table_wb_T_27[99:0] & busy_table}; // @[rename-busytable.scala:48:27, :50:{34,36}, :51:48] wire [127:0] _busy_table_next_T = 128'h1 << io_ren_uops_0_pdst_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_next_T_1 = {100{io_rebusy_reqs_0_0}}; // @[rename-busytable.scala:27:7, :54:55] wire [127:0] _busy_table_next_T_2 = {28'h0, _busy_table_next_T[99:0] & _busy_table_next_T_1}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_3 = 128'h1 << io_ren_uops_1_pdst_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_next_T_4 = {100{io_rebusy_reqs_1_0}}; // @[rename-busytable.scala:27:7, :54:55] wire [127:0] _busy_table_next_T_5 = {28'h0, _busy_table_next_T_3[99:0] & _busy_table_next_T_4}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_6 = 128'h1 << io_ren_uops_2_pdst_0; // @[OneHot.scala:58:35] wire [99:0] _busy_table_next_T_7 = {100{io_rebusy_reqs_2_0}}; // @[rename-busytable.scala:27:7, :54:55] wire [127:0] _busy_table_next_T_8 = {28'h0, _busy_table_next_T_6[99:0] & _busy_table_next_T_7}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_9 = _busy_table_next_T_2 | _busy_table_next_T_5; // @[rename-busytable.scala:54:{49,87}] wire [127:0] _busy_table_next_T_10 = _busy_table_next_T_9 | _busy_table_next_T_8; // @[rename-busytable.scala:54:{49,87}] wire [127:0] busy_table_next = busy_table_wb | _busy_table_next_T_10; // @[rename-busytable.scala:50:34, :53:39, :54:87] wire [99:0] _io_busy_resps_0_prs1_busy_T = busy_table >> io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :48:27, :67:45] wire _io_busy_resps_0_prs1_busy_T_1 = _io_busy_resps_0_prs1_busy_T[0]; // @[rename-busytable.scala:67:45] assign _io_busy_resps_0_prs1_busy_T_3 = _io_busy_resps_0_prs1_busy_T_1; // @[rename-busytable.scala:67:{45,67}] assign io_busy_resps_0_prs1_busy_0 = _io_busy_resps_0_prs1_busy_T_3; // @[rename-busytable.scala:27:7, :67:67] wire [99:0] _io_busy_resps_0_prs2_busy_T = busy_table >> io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :48:27, :68:45] wire _io_busy_resps_0_prs2_busy_T_1 = _io_busy_resps_0_prs2_busy_T[0]; // @[rename-busytable.scala:68:45] assign _io_busy_resps_0_prs2_busy_T_3 = _io_busy_resps_0_prs2_busy_T_1; // @[rename-busytable.scala:68:{45,67}] assign io_busy_resps_0_prs2_busy_0 = _io_busy_resps_0_prs2_busy_T_3; // @[rename-busytable.scala:27:7, :68:67] wire _io_busy_resps_0_prs3_busy_T_1 = _io_busy_resps_0_prs3_busy_T[0]; // @[rename-busytable.scala:69:45] wire _io_busy_resps_0_prs3_busy_T_3 = _io_busy_resps_0_prs3_busy_T_1; // @[rename-busytable.scala:69:{45,67}] wire _prs1_was_bypassed_T = io_ren_uops_1_lrs1_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :61:27] wire _prs1_was_bypassed_T_1 = _prs1_was_bypassed_T & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :61:{27,51}] wire prs1_was_bypassed = _prs1_was_bypassed_T_1; // @[rename-busytable.scala:61:{51,92}] wire _prs2_was_bypassed_T = io_ren_uops_1_lrs2_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :63:27] wire _prs2_was_bypassed_T_1 = _prs2_was_bypassed_T & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :63:{27,51}] wire prs2_was_bypassed = _prs2_was_bypassed_T_1; // @[rename-busytable.scala:63:{51,92}] wire _prs3_was_bypassed_T = io_ren_uops_1_lrs3_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :65:27] wire _prs3_was_bypassed_T_1 = _prs3_was_bypassed_T & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :65:{27,51}] wire prs3_was_bypassed = _prs3_was_bypassed_T_1; // @[rename-busytable.scala:65:{51,92}] wire [99:0] _io_busy_resps_1_prs1_busy_T = busy_table >> io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :48:27, :67:45] wire _io_busy_resps_1_prs1_busy_T_1 = _io_busy_resps_1_prs1_busy_T[0]; // @[rename-busytable.scala:67:45] assign _io_busy_resps_1_prs1_busy_T_3 = _io_busy_resps_1_prs1_busy_T_1; // @[rename-busytable.scala:67:{45,67}] assign io_busy_resps_1_prs1_busy_0 = _io_busy_resps_1_prs1_busy_T_3; // @[rename-busytable.scala:27:7, :67:67] wire [99:0] _io_busy_resps_1_prs2_busy_T = busy_table >> io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :48:27, :68:45] wire _io_busy_resps_1_prs2_busy_T_1 = _io_busy_resps_1_prs2_busy_T[0]; // @[rename-busytable.scala:68:45] assign _io_busy_resps_1_prs2_busy_T_3 = _io_busy_resps_1_prs2_busy_T_1; // @[rename-busytable.scala:68:{45,67}] assign io_busy_resps_1_prs2_busy_0 = _io_busy_resps_1_prs2_busy_T_3; // @[rename-busytable.scala:27:7, :68:67] wire _io_busy_resps_1_prs3_busy_T_1 = _io_busy_resps_1_prs3_busy_T[0]; // @[rename-busytable.scala:69:45] wire _io_busy_resps_1_prs3_busy_T_3 = _io_busy_resps_1_prs3_busy_T_1; // @[rename-busytable.scala:69:{45,67}] wire _prs1_was_bypassed_T_2 = io_ren_uops_2_lrs1_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :61:27] wire _prs1_was_bypassed_T_3 = _prs1_was_bypassed_T_2 & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :61:{27,51}] wire _prs1_was_bypassed_T_6 = _prs1_was_bypassed_T_3; // @[rename-busytable.scala:61:{51,92}] wire _prs1_was_bypassed_T_4 = io_ren_uops_2_lrs1_0 == io_ren_uops_1_ldst_0; // @[rename-busytable.scala:27:7, :61:27] wire _prs1_was_bypassed_T_5 = _prs1_was_bypassed_T_4 & io_rebusy_reqs_1_0; // @[rename-busytable.scala:27:7, :61:{27,51}] wire prs1_was_bypassed_1 = _prs1_was_bypassed_T_6 | _prs1_was_bypassed_T_5; // @[rename-busytable.scala:61:{51,92}] wire _prs2_was_bypassed_T_2 = io_ren_uops_2_lrs2_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :63:27] wire _prs2_was_bypassed_T_3 = _prs2_was_bypassed_T_2 & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :63:{27,51}] wire _prs2_was_bypassed_T_6 = _prs2_was_bypassed_T_3; // @[rename-busytable.scala:63:{51,92}] wire _prs2_was_bypassed_T_4 = io_ren_uops_2_lrs2_0 == io_ren_uops_1_ldst_0; // @[rename-busytable.scala:27:7, :63:27] wire _prs2_was_bypassed_T_5 = _prs2_was_bypassed_T_4 & io_rebusy_reqs_1_0; // @[rename-busytable.scala:27:7, :63:{27,51}] wire prs2_was_bypassed_1 = _prs2_was_bypassed_T_6 | _prs2_was_bypassed_T_5; // @[rename-busytable.scala:63:{51,92}] wire _prs3_was_bypassed_T_2 = io_ren_uops_2_lrs3_0 == io_ren_uops_0_ldst_0; // @[rename-busytable.scala:27:7, :65:27] wire _prs3_was_bypassed_T_3 = _prs3_was_bypassed_T_2 & io_rebusy_reqs_0_0; // @[rename-busytable.scala:27:7, :65:{27,51}] wire _prs3_was_bypassed_T_6 = _prs3_was_bypassed_T_3; // @[rename-busytable.scala:65:{51,92}] wire _prs3_was_bypassed_T_4 = io_ren_uops_2_lrs3_0 == io_ren_uops_1_ldst_0; // @[rename-busytable.scala:27:7, :65:27] wire _prs3_was_bypassed_T_5 = _prs3_was_bypassed_T_4 & io_rebusy_reqs_1_0; // @[rename-busytable.scala:27:7, :65:{27,51}] wire prs3_was_bypassed_1 = _prs3_was_bypassed_T_6 | _prs3_was_bypassed_T_5; // @[rename-busytable.scala:65:{51,92}] wire [99:0] _io_busy_resps_2_prs1_busy_T = busy_table >> io_ren_uops_2_prs1_0; // @[rename-busytable.scala:27:7, :48:27, :67:45] wire _io_busy_resps_2_prs1_busy_T_1 = _io_busy_resps_2_prs1_busy_T[0]; // @[rename-busytable.scala:67:45] assign _io_busy_resps_2_prs1_busy_T_3 = _io_busy_resps_2_prs1_busy_T_1; // @[rename-busytable.scala:67:{45,67}] assign io_busy_resps_2_prs1_busy_0 = _io_busy_resps_2_prs1_busy_T_3; // @[rename-busytable.scala:27:7, :67:67] wire [99:0] _io_busy_resps_2_prs2_busy_T = busy_table >> io_ren_uops_2_prs2_0; // @[rename-busytable.scala:27:7, :48:27, :68:45] wire _io_busy_resps_2_prs2_busy_T_1 = _io_busy_resps_2_prs2_busy_T[0]; // @[rename-busytable.scala:68:45] assign _io_busy_resps_2_prs2_busy_T_3 = _io_busy_resps_2_prs2_busy_T_1; // @[rename-busytable.scala:68:{45,67}] assign io_busy_resps_2_prs2_busy_0 = _io_busy_resps_2_prs2_busy_T_3; // @[rename-busytable.scala:27:7, :68:67] wire _io_busy_resps_2_prs3_busy_T_1 = _io_busy_resps_2_prs3_busy_T[0]; // @[rename-busytable.scala:69:45] wire _io_busy_resps_2_prs3_busy_T_3 = _io_busy_resps_2_prs3_busy_T_1; // @[rename-busytable.scala:69:{45,67}] always @(posedge clock) begin // @[rename-busytable.scala:27:7] if (reset) // @[rename-busytable.scala:27:7] busy_table <= 100'h0; // @[rename-busytable.scala:48:27] else // @[rename-busytable.scala:27:7] busy_table <= busy_table_next[99:0]; // @[rename-busytable.scala:48:27, :53:39, :56:14] always @(posedge) assign io_busy_resps_0_prs1_busy = io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_0_prs2_busy = io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_1_prs1_busy = io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_1_prs2_busy = io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_2_prs1_busy = io_busy_resps_2_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_2_prs2_busy = io_busy_resps_2_prs2_busy_0; // @[rename-busytable.scala:27:7] assign io_debug_busytable = io_debug_busytable_0; // @[rename-busytable.scala:27:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }

module EgressUnit_31( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [36:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [36:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30]

Generate the Verilog code corresponding to the following Chisel files. File ShiftQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ /** Implements the same interface as chisel3.util.Queue, but uses a shift * register internally. It is less energy efficient whenever the queue * has more than one entry populated, but is faster on the dequeue side. * It is efficient for usually-empty flow-through queues. */ class ShiftQueue[T <: Data](gen: T, val entries: Int, pipe: Boolean = false, flow: Boolean = false) extends Module { val io = IO(new QueueIO(gen, entries) { val mask = Output(UInt(entries.W)) }) private val valid = RegInit(VecInit(Seq.fill(entries) { false.B })) private val elts = Reg(Vec(entries, gen)) for (i <- 0 until entries) { def paddedValid(i: Int) = if (i == -1) true.B else if (i == entries) false.B else valid(i) val wdata = if (i == entries-1) io.enq.bits else Mux(valid(i+1), elts(i+1), io.enq.bits) val wen = Mux(io.deq.ready, paddedValid(i+1) || io.enq.fire && ((i == 0 && !flow).B || valid(i)), io.enq.fire && paddedValid(i-1) && !valid(i)) when (wen) { elts(i) := wdata } valid(i) := Mux(io.deq.ready, paddedValid(i+1) || io.enq.fire && ((i == 0 && !flow).B || valid(i)), io.enq.fire && paddedValid(i-1) || valid(i)) } io.enq.ready := !valid(entries-1) io.deq.valid := valid(0) io.deq.bits := elts.head if (flow) { when (io.enq.valid) { io.deq.valid := true.B } when (!valid(0)) { io.deq.bits := io.enq.bits } } if (pipe) { when (io.deq.ready) { io.enq.ready := true.B } } io.mask := valid.asUInt io.count := PopCount(io.mask) } object ShiftQueue { def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false, flow: Boolean = false): DecoupledIO[T] = { val q = Module(new ShiftQueue(enq.bits.cloneType, entries, pipe, flow)) q.io.enq <> enq q.io.deq } }

module ShiftQueue( // @[ShiftQueue.scala:12:7] input clock, // @[ShiftQueue.scala:12:7] input reset, // @[ShiftQueue.scala:12:7] output io_enq_ready, // @[ShiftQueue.scala:17:14] input io_enq_valid, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_taken, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] input [47:0] io_enq_bits_btb_target, // @[ShiftQueue.scala:17:14] input [4:0] io_enq_bits_btb_entry, // @[ShiftQueue.scala:17:14] input [7:0] io_enq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] input [48:0] io_enq_bits_pc, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_data, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_replay, // @[ShiftQueue.scala:17:14] input io_deq_ready, // @[ShiftQueue.scala:17:14] output io_deq_valid, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_taken, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] output [47:0] io_deq_bits_btb_target, // @[ShiftQueue.scala:17:14] output [4:0] io_deq_bits_btb_entry, // @[ShiftQueue.scala:17:14] output [7:0] io_deq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] output [48:0] io_deq_bits_pc, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_data, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_gf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_replay, // @[ShiftQueue.scala:17:14] output [4:0] io_mask // @[ShiftQueue.scala:17:14] ); wire io_enq_valid_0 = io_enq_valid; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_cfiType_0 = io_enq_bits_btb_cfiType; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_taken_0 = io_enq_bits_btb_taken; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_mask_0 = io_enq_bits_btb_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bridx_0 = io_enq_bits_btb_bridx; // @[ShiftQueue.scala:12:7] wire [47:0] io_enq_bits_btb_target_0 = io_enq_bits_btb_target; // @[ShiftQueue.scala:12:7] wire [4:0] io_enq_bits_btb_entry_0 = io_enq_bits_btb_entry; // @[ShiftQueue.scala:12:7] wire [7:0] io_enq_bits_btb_bht_history_0 = io_enq_bits_btb_bht_history; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bht_value_0 = io_enq_bits_btb_bht_value; // @[ShiftQueue.scala:12:7] wire [48:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_data_0 = io_enq_bits_data; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_pf_inst_0 = io_enq_bits_xcpt_pf_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_ae_inst_0 = io_enq_bits_xcpt_ae_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_replay_0 = io_enq_bits_replay; // @[ShiftQueue.scala:12:7] wire io_deq_ready_0 = io_deq_ready; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_gf_inst = 1'h0; // @[ShiftQueue.scala:12:7] wire _valid_WIRE_0 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_1 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_2 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_3 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_4 = 1'h0; // @[ShiftQueue.scala:21:38] wire _io_enq_ready_T; // @[ShiftQueue.scala:40:19] wire [2:0] _io_count_T_12; // @[ShiftQueue.scala:54:23] wire [4:0] _io_mask_T; // @[ShiftQueue.scala:53:20] wire io_enq_ready_0; // @[ShiftQueue.scala:12:7] wire [7:0] io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] wire [47:0] io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] wire [4:0] io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] wire [48:0] io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] wire io_deq_valid_0; // @[ShiftQueue.scala:12:7] wire [2:0] io_count; // @[ShiftQueue.scala:12:7] wire [4:0] io_mask_0; // @[ShiftQueue.scala:12:7] reg valid_0; // @[ShiftQueue.scala:21:30] wire _wen_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_0_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :36:67] reg valid_1; // @[ShiftQueue.scala:21:30] wire _wen_T_9 = valid_1; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_1_T_1 = valid_1; // @[ShiftQueue.scala:21:30, :36:67] reg valid_2; // @[ShiftQueue.scala:21:30] wire _wen_T_17 = valid_2; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_2_T_1 = valid_2; // @[ShiftQueue.scala:21:30, :36:67] reg valid_3; // @[ShiftQueue.scala:21:30] wire _wen_T_25 = valid_3; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_3_T_1 = valid_3; // @[ShiftQueue.scala:21:30, :36:67] reg valid_4; // @[ShiftQueue.scala:21:30] wire _wen_T_33 = valid_4; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_4_T_1 = valid_4; // @[ShiftQueue.scala:21:30, :36:67] reg [1:0] elts_0_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_0_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bridx; // @[ShiftQueue.scala:22:25] reg [47:0] elts_0_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_0_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_0_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [48:0] elts_0_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_mask; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_0_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_1_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bridx; // @[ShiftQueue.scala:22:25] reg [47:0] elts_1_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_1_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_1_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [48:0] elts_1_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_mask; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_1_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_2_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bridx; // @[ShiftQueue.scala:22:25] reg [47:0] elts_2_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_2_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_2_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [48:0] elts_2_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_mask; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_2_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_3_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bridx; // @[ShiftQueue.scala:22:25] reg [47:0] elts_3_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_3_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_3_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [48:0] elts_3_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_mask; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_3_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_4_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bridx; // @[ShiftQueue.scala:22:25] reg [47:0] elts_4_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_4_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_4_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [48:0] elts_4_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_mask; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_4_replay; // @[ShiftQueue.scala:22:25] wire [1:0] wdata_btb_cfiType = valid_1 ? elts_1_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_taken = valid_1 ? elts_1_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_btb_mask = valid_1 ? elts_1_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bridx = valid_1 ? elts_1_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [47:0] wdata_btb_target = valid_1 ? elts_1_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_btb_entry = valid_1 ? elts_1_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_btb_bht_history = valid_1 ? elts_1_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bht_value = valid_1 ? elts_1_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [48:0] wdata_pc = valid_1 ? elts_1_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_data = valid_1 ? elts_1_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_mask = valid_1 ? elts_1_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_pf_inst = valid_1 ? elts_1_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_gf_inst = valid_1 & elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_xcpt_ae_inst = valid_1 ? elts_1_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_replay = valid_1 ? elts_1_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _GEN = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _wen_T; // @[Decoupled.scala:51:35] assign _wen_T = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_4; // @[Decoupled.scala:51:35] assign _wen_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T; // @[Decoupled.scala:51:35] assign _valid_0_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T_4; // @[Decoupled.scala:51:35] assign _valid_0_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_8; // @[Decoupled.scala:51:35] assign _wen_T_8 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_12; // @[Decoupled.scala:51:35] assign _wen_T_12 = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T; // @[Decoupled.scala:51:35] assign _valid_1_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T_4; // @[Decoupled.scala:51:35] assign _valid_1_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_16; // @[Decoupled.scala:51:35] assign _wen_T_16 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_20; // @[Decoupled.scala:51:35] assign _wen_T_20 = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T; // @[Decoupled.scala:51:35] assign _valid_2_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T_4; // @[Decoupled.scala:51:35] assign _valid_2_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_24; // @[Decoupled.scala:51:35] assign _wen_T_24 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_28; // @[Decoupled.scala:51:35] assign _wen_T_28 = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T; // @[Decoupled.scala:51:35] assign _valid_3_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T_4; // @[Decoupled.scala:51:35] assign _valid_3_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_32; // @[Decoupled.scala:51:35] assign _wen_T_32 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_36; // @[Decoupled.scala:51:35] assign _wen_T_36 = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T; // @[Decoupled.scala:51:35] assign _valid_4_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T_4; // @[Decoupled.scala:51:35] assign _valid_4_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Decoupled.scala:51:35] wire _wen_T_3 = valid_1 | _wen_T_2; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_5 = _wen_T_4; // @[Decoupled.scala:51:35] wire _wen_T_6 = ~valid_0; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_7 = _wen_T_5 & _wen_T_6; // @[ShiftQueue.scala:31:{23,43,46}] wire wen = io_deq_ready_0 ? _wen_T_3 : _wen_T_7; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_0_T_2 = _valid_0_T & _valid_0_T_1; // @[Decoupled.scala:51:35] wire _valid_0_T_3 = valid_1 | _valid_0_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_0_T_5 = _valid_0_T_4; // @[Decoupled.scala:51:35] wire _valid_0_T_6 = _valid_0_T_5 | valid_0; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_0_T_7 = io_deq_ready_0 ? _valid_0_T_3 : _valid_0_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_1_btb_cfiType = valid_2 ? elts_2_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_taken = valid_2 ? elts_2_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_btb_mask = valid_2 ? elts_2_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bridx = valid_2 ? elts_2_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [47:0] wdata_1_btb_target = valid_2 ? elts_2_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_1_btb_entry = valid_2 ? elts_2_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_1_btb_bht_history = valid_2 ? elts_2_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bht_value = valid_2 ? elts_2_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [48:0] wdata_1_pc = valid_2 ? elts_2_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_data = valid_2 ? elts_2_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_mask = valid_2 ? elts_2_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_pf_inst = valid_2 ? elts_2_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_gf_inst = valid_2 & elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_1_xcpt_ae_inst = valid_2 ? elts_2_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_replay = valid_2 ? elts_2_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_10 = _wen_T_8 & _wen_T_9; // @[Decoupled.scala:51:35] wire _wen_T_11 = valid_2 | _wen_T_10; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_13 = _wen_T_12 & valid_0; // @[Decoupled.scala:51:35] wire _wen_T_14 = ~valid_1; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_15 = _wen_T_13 & _wen_T_14; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_1 = io_deq_ready_0 ? _wen_T_11 : _wen_T_15; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_1_T_2 = _valid_1_T & _valid_1_T_1; // @[Decoupled.scala:51:35] wire _valid_1_T_3 = valid_2 | _valid_1_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_1_T_5 = _valid_1_T_4 & valid_0; // @[Decoupled.scala:51:35] wire _valid_1_T_6 = _valid_1_T_5 | valid_1; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_1_T_7 = io_deq_ready_0 ? _valid_1_T_3 : _valid_1_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_2_btb_cfiType = valid_3 ? elts_3_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_taken = valid_3 ? elts_3_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_btb_mask = valid_3 ? elts_3_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bridx = valid_3 ? elts_3_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [47:0] wdata_2_btb_target = valid_3 ? elts_3_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_2_btb_entry = valid_3 ? elts_3_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_2_btb_bht_history = valid_3 ? elts_3_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bht_value = valid_3 ? elts_3_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [48:0] wdata_2_pc = valid_3 ? elts_3_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_data = valid_3 ? elts_3_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_mask = valid_3 ? elts_3_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_pf_inst = valid_3 ? elts_3_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_gf_inst = valid_3 & elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_2_xcpt_ae_inst = valid_3 ? elts_3_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_replay = valid_3 ? elts_3_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_18 = _wen_T_16 & _wen_T_17; // @[Decoupled.scala:51:35] wire _wen_T_19 = valid_3 | _wen_T_18; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_21 = _wen_T_20 & valid_1; // @[Decoupled.scala:51:35] wire _wen_T_22 = ~valid_2; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_23 = _wen_T_21 & _wen_T_22; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_2 = io_deq_ready_0 ? _wen_T_19 : _wen_T_23; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_2_T_2 = _valid_2_T & _valid_2_T_1; // @[Decoupled.scala:51:35] wire _valid_2_T_3 = valid_3 | _valid_2_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_2_T_5 = _valid_2_T_4 & valid_1; // @[Decoupled.scala:51:35] wire _valid_2_T_6 = _valid_2_T_5 | valid_2; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_2_T_7 = io_deq_ready_0 ? _valid_2_T_3 : _valid_2_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_3_btb_cfiType = valid_4 ? elts_4_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_taken = valid_4 ? elts_4_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_btb_mask = valid_4 ? elts_4_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bridx = valid_4 ? elts_4_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [47:0] wdata_3_btb_target = valid_4 ? elts_4_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_3_btb_entry = valid_4 ? elts_4_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_3_btb_bht_history = valid_4 ? elts_4_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bht_value = valid_4 ? elts_4_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [48:0] wdata_3_pc = valid_4 ? elts_4_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_data = valid_4 ? elts_4_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_mask = valid_4 ? elts_4_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_pf_inst = valid_4 ? elts_4_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_gf_inst = valid_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_3_xcpt_ae_inst = valid_4 ? elts_4_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_replay = valid_4 ? elts_4_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_26 = _wen_T_24 & _wen_T_25; // @[Decoupled.scala:51:35] wire _wen_T_27 = valid_4 | _wen_T_26; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_29 = _wen_T_28 & valid_2; // @[Decoupled.scala:51:35] wire _wen_T_30 = ~valid_3; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_31 = _wen_T_29 & _wen_T_30; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_3 = io_deq_ready_0 ? _wen_T_27 : _wen_T_31; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_3_T_2 = _valid_3_T & _valid_3_T_1; // @[Decoupled.scala:51:35] wire _valid_3_T_3 = valid_4 | _valid_3_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_3_T_5 = _valid_3_T_4 & valid_2; // @[Decoupled.scala:51:35] wire _valid_3_T_6 = _valid_3_T_5 | valid_3; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_3_T_7 = io_deq_ready_0 ? _valid_3_T_3 : _valid_3_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire _wen_T_34 = _wen_T_32 & _wen_T_33; // @[Decoupled.scala:51:35] wire _wen_T_35 = _wen_T_34; // @[ShiftQueue.scala:30:{28,43}] wire _wen_T_37 = _wen_T_36 & valid_3; // @[Decoupled.scala:51:35] wire _wen_T_38 = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_39 = _wen_T_37 & _wen_T_38; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_4 = io_deq_ready_0 ? _wen_T_35 : _wen_T_39; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_4_T_2 = _valid_4_T & _valid_4_T_1; // @[Decoupled.scala:51:35] wire _valid_4_T_3 = _valid_4_T_2; // @[ShiftQueue.scala:36:{28,43}] wire _valid_4_T_5 = _valid_4_T_4 & valid_3; // @[Decoupled.scala:51:35] wire _valid_4_T_6 = _valid_4_T_5 | valid_4; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_4_T_7 = io_deq_ready_0 ? _valid_4_T_3 : _valid_4_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] assign _io_enq_ready_T = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46, :40:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[ShiftQueue.scala:12:7, :40:19] assign io_deq_valid_0 = io_enq_valid_0 | valid_0; // @[ShiftQueue.scala:12:7, :21:30, :41:16, :45:{25,40}] assign io_deq_bits_btb_cfiType_0 = valid_0 ? elts_0_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_taken_0 = valid_0 ? elts_0_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_mask_0 = valid_0 ? elts_0_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bridx_0 = valid_0 ? elts_0_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_target_0 = valid_0 ? elts_0_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_entry_0 = valid_0 ? elts_0_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_history_0 = valid_0 ? elts_0_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_value_0 = valid_0 ? elts_0_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_pc_0 = valid_0 ? elts_0_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_data_0 = valid_0 ? elts_0_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_mask_0 = valid_0 ? elts_0_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_pf_inst_0 = valid_0 ? elts_0_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_gf_inst_0 = valid_0 & elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_ae_inst_0 = valid_0 ? elts_0_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_replay_0 = valid_0 ? elts_0_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] wire [1:0] io_mask_lo = {valid_1, valid_0}; // @[ShiftQueue.scala:21:30, :53:20] wire [1:0] io_mask_hi_hi = {valid_4, valid_3}; // @[ShiftQueue.scala:21:30, :53:20] wire [2:0] io_mask_hi = {io_mask_hi_hi, valid_2}; // @[ShiftQueue.scala:21:30, :53:20] assign _io_mask_T = {io_mask_hi, io_mask_lo}; // @[ShiftQueue.scala:53:20] assign io_mask_0 = _io_mask_T; // @[ShiftQueue.scala:12:7, :53:20] wire _io_count_T = io_mask_0[0]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_1 = io_mask_0[1]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_2 = io_mask_0[2]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_3 = io_mask_0[3]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_4 = io_mask_0[4]; // @[ShiftQueue.scala:12:7, :54:23] wire [1:0] _io_count_T_5 = {1'h0, _io_count_T} + {1'h0, _io_count_T_1}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_6 = _io_count_T_5; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_7 = {1'h0, _io_count_T_3} + {1'h0, _io_count_T_4}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_8 = _io_count_T_7; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_9 = {2'h0, _io_count_T_2} + {1'h0, _io_count_T_8}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_10 = _io_count_T_9[1:0]; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_11 = {1'h0, _io_count_T_6} + {1'h0, _io_count_T_10}; // @[ShiftQueue.scala:54:23] assign _io_count_T_12 = _io_count_T_11; // @[ShiftQueue.scala:54:23] assign io_count = _io_count_T_12; // @[ShiftQueue.scala:12:7, :54:23] always @(posedge clock) begin // @[ShiftQueue.scala:12:7] if (reset) begin // @[ShiftQueue.scala:12:7] valid_0 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_1 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_2 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_3 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_4 <= 1'h0; // @[ShiftQueue.scala:21:30] end else begin // @[ShiftQueue.scala:12:7] valid_0 <= _valid_0_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_1 <= _valid_1_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_2 <= _valid_2_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_3 <= _valid_3_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_4 <= _valid_4_T_7; // @[ShiftQueue.scala:21:30, :35:10] end if (wen) begin // @[ShiftQueue.scala:29:10] elts_0_btb_cfiType <= wdata_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_taken <= wdata_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_mask <= wdata_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bridx <= wdata_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_target <= wdata_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_entry <= wdata_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_history <= wdata_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_value <= wdata_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_0_pc <= wdata_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_0_data <= wdata_data; // @[ShiftQueue.scala:22:25, :27:57] elts_0_mask <= wdata_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_pf_inst <= wdata_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_gf_inst <= wdata_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_ae_inst <= wdata_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_replay <= wdata_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_1) begin // @[ShiftQueue.scala:29:10] elts_1_btb_cfiType <= wdata_1_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_taken <= wdata_1_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_mask <= wdata_1_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bridx <= wdata_1_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_target <= wdata_1_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_entry <= wdata_1_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_history <= wdata_1_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_value <= wdata_1_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_1_pc <= wdata_1_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_1_data <= wdata_1_data; // @[ShiftQueue.scala:22:25, :27:57] elts_1_mask <= wdata_1_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_pf_inst <= wdata_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_gf_inst <= wdata_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_ae_inst <= wdata_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_replay <= wdata_1_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_2) begin // @[ShiftQueue.scala:29:10] elts_2_btb_cfiType <= wdata_2_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_taken <= wdata_2_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_mask <= wdata_2_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bridx <= wdata_2_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_target <= wdata_2_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_entry <= wdata_2_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_history <= wdata_2_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_value <= wdata_2_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_2_pc <= wdata_2_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_2_data <= wdata_2_data; // @[ShiftQueue.scala:22:25, :27:57] elts_2_mask <= wdata_2_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_pf_inst <= wdata_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_gf_inst <= wdata_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_ae_inst <= wdata_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_replay <= wdata_2_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_3) begin // @[ShiftQueue.scala:29:10] elts_3_btb_cfiType <= wdata_3_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_taken <= wdata_3_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_mask <= wdata_3_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bridx <= wdata_3_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_target <= wdata_3_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_entry <= wdata_3_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_history <= wdata_3_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_value <= wdata_3_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_3_pc <= wdata_3_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_3_data <= wdata_3_data; // @[ShiftQueue.scala:22:25, :27:57] elts_3_mask <= wdata_3_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_pf_inst <= wdata_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_gf_inst <= wdata_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_ae_inst <= wdata_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_replay <= wdata_3_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_4) begin // @[ShiftQueue.scala:29:10] elts_4_btb_cfiType <= io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_taken <= io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_mask <= io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bridx <= io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_target <= io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_entry <= io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_history <= io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_value <= io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_pc <= io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_data <= io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_mask <= io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_pf_inst <= io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_replay <= io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :22:25] end elts_4_xcpt_gf_inst <= ~wen_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :29:10, :32:{16,26}] always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[ShiftQueue.scala:12:7] assign io_deq_valid = io_deq_valid_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_cfiType = io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_taken = io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_mask = io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bridx = io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_target = io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_entry = io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_history = io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_value = io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_pc = io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_pf_inst = io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_gf_inst = io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_ae_inst = io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_replay = io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] assign io_mask = io_mask_0; // @[ShiftQueue.scala:12:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_146( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_156 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundRawFNToRecFN_e8_s24_110( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_110 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_56( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File tage.scala: package boom.v4.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f2_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)*l, histLength)-1, i*l) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val us = SyncReadMem(nRows, Vec(bankWidth*2, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) us.suggestName(s"tage_u_${histLength}") table.suggestName(s"tage_table_${histLength}") val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry)) val s2_req_rus = Wire(Vec(bankWidth*2, Bool())) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f2_resp(w).valid := s2_req_rhits(w) io.f2_resp(w).bits.u := Cat(s2_req_rus(w*2+1), s2_req_rus(w*2)) io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val clear_u_mask = VecInit((0 until bankWidth*2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) val wen = WireInit(doing_reset || io.update_mask.reduce(_||_)) val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid) when (RegNext(wen) && singlePorted.B) { s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry)) } .otherwise { s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry))) } when (wen) { val widx = Mux(doing_reset, reset_idx, update_idx) val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))) val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt) table.write(widx, wdata, wmask.asBools) } val update_u_mask = VecInit((0 until bankWidth*2) map {i => io.update_u_mask(i / 2)}) val update_u_wen = WireInit(doing_reset || doing_clear_u || update_u_mask.reduce(_||_)) val u_rdata = if (singlePorted) { us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid) } else { us.read(s1_hashed_idx, io.f1_req_valid) } s2_req_rus := u_rdata when (update_u_wen) { val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx)) val wdata = Mux(doing_reset || doing_clear_u, VecInit(0.U((bankWidth*2).W).asBools), VecInit(io.update_u.asUInt.asBools)) val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt)) us.write(widx, wdata, wmask.asBools) } val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_||_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag } when (io.update_mask.reduce(_||_)) { when (wrbypass_hits.reduce(_||_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048, singlePorted: Boolean = false ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc)) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f2_resps = VecInit(tables.map(_.io.f2_resp)) val f3_resps = RegNext(f2_resps) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var s2_provided = false.B var s2_provider = 0.U var s2_alt_provided = false.B var s2_alt_provider = 0.U for (i <- 0 until tageNTables) { val hit = f2_resps(i)(w).valid s2_alt_provided = s2_alt_provided || (s2_provided && hit) s2_provided = s2_provided || hit s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider) s2_provider = Mux(hit, i.U, s2_provider) } val s3_provided = RegNext(s2_provided) val s3_provider = RegNext(s2_provider) val s3_alt_provided = RegNext(s2_alt_provided) val s3_alt_provider = RegNext(s2_alt_provider) val prov = RegNext(f2_resps(s2_provider)(w).bits) val alt = RegNext(f2_resps(s2_alt_provider)(w).bits) io.resp.f3(w).taken := Mux(s3_provided, Mux(prov.ctr === 3.U || prov.ctr === 4.U, Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken), prov.ctr(2)), io.resp_in(0).f3(w).taken ) f3_meta.provider(w).valid := s3_provided f3_meta.provider(w).bits := s3_provider f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken f3_meta.provider_u(w) := prov.u f3_meta.provider_ctr(w) := prov.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }

module TageTable_4( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f2_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14] output io_f2_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14] output io_f2_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14] output io_f2_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire [51:0] _tage_table_32_R0_data; // @[tage.scala:90:27] wire [7:0] _tage_u_32_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26] wire [12:0] _wdata_WIRE_0 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_1 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_2 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_3 = 13'h0; // @[tage.scala:130:41] wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34] wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58] wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34] wire s2_req_rhits_0; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_1; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_2; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_3; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34] wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26] wire [7:0] _reset_idx_T = _GEN + {7'h0, doing_reset}; // @[tage.scala:72:28, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [6:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2 = io_f1_req_ghist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3 = io_f1_req_ghist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [3:0] idx_history_hist_chunks_4 = io_f1_req_ghist_0[31:28]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_1 = _idx_history_T ^ idx_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_2 = _idx_history_T_1 ^ idx_history_hist_chunks_3; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history = {_idx_history_T_2[6:4], _idx_history_T_2[3:0] ^ idx_history_hist_chunks_4}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T = io_f1_req_pc_0[39:11]; // @[frontend.scala:149:35] wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[10:4] ^ idx_history}; // @[frontend.scala:149:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99] wire [6:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12] wire [8:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2 = io_f1_req_ghist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [4:0] tag_history_hist_chunks_3 = io_f1_req_ghist_0[31:27]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_1 = _tag_history_T ^ tag_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history = {_tag_history_T_1[8:5], _tag_history_T_1[4:0] ^ tag_history_hist_chunks_3}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_1 = {_tag_T[28:9], _tag_T[8:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] s1_tag = _tag_T_1[8:0]; // @[tage.scala:62:{50,64}] wire wdata_1_0; // @[tage.scala:145:20] wire wdata_1_1; // @[tage.scala:145:20] wire wdata_1_2; // @[tage.scala:145:20] wire wdata_1_3; // @[tage.scala:145:20] wire wdata_1_4; // @[tage.scala:145:20] wire wdata_1_5; // @[tage.scala:145:20] wire wdata_1_6; // @[tage.scala:145:20] wire wdata_1_7; // @[tage.scala:145:20] wire s2_req_rus_0 = _tage_u_32_R0_data[0]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_1 = _tage_u_32_R0_data[1]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_2 = _tage_u_32_R0_data[2]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_3 = _tage_u_32_R0_data[3]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_4 = _tage_u_32_R0_data[4]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_5 = _tage_u_32_R0_data[5]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_6 = _tage_u_32_R0_data[6]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_7 = _tage_u_32_R0_data[7]; // @[tage.scala:89:27, :99:24] wire [12:0] wdata_0; // @[tage.scala:130:20] wire [12:0] wdata_1; // @[tage.scala:130:20] wire [12:0] wdata_2; // @[tage.scala:130:20] wire [12:0] wdata_3; // @[tage.scala:130:20] reg [8:0] s2_tag; // @[tage.scala:96:29] assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26] wire s2_req_rtage_0_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_0_tag; // @[tage.scala:98:26] wire s2_req_rtage_1_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_1_tag; // @[tage.scala:98:26] wire s2_req_rtage_2_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_2_tag; // @[tage.scala:98:26] wire s2_req_rtage_3_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_3_tag; // @[tage.scala:98:26] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29] assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29] assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29] assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29] assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31] wire _clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31, :114:31] wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}] wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}] wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109] wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109] wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109] wire [6:0] idx_history_hist_chunks_0_1 = io_update_hist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1_1 = io_update_hist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2_1 = io_update_hist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3_1 = io_update_hist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [3:0] idx_history_hist_chunks_4_1 = io_update_hist_0[31:28]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T_3 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_4 = _idx_history_T_3 ^ idx_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_5 = _idx_history_T_4 ^ idx_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history_1 = {_idx_history_T_5[6:4], _idx_history_T_5[3:0] ^ idx_history_hist_chunks_4_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_2 = io_update_pc_0[39:11]; // @[frontend.scala:149:35] wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[10:4] ^ idx_history_1}; // @[frontend.scala:149:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [8:0] tag_history_hist_chunks_0_1 = io_update_hist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1_1 = io_update_hist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2_1 = io_update_hist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [4:0] tag_history_hist_chunks_3_1 = io_update_hist_0[31:27]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T_2 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_3 = _tag_history_T_2 ^ tag_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history_1 = {_tag_history_T_3[8:5], _tag_history_T_3[4:0] ^ tag_history_hist_chunks_3_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_3 = {_tag_T_2[28:9], _tag_T_2[8:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] update_tag = _tag_T_3[8:0]; // @[tage.scala:62:{50,64}] wire [8:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26] wire _wen_T = io_update_mask_0_0 | io_update_mask_1_0; // @[tage.scala:24:7, :121:60] wire _wen_T_1 = _wen_T | io_update_mask_2_0; // @[tage.scala:24:7, :121:60] wire _wen_T_2 = _wen_T_1 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60] wire _wen_T_3 = doing_reset | _wen_T_2; // @[tage.scala:72:28, :121:{34,60}] wire wen = _wen_T_3; // @[tage.scala:121:{21,34}] reg REG; // @[tage.scala:123:16] assign s2_req_rtage_0_ctr = _tage_table_32_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_tag = _tage_table_32_R0_data[11:3]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_valid = _tage_table_32_R0_data[12]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_ctr = _tage_table_32_R0_data[15:13]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_tag = _tage_table_32_R0_data[24:16]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_valid = _tage_table_32_R0_data[25]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_ctr = _tage_table_32_R0_data[28:26]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_tag = _tage_table_32_R0_data[37:29]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_valid = _tage_table_32_R0_data[38]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_ctr = _tage_table_32_R0_data[41:39]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_tag = _tage_table_32_R0_data[50:42]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_valid = _tage_table_32_R0_data[51]; // @[tage.scala:90:27, :98:26, :126:49] wire [6:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19] wire [9:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}] assign wdata_0 = doing_reset ? 13'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}] assign wdata_1 = doing_reset ? 13'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}] assign wdata_2 = doing_reset ? 13'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}] assign wdata_3 = doing_reset ? 13'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}] wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70] wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70] wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70] wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}] wire _GEN_0 = doing_reset | doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43] wire _update_u_wen_T; // @[tage.scala:136:43] assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43] wire _wdata_T_4; // @[tage.scala:145:33] assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33] wire _update_u_wen_T_1 = update_u_mask_0 | update_u_mask_1; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_2 = _update_u_wen_T_1 | update_u_mask_2; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_3 = _update_u_wen_T_2 | update_u_mask_3; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_4 = _update_u_wen_T_3 | update_u_mask_4; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_5 = _update_u_wen_T_4 | update_u_mask_5; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_6 = _update_u_wen_T_5 | update_u_mask_6; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_7 = _update_u_wen_T_6 | update_u_mask_7; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_8 = _update_u_wen_T | _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}] wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}] wire [7:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47] wire [7:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}] wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110] wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110] wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110] wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}] wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}] wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}] wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}] wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}] wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}] wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}] wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}] assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}] assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}] assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}] assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}] assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}] assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}] assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}] assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}] wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106] wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106] wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106] wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}] wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}] reg [8:0] wrbypass_tags_0; // @[tage.scala:154:29] reg [8:0] wrbypass_tags_1; // @[tage.scala:154:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:155:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:155:29] reg [2:0] wrbypass_0_0; // @[tage.scala:156:29] reg [2:0] wrbypass_0_1; // @[tage.scala:156:29] reg [2:0] wrbypass_0_2; // @[tage.scala:156:29] reg [2:0] wrbypass_0_3; // @[tage.scala:156:29] reg [2:0] wrbypass_1_0; // @[tage.scala:156:29] reg [2:0] wrbypass_1_1; // @[tage.scala:156:29] reg [2:0] wrbypass_1_2; // @[tage.scala:156:29] reg [2:0] wrbypass_1_3; // @[tage.scala:156:29] reg wrbypass_enq_idx; // @[tage.scala:157:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:159:33, :164:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}] wire _T_31 = _wen_T | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_31 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] wire _GEN_15 = ~_T_31 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_31 | wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39] end else // @[tage.scala:157:33, :180:38, :181:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29] REG <= wen; // @[tage.scala:121:21, :123:16] if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29] if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29] if (~_T_31 | _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] end else begin // @[tage.scala:156:29, :180:38, :181:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end always @(posedge) tage_u_32 tage_u_32 ( // @[tage.scala:89:27] .R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_u_32_R0_data), .W0_addr (widx_1[6:0]), // @[tage.scala:144:19, :147:13] .W0_en (update_u_wen), // @[tage.scala:136:30] .W0_clk (clock), .W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20] .W0_mask (wmask_1) // @[tage.scala:146:20] ); // @[tage.scala:89:27] tage_table_32 tage_table_32 ( // @[tage.scala:90:27] .R0_addr (_rdata_WIRE), // @[tage.scala:122:99] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_table_32_R0_data), .W0_addr (widx), // @[tage.scala:129:19] .W0_en (wen), // @[tage.scala:121:21] .W0_clk (clock), .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20] .W0_mask (wmask) // @[tage.scala:131:20] ); // @[tage.scala:90:27] assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_11( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1492 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1492; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1492; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1565 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1565; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1565; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1565; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1418 = _T_1492 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1418 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1418 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1418 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1418 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1418 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1464 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1464 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1433 = _T_1565 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1433 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1433 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1433 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1536 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1536 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1518 = _T_1565 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1518 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1518 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1518 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } def logCritical(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_*)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } } def logWaveStyle(format: String, args: Bits*)(implicit p: Parameters) { } } object CompressAccelParams { } File CompressedBitsBuffer.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig, HellaCacheArbiter} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.tilelink._ class WriteBitsBundle(val dataWidth: Int) extends Bundle { val data = UInt(dataWidth.W) val validbits = UInt(log2Ceil(dataWidth + 1).W) val end_of_message = Bool() } class BitsConsumerBundle(val dataWidth: Int) extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) val consumed_bytes = Input(UInt(log2Ceil(dataWidth + 1).W)) val avail_bytes = Output(UInt(log2Ceil(dataWidth + 1).W)) val data = Output(UInt(dataWidth.W)) val last_chunk = Output(Bool()) } class CompressedBitsBuffIO(val dataWidth: Int) extends Bundle { val writes_in = Flipped(Decoupled(new WriteBitsBundle(dataWidth))) val consumer = new BitsConsumerBundle(dataWidth) } // input interface is just like memwriter except that it is in bit granularity instead of byte granularity // output interface is just like memloader class CompressedBitsBuff(val unroll_cnt: Int, val max_bits_per_code: Int)(implicit p: Parameters) extends Module { // val HUF_CODE_MAX_BITS = 11 val dataWidth = max_bits_per_code * unroll_cnt val dataWidthByteAligned = if (dataWidth % 8 == 0) dataWidth else (dataWidth/8 + 1) * 8 // 8 byte interface val NUM_QUEUES = if (dataWidthByteAligned <= 64) { 64 } else if (dataWidthByteAligned <= 128) { 128 } else if (dataWidthByteAligned <= 256) { 256 } else { 0 // doens't make sense } val QUEUE_DEPTH = 16 assert(NUM_QUEUES >= dataWidthByteAligned) val io = IO(new CompressedBitsBuffIO(NUM_QUEUES)) val incoming_writes = Module(new Queue(new WriteBitsBundle(NUM_QUEUES), 8)) incoming_writes.io.enq <> io.writes_in // val data = UInt(dataWidth.W) // val validbits = UInt(log2Ceil(dataWidth + 1).W) // val end_of_message = Bool() val buf_lens_q = Module(new Queue(UInt(64.W), 10)) val buf_lens_tracker = RegInit(0.U(64.W)) when (incoming_writes.io.deq.fire) { when (incoming_writes.io.deq.bits.end_of_message) { buf_lens_tracker := 0.U } .otherwise { buf_lens_tracker := buf_lens_tracker + incoming_writes.io.deq.bits.validbits } } val buffers = Seq.fill(NUM_QUEUES)(Module(new Queue(UInt(1.W), QUEUE_DEPTH)).io) val write_start_idx = RegInit(0.U(log2Up(NUM_QUEUES + 1).W)) val bits_to_write = incoming_writes.io.deq.bits.validbits val wrap_len_idx_wide = write_start_idx + bits_to_write val wrap_len_idx_end = wrap_len_idx_wide % NUM_QUEUES.U val wrapped = wrap_len_idx_wide >= NUM_QUEUES.U val all_queues_ready = buffers.map(_.enq.ready).reduce(_ && _) val end_of_buf = incoming_writes.io.deq.bits.end_of_message val account_for_buf_length = (!end_of_buf) || (end_of_buf && buf_lens_q.io.enq.ready) val input_fire_all_queues = DecoupledHelper( all_queues_ready, account_for_buf_length, incoming_writes.io.deq.valid) incoming_writes.io.deq.ready := input_fire_all_queues.fire(incoming_writes.io.deq.valid) val write_data_bit_vec = Wire(Vec(NUM_QUEUES, UInt(1.W))) write_data_bit_vec.foreach(x => x := 0.U) for (i <- 0 until NUM_QUEUES) { val corresponding_buf_idx = (i.U +& write_start_idx) % NUM_QUEUES.U write_data_bit_vec(corresponding_buf_idx) := incoming_writes.io.deq.bits.data >> i.U } for (i <- 0 until NUM_QUEUES) { val use_this_queue = Mux(wrapped, (i.U < wrap_len_idx_end) || (i.U >= write_start_idx), (i.U >= write_start_idx) && (i.U < wrap_len_idx_end) ) buffers(i).enq.valid := input_fire_all_queues.fire && use_this_queue buffers(i).enq.bits := write_data_bit_vec(i) } buf_lens_q.io.enq.valid := input_fire_all_queues.fire(account_for_buf_length) && end_of_buf buf_lens_q.io.enq.bits := buf_lens_tracker +& incoming_writes.io.deq.bits.validbits when (buf_lens_q.io.enq.fire) { CompressAccelLogger.logInfo("BITBUFF_BUFLEN_ENQ_FIRE, total_bits: %d\n", buf_lens_q.io.enq.bits) } when (input_fire_all_queues.fire) { write_start_idx := wrap_len_idx_end CompressAccelLogger.logInfo("BITBUF_WRITEFIRE\n") CompressAccelLogger.logInfo("write_start_idx: %d, written_bits: %d\n", write_start_idx, bits_to_write) } val read_start_idx = RegInit(0.U(log2Up(NUM_QUEUES + 1).W)) val bufVecData = Wire(Vec(NUM_QUEUES, UInt(1.W))) val bufVecReadys = Wire(Vec(NUM_QUEUES, Bool())) val bufVecValids = Wire(Vec(NUM_QUEUES, Bool())) bufVecReadys.foreach(x => x := false.B) for (i <- 0 until NUM_QUEUES) { bufVecData(i) := buffers(i).deq.bits bufVecValids(i) := buffers(i).deq.valid buffers(i).deq.ready := bufVecReadys(i) } val remapVecData = Wire(Vec(NUM_QUEUES, UInt(1.W))) val remapVecReadys = Wire(Vec(NUM_QUEUES, Bool())) val remapVecValids = Wire(Vec(NUM_QUEUES, Bool())) for (i <- 0 until NUM_QUEUES) { val remap_idx = (i.U +& read_start_idx) % NUM_QUEUES.U remapVecData(i) := bufVecData(remap_idx) remapVecValids(i) := bufVecValids(remap_idx) bufVecReadys(remap_idx) := remapVecReadys(i) } val count_valid_bits = remapVecValids.map(_.asUInt).reduce(_ +& _) val count_valid_bytes = count_valid_bits >> 3.U val remain_valid_bits = count_valid_bits - (count_valid_bytes << 3.U) val byte_aligned = (remain_valid_bits === 0.U) val len_already_consumed = RegInit(0.U(64.W)) val unconsumed_bits_so_far = buf_lens_q.io.deq.bits - len_already_consumed val last_chunk = buf_lens_q.io.deq.valid && (unconsumed_bits_so_far <= NUM_QUEUES.U) val avail_bytes = Mux((last_chunk && !byte_aligned), count_valid_bytes + 1.U, count_valid_bytes) val enough_data = avail_bytes =/= 0.U val count_valid_bits_u8 = Wire(UInt(8.W)) count_valid_bits_u8 := count_valid_bits val valid_bit_mask = (1.U << count_valid_bits_u8) - 1.U io.consumer.data := Cat(remapVecData.reverse) & valid_bit_mask io.consumer.avail_bytes := avail_bytes io.consumer.last_chunk := last_chunk val read_fire = DecoupledHelper( io.consumer.ready, enough_data) io.consumer.valid := read_fire.fire(io.consumer.ready) val consumed_bits_wide = io.consumer.consumed_bytes << 3.U val consumed_bits_overflow = consumed_bits_wide > count_valid_bits val consumed_bits = Mux(last_chunk && !byte_aligned && consumed_bits_overflow, count_valid_bits, consumed_bits_wide) val buf_last = buf_lens_q.io.deq.valid && (buf_lens_q.io.deq.bits === (len_already_consumed + consumed_bits)) val nxt_len_already_consumed = Mux(buf_last, 0.U, len_already_consumed + consumed_bits) when (read_fire.fire) { read_start_idx := (read_start_idx +& consumed_bits) % NUM_QUEUES.U when (buf_last) { len_already_consumed := 0.U } .otherwise { len_already_consumed := nxt_len_already_consumed } } for (i <- 0 until NUM_QUEUES) { remapVecReadys(i) := (i.U < consumed_bits) && read_fire.fire } buf_lens_q.io.deq.ready := read_fire.fire && buf_last // connecting ready & valid...? when (read_fire.fire) { CompressAccelLogger.logInfo("BITBUF_RDFIRE\n") CompressAccelLogger.logInfo("consumer.data: 0x%x\n", io.consumer.data) CompressAccelLogger.logInfo("consumer.last_chunk: %d\n", io.consumer.last_chunk) CompressAccelLogger.logInfo("consumer.avail_bytes: %d\n", io.consumer.avail_bytes) CompressAccelLogger.logInfo("consumer.consumed_bytes: %d\n", io.consumer.consumed_bytes) CompressAccelLogger.logInfo("consumed_bits_wide: %d\n", consumed_bits_wide) CompressAccelLogger.logInfo("consumed_bits_overflow: %d\n", consumed_bits_overflow) CompressAccelLogger.logInfo("consumed_bits: %d\n", consumed_bits) CompressAccelLogger.logInfo("buf_last: %d\n", buf_last) CompressAccelLogger.logInfo("read_start_idx: %d\n", read_start_idx) CompressAccelLogger.logInfo("count_valid_bits: %d\n", count_valid_bits) CompressAccelLogger.logInfo("count_valid_bytes: %d\n", count_valid_bytes) CompressAccelLogger.logInfo("remain_valid_bits: %d\n", remain_valid_bits) CompressAccelLogger.logInfo("byte_aligned: %d\n", byte_aligned) CompressAccelLogger.logInfo("len_already_consumed: %d\n", len_already_consumed) CompressAccelLogger.logInfo("nxt_len_already_consumed: %d\n", nxt_len_already_consumed) CompressAccelLogger.logInfo("unconsumed_bits_so_far: %d\n", unconsumed_bits_so_far) CompressAccelLogger.logInfo("last_chunk: %d\n", last_chunk) CompressAccelLogger.logInfo("valid_bit_mask: 0x%x\n", valid_bit_mask) for (i <- 0 until NUM_QUEUES) { CompressAccelLogger.logInfo("bufVecReadys(%d): %d\n", i.U, bufVecReadys(i)) } for (i <- 0 until NUM_QUEUES) { CompressAccelLogger.logInfo("bufVecValids(%d): %d\n", i.U, bufVecValids(i)) } } for (i <- 0 until NUM_QUEUES) { when (buffers(i).deq.fire) { CompressAccelLogger.logInfo("buffer(%d) fired\n", i.U) } } when (buf_lens_q.io.deq.fire) { CompressAccelLogger.logInfo("BITBUFF buf_lens_q dequeued\n") } }

module CompressedBitsBuff( // @[CompressedBitsBuffer.scala:38:7] input clock, // @[CompressedBitsBuffer.scala:38:7] input reset, // @[CompressedBitsBuffer.scala:38:7] output io_writes_in_ready, // @[CompressedBitsBuffer.scala:56:14] input io_writes_in_valid, // @[CompressedBitsBuffer.scala:56:14] input [63:0] io_writes_in_bits_data, // @[CompressedBitsBuffer.scala:56:14] input [6:0] io_writes_in_bits_validbits, // @[CompressedBitsBuffer.scala:56:14] input io_writes_in_bits_end_of_message, // @[CompressedBitsBuffer.scala:56:14] output io_consumer_valid, // @[CompressedBitsBuffer.scala:56:14] input io_consumer_ready, // @[CompressedBitsBuffer.scala:56:14] input [6:0] io_consumer_consumed_bytes, // @[CompressedBitsBuffer.scala:56:14] output [6:0] io_consumer_avail_bytes, // @[CompressedBitsBuffer.scala:56:14] output [63:0] io_consumer_data, // @[CompressedBitsBuffer.scala:56:14] output io_consumer_last_chunk // @[CompressedBitsBuffer.scala:56:14] ); wire _Queue16_UInt1_63_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_63_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_62_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_62_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_61_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_61_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_60_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_60_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_59_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_59_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_58_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_58_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_57_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_57_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_56_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_56_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_55_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_55_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_54_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_54_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_53_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_53_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_52_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_52_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_51_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_51_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_50_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_50_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_49_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_49_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_48_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_48_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_47_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_47_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_46_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_46_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_45_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_45_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_44_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_44_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_43_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_43_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_42_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_42_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_41_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_41_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_40_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_40_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_39_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_39_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_38_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_38_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_37_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_37_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_36_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_36_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_35_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_35_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_34_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_34_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_33_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_33_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_32_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_32_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_31_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_31_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_30_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_30_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_29_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_29_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_28_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_28_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_27_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_27_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_26_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_26_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_25_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_25_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_24_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_24_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_23_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_23_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_22_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_22_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_21_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_21_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_20_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_20_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_19_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_19_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_18_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_18_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_17_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_17_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_16_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_16_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_15_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_15_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_14_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_14_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_13_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_13_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_12_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_12_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_11_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_11_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_10_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_10_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_9_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_9_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_8_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_8_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_7_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_7_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_6_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_6_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_5_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_5_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_4_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_4_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_3_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_3_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_2_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_2_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_1_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_1_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44] wire _Queue16_UInt1_io_deq_valid; // @[CompressedBitsBuffer.scala:76:44] wire _buf_lens_q_io_enq_ready; // @[CompressedBitsBuffer.scala:65:26] wire _buf_lens_q_io_deq_valid; // @[CompressedBitsBuffer.scala:65:26] wire [63:0] _buf_lens_q_io_deq_bits; // @[CompressedBitsBuffer.scala:65:26] wire _incoming_writes_io_deq_valid; // @[CompressedBitsBuffer.scala:58:31] wire [63:0] _incoming_writes_io_deq_bits_data; // @[CompressedBitsBuffer.scala:58:31] wire [6:0] _incoming_writes_io_deq_bits_validbits; // @[CompressedBitsBuffer.scala:58:31] wire _incoming_writes_io_deq_bits_end_of_message; // @[CompressedBitsBuffer.scala:58:31] wire io_writes_in_valid_0 = io_writes_in_valid; // @[CompressedBitsBuffer.scala:38:7] wire [63:0] io_writes_in_bits_data_0 = io_writes_in_bits_data; // @[CompressedBitsBuffer.scala:38:7] wire [6:0] io_writes_in_bits_validbits_0 = io_writes_in_bits_validbits; // @[CompressedBitsBuffer.scala:38:7] wire io_writes_in_bits_end_of_message_0 = io_writes_in_bits_end_of_message; // @[CompressedBitsBuffer.scala:38:7] wire io_consumer_ready_0 = io_consumer_ready; // @[CompressedBitsBuffer.scala:38:7] wire [6:0] io_consumer_consumed_bytes_0 = io_consumer_consumed_bytes; // @[CompressedBitsBuffer.scala:38:7] wire enough_data; // @[CompressedBitsBuffer.scala:162:33] wire last_chunk; // @[CompressedBitsBuffer.scala:157:44] wire io_writes_in_ready_0; // @[CompressedBitsBuffer.scala:38:7] wire io_consumer_valid_0; // @[CompressedBitsBuffer.scala:38:7] wire [6:0] io_consumer_avail_bytes_0; // @[CompressedBitsBuffer.scala:38:7] wire [63:0] io_consumer_data_0; // @[CompressedBitsBuffer.scala:38:7] wire io_consumer_last_chunk_0; // @[CompressedBitsBuffer.scala:38:7] reg [63:0] buf_lens_tracker; // @[CompressedBitsBuffer.scala:66:33] wire [64:0] _GEN = {1'h0, buf_lens_tracker} + {58'h0, _incoming_writes_io_deq_bits_validbits}; // @[CompressedBitsBuffer.scala:58:31, :66:33, :72:44] wire [64:0] _buf_lens_tracker_T; // @[CompressedBitsBuffer.scala:72:44] assign _buf_lens_tracker_T = _GEN; // @[CompressedBitsBuffer.scala:72:44] wire [64:0] _buf_lens_q_io_enq_bits_T; // @[CompressedBitsBuffer.scala:113:46] assign _buf_lens_q_io_enq_bits_T = _GEN; // @[CompressedBitsBuffer.scala:72:44, :113:46] wire [63:0] _buf_lens_tracker_T_1 = _buf_lens_tracker_T[63:0]; // @[CompressedBitsBuffer.scala:72:44] reg [6:0] write_start_idx; // @[CompressedBitsBuffer.scala:77:32] wire [7:0] _corresponding_buf_idx_T = {1'h0, write_start_idx}; // @[CompressedBitsBuffer.scala:77:32, :80:43, :99:38] wire [7:0] _wrap_len_idx_wide_T = _corresponding_buf_idx_T + {1'h0, _incoming_writes_io_deq_bits_validbits}; // @[CompressedBitsBuffer.scala:58:31, :80:43, :99:38] wire [6:0] wrap_len_idx_wide = _wrap_len_idx_wide_T[6:0]; // @[CompressedBitsBuffer.scala:80:43] wire [6:0] wrap_len_idx_end = wrap_len_idx_wide % 7'h40; // @[CompressedBitsBuffer.scala:80:43, :81:44] wire wrapped = wrap_len_idx_wide[6]; // @[CompressedBitsBuffer.scala:80:43, :82:35] wire _all_queues_ready_T = _Queue16_UInt1_io_enq_ready & _Queue16_UInt1_1_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue16_UInt1_2_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue16_UInt1_3_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue16_UInt1_4_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue16_UInt1_5_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue16_UInt1_6_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue16_UInt1_7_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue16_UInt1_8_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue16_UInt1_9_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue16_UInt1_10_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue16_UInt1_11_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue16_UInt1_12_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue16_UInt1_13_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue16_UInt1_14_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue16_UInt1_15_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue16_UInt1_16_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue16_UInt1_17_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue16_UInt1_18_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue16_UInt1_19_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue16_UInt1_20_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue16_UInt1_21_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue16_UInt1_22_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue16_UInt1_23_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue16_UInt1_24_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue16_UInt1_25_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue16_UInt1_26_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue16_UInt1_27_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue16_UInt1_28_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue16_UInt1_29_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue16_UInt1_30_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_30 = _all_queues_ready_T_29 & _Queue16_UInt1_31_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_31 = _all_queues_ready_T_30 & _Queue16_UInt1_32_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_32 = _all_queues_ready_T_31 & _Queue16_UInt1_33_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_33 = _all_queues_ready_T_32 & _Queue16_UInt1_34_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_34 = _all_queues_ready_T_33 & _Queue16_UInt1_35_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_35 = _all_queues_ready_T_34 & _Queue16_UInt1_36_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_36 = _all_queues_ready_T_35 & _Queue16_UInt1_37_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_37 = _all_queues_ready_T_36 & _Queue16_UInt1_38_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_38 = _all_queues_ready_T_37 & _Queue16_UInt1_39_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_39 = _all_queues_ready_T_38 & _Queue16_UInt1_40_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_40 = _all_queues_ready_T_39 & _Queue16_UInt1_41_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_41 = _all_queues_ready_T_40 & _Queue16_UInt1_42_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_42 = _all_queues_ready_T_41 & _Queue16_UInt1_43_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_43 = _all_queues_ready_T_42 & _Queue16_UInt1_44_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_44 = _all_queues_ready_T_43 & _Queue16_UInt1_45_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_45 = _all_queues_ready_T_44 & _Queue16_UInt1_46_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_46 = _all_queues_ready_T_45 & _Queue16_UInt1_47_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_47 = _all_queues_ready_T_46 & _Queue16_UInt1_48_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_48 = _all_queues_ready_T_47 & _Queue16_UInt1_49_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_49 = _all_queues_ready_T_48 & _Queue16_UInt1_50_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_50 = _all_queues_ready_T_49 & _Queue16_UInt1_51_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_51 = _all_queues_ready_T_50 & _Queue16_UInt1_52_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_52 = _all_queues_ready_T_51 & _Queue16_UInt1_53_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_53 = _all_queues_ready_T_52 & _Queue16_UInt1_54_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_54 = _all_queues_ready_T_53 & _Queue16_UInt1_55_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_55 = _all_queues_ready_T_54 & _Queue16_UInt1_56_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_56 = _all_queues_ready_T_55 & _Queue16_UInt1_57_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_57 = _all_queues_ready_T_56 & _Queue16_UInt1_58_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_58 = _all_queues_ready_T_57 & _Queue16_UInt1_59_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_59 = _all_queues_ready_T_58 & _Queue16_UInt1_60_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_60 = _all_queues_ready_T_59 & _Queue16_UInt1_61_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _all_queues_ready_T_61 = _all_queues_ready_T_60 & _Queue16_UInt1_62_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire all_queues_ready = _all_queues_ready_T_61 & _Queue16_UInt1_63_io_enq_ready; // @[CompressedBitsBuffer.scala:76:44, :84:60] wire _account_for_buf_length_T = ~_incoming_writes_io_deq_bits_end_of_message; // @[CompressedBitsBuffer.scala:58:31, :87:33] wire _account_for_buf_length_T_1 = _incoming_writes_io_deq_bits_end_of_message & _buf_lens_q_io_enq_ready; // @[CompressedBitsBuffer.scala:58:31, :65:26, :87:61] wire account_for_buf_length = _account_for_buf_length_T | _account_for_buf_length_T_1; // @[CompressedBitsBuffer.scala:87:{33,46,61}] wire _incoming_writes_io_deq_ready_T = all_queues_ready & account_for_buf_length; // @[Misc.scala:26:53] wire write_data_bit_vec_0; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_1; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_2; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_3; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_4; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_5; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_6; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_7; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_8; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_9; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_10; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_11; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_12; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_13; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_14; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_15; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_16; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_17; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_18; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_19; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_20; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_21; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_22; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_23; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_24; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_25; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_26; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_27; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_28; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_29; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_30; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_31; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_32; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_33; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_34; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_35; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_36; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_37; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_38; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_39; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_40; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_41; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_42; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_43; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_44; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_45; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_46; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_47; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_48; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_49; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_50; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_51; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_52; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_53; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_54; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_55; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_56; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_57; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_58; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_59; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_60; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_61; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_62; // @[CompressedBitsBuffer.scala:96:32] wire write_data_bit_vec_63; // @[CompressedBitsBuffer.scala:96:32] wire [7:0] _GEN_0 = _corresponding_buf_idx_T % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx = _GEN_0[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T; // @[CompressedBitsBuffer.scala:100:83] wire [7:0] _corresponding_buf_idx_T_1 = _corresponding_buf_idx_T + 8'h1; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_1 = _corresponding_buf_idx_T_1 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_1 = _GEN_1[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_1 = {1'h0, _incoming_writes_io_deq_bits_data[63:1]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_2 = _corresponding_buf_idx_T + 8'h2; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_2 = _corresponding_buf_idx_T_2 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_2 = _GEN_2[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_2 = {2'h0, _incoming_writes_io_deq_bits_data[63:2]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_3 = _corresponding_buf_idx_T + 8'h3; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_3 = _corresponding_buf_idx_T_3 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_3 = _GEN_3[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_3 = {3'h0, _incoming_writes_io_deq_bits_data[63:3]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_4 = _corresponding_buf_idx_T + 8'h4; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_4 = _corresponding_buf_idx_T_4 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_4 = _GEN_4[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_4 = {4'h0, _incoming_writes_io_deq_bits_data[63:4]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_5 = _corresponding_buf_idx_T + 8'h5; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_5 = _corresponding_buf_idx_T_5 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_5 = _GEN_5[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_5 = {5'h0, _incoming_writes_io_deq_bits_data[63:5]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_6 = _corresponding_buf_idx_T + 8'h6; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_6 = _corresponding_buf_idx_T_6 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_6 = _GEN_6[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_6 = {6'h0, _incoming_writes_io_deq_bits_data[63:6]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_7 = _corresponding_buf_idx_T + 8'h7; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_7 = _corresponding_buf_idx_T_7 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_7 = _GEN_7[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_7 = {7'h0, _incoming_writes_io_deq_bits_data[63:7]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_8 = _corresponding_buf_idx_T + 8'h8; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_8 = _corresponding_buf_idx_T_8 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_8 = _GEN_8[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_8 = {8'h0, _incoming_writes_io_deq_bits_data[63:8]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_9 = _corresponding_buf_idx_T + 8'h9; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_9 = _corresponding_buf_idx_T_9 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_9 = _GEN_9[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_9 = {9'h0, _incoming_writes_io_deq_bits_data[63:9]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_10 = _corresponding_buf_idx_T + 8'hA; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_10 = _corresponding_buf_idx_T_10 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_10 = _GEN_10[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_10 = {10'h0, _incoming_writes_io_deq_bits_data[63:10]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_11 = _corresponding_buf_idx_T + 8'hB; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_11 = _corresponding_buf_idx_T_11 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_11 = _GEN_11[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_11 = {11'h0, _incoming_writes_io_deq_bits_data[63:11]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_12 = _corresponding_buf_idx_T + 8'hC; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_12 = _corresponding_buf_idx_T_12 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_12 = _GEN_12[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_12 = {12'h0, _incoming_writes_io_deq_bits_data[63:12]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_13 = _corresponding_buf_idx_T + 8'hD; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_13 = _corresponding_buf_idx_T_13 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_13 = _GEN_13[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_13 = {13'h0, _incoming_writes_io_deq_bits_data[63:13]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_14 = _corresponding_buf_idx_T + 8'hE; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_14 = _corresponding_buf_idx_T_14 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_14 = _GEN_14[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_14 = {14'h0, _incoming_writes_io_deq_bits_data[63:14]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_15 = _corresponding_buf_idx_T + 8'hF; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_15 = _corresponding_buf_idx_T_15 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_15 = _GEN_15[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_15 = {15'h0, _incoming_writes_io_deq_bits_data[63:15]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_16 = _corresponding_buf_idx_T + 8'h10; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_16 = _corresponding_buf_idx_T_16 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_16 = _GEN_16[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_16 = {16'h0, _incoming_writes_io_deq_bits_data[63:16]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_17 = _corresponding_buf_idx_T + 8'h11; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_17 = _corresponding_buf_idx_T_17 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_17 = _GEN_17[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_17 = {17'h0, _incoming_writes_io_deq_bits_data[63:17]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_18 = _corresponding_buf_idx_T + 8'h12; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_18 = _corresponding_buf_idx_T_18 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_18 = _GEN_18[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_18 = {18'h0, _incoming_writes_io_deq_bits_data[63:18]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_19 = _corresponding_buf_idx_T + 8'h13; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_19 = _corresponding_buf_idx_T_19 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_19 = _GEN_19[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_19 = {19'h0, _incoming_writes_io_deq_bits_data[63:19]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_20 = _corresponding_buf_idx_T + 8'h14; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_20 = _corresponding_buf_idx_T_20 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_20 = _GEN_20[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_20 = {20'h0, _incoming_writes_io_deq_bits_data[63:20]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_21 = _corresponding_buf_idx_T + 8'h15; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_21 = _corresponding_buf_idx_T_21 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_21 = _GEN_21[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_21 = {21'h0, _incoming_writes_io_deq_bits_data[63:21]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_22 = _corresponding_buf_idx_T + 8'h16; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_22 = _corresponding_buf_idx_T_22 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_22 = _GEN_22[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_22 = {22'h0, _incoming_writes_io_deq_bits_data[63:22]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_23 = _corresponding_buf_idx_T + 8'h17; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_23 = _corresponding_buf_idx_T_23 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_23 = _GEN_23[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_23 = {23'h0, _incoming_writes_io_deq_bits_data[63:23]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_24 = _corresponding_buf_idx_T + 8'h18; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_24 = _corresponding_buf_idx_T_24 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_24 = _GEN_24[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_24 = {24'h0, _incoming_writes_io_deq_bits_data[63:24]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_25 = _corresponding_buf_idx_T + 8'h19; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_25 = _corresponding_buf_idx_T_25 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_25 = _GEN_25[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_25 = {25'h0, _incoming_writes_io_deq_bits_data[63:25]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_26 = _corresponding_buf_idx_T + 8'h1A; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_26 = _corresponding_buf_idx_T_26 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_26 = _GEN_26[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_26 = {26'h0, _incoming_writes_io_deq_bits_data[63:26]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_27 = _corresponding_buf_idx_T + 8'h1B; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_27 = _corresponding_buf_idx_T_27 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_27 = _GEN_27[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_27 = {27'h0, _incoming_writes_io_deq_bits_data[63:27]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_28 = _corresponding_buf_idx_T + 8'h1C; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_28 = _corresponding_buf_idx_T_28 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_28 = _GEN_28[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_28 = {28'h0, _incoming_writes_io_deq_bits_data[63:28]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_29 = _corresponding_buf_idx_T + 8'h1D; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_29 = _corresponding_buf_idx_T_29 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_29 = _GEN_29[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_29 = {29'h0, _incoming_writes_io_deq_bits_data[63:29]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_30 = _corresponding_buf_idx_T + 8'h1E; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_30 = _corresponding_buf_idx_T_30 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_30 = _GEN_30[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_30 = {30'h0, _incoming_writes_io_deq_bits_data[63:30]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_31 = _corresponding_buf_idx_T + 8'h1F; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_31 = _corresponding_buf_idx_T_31 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_31 = _GEN_31[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_31 = {31'h0, _incoming_writes_io_deq_bits_data[63:31]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_32 = _corresponding_buf_idx_T + 8'h20; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_32 = _corresponding_buf_idx_T_32 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_32 = _GEN_32[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_32 = {32'h0, _incoming_writes_io_deq_bits_data[63:32]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_33 = _corresponding_buf_idx_T + 8'h21; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_33 = _corresponding_buf_idx_T_33 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_33 = _GEN_33[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_33 = {33'h0, _incoming_writes_io_deq_bits_data[63:33]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_34 = _corresponding_buf_idx_T + 8'h22; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_34 = _corresponding_buf_idx_T_34 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_34 = _GEN_34[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_34 = {34'h0, _incoming_writes_io_deq_bits_data[63:34]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_35 = _corresponding_buf_idx_T + 8'h23; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_35 = _corresponding_buf_idx_T_35 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_35 = _GEN_35[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_35 = {35'h0, _incoming_writes_io_deq_bits_data[63:35]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_36 = _corresponding_buf_idx_T + 8'h24; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_36 = _corresponding_buf_idx_T_36 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_36 = _GEN_36[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_36 = {36'h0, _incoming_writes_io_deq_bits_data[63:36]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_37 = _corresponding_buf_idx_T + 8'h25; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_37 = _corresponding_buf_idx_T_37 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_37 = _GEN_37[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_37 = {37'h0, _incoming_writes_io_deq_bits_data[63:37]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_38 = _corresponding_buf_idx_T + 8'h26; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_38 = _corresponding_buf_idx_T_38 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_38 = _GEN_38[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_38 = {38'h0, _incoming_writes_io_deq_bits_data[63:38]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_39 = _corresponding_buf_idx_T + 8'h27; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_39 = _corresponding_buf_idx_T_39 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_39 = _GEN_39[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_39 = {39'h0, _incoming_writes_io_deq_bits_data[63:39]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_40 = _corresponding_buf_idx_T + 8'h28; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_40 = _corresponding_buf_idx_T_40 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_40 = _GEN_40[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_40 = {40'h0, _incoming_writes_io_deq_bits_data[63:40]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_41 = _corresponding_buf_idx_T + 8'h29; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_41 = _corresponding_buf_idx_T_41 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_41 = _GEN_41[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_41 = {41'h0, _incoming_writes_io_deq_bits_data[63:41]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_42 = _corresponding_buf_idx_T + 8'h2A; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_42 = _corresponding_buf_idx_T_42 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_42 = _GEN_42[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_42 = {42'h0, _incoming_writes_io_deq_bits_data[63:42]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_43 = _corresponding_buf_idx_T + 8'h2B; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_43 = _corresponding_buf_idx_T_43 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_43 = _GEN_43[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_43 = {43'h0, _incoming_writes_io_deq_bits_data[63:43]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_44 = _corresponding_buf_idx_T + 8'h2C; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_44 = _corresponding_buf_idx_T_44 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_44 = _GEN_44[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_44 = {44'h0, _incoming_writes_io_deq_bits_data[63:44]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_45 = _corresponding_buf_idx_T + 8'h2D; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_45 = _corresponding_buf_idx_T_45 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_45 = _GEN_45[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_45 = {45'h0, _incoming_writes_io_deq_bits_data[63:45]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_46 = _corresponding_buf_idx_T + 8'h2E; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_46 = _corresponding_buf_idx_T_46 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_46 = _GEN_46[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_46 = {46'h0, _incoming_writes_io_deq_bits_data[63:46]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_47 = _corresponding_buf_idx_T + 8'h2F; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_47 = _corresponding_buf_idx_T_47 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_47 = _GEN_47[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_47 = {47'h0, _incoming_writes_io_deq_bits_data[63:47]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_48 = _corresponding_buf_idx_T + 8'h30; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_48 = _corresponding_buf_idx_T_48 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_48 = _GEN_48[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_48 = {48'h0, _incoming_writes_io_deq_bits_data[63:48]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_49 = _corresponding_buf_idx_T + 8'h31; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_49 = _corresponding_buf_idx_T_49 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_49 = _GEN_49[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_49 = {49'h0, _incoming_writes_io_deq_bits_data[63:49]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_50 = _corresponding_buf_idx_T + 8'h32; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_50 = _corresponding_buf_idx_T_50 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_50 = _GEN_50[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_50 = {50'h0, _incoming_writes_io_deq_bits_data[63:50]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_51 = _corresponding_buf_idx_T + 8'h33; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_51 = _corresponding_buf_idx_T_51 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_51 = _GEN_51[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_51 = {51'h0, _incoming_writes_io_deq_bits_data[63:51]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_52 = _corresponding_buf_idx_T + 8'h34; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_52 = _corresponding_buf_idx_T_52 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_52 = _GEN_52[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_52 = {52'h0, _incoming_writes_io_deq_bits_data[63:52]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_53 = _corresponding_buf_idx_T + 8'h35; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_53 = _corresponding_buf_idx_T_53 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_53 = _GEN_53[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_53 = {53'h0, _incoming_writes_io_deq_bits_data[63:53]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_54 = _corresponding_buf_idx_T + 8'h36; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_54 = _corresponding_buf_idx_T_54 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_54 = _GEN_54[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_54 = {54'h0, _incoming_writes_io_deq_bits_data[63:54]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_55 = _corresponding_buf_idx_T + 8'h37; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_55 = _corresponding_buf_idx_T_55 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_55 = _GEN_55[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_55 = {55'h0, _incoming_writes_io_deq_bits_data[63:55]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_56 = _corresponding_buf_idx_T + 8'h38; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_56 = _corresponding_buf_idx_T_56 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_56 = _GEN_56[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_56 = {56'h0, _incoming_writes_io_deq_bits_data[63:56]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_57 = _corresponding_buf_idx_T + 8'h39; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_57 = _corresponding_buf_idx_T_57 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_57 = _GEN_57[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_57 = {57'h0, _incoming_writes_io_deq_bits_data[63:57]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_58 = _corresponding_buf_idx_T + 8'h3A; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_58 = _corresponding_buf_idx_T_58 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_58 = _GEN_58[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_58 = {58'h0, _incoming_writes_io_deq_bits_data[63:58]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_59 = _corresponding_buf_idx_T + 8'h3B; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_59 = _corresponding_buf_idx_T_59 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_59 = _GEN_59[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_59 = {59'h0, _incoming_writes_io_deq_bits_data[63:59]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_60 = _corresponding_buf_idx_T + 8'h3C; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_60 = _corresponding_buf_idx_T_60 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_60 = _GEN_60[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_60 = {60'h0, _incoming_writes_io_deq_bits_data[63:60]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_61 = _corresponding_buf_idx_T + 8'h3D; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_61 = _corresponding_buf_idx_T_61 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_61 = _GEN_61[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_61 = {61'h0, _incoming_writes_io_deq_bits_data[63:61]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_62 = _corresponding_buf_idx_T + 8'h3E; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_62 = _corresponding_buf_idx_T_62 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_62 = _GEN_62[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_62 = {62'h0, _incoming_writes_io_deq_bits_data[63:62]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] wire [7:0] _corresponding_buf_idx_T_63 = _corresponding_buf_idx_T + 8'h3F; // @[CompressedBitsBuffer.scala:99:38] wire [7:0] _GEN_63 = _corresponding_buf_idx_T_63 % 8'h40; // @[CompressedBitsBuffer.scala:99:{38,58}] wire [6:0] corresponding_buf_idx_63 = _GEN_63[6:0]; // @[CompressedBitsBuffer.scala:99:58] wire [63:0] _write_data_bit_vec_T_63 = {63'h0, _incoming_writes_io_deq_bits_data[63]}; // @[CompressedBitsBuffer.scala:58:31, :100:83] assign write_data_bit_vec_0 = corresponding_buf_idx_63[5:0] == 6'h0 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h0 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h0 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h0 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h0 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h0 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h0 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h0 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h0 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h0 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h0 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h0 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h0 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h0 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h0 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h0 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h0 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h0 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h0 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h0 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h0 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h0 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h0 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h0 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h0 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h0 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h0 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h0 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h0 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h0 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h0 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h0 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h0 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h0 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h0 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h0 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h0 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h0 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h0 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h0 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h0 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h0 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h0 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h0 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h0 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h0 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h0 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h0 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h0 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h0 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h0 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h0 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h0 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h0 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h0 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h0 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h0 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h0 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h0 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h0 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h0 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h0 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h0 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h0 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_1 = corresponding_buf_idx_63[5:0] == 6'h1 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_2 = corresponding_buf_idx_63[5:0] == 6'h2 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_3 = corresponding_buf_idx_63[5:0] == 6'h3 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_4 = corresponding_buf_idx_63[5:0] == 6'h4 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h4 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h4 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h4 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h4 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h4 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h4 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h4 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h4 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h4 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h4 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h4 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h4 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h4 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h4 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h4 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h4 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h4 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h4 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h4 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h4 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h4 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h4 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h4 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h4 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h4 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h4 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h4 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h4 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h4 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h4 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h4 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h4 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h4 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h4 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h4 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h4 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h4 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h4 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h4 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h4 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h4 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h4 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h4 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h4 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h4 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h4 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h4 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h4 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h4 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h4 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h4 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h4 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h4 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h4 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h4 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h4 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h4 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h4 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h4 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h4 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h4 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h4 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h4 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_5 = corresponding_buf_idx_63[5:0] == 6'h5 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h5 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h5 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h5 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h5 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h5 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h5 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h5 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h5 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h5 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h5 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h5 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h5 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h5 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h5 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h5 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h5 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h5 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h5 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h5 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h5 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h5 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h5 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h5 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h5 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h5 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h5 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h5 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h5 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h5 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h5 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h5 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h5 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h5 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h5 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h5 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h5 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h5 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h5 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h5 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h5 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h5 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h5 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h5 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h5 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h5 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h5 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h5 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h5 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h5 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h5 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h5 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h5 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h5 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h5 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h5 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h5 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h5 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h5 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h5 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h5 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h5 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h5 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h5 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_6 = corresponding_buf_idx_63[5:0] == 6'h6 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h6 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h6 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h6 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h6 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h6 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h6 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h6 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h6 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h6 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h6 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h6 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h6 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h6 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h6 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h6 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h6 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h6 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h6 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h6 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h6 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h6 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h6 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h6 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h6 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h6 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h6 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h6 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h6 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h6 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h6 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h6 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h6 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h6 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h6 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h6 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h6 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h6 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h6 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h6 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h6 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h6 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h6 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h6 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h6 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h6 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h6 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h6 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h6 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h6 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h6 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h6 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h6 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h6 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h6 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h6 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h6 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h6 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h6 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h6 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h6 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h6 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h6 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h6 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_7 = corresponding_buf_idx_63[5:0] == 6'h7 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h7 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h7 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h7 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h7 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h7 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h7 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h7 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h7 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h7 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h7 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h7 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h7 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h7 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h7 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h7 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h7 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h7 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h7 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h7 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h7 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h7 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h7 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h7 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h7 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h7 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h7 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h7 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h7 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h7 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h7 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h7 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h7 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h7 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h7 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h7 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h7 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h7 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h7 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h7 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h7 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h7 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h7 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h7 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h7 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h7 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h7 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h7 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h7 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h7 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h7 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h7 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h7 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h7 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h7 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h7 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h7 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h7 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h7 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h7 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h7 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h7 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h7 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h7 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_8 = corresponding_buf_idx_63[5:0] == 6'h8 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h8 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h8 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h8 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h8 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h8 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h8 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h8 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h8 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h8 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h8 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h8 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h8 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h8 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h8 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h8 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h8 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h8 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h8 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h8 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h8 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h8 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h8 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h8 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h8 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h8 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h8 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h8 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h8 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h8 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h8 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h8 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h8 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h8 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h8 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h8 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h8 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h8 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h8 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h8 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h8 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h8 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h8 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h8 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h8 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h8 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h8 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h8 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h8 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h8 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h8 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h8 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h8 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h8 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h8 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h8 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h8 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h8 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h8 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h8 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h8 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h8 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h8 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h8 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_9 = corresponding_buf_idx_63[5:0] == 6'h9 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h9 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h9 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h9 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h9 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h9 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h9 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h9 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h9 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h9 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h9 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h9 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h9 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h9 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h9 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h9 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h9 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h9 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h9 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h9 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h9 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h9 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h9 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h9 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h9 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h9 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h9 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h9 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h9 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h9 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h9 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h9 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h9 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h9 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h9 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h9 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h9 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h9 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h9 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h9 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h9 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h9 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h9 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h9 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h9 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h9 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h9 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h9 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h9 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h9 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h9 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h9 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h9 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h9 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h9 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h9 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h9 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h9 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h9 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h9 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h9 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h9 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h9 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h9 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_10 = corresponding_buf_idx_63[5:0] == 6'hA ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hA ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hA ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hA ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hA ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hA ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hA ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hA ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hA ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hA ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hA ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hA ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hA ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hA ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hA ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hA ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hA ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hA ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hA ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hA ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hA ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hA ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hA ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hA ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hA ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hA ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hA ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hA ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hA ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hA ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hA ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hA ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hA ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hA ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hA ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hA ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hA ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hA ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hA ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hA ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hA ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hA ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hA ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hA ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hA ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hA ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hA ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hA ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hA ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hA ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hA ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hA ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hA ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hA ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hA ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hA ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hA ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hA ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hA ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hA ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hA ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hA ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hA ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hA & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_11 = corresponding_buf_idx_63[5:0] == 6'hB ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hB ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hB ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hB ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hB ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hB ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hB ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hB ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hB ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hB ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hB ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hB ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hB ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hB ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hB ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hB ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hB ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hB ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hB ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hB ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hB ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hB ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hB ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hB ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hB ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hB ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hB ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hB ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hB ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hB ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hB ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hB ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hB ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hB ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hB ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hB ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hB ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hB ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hB ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hB ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hB ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hB ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hB ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hB ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hB ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hB ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hB ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hB ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hB ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hB ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hB ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hB ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hB ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hB ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hB ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hB ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hB ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hB ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hB ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hB ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hB ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hB ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hB ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hB & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_12 = corresponding_buf_idx_63[5:0] == 6'hC ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hC ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hC ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hC ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hC ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hC ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hC ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hC ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hC ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hC ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hC ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hC ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hC ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hC ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hC ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hC ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hC ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hC ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hC ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hC ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hC ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hC ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hC ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hC ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hC ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hC ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hC ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hC ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hC ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hC ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hC ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hC ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hC ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hC ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hC ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hC ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hC ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hC ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hC ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hC ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hC ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hC ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hC ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hC ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hC ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hC ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hC ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hC ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hC ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hC ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hC ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hC ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hC ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hC ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hC ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hC ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hC ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hC ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hC ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hC ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hC ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hC ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hC ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hC & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_13 = corresponding_buf_idx_63[5:0] == 6'hD ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hD ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hD ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hD ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hD ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hD ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hD ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hD ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hD ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hD ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hD ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hD ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hD ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hD ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hD ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hD ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hD ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hD ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hD ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hD ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hD ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hD ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hD ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hD ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hD ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hD ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hD ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hD ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hD ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hD ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hD ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hD ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hD ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hD ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hD ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hD ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hD ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hD ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hD ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hD ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hD ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hD ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hD ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hD ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hD ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hD ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hD ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hD ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hD ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hD ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hD ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hD ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hD ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hD ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hD ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hD ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hD ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hD ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hD ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hD ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hD ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hD ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hD ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hD & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_14 = corresponding_buf_idx_63[5:0] == 6'hE ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hE ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hE ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hE ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hE ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hE ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hE ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hE ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hE ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hE ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hE ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hE ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hE ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hE ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hE ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hE ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hE ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hE ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hE ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hE ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hE ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hE ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hE ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hE ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hE ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hE ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hE ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hE ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hE ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hE ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hE ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hE ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hE ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hE ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hE ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hE ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hE ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hE ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hE ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hE ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hE ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hE ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hE ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hE ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hE ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hE ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hE ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hE ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hE ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hE ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hE ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hE ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hE ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hE ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hE ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hE ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hE ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hE ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hE ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hE ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hE ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hE ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hE ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hE & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_15 = corresponding_buf_idx_63[5:0] == 6'hF ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'hF ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'hF ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'hF ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'hF ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'hF ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'hF ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'hF ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'hF ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'hF ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'hF ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'hF ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'hF ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'hF ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'hF ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'hF ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'hF ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'hF ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'hF ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'hF ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'hF ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'hF ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'hF ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'hF ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'hF ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'hF ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'hF ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'hF ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'hF ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'hF ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'hF ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'hF ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'hF ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'hF ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'hF ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'hF ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'hF ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'hF ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'hF ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'hF ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'hF ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'hF ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'hF ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'hF ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'hF ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'hF ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'hF ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'hF ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'hF ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'hF ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'hF ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'hF ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'hF ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'hF ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'hF ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'hF ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'hF ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'hF ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'hF ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'hF ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'hF ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'hF ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'hF ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'hF & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_16 = corresponding_buf_idx_63[5:0] == 6'h10 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h10 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h10 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h10 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h10 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h10 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h10 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h10 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h10 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h10 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h10 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h10 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h10 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h10 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h10 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h10 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h10 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h10 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h10 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h10 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h10 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h10 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h10 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h10 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h10 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h10 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h10 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h10 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h10 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h10 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h10 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h10 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h10 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h10 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h10 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h10 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h10 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h10 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h10 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h10 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h10 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h10 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h10 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h10 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h10 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h10 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h10 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h10 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h10 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h10 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h10 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h10 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h10 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h10 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h10 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h10 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h10 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h10 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h10 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h10 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h10 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h10 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h10 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h10 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_17 = corresponding_buf_idx_63[5:0] == 6'h11 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h11 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h11 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h11 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h11 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h11 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h11 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h11 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h11 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h11 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h11 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h11 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h11 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h11 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h11 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h11 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h11 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h11 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h11 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h11 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h11 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h11 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h11 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h11 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h11 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h11 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h11 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h11 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h11 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h11 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h11 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h11 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h11 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h11 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h11 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h11 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h11 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h11 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h11 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h11 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h11 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h11 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h11 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h11 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h11 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h11 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h11 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h11 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h11 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h11 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h11 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h11 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h11 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h11 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h11 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h11 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h11 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h11 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h11 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h11 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h11 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h11 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h11 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h11 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_18 = corresponding_buf_idx_63[5:0] == 6'h12 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h12 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h12 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h12 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h12 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h12 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h12 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h12 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h12 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h12 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h12 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h12 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h12 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h12 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h12 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h12 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h12 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h12 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h12 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h12 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h12 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h12 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h12 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h12 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h12 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h12 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h12 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h12 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h12 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h12 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h12 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h12 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h12 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h12 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h12 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h12 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h12 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h12 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h12 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h12 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h12 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h12 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h12 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h12 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h12 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h12 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h12 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h12 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h12 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h12 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h12 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h12 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h12 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h12 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h12 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h12 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h12 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h12 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h12 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h12 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h12 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h12 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h12 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h12 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_19 = corresponding_buf_idx_63[5:0] == 6'h13 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h13 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h13 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h13 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h13 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h13 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h13 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h13 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h13 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h13 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h13 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h13 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h13 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h13 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h13 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h13 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h13 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h13 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h13 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h13 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h13 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h13 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h13 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h13 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h13 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h13 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h13 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h13 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h13 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h13 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h13 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h13 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h13 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h13 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h13 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h13 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h13 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h13 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h13 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h13 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h13 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h13 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h13 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h13 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h13 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h13 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h13 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h13 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h13 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h13 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h13 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h13 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h13 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h13 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h13 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h13 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h13 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h13 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h13 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h13 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h13 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h13 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h13 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h13 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_20 = corresponding_buf_idx_63[5:0] == 6'h14 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h14 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h14 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h14 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h14 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h14 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h14 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h14 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h14 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h14 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h14 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h14 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h14 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h14 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h14 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h14 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h14 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h14 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h14 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h14 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h14 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h14 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h14 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h14 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h14 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h14 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h14 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h14 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h14 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h14 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h14 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h14 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h14 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h14 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h14 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h14 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h14 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h14 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h14 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h14 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h14 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h14 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h14 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h14 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h14 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h14 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h14 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h14 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h14 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h14 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h14 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h14 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h14 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h14 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h14 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h14 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h14 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h14 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h14 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h14 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h14 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h14 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h14 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h14 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_21 = corresponding_buf_idx_63[5:0] == 6'h15 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h15 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h15 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h15 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h15 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h15 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h15 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h15 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h15 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h15 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h15 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h15 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h15 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h15 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h15 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h15 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h15 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h15 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h15 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h15 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h15 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h15 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h15 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h15 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h15 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h15 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h15 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h15 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h15 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h15 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h15 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h15 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h15 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h15 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h15 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h15 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h15 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h15 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h15 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h15 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h15 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h15 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h15 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h15 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h15 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h15 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h15 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h15 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h15 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h15 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h15 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h15 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h15 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h15 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h15 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h15 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h15 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h15 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h15 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h15 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h15 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h15 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h15 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h15 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_22 = corresponding_buf_idx_63[5:0] == 6'h16 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h16 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h16 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h16 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h16 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h16 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h16 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h16 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h16 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h16 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h16 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h16 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h16 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h16 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h16 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h16 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h16 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h16 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h16 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h16 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h16 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h16 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h16 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h16 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h16 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h16 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h16 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h16 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h16 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h16 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h16 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h16 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h16 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h16 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h16 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h16 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h16 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h16 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h16 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h16 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h16 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h16 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h16 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h16 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h16 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h16 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h16 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h16 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h16 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h16 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h16 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h16 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h16 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h16 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h16 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h16 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h16 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h16 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h16 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h16 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h16 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h16 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h16 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h16 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_23 = corresponding_buf_idx_63[5:0] == 6'h17 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h17 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h17 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h17 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h17 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h17 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h17 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h17 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h17 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h17 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h17 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h17 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h17 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h17 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h17 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h17 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h17 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h17 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h17 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h17 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h17 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h17 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h17 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h17 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h17 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h17 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h17 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h17 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h17 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h17 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h17 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h17 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h17 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h17 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h17 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h17 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h17 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h17 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h17 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h17 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h17 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h17 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h17 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h17 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h17 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h17 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h17 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h17 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h17 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h17 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h17 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h17 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h17 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h17 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h17 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h17 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h17 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h17 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h17 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h17 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h17 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h17 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h17 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h17 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_24 = corresponding_buf_idx_63[5:0] == 6'h18 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h18 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h18 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h18 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h18 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h18 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h18 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h18 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h18 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h18 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h18 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h18 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h18 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h18 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h18 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h18 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h18 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h18 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h18 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h18 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h18 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h18 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h18 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h18 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h18 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h18 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h18 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h18 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h18 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h18 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h18 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h18 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h18 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h18 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h18 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h18 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h18 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h18 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h18 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h18 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h18 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h18 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h18 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h18 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h18 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h18 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h18 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h18 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h18 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h18 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h18 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h18 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h18 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h18 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h18 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h18 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h18 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h18 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h18 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h18 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h18 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h18 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h18 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h18 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_25 = corresponding_buf_idx_63[5:0] == 6'h19 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h19 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h19 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h19 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h19 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h19 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h19 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h19 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h19 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h19 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h19 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h19 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h19 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h19 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h19 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h19 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h19 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h19 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h19 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h19 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h19 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h19 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h19 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h19 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h19 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h19 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h19 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h19 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h19 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h19 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h19 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h19 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h19 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h19 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h19 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h19 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h19 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h19 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h19 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h19 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h19 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h19 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h19 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h19 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h19 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h19 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h19 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h19 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h19 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h19 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h19 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h19 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h19 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h19 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h19 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h19 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h19 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h19 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h19 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h19 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h19 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h19 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h19 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h19 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_26 = corresponding_buf_idx_63[5:0] == 6'h1A ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1A ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1A ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1A ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1A ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1A ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1A ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1A ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1A ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1A ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1A ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1A ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1A ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1A ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1A ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1A ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1A ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1A ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1A ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1A ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1A ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1A ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1A ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1A ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1A ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1A ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1A ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1A ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1A ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1A ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1A ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1A ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1A ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1A ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1A ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1A ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1A ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1A ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1A ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1A ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1A ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1A ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1A ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1A ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1A ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1A ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1A ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1A ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1A ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1A ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1A ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1A ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1A ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1A ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1A ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1A ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1A ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1A ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1A ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1A ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1A ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1A ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1A ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1A & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_27 = corresponding_buf_idx_63[5:0] == 6'h1B ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1B ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1B ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1B ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1B ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1B ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1B ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1B ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1B ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1B ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1B ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1B ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1B ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1B ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1B ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1B ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1B ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1B ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1B ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1B ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1B ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1B ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1B ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1B ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1B ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1B ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1B ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1B ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1B ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1B ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1B ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1B ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1B ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1B ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1B ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1B ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1B ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1B ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1B ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1B ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1B ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1B ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1B ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1B ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1B ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1B ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1B ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1B ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1B ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1B ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1B ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1B ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1B ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1B ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1B ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1B ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1B ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1B ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1B ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1B ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1B ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1B ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1B ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1B & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_28 = corresponding_buf_idx_63[5:0] == 6'h1C ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1C ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1C ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1C ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1C ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1C ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1C ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1C ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1C ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1C ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1C ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1C ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1C ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1C ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1C ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1C ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1C ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1C ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1C ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1C ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1C ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1C ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1C ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1C ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1C ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1C ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1C ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1C ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1C ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1C ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1C ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1C ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1C ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1C ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1C ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1C ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1C ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1C ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1C ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1C ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1C ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1C ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1C ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1C ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1C ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1C ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1C ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1C ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1C ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1C ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1C ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1C ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1C ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1C ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1C ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1C ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1C ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1C ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1C ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1C ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1C ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1C ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1C ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1C & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_29 = corresponding_buf_idx_63[5:0] == 6'h1D ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1D ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1D ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1D ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1D ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1D ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1D ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1D ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1D ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1D ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1D ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1D ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1D ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1D ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1D ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1D ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1D ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1D ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1D ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1D ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1D ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1D ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1D ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1D ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1D ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1D ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1D ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1D ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1D ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1D ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1D ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1D ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1D ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1D ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1D ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1D ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1D ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1D ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1D ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1D ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1D ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1D ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1D ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1D ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1D ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1D ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1D ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1D ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1D ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1D ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1D ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1D ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1D ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1D ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1D ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1D ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1D ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1D ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1D ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1D ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1D ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1D ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1D ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1D & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_30 = corresponding_buf_idx_63[5:0] == 6'h1E ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1E ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1E ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1E ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1E ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1E ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1E ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1E ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1E ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1E ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1E ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1E ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1E ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1E ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1E ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1E ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1E ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1E ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1E ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1E ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1E ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1E ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1E ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1E ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1E ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1E ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1E ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1E ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1E ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1E ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1E ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1E ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1E ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1E ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1E ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1E ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1E ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1E ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1E ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1E ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1E ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1E ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1E ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1E ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1E ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1E ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1E ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1E ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1E ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1E ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1E ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1E ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1E ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1E ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1E ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1E ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1E ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1E ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1E ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1E ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1E ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1E ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1E ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1E & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_31 = corresponding_buf_idx_63[5:0] == 6'h1F ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h1F ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h1F ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h1F ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h1F ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h1F ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h1F ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h1F ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h1F ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h1F ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h1F ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h1F ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h1F ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h1F ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h1F ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h1F ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h1F ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h1F ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h1F ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h1F ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h1F ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h1F ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h1F ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h1F ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h1F ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h1F ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h1F ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h1F ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h1F ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h1F ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h1F ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h1F ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h1F ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h1F ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h1F ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h1F ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h1F ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h1F ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h1F ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h1F ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h1F ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h1F ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h1F ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h1F ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h1F ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h1F ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h1F ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h1F ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h1F ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h1F ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h1F ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h1F ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h1F ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h1F ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h1F ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h1F ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h1F ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h1F ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h1F ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h1F ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h1F ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h1F ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h1F ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h1F & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_32 = corresponding_buf_idx_63[5:0] == 6'h20 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h20 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h20 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h20 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h20 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h20 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h20 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h20 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h20 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h20 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h20 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h20 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h20 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h20 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h20 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h20 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h20 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h20 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h20 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h20 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h20 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h20 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h20 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h20 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h20 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h20 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h20 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h20 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h20 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h20 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h20 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h20 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h20 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h20 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h20 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h20 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h20 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h20 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h20 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h20 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h20 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h20 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h20 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h20 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h20 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h20 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h20 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h20 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h20 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h20 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h20 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h20 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h20 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h20 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h20 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h20 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h20 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h20 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h20 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h20 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h20 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h20 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h20 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h20 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_33 = corresponding_buf_idx_63[5:0] == 6'h21 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h21 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h21 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h21 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h21 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h21 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h21 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h21 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h21 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h21 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h21 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h21 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h21 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h21 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h21 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h21 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h21 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h21 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h21 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h21 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h21 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h21 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h21 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h21 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h21 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h21 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h21 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h21 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h21 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h21 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h21 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h21 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h21 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h21 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h21 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h21 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h21 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h21 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h21 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h21 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h21 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h21 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h21 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h21 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h21 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h21 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h21 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h21 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h21 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h21 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h21 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h21 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h21 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h21 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h21 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h21 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h21 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h21 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h21 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h21 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h21 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h21 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h21 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h21 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_34 = corresponding_buf_idx_63[5:0] == 6'h22 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h22 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h22 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h22 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h22 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h22 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h22 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h22 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h22 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h22 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h22 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h22 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h22 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h22 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h22 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h22 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h22 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h22 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h22 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h22 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h22 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h22 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h22 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h22 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h22 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h22 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h22 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h22 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h22 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h22 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h22 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h22 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h22 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h22 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h22 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h22 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h22 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h22 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h22 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h22 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h22 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h22 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h22 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h22 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h22 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h22 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h22 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h22 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h22 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h22 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h22 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h22 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h22 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h22 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h22 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h22 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h22 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h22 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h22 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h22 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h22 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h22 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h22 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h22 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_35 = corresponding_buf_idx_63[5:0] == 6'h23 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h23 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h23 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h23 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h23 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h23 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h23 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h23 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h23 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h23 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h23 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h23 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h23 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h23 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h23 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h23 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h23 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h23 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h23 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h23 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h23 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h23 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h23 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h23 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h23 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h23 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h23 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h23 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h23 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h23 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h23 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h23 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h23 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h23 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h23 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h23 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h23 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h23 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h23 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h23 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h23 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h23 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h23 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h23 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h23 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h23 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h23 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h23 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h23 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h23 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h23 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h23 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h23 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h23 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h23 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h23 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h23 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h23 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h23 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h23 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h23 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h23 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h23 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h23 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_36 = corresponding_buf_idx_63[5:0] == 6'h24 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h24 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h24 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h24 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h24 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h24 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h24 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h24 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h24 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h24 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h24 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h24 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h24 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h24 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h24 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h24 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h24 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h24 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h24 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h24 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h24 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h24 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h24 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h24 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h24 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h24 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h24 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h24 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h24 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h24 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h24 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h24 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h24 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h24 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h24 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h24 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h24 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h24 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h24 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h24 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h24 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h24 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h24 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h24 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h24 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h24 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h24 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h24 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h24 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h24 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h24 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h24 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h24 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h24 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h24 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h24 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h24 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h24 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h24 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h24 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h24 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h24 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h24 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h24 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_37 = corresponding_buf_idx_63[5:0] == 6'h25 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h25 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h25 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h25 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h25 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h25 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h25 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h25 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h25 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h25 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h25 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h25 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h25 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h25 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h25 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h25 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h25 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h25 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h25 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h25 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h25 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h25 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h25 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h25 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h25 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h25 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h25 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h25 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h25 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h25 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h25 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h25 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h25 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h25 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h25 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h25 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h25 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h25 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h25 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h25 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h25 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h25 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h25 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h25 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h25 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h25 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h25 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h25 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h25 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h25 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h25 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h25 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h25 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h25 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h25 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h25 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h25 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h25 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h25 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h25 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h25 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h25 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h25 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h25 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_38 = corresponding_buf_idx_63[5:0] == 6'h26 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h26 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h26 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h26 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h26 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h26 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h26 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h26 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h26 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h26 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h26 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h26 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h26 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h26 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h26 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h26 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h26 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h26 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h26 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h26 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h26 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h26 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h26 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h26 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h26 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h26 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h26 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h26 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h26 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h26 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h26 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h26 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h26 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h26 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h26 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h26 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h26 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h26 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h26 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h26 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h26 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h26 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h26 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h26 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h26 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h26 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h26 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h26 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h26 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h26 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h26 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h26 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h26 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h26 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h26 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h26 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h26 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h26 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h26 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h26 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h26 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h26 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h26 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h26 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_39 = corresponding_buf_idx_63[5:0] == 6'h27 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h27 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h27 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h27 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h27 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h27 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h27 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h27 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h27 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h27 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h27 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h27 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h27 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h27 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h27 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h27 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h27 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h27 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h27 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h27 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h27 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h27 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h27 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h27 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h27 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h27 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h27 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h27 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h27 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h27 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h27 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h27 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h27 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h27 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h27 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h27 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h27 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h27 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h27 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h27 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h27 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h27 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h27 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h27 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h27 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h27 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h27 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h27 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h27 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h27 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h27 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h27 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h27 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h27 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h27 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h27 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h27 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h27 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h27 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h27 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h27 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h27 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h27 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h27 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_40 = corresponding_buf_idx_63[5:0] == 6'h28 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h28 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h28 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h28 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h28 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h28 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h28 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h28 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h28 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h28 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h28 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h28 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h28 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h28 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h28 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h28 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h28 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h28 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h28 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h28 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h28 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h28 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h28 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h28 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h28 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h28 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h28 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h28 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h28 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h28 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h28 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h28 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h28 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h28 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h28 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h28 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h28 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h28 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h28 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h28 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h28 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h28 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h28 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h28 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h28 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h28 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h28 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h28 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h28 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h28 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h28 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h28 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h28 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h28 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h28 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h28 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h28 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h28 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h28 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h28 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h28 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h28 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h28 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h28 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_41 = corresponding_buf_idx_63[5:0] == 6'h29 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h29 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h29 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h29 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h29 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h29 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h29 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h29 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h29 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h29 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h29 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h29 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h29 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h29 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h29 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h29 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h29 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h29 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h29 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h29 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h29 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h29 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h29 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h29 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h29 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h29 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h29 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h29 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h29 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h29 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h29 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h29 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h29 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h29 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h29 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h29 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h29 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h29 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h29 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h29 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h29 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h29 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h29 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h29 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h29 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h29 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h29 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h29 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h29 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h29 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h29 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h29 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h29 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h29 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h29 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h29 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h29 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h29 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h29 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h29 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h29 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h29 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h29 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h29 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_42 = corresponding_buf_idx_63[5:0] == 6'h2A ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2A ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2A ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2A ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2A ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2A ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2A ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2A ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2A ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2A ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2A ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2A ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2A ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2A ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2A ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2A ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2A ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2A ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2A ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2A ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2A ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2A ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2A ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2A ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2A ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2A ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2A ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2A ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2A ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2A ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2A ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2A ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2A ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2A ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2A ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2A ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2A ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2A ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2A ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2A ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2A ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2A ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2A ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2A ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2A ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2A ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2A ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2A ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2A ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2A ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2A ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2A ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2A ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2A ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2A ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2A ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2A ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2A ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2A ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2A ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2A ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2A ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2A ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2A & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_43 = corresponding_buf_idx_63[5:0] == 6'h2B ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2B ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2B ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2B ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2B ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2B ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2B ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2B ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2B ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2B ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2B ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2B ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2B ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2B ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2B ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2B ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2B ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2B ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2B ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2B ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2B ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2B ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2B ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2B ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2B ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2B ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2B ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2B ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2B ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2B ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2B ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2B ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2B ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2B ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2B ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2B ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2B ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2B ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2B ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2B ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2B ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2B ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2B ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2B ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2B ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2B ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2B ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2B ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2B ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2B ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2B ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2B ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2B ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2B ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2B ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2B ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2B ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2B ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2B ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2B ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2B ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2B ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2B ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2B & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_44 = corresponding_buf_idx_63[5:0] == 6'h2C ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2C ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2C ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2C ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2C ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2C ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2C ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2C ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2C ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2C ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2C ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2C ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2C ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2C ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2C ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2C ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2C ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2C ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2C ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2C ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2C ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2C ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2C ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2C ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2C ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2C ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2C ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2C ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2C ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2C ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2C ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2C ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2C ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2C ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2C ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2C ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2C ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2C ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2C ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2C ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2C ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2C ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2C ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2C ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2C ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2C ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2C ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2C ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2C ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2C ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2C ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2C ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2C ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2C ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2C ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2C ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2C ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2C ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2C ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2C ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2C ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2C ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2C ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2C & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_45 = corresponding_buf_idx_63[5:0] == 6'h2D ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2D ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2D ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2D ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2D ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2D ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2D ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2D ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2D ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2D ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2D ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2D ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2D ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2D ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2D ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2D ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2D ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2D ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2D ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2D ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2D ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2D ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2D ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2D ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2D ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2D ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2D ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2D ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2D ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2D ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2D ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2D ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2D ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2D ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2D ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2D ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2D ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2D ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2D ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2D ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2D ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2D ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2D ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2D ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2D ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2D ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2D ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2D ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2D ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2D ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2D ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2D ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2D ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2D ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2D ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2D ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2D ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2D ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2D ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2D ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2D ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2D ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2D ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2D & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_46 = corresponding_buf_idx_63[5:0] == 6'h2E ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2E ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2E ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2E ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2E ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2E ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2E ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2E ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2E ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2E ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2E ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2E ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2E ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2E ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2E ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2E ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2E ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2E ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2E ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2E ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2E ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2E ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2E ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2E ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2E ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2E ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2E ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2E ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2E ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2E ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2E ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2E ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2E ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2E ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2E ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2E ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2E ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2E ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2E ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2E ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2E ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2E ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2E ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2E ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2E ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2E ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2E ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2E ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2E ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2E ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2E ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2E ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2E ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2E ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2E ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2E ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2E ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2E ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2E ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2E ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2E ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2E ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2E ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2E & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_47 = corresponding_buf_idx_63[5:0] == 6'h2F ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h2F ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h2F ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h2F ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h2F ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h2F ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h2F ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h2F ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h2F ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h2F ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h2F ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h2F ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h2F ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h2F ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h2F ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h2F ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h2F ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h2F ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h2F ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h2F ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h2F ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h2F ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h2F ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h2F ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h2F ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h2F ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h2F ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h2F ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h2F ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h2F ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h2F ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h2F ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h2F ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h2F ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h2F ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h2F ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h2F ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h2F ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h2F ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h2F ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h2F ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h2F ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h2F ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h2F ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h2F ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h2F ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h2F ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h2F ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h2F ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h2F ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h2F ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h2F ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h2F ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h2F ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h2F ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h2F ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h2F ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h2F ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h2F ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h2F ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h2F ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h2F ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h2F ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h2F & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_48 = corresponding_buf_idx_63[5:0] == 6'h30 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h30 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h30 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h30 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h30 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h30 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h30 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h30 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h30 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h30 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h30 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h30 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h30 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h30 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h30 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h30 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h30 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h30 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h30 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h30 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h30 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h30 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h30 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h30 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h30 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h30 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h30 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h30 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h30 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h30 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h30 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h30 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h30 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h30 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h30 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h30 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h30 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h30 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h30 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h30 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h30 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h30 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h30 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h30 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h30 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h30 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h30 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h30 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h30 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h30 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h30 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h30 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h30 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h30 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h30 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h30 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h30 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h30 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h30 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h30 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h30 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h30 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h30 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h30 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_49 = corresponding_buf_idx_63[5:0] == 6'h31 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h31 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h31 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h31 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h31 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h31 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h31 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h31 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h31 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h31 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h31 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h31 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h31 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h31 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h31 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h31 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h31 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h31 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h31 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h31 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h31 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h31 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h31 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h31 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h31 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h31 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h31 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h31 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h31 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h31 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h31 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h31 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h31 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h31 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h31 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h31 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h31 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h31 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h31 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h31 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h31 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h31 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h31 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h31 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h31 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h31 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h31 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h31 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h31 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h31 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h31 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h31 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h31 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h31 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h31 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h31 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h31 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h31 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h31 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h31 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h31 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h31 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h31 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h31 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_50 = corresponding_buf_idx_63[5:0] == 6'h32 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h32 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h32 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h32 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h32 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h32 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h32 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h32 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h32 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h32 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h32 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h32 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h32 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h32 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h32 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h32 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h32 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h32 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h32 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h32 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h32 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h32 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h32 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h32 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h32 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h32 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h32 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h32 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h32 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h32 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h32 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h32 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h32 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h32 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h32 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h32 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h32 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h32 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h32 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h32 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h32 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h32 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h32 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h32 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h32 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h32 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h32 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h32 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h32 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h32 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h32 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h32 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h32 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h32 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h32 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h32 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h32 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h32 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h32 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h32 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h32 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h32 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h32 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h32 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_51 = corresponding_buf_idx_63[5:0] == 6'h33 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h33 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h33 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h33 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h33 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h33 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h33 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h33 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h33 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h33 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h33 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h33 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h33 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h33 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h33 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h33 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h33 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h33 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h33 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h33 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h33 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h33 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h33 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h33 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h33 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h33 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h33 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h33 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h33 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h33 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h33 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h33 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h33 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h33 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h33 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h33 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h33 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h33 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h33 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h33 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h33 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h33 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h33 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h33 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h33 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h33 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h33 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h33 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h33 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h33 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h33 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h33 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h33 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h33 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h33 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h33 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h33 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h33 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h33 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h33 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h33 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h33 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h33 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h33 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_52 = corresponding_buf_idx_63[5:0] == 6'h34 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h34 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h34 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h34 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h34 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h34 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h34 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h34 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h34 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h34 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h34 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h34 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h34 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h34 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h34 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h34 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h34 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h34 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h34 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h34 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h34 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h34 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h34 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h34 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h34 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h34 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h34 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h34 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h34 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h34 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h34 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h34 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h34 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h34 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h34 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h34 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h34 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h34 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h34 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h34 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h34 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h34 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h34 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h34 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h34 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h34 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h34 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h34 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h34 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h34 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h34 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h34 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h34 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h34 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h34 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h34 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h34 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h34 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h34 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h34 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h34 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h34 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h34 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h34 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_53 = corresponding_buf_idx_63[5:0] == 6'h35 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h35 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h35 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h35 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h35 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h35 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h35 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h35 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h35 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h35 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h35 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h35 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h35 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h35 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h35 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h35 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h35 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h35 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h35 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h35 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h35 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h35 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h35 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h35 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h35 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h35 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h35 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h35 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h35 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h35 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h35 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h35 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h35 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h35 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h35 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h35 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h35 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h35 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h35 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h35 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h35 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h35 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h35 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h35 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h35 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h35 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h35 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h35 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h35 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h35 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h35 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h35 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h35 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h35 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h35 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h35 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h35 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h35 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h35 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h35 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h35 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h35 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h35 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h35 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_54 = corresponding_buf_idx_63[5:0] == 6'h36 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h36 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h36 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h36 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h36 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h36 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h36 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h36 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h36 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h36 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h36 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h36 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h36 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h36 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h36 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h36 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h36 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h36 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h36 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h36 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h36 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h36 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h36 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h36 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h36 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h36 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h36 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h36 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h36 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h36 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h36 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h36 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h36 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h36 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h36 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h36 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h36 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h36 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h36 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h36 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h36 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h36 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h36 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h36 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h36 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h36 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h36 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h36 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h36 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h36 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h36 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h36 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h36 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h36 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h36 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h36 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h36 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h36 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h36 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h36 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h36 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h36 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h36 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h36 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_55 = corresponding_buf_idx_63[5:0] == 6'h37 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h37 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h37 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h37 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h37 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h37 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h37 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h37 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h37 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h37 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h37 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h37 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h37 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h37 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h37 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h37 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h37 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h37 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h37 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h37 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h37 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h37 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h37 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h37 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h37 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h37 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h37 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h37 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h37 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h37 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h37 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h37 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h37 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h37 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h37 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h37 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h37 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h37 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h37 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h37 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h37 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h37 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h37 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h37 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h37 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h37 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h37 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h37 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h37 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h37 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h37 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h37 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h37 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h37 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h37 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h37 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h37 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h37 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h37 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h37 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h37 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h37 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h37 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h37 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_56 = corresponding_buf_idx_63[5:0] == 6'h38 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h38 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h38 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h38 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h38 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h38 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h38 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h38 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h38 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h38 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h38 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h38 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h38 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h38 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h38 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h38 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h38 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h38 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h38 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h38 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h38 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h38 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h38 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h38 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h38 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h38 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h38 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h38 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h38 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h38 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h38 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h38 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h38 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h38 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h38 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h38 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h38 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h38 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h38 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h38 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h38 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h38 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h38 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h38 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h38 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h38 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h38 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h38 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h38 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h38 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h38 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h38 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h38 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h38 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h38 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h38 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h38 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h38 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h38 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h38 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h38 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h38 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h38 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h38 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_57 = corresponding_buf_idx_63[5:0] == 6'h39 ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h39 ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h39 ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h39 ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h39 ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h39 ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h39 ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h39 ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h39 ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h39 ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h39 ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h39 ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h39 ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h39 ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h39 ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h39 ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h39 ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h39 ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h39 ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h39 ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h39 ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h39 ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h39 ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h39 ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h39 ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h39 ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h39 ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h39 ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h39 ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h39 ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h39 ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h39 ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h39 ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h39 ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h39 ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h39 ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h39 ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h39 ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h39 ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h39 ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h39 ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h39 ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h39 ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h39 ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h39 ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h39 ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h39 ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h39 ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h39 ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h39 ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h39 ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h39 ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h39 ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h39 ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h39 ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h39 ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h39 ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h39 ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h39 ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h39 ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h39 ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h39 ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h39 ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h39 & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_58 = corresponding_buf_idx_63[5:0] == 6'h3A ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3A ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3A ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3A ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3A ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3A ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3A ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3A ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3A ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3A ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3A ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3A ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3A ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3A ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3A ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3A ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3A ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3A ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3A ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3A ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3A ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3A ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3A ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3A ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3A ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3A ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3A ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3A ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3A ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3A ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3A ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3A ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3A ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3A ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3A ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3A ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3A ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3A ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3A ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3A ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3A ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3A ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3A ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3A ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3A ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3A ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3A ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3A ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3A ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3A ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3A ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3A ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3A ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3A ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3A ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3A ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3A ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3A ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3A ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3A ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3A ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3A ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3A ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3A & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_59 = corresponding_buf_idx_63[5:0] == 6'h3B ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3B ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3B ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3B ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3B ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3B ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3B ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3B ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3B ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3B ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3B ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3B ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3B ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3B ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3B ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3B ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3B ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3B ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3B ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3B ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3B ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3B ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3B ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3B ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3B ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3B ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3B ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3B ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3B ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3B ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3B ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3B ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3B ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3B ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3B ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3B ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3B ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3B ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3B ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3B ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3B ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3B ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3B ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3B ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3B ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3B ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3B ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3B ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3B ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3B ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3B ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3B ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3B ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3B ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3B ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3B ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3B ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3B ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3B ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3B ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3B ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3B ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3B ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3B & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_60 = corresponding_buf_idx_63[5:0] == 6'h3C ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3C ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3C ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3C ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3C ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3C ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3C ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3C ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3C ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3C ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3C ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3C ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3C ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3C ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3C ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3C ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3C ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3C ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3C ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3C ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3C ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3C ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3C ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3C ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3C ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3C ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3C ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3C ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3C ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3C ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3C ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3C ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3C ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3C ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3C ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3C ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3C ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3C ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3C ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3C ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3C ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3C ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3C ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3C ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3C ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3C ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3C ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3C ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3C ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3C ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3C ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3C ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3C ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3C ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3C ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3C ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3C ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3C ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3C ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3C ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3C ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3C ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3C ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3C & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_61 = corresponding_buf_idx_63[5:0] == 6'h3D ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3D ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3D ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3D ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3D ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3D ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3D ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3D ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3D ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3D ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3D ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3D ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3D ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3D ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3D ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3D ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3D ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3D ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3D ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3D ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3D ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3D ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3D ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3D ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3D ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3D ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3D ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3D ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3D ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3D ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3D ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3D ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3D ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3D ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3D ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3D ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3D ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3D ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3D ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3D ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3D ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3D ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3D ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3D ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3D ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3D ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3D ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3D ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3D ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3D ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3D ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3D ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3D ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3D ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3D ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3D ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3D ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3D ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3D ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3D ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3D ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3D ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3D ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3D & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_62 = corresponding_buf_idx_63[5:0] == 6'h3E ? _write_data_bit_vec_T_63[0] : corresponding_buf_idx_62[5:0] == 6'h3E ? _write_data_bit_vec_T_62[0] : corresponding_buf_idx_61[5:0] == 6'h3E ? _write_data_bit_vec_T_61[0] : corresponding_buf_idx_60[5:0] == 6'h3E ? _write_data_bit_vec_T_60[0] : corresponding_buf_idx_59[5:0] == 6'h3E ? _write_data_bit_vec_T_59[0] : corresponding_buf_idx_58[5:0] == 6'h3E ? _write_data_bit_vec_T_58[0] : corresponding_buf_idx_57[5:0] == 6'h3E ? _write_data_bit_vec_T_57[0] : corresponding_buf_idx_56[5:0] == 6'h3E ? _write_data_bit_vec_T_56[0] : corresponding_buf_idx_55[5:0] == 6'h3E ? _write_data_bit_vec_T_55[0] : corresponding_buf_idx_54[5:0] == 6'h3E ? _write_data_bit_vec_T_54[0] : corresponding_buf_idx_53[5:0] == 6'h3E ? _write_data_bit_vec_T_53[0] : corresponding_buf_idx_52[5:0] == 6'h3E ? _write_data_bit_vec_T_52[0] : corresponding_buf_idx_51[5:0] == 6'h3E ? _write_data_bit_vec_T_51[0] : corresponding_buf_idx_50[5:0] == 6'h3E ? _write_data_bit_vec_T_50[0] : corresponding_buf_idx_49[5:0] == 6'h3E ? _write_data_bit_vec_T_49[0] : corresponding_buf_idx_48[5:0] == 6'h3E ? _write_data_bit_vec_T_48[0] : corresponding_buf_idx_47[5:0] == 6'h3E ? _write_data_bit_vec_T_47[0] : corresponding_buf_idx_46[5:0] == 6'h3E ? _write_data_bit_vec_T_46[0] : corresponding_buf_idx_45[5:0] == 6'h3E ? _write_data_bit_vec_T_45[0] : corresponding_buf_idx_44[5:0] == 6'h3E ? _write_data_bit_vec_T_44[0] : corresponding_buf_idx_43[5:0] == 6'h3E ? _write_data_bit_vec_T_43[0] : corresponding_buf_idx_42[5:0] == 6'h3E ? _write_data_bit_vec_T_42[0] : corresponding_buf_idx_41[5:0] == 6'h3E ? _write_data_bit_vec_T_41[0] : corresponding_buf_idx_40[5:0] == 6'h3E ? _write_data_bit_vec_T_40[0] : corresponding_buf_idx_39[5:0] == 6'h3E ? _write_data_bit_vec_T_39[0] : corresponding_buf_idx_38[5:0] == 6'h3E ? _write_data_bit_vec_T_38[0] : corresponding_buf_idx_37[5:0] == 6'h3E ? _write_data_bit_vec_T_37[0] : corresponding_buf_idx_36[5:0] == 6'h3E ? _write_data_bit_vec_T_36[0] : corresponding_buf_idx_35[5:0] == 6'h3E ? _write_data_bit_vec_T_35[0] : corresponding_buf_idx_34[5:0] == 6'h3E ? _write_data_bit_vec_T_34[0] : corresponding_buf_idx_33[5:0] == 6'h3E ? _write_data_bit_vec_T_33[0] : corresponding_buf_idx_32[5:0] == 6'h3E ? _write_data_bit_vec_T_32[0] : corresponding_buf_idx_31[5:0] == 6'h3E ? _write_data_bit_vec_T_31[0] : corresponding_buf_idx_30[5:0] == 6'h3E ? _write_data_bit_vec_T_30[0] : corresponding_buf_idx_29[5:0] == 6'h3E ? _write_data_bit_vec_T_29[0] : corresponding_buf_idx_28[5:0] == 6'h3E ? _write_data_bit_vec_T_28[0] : corresponding_buf_idx_27[5:0] == 6'h3E ? _write_data_bit_vec_T_27[0] : corresponding_buf_idx_26[5:0] == 6'h3E ? _write_data_bit_vec_T_26[0] : corresponding_buf_idx_25[5:0] == 6'h3E ? _write_data_bit_vec_T_25[0] : corresponding_buf_idx_24[5:0] == 6'h3E ? _write_data_bit_vec_T_24[0] : corresponding_buf_idx_23[5:0] == 6'h3E ? _write_data_bit_vec_T_23[0] : corresponding_buf_idx_22[5:0] == 6'h3E ? _write_data_bit_vec_T_22[0] : corresponding_buf_idx_21[5:0] == 6'h3E ? _write_data_bit_vec_T_21[0] : corresponding_buf_idx_20[5:0] == 6'h3E ? _write_data_bit_vec_T_20[0] : corresponding_buf_idx_19[5:0] == 6'h3E ? _write_data_bit_vec_T_19[0] : corresponding_buf_idx_18[5:0] == 6'h3E ? _write_data_bit_vec_T_18[0] : corresponding_buf_idx_17[5:0] == 6'h3E ? _write_data_bit_vec_T_17[0] : corresponding_buf_idx_16[5:0] == 6'h3E ? _write_data_bit_vec_T_16[0] : corresponding_buf_idx_15[5:0] == 6'h3E ? _write_data_bit_vec_T_15[0] : corresponding_buf_idx_14[5:0] == 6'h3E ? _write_data_bit_vec_T_14[0] : corresponding_buf_idx_13[5:0] == 6'h3E ? _write_data_bit_vec_T_13[0] : corresponding_buf_idx_12[5:0] == 6'h3E ? _write_data_bit_vec_T_12[0] : corresponding_buf_idx_11[5:0] == 6'h3E ? _write_data_bit_vec_T_11[0] : corresponding_buf_idx_10[5:0] == 6'h3E ? _write_data_bit_vec_T_10[0] : corresponding_buf_idx_9[5:0] == 6'h3E ? _write_data_bit_vec_T_9[0] : corresponding_buf_idx_8[5:0] == 6'h3E ? _write_data_bit_vec_T_8[0] : corresponding_buf_idx_7[5:0] == 6'h3E ? _write_data_bit_vec_T_7[0] : corresponding_buf_idx_6[5:0] == 6'h3E ? _write_data_bit_vec_T_6[0] : corresponding_buf_idx_5[5:0] == 6'h3E ? _write_data_bit_vec_T_5[0] : corresponding_buf_idx_4[5:0] == 6'h3E ? _write_data_bit_vec_T_4[0] : corresponding_buf_idx_3[5:0] == 6'h3E ? _write_data_bit_vec_T_3[0] : corresponding_buf_idx_2[5:0] == 6'h3E ? _write_data_bit_vec_T_2[0] : corresponding_buf_idx_1[5:0] == 6'h3E ? _write_data_bit_vec_T_1[0] : corresponding_buf_idx[5:0] == 6'h3E & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] assign write_data_bit_vec_63 = (&(corresponding_buf_idx_63[5:0])) ? _write_data_bit_vec_T_63[0] : (&(corresponding_buf_idx_62[5:0])) ? _write_data_bit_vec_T_62[0] : (&(corresponding_buf_idx_61[5:0])) ? _write_data_bit_vec_T_61[0] : (&(corresponding_buf_idx_60[5:0])) ? _write_data_bit_vec_T_60[0] : (&(corresponding_buf_idx_59[5:0])) ? _write_data_bit_vec_T_59[0] : (&(corresponding_buf_idx_58[5:0])) ? _write_data_bit_vec_T_58[0] : (&(corresponding_buf_idx_57[5:0])) ? _write_data_bit_vec_T_57[0] : (&(corresponding_buf_idx_56[5:0])) ? _write_data_bit_vec_T_56[0] : (&(corresponding_buf_idx_55[5:0])) ? _write_data_bit_vec_T_55[0] : (&(corresponding_buf_idx_54[5:0])) ? _write_data_bit_vec_T_54[0] : (&(corresponding_buf_idx_53[5:0])) ? _write_data_bit_vec_T_53[0] : (&(corresponding_buf_idx_52[5:0])) ? _write_data_bit_vec_T_52[0] : (&(corresponding_buf_idx_51[5:0])) ? _write_data_bit_vec_T_51[0] : (&(corresponding_buf_idx_50[5:0])) ? _write_data_bit_vec_T_50[0] : (&(corresponding_buf_idx_49[5:0])) ? _write_data_bit_vec_T_49[0] : (&(corresponding_buf_idx_48[5:0])) ? _write_data_bit_vec_T_48[0] : (&(corresponding_buf_idx_47[5:0])) ? _write_data_bit_vec_T_47[0] : (&(corresponding_buf_idx_46[5:0])) ? _write_data_bit_vec_T_46[0] : (&(corresponding_buf_idx_45[5:0])) ? _write_data_bit_vec_T_45[0] : (&(corresponding_buf_idx_44[5:0])) ? _write_data_bit_vec_T_44[0] : (&(corresponding_buf_idx_43[5:0])) ? _write_data_bit_vec_T_43[0] : (&(corresponding_buf_idx_42[5:0])) ? _write_data_bit_vec_T_42[0] : (&(corresponding_buf_idx_41[5:0])) ? _write_data_bit_vec_T_41[0] : (&(corresponding_buf_idx_40[5:0])) ? _write_data_bit_vec_T_40[0] : (&(corresponding_buf_idx_39[5:0])) ? _write_data_bit_vec_T_39[0] : (&(corresponding_buf_idx_38[5:0])) ? _write_data_bit_vec_T_38[0] : (&(corresponding_buf_idx_37[5:0])) ? _write_data_bit_vec_T_37[0] : (&(corresponding_buf_idx_36[5:0])) ? _write_data_bit_vec_T_36[0] : (&(corresponding_buf_idx_35[5:0])) ? _write_data_bit_vec_T_35[0] : (&(corresponding_buf_idx_34[5:0])) ? _write_data_bit_vec_T_34[0] : (&(corresponding_buf_idx_33[5:0])) ? _write_data_bit_vec_T_33[0] : (&(corresponding_buf_idx_32[5:0])) ? _write_data_bit_vec_T_32[0] : (&(corresponding_buf_idx_31[5:0])) ? _write_data_bit_vec_T_31[0] : (&(corresponding_buf_idx_30[5:0])) ? _write_data_bit_vec_T_30[0] : (&(corresponding_buf_idx_29[5:0])) ? _write_data_bit_vec_T_29[0] : (&(corresponding_buf_idx_28[5:0])) ? _write_data_bit_vec_T_28[0] : (&(corresponding_buf_idx_27[5:0])) ? _write_data_bit_vec_T_27[0] : (&(corresponding_buf_idx_26[5:0])) ? _write_data_bit_vec_T_26[0] : (&(corresponding_buf_idx_25[5:0])) ? _write_data_bit_vec_T_25[0] : (&(corresponding_buf_idx_24[5:0])) ? _write_data_bit_vec_T_24[0] : (&(corresponding_buf_idx_23[5:0])) ? _write_data_bit_vec_T_23[0] : (&(corresponding_buf_idx_22[5:0])) ? _write_data_bit_vec_T_22[0] : (&(corresponding_buf_idx_21[5:0])) ? _write_data_bit_vec_T_21[0] : (&(corresponding_buf_idx_20[5:0])) ? _write_data_bit_vec_T_20[0] : (&(corresponding_buf_idx_19[5:0])) ? _write_data_bit_vec_T_19[0] : (&(corresponding_buf_idx_18[5:0])) ? _write_data_bit_vec_T_18[0] : (&(corresponding_buf_idx_17[5:0])) ? _write_data_bit_vec_T_17[0] : (&(corresponding_buf_idx_16[5:0])) ? _write_data_bit_vec_T_16[0] : (&(corresponding_buf_idx_15[5:0])) ? _write_data_bit_vec_T_15[0] : (&(corresponding_buf_idx_14[5:0])) ? _write_data_bit_vec_T_14[0] : (&(corresponding_buf_idx_13[5:0])) ? _write_data_bit_vec_T_13[0] : (&(corresponding_buf_idx_12[5:0])) ? _write_data_bit_vec_T_12[0] : (&(corresponding_buf_idx_11[5:0])) ? _write_data_bit_vec_T_11[0] : (&(corresponding_buf_idx_10[5:0])) ? _write_data_bit_vec_T_10[0] : (&(corresponding_buf_idx_9[5:0])) ? _write_data_bit_vec_T_9[0] : (&(corresponding_buf_idx_8[5:0])) ? _write_data_bit_vec_T_8[0] : (&(corresponding_buf_idx_7[5:0])) ? _write_data_bit_vec_T_7[0] : (&(corresponding_buf_idx_6[5:0])) ? _write_data_bit_vec_T_6[0] : (&(corresponding_buf_idx_5[5:0])) ? _write_data_bit_vec_T_5[0] : (&(corresponding_buf_idx_4[5:0])) ? _write_data_bit_vec_T_4[0] : (&(corresponding_buf_idx_3[5:0])) ? _write_data_bit_vec_T_3[0] : (&(corresponding_buf_idx_2[5:0])) ? _write_data_bit_vec_T_2[0] : (&(corresponding_buf_idx_1[5:0])) ? _write_data_bit_vec_T_1[0] : (&(corresponding_buf_idx[5:0])) & _write_data_bit_vec_T[0]; // @[CompressedBitsBuffer.scala:96:32, :97:37, :99:58, :100:{47,83}] wire _use_this_queue_T = |wrap_len_idx_end; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_64 = write_start_idx == 7'h0; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_1; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_1 = _GEN_64; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_3; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_3 = _GEN_64; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_4 = |wrap_len_idx_end; // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_6 = |(wrap_len_idx_end[6:1]); // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_65 = write_start_idx < 7'h2; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_7; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_7 = _GEN_65; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_9; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_9 = _GEN_65; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_10 = |(wrap_len_idx_end[6:1]); // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_66 = wrap_len_idx_end > 7'h2; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_12; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_12 = _GEN_66; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_16; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_16 = _GEN_66; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_67 = write_start_idx < 7'h3; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_13; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_13 = _GEN_67; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_15; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_15 = _GEN_67; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_18 = |(wrap_len_idx_end[6:2]); // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_68 = write_start_idx < 7'h4; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_19; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_19 = _GEN_68; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_21; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_21 = _GEN_68; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_22 = |(wrap_len_idx_end[6:2]); // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_69 = wrap_len_idx_end > 7'h4; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_24; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_24 = _GEN_69; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_28; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_28 = _GEN_69; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_70 = write_start_idx < 7'h5; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_25; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_25 = _GEN_70; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_27; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_27 = _GEN_70; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_71 = wrap_len_idx_end > 7'h5; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_30; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_30 = _GEN_71; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_34; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_34 = _GEN_71; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_72 = write_start_idx < 7'h6; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_31; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_31 = _GEN_72; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_33; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_33 = _GEN_72; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_73 = wrap_len_idx_end > 7'h6; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_36; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_36 = _GEN_73; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_40; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_40 = _GEN_73; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_74 = write_start_idx < 7'h7; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_37; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_37 = _GEN_74; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_39; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_39 = _GEN_74; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_42 = |(wrap_len_idx_end[6:3]); // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_75 = write_start_idx < 7'h8; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_43; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_43 = _GEN_75; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_45; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_45 = _GEN_75; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_46 = |(wrap_len_idx_end[6:3]); // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_76 = wrap_len_idx_end > 7'h8; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_48; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_48 = _GEN_76; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_52; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_52 = _GEN_76; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_77 = write_start_idx < 7'h9; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_49; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_49 = _GEN_77; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_51; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_51 = _GEN_77; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_78 = wrap_len_idx_end > 7'h9; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_54; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_54 = _GEN_78; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_58; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_58 = _GEN_78; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_79 = write_start_idx < 7'hA; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_55; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_55 = _GEN_79; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_57; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_57 = _GEN_79; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_80 = wrap_len_idx_end > 7'hA; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_60; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_60 = _GEN_80; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_64; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_64 = _GEN_80; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_81 = write_start_idx < 7'hB; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_61; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_61 = _GEN_81; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_63; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_63 = _GEN_81; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_82 = wrap_len_idx_end > 7'hB; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_66; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_66 = _GEN_82; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_70; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_70 = _GEN_82; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_83 = write_start_idx < 7'hC; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_67; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_67 = _GEN_83; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_69; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_69 = _GEN_83; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_84 = wrap_len_idx_end > 7'hC; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_72; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_72 = _GEN_84; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_76; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_76 = _GEN_84; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_85 = write_start_idx < 7'hD; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_73; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_73 = _GEN_85; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_75; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_75 = _GEN_85; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_86 = wrap_len_idx_end > 7'hD; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_78; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_78 = _GEN_86; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_82; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_82 = _GEN_86; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_87 = write_start_idx < 7'hE; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_79; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_79 = _GEN_87; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_81; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_81 = _GEN_87; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_88 = wrap_len_idx_end > 7'hE; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_84; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_84 = _GEN_88; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_88; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_88 = _GEN_88; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_89 = write_start_idx < 7'hF; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_85; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_85 = _GEN_89; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_87; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_87 = _GEN_89; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_90 = |(wrap_len_idx_end[6:4]); // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_90 = write_start_idx < 7'h10; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_91; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_91 = _GEN_90; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_93; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_93 = _GEN_90; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_94 = |(wrap_len_idx_end[6:4]); // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_91 = wrap_len_idx_end > 7'h10; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_96; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_96 = _GEN_91; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_100; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_100 = _GEN_91; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_92 = write_start_idx < 7'h11; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_97; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_97 = _GEN_92; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_99; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_99 = _GEN_92; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_93 = wrap_len_idx_end > 7'h11; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_102; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_102 = _GEN_93; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_106; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_106 = _GEN_93; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_94 = write_start_idx < 7'h12; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_103; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_103 = _GEN_94; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_105; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_105 = _GEN_94; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_95 = wrap_len_idx_end > 7'h12; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_108; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_108 = _GEN_95; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_112; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_112 = _GEN_95; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_96 = write_start_idx < 7'h13; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_109; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_109 = _GEN_96; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_111; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_111 = _GEN_96; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_97 = wrap_len_idx_end > 7'h13; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_114; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_114 = _GEN_97; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_118; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_118 = _GEN_97; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_98 = write_start_idx < 7'h14; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_115; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_115 = _GEN_98; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_117; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_117 = _GEN_98; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_99 = wrap_len_idx_end > 7'h14; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_120; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_120 = _GEN_99; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_124; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_124 = _GEN_99; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_100 = write_start_idx < 7'h15; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_121; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_121 = _GEN_100; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_123; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_123 = _GEN_100; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_101 = wrap_len_idx_end > 7'h15; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_126; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_126 = _GEN_101; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_130; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_130 = _GEN_101; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_102 = write_start_idx < 7'h16; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_127; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_127 = _GEN_102; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_129; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_129 = _GEN_102; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_103 = wrap_len_idx_end > 7'h16; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_132; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_132 = _GEN_103; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_136; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_136 = _GEN_103; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_104 = write_start_idx < 7'h17; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_133; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_133 = _GEN_104; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_135; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_135 = _GEN_104; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_105 = wrap_len_idx_end > 7'h17; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_138; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_138 = _GEN_105; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_142; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_142 = _GEN_105; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_106 = write_start_idx < 7'h18; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_139; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_139 = _GEN_106; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_141; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_141 = _GEN_106; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_107 = wrap_len_idx_end > 7'h18; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_144; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_144 = _GEN_107; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_148; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_148 = _GEN_107; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_108 = write_start_idx < 7'h19; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_145; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_145 = _GEN_108; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_147; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_147 = _GEN_108; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_109 = wrap_len_idx_end > 7'h19; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_150; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_150 = _GEN_109; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_154; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_154 = _GEN_109; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_110 = write_start_idx < 7'h1A; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_151; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_151 = _GEN_110; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_153; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_153 = _GEN_110; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_111 = wrap_len_idx_end > 7'h1A; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_156; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_156 = _GEN_111; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_160; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_160 = _GEN_111; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_112 = write_start_idx < 7'h1B; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_157; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_157 = _GEN_112; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_159; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_159 = _GEN_112; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_113 = wrap_len_idx_end > 7'h1B; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_162; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_162 = _GEN_113; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_166; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_166 = _GEN_113; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_114 = write_start_idx < 7'h1C; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_163; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_163 = _GEN_114; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_165; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_165 = _GEN_114; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_115 = wrap_len_idx_end > 7'h1C; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_168; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_168 = _GEN_115; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_172; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_172 = _GEN_115; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_116 = write_start_idx < 7'h1D; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_169; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_169 = _GEN_116; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_171; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_171 = _GEN_116; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_117 = wrap_len_idx_end > 7'h1D; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_174; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_174 = _GEN_117; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_178; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_178 = _GEN_117; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_118 = write_start_idx < 7'h1E; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_175; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_175 = _GEN_118; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_177; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_177 = _GEN_118; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_119 = wrap_len_idx_end > 7'h1E; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_180; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_180 = _GEN_119; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_184; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_184 = _GEN_119; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_120 = write_start_idx < 7'h1F; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_181; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_181 = _GEN_120; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_183; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_183 = _GEN_120; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_186 = |(wrap_len_idx_end[6:5]); // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _GEN_121 = write_start_idx < 7'h20; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_187; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_187 = _GEN_121; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_189; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_189 = _GEN_121; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_190 = |(wrap_len_idx_end[6:5]); // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_122 = wrap_len_idx_end > 7'h20; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_192; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_192 = _GEN_122; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_196; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_196 = _GEN_122; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_123 = write_start_idx < 7'h21; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_193; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_193 = _GEN_123; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_195; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_195 = _GEN_123; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_194 = _use_this_queue_T_192 | _use_this_queue_T_193; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_197 = _use_this_queue_T_195 & _use_this_queue_T_196; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_32 = wrapped ? _use_this_queue_T_194 : _use_this_queue_T_197; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_124 = wrap_len_idx_end > 7'h21; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_198; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_198 = _GEN_124; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_202; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_202 = _GEN_124; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_125 = write_start_idx < 7'h22; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_199; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_199 = _GEN_125; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_201; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_201 = _GEN_125; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_200 = _use_this_queue_T_198 | _use_this_queue_T_199; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_203 = _use_this_queue_T_201 & _use_this_queue_T_202; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_33 = wrapped ? _use_this_queue_T_200 : _use_this_queue_T_203; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_126 = wrap_len_idx_end > 7'h22; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_204; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_204 = _GEN_126; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_208; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_208 = _GEN_126; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_127 = write_start_idx < 7'h23; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_205; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_205 = _GEN_127; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_207; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_207 = _GEN_127; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_206 = _use_this_queue_T_204 | _use_this_queue_T_205; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_209 = _use_this_queue_T_207 & _use_this_queue_T_208; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_34 = wrapped ? _use_this_queue_T_206 : _use_this_queue_T_209; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_128 = wrap_len_idx_end > 7'h23; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_210; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_210 = _GEN_128; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_214; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_214 = _GEN_128; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_129 = write_start_idx < 7'h24; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_211; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_211 = _GEN_129; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_213; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_213 = _GEN_129; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_212 = _use_this_queue_T_210 | _use_this_queue_T_211; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_215 = _use_this_queue_T_213 & _use_this_queue_T_214; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_35 = wrapped ? _use_this_queue_T_212 : _use_this_queue_T_215; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_130 = wrap_len_idx_end > 7'h24; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_216; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_216 = _GEN_130; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_220; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_220 = _GEN_130; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_131 = write_start_idx < 7'h25; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_217; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_217 = _GEN_131; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_219; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_219 = _GEN_131; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_218 = _use_this_queue_T_216 | _use_this_queue_T_217; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_221 = _use_this_queue_T_219 & _use_this_queue_T_220; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_36 = wrapped ? _use_this_queue_T_218 : _use_this_queue_T_221; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_132 = wrap_len_idx_end > 7'h25; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_222; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_222 = _GEN_132; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_226; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_226 = _GEN_132; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_133 = write_start_idx < 7'h26; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_223; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_223 = _GEN_133; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_225; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_225 = _GEN_133; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_224 = _use_this_queue_T_222 | _use_this_queue_T_223; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_227 = _use_this_queue_T_225 & _use_this_queue_T_226; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_37 = wrapped ? _use_this_queue_T_224 : _use_this_queue_T_227; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_134 = wrap_len_idx_end > 7'h26; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_228; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_228 = _GEN_134; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_232; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_232 = _GEN_134; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_135 = write_start_idx < 7'h27; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_229; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_229 = _GEN_135; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_231; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_231 = _GEN_135; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_230 = _use_this_queue_T_228 | _use_this_queue_T_229; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_233 = _use_this_queue_T_231 & _use_this_queue_T_232; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_38 = wrapped ? _use_this_queue_T_230 : _use_this_queue_T_233; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_136 = wrap_len_idx_end > 7'h27; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_234; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_234 = _GEN_136; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_238; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_238 = _GEN_136; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_137 = write_start_idx < 7'h28; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_235; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_235 = _GEN_137; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_237; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_237 = _GEN_137; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_236 = _use_this_queue_T_234 | _use_this_queue_T_235; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_239 = _use_this_queue_T_237 & _use_this_queue_T_238; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_39 = wrapped ? _use_this_queue_T_236 : _use_this_queue_T_239; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_138 = wrap_len_idx_end > 7'h28; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_240; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_240 = _GEN_138; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_244; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_244 = _GEN_138; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_139 = write_start_idx < 7'h29; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_241; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_241 = _GEN_139; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_243; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_243 = _GEN_139; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_242 = _use_this_queue_T_240 | _use_this_queue_T_241; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_245 = _use_this_queue_T_243 & _use_this_queue_T_244; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_40 = wrapped ? _use_this_queue_T_242 : _use_this_queue_T_245; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_140 = wrap_len_idx_end > 7'h29; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_246; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_246 = _GEN_140; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_250; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_250 = _GEN_140; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_141 = write_start_idx < 7'h2A; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_247; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_247 = _GEN_141; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_249; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_249 = _GEN_141; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_248 = _use_this_queue_T_246 | _use_this_queue_T_247; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_251 = _use_this_queue_T_249 & _use_this_queue_T_250; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_41 = wrapped ? _use_this_queue_T_248 : _use_this_queue_T_251; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_142 = wrap_len_idx_end > 7'h2A; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_252; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_252 = _GEN_142; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_256; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_256 = _GEN_142; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_143 = write_start_idx < 7'h2B; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_253; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_253 = _GEN_143; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_255; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_255 = _GEN_143; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_254 = _use_this_queue_T_252 | _use_this_queue_T_253; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_257 = _use_this_queue_T_255 & _use_this_queue_T_256; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_42 = wrapped ? _use_this_queue_T_254 : _use_this_queue_T_257; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_144 = wrap_len_idx_end > 7'h2B; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_258; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_258 = _GEN_144; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_262; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_262 = _GEN_144; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_145 = write_start_idx < 7'h2C; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_259; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_259 = _GEN_145; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_261; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_261 = _GEN_145; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_260 = _use_this_queue_T_258 | _use_this_queue_T_259; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_263 = _use_this_queue_T_261 & _use_this_queue_T_262; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_43 = wrapped ? _use_this_queue_T_260 : _use_this_queue_T_263; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_146 = wrap_len_idx_end > 7'h2C; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_264; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_264 = _GEN_146; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_268; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_268 = _GEN_146; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_147 = write_start_idx < 7'h2D; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_265; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_265 = _GEN_147; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_267; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_267 = _GEN_147; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_266 = _use_this_queue_T_264 | _use_this_queue_T_265; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_269 = _use_this_queue_T_267 & _use_this_queue_T_268; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_44 = wrapped ? _use_this_queue_T_266 : _use_this_queue_T_269; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_148 = wrap_len_idx_end > 7'h2D; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_270; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_270 = _GEN_148; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_274; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_274 = _GEN_148; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_149 = write_start_idx < 7'h2E; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_271; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_271 = _GEN_149; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_273; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_273 = _GEN_149; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_272 = _use_this_queue_T_270 | _use_this_queue_T_271; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_275 = _use_this_queue_T_273 & _use_this_queue_T_274; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_45 = wrapped ? _use_this_queue_T_272 : _use_this_queue_T_275; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_150 = wrap_len_idx_end > 7'h2E; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_276; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_276 = _GEN_150; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_280; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_280 = _GEN_150; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_151 = write_start_idx < 7'h2F; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_277; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_277 = _GEN_151; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_279; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_279 = _GEN_151; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_278 = _use_this_queue_T_276 | _use_this_queue_T_277; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_281 = _use_this_queue_T_279 & _use_this_queue_T_280; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_46 = wrapped ? _use_this_queue_T_278 : _use_this_queue_T_281; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_152 = wrap_len_idx_end > 7'h2F; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_282; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_282 = _GEN_152; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_286; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_286 = _GEN_152; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_153 = write_start_idx < 7'h30; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_283; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_283 = _GEN_153; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_285; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_285 = _GEN_153; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_284 = _use_this_queue_T_282 | _use_this_queue_T_283; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_287 = _use_this_queue_T_285 & _use_this_queue_T_286; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_47 = wrapped ? _use_this_queue_T_284 : _use_this_queue_T_287; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_154 = wrap_len_idx_end > 7'h30; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_288; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_288 = _GEN_154; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_292; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_292 = _GEN_154; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_155 = write_start_idx < 7'h31; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_289; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_289 = _GEN_155; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_291; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_291 = _GEN_155; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_290 = _use_this_queue_T_288 | _use_this_queue_T_289; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_293 = _use_this_queue_T_291 & _use_this_queue_T_292; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_48 = wrapped ? _use_this_queue_T_290 : _use_this_queue_T_293; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_156 = wrap_len_idx_end > 7'h31; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_294; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_294 = _GEN_156; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_298; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_298 = _GEN_156; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_157 = write_start_idx < 7'h32; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_295; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_295 = _GEN_157; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_297; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_297 = _GEN_157; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_296 = _use_this_queue_T_294 | _use_this_queue_T_295; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_299 = _use_this_queue_T_297 & _use_this_queue_T_298; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_49 = wrapped ? _use_this_queue_T_296 : _use_this_queue_T_299; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_158 = wrap_len_idx_end > 7'h32; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_300; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_300 = _GEN_158; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_304; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_304 = _GEN_158; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_159 = write_start_idx < 7'h33; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_301; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_301 = _GEN_159; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_303; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_303 = _GEN_159; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_302 = _use_this_queue_T_300 | _use_this_queue_T_301; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_305 = _use_this_queue_T_303 & _use_this_queue_T_304; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_50 = wrapped ? _use_this_queue_T_302 : _use_this_queue_T_305; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_160 = wrap_len_idx_end > 7'h33; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_306; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_306 = _GEN_160; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_310; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_310 = _GEN_160; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_161 = write_start_idx < 7'h34; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_307; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_307 = _GEN_161; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_309; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_309 = _GEN_161; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_308 = _use_this_queue_T_306 | _use_this_queue_T_307; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_311 = _use_this_queue_T_309 & _use_this_queue_T_310; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_51 = wrapped ? _use_this_queue_T_308 : _use_this_queue_T_311; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_162 = wrap_len_idx_end > 7'h34; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_312; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_312 = _GEN_162; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_316; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_316 = _GEN_162; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_163 = write_start_idx < 7'h35; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_313; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_313 = _GEN_163; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_315; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_315 = _GEN_163; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_314 = _use_this_queue_T_312 | _use_this_queue_T_313; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_317 = _use_this_queue_T_315 & _use_this_queue_T_316; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_52 = wrapped ? _use_this_queue_T_314 : _use_this_queue_T_317; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_164 = wrap_len_idx_end > 7'h35; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_318; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_318 = _GEN_164; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_322; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_322 = _GEN_164; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_165 = write_start_idx < 7'h36; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_319; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_319 = _GEN_165; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_321; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_321 = _GEN_165; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_320 = _use_this_queue_T_318 | _use_this_queue_T_319; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_323 = _use_this_queue_T_321 & _use_this_queue_T_322; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_53 = wrapped ? _use_this_queue_T_320 : _use_this_queue_T_323; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_166 = wrap_len_idx_end > 7'h36; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_324; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_324 = _GEN_166; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_328; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_328 = _GEN_166; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_167 = write_start_idx < 7'h37; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_325; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_325 = _GEN_167; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_327; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_327 = _GEN_167; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_326 = _use_this_queue_T_324 | _use_this_queue_T_325; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_329 = _use_this_queue_T_327 & _use_this_queue_T_328; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_54 = wrapped ? _use_this_queue_T_326 : _use_this_queue_T_329; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_168 = wrap_len_idx_end > 7'h37; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_330; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_330 = _GEN_168; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_334; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_334 = _GEN_168; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_169 = write_start_idx < 7'h38; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_331; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_331 = _GEN_169; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_333; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_333 = _GEN_169; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_332 = _use_this_queue_T_330 | _use_this_queue_T_331; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_335 = _use_this_queue_T_333 & _use_this_queue_T_334; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_55 = wrapped ? _use_this_queue_T_332 : _use_this_queue_T_335; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_170 = wrap_len_idx_end > 7'h38; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_336; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_336 = _GEN_170; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_340; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_340 = _GEN_170; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_171 = write_start_idx < 7'h39; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_337; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_337 = _GEN_171; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_339; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_339 = _GEN_171; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_338 = _use_this_queue_T_336 | _use_this_queue_T_337; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_341 = _use_this_queue_T_339 & _use_this_queue_T_340; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_56 = wrapped ? _use_this_queue_T_338 : _use_this_queue_T_341; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_172 = wrap_len_idx_end > 7'h39; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_342; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_342 = _GEN_172; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_346; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_346 = _GEN_172; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_173 = write_start_idx < 7'h3A; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_343; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_343 = _GEN_173; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_345; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_345 = _GEN_173; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_344 = _use_this_queue_T_342 | _use_this_queue_T_343; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_347 = _use_this_queue_T_345 & _use_this_queue_T_346; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_57 = wrapped ? _use_this_queue_T_344 : _use_this_queue_T_347; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_174 = wrap_len_idx_end > 7'h3A; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_348; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_348 = _GEN_174; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_352; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_352 = _GEN_174; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_175 = write_start_idx < 7'h3B; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_349; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_349 = _GEN_175; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_351; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_351 = _GEN_175; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_350 = _use_this_queue_T_348 | _use_this_queue_T_349; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_353 = _use_this_queue_T_351 & _use_this_queue_T_352; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_58 = wrapped ? _use_this_queue_T_350 : _use_this_queue_T_353; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_176 = wrap_len_idx_end > 7'h3B; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_354; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_354 = _GEN_176; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_358; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_358 = _GEN_176; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_177 = write_start_idx < 7'h3C; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_355; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_355 = _GEN_177; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_357; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_357 = _GEN_177; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_356 = _use_this_queue_T_354 | _use_this_queue_T_355; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_359 = _use_this_queue_T_357 & _use_this_queue_T_358; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_59 = wrapped ? _use_this_queue_T_356 : _use_this_queue_T_359; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_178 = wrap_len_idx_end > 7'h3C; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_360; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_360 = _GEN_178; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_364; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_364 = _GEN_178; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_179 = write_start_idx < 7'h3D; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_361; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_361 = _GEN_179; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_363; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_363 = _GEN_179; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_362 = _use_this_queue_T_360 | _use_this_queue_T_361; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_365 = _use_this_queue_T_363 & _use_this_queue_T_364; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_60 = wrapped ? _use_this_queue_T_362 : _use_this_queue_T_365; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_180 = wrap_len_idx_end > 7'h3D; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_366; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_366 = _GEN_180; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_370; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_370 = _GEN_180; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_181 = write_start_idx < 7'h3E; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_367; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_367 = _GEN_181; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_369; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_369 = _GEN_181; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_368 = _use_this_queue_T_366 | _use_this_queue_T_367; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_371 = _use_this_queue_T_369 & _use_this_queue_T_370; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_61 = wrapped ? _use_this_queue_T_368 : _use_this_queue_T_371; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _GEN_182 = wrap_len_idx_end > 7'h3E; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_372; // @[CompressedBitsBuffer.scala:105:37] assign _use_this_queue_T_372 = _GEN_182; // @[CompressedBitsBuffer.scala:105:37] wire _use_this_queue_T_376; // @[CompressedBitsBuffer.scala:106:65] assign _use_this_queue_T_376 = _GEN_182; // @[CompressedBitsBuffer.scala:105:37, :106:65] wire _GEN_183 = write_start_idx < 7'h3F; // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_373; // @[CompressedBitsBuffer.scala:105:65] assign _use_this_queue_T_373 = _GEN_183; // @[CompressedBitsBuffer.scala:105:65] wire _use_this_queue_T_375; // @[CompressedBitsBuffer.scala:106:37] assign _use_this_queue_T_375 = _GEN_183; // @[CompressedBitsBuffer.scala:105:65, :106:37] wire _use_this_queue_T_374 = _use_this_queue_T_372 | _use_this_queue_T_373; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_377 = _use_this_queue_T_375 & _use_this_queue_T_376; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_62 = wrapped ? _use_this_queue_T_374 : _use_this_queue_T_377; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _use_this_queue_T_378 = wrap_len_idx_end[6]; // @[CompressedBitsBuffer.scala:81:44, :105:37] wire _use_this_queue_T_382 = wrap_len_idx_end[6]; // @[CompressedBitsBuffer.scala:81:44, :105:37, :106:65] wire _use_this_queue_T_379 = ~(write_start_idx[6]); // @[CompressedBitsBuffer.scala:77:32, :105:65] wire _use_this_queue_T_380 = _use_this_queue_T_378 | _use_this_queue_T_379; // @[CompressedBitsBuffer.scala:105:{37,57,65}] wire _use_this_queue_T_381 = ~(write_start_idx[6]); // @[CompressedBitsBuffer.scala:77:32, :105:65, :106:37] wire _use_this_queue_T_383 = _use_this_queue_T_381 & _use_this_queue_T_382; // @[CompressedBitsBuffer.scala:106:{37,57,65}] wire use_this_queue_63 = wrapped ? _use_this_queue_T_380 : _use_this_queue_T_383; // @[CompressedBitsBuffer.scala:82:35, :104:29, :105:57, :106:57] wire _buf_lens_q_io_enq_valid_T = all_queues_ready & _incoming_writes_io_deq_valid; // @[Misc.scala:26:53] wire _buf_lens_q_io_enq_valid_T_1 = _buf_lens_q_io_enq_valid_T & _incoming_writes_io_deq_bits_end_of_message; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _T_263 = _incoming_writes_io_deq_ready_T & _incoming_writes_io_deq_valid; // @[Misc.scala:26:53, :29:18] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [6:0] read_start_idx; // @[CompressedBitsBuffer.scala:126:31] wire bufVecData_0; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_1; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_2; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_3; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_4; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_5; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_6; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_7; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_8; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_9; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_10; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_11; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_12; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_13; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_14; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_15; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_16; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_17; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_18; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_19; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_20; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_21; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_22; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_23; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_24; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_25; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_26; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_27; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_28; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_29; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_30; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_31; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_32; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_33; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_34; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_35; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_36; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_37; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_38; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_39; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_40; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_41; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_42; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_43; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_44; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_45; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_46; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_47; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_48; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_49; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_50; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_51; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_52; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_53; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_54; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_55; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_56; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_57; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_58; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_59; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_60; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_61; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_62; // @[CompressedBitsBuffer.scala:128:24] wire bufVecData_63; // @[CompressedBitsBuffer.scala:128:24] wire bufVecReadys_0; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_1; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_2; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_3; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_4; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_5; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_6; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_7; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_8; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_9; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_10; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_11; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_12; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_13; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_14; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_15; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_16; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_17; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_18; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_19; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_20; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_21; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_22; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_23; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_24; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_25; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_26; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_27; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_28; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_29; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_30; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_31; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_32; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_33; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_34; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_35; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_36; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_37; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_38; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_39; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_40; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_41; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_42; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_43; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_44; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_45; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_46; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_47; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_48; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_49; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_50; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_51; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_52; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_53; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_54; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_55; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_56; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_57; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_58; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_59; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_60; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_61; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_62; // @[CompressedBitsBuffer.scala:129:26] wire bufVecReadys_63; // @[CompressedBitsBuffer.scala:129:26] wire bufVecValids_0; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_1; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_2; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_3; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_4; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_5; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_6; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_7; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_8; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_9; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_10; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_11; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_12; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_13; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_14; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_15; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_16; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_17; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_18; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_19; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_20; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_21; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_22; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_23; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_24; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_25; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_26; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_27; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_28; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_29; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_30; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_31; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_32; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_33; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_34; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_35; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_36; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_37; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_38; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_39; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_40; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_41; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_42; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_43; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_44; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_45; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_46; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_47; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_48; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_49; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_50; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_51; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_52; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_53; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_54; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_55; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_56; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_57; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_58; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_59; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_60; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_61; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_62; // @[CompressedBitsBuffer.scala:130:26] wire bufVecValids_63; // @[CompressedBitsBuffer.scala:130:26] wire remapVecData_0; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_1; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_2; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_3; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_4; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_5; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_6; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_7; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_8; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_9; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_10; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_11; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_12; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_13; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_14; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_15; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_16; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_17; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_18; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_19; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_20; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_21; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_22; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_23; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_24; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_25; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_26; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_27; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_28; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_29; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_30; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_31; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_32; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_33; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_34; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_35; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_36; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_37; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_38; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_39; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_40; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_41; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_42; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_43; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_44; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_45; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_46; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_47; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_48; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_49; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_50; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_51; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_52; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_53; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_54; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_55; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_56; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_57; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_58; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_59; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_60; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_61; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_62; // @[CompressedBitsBuffer.scala:139:26] wire remapVecData_63; // @[CompressedBitsBuffer.scala:139:26] wire _remapVecReadys_0_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_1_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_2_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_3_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_4_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_5_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_6_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_7_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_8_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_9_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_10_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_11_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_12_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_13_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_14_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_15_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_16_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_17_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_18_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_19_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_20_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_21_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_22_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_23_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_24_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_25_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_26_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_27_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_28_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_29_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_30_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_31_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_32_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_33_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_34_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_35_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_36_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_37_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_38_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_39_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_40_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_41_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_42_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_43_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_44_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_45_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_46_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_47_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_48_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_49_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_50_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_51_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_52_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_53_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_54_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_55_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_56_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_57_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_58_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_59_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_60_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_61_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_62_T_2; // @[CompressedBitsBuffer.scala:197:48] wire _remapVecReadys_63_T_2; // @[CompressedBitsBuffer.scala:197:48] wire remapVecReadys_0; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_1; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_2; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_3; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_4; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_5; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_6; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_7; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_8; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_9; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_10; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_11; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_12; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_13; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_14; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_15; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_16; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_17; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_18; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_19; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_20; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_21; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_22; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_23; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_24; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_25; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_26; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_27; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_28; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_29; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_30; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_31; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_32; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_33; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_34; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_35; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_36; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_37; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_38; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_39; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_40; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_41; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_42; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_43; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_44; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_45; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_46; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_47; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_48; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_49; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_50; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_51; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_52; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_53; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_54; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_55; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_56; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_57; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_58; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_59; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_60; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_61; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_62; // @[CompressedBitsBuffer.scala:140:28] wire remapVecReadys_63; // @[CompressedBitsBuffer.scala:140:28] wire remapVecValids_0; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_1; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_2; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_3; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_4; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_5; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_6; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_7; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_8; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_9; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_10; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_11; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_12; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_13; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_14; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_15; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_16; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_17; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_18; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_19; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_20; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_21; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_22; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_23; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_24; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_25; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_26; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_27; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_28; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_29; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_30; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_31; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_32; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_33; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_34; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_35; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_36; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_37; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_38; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_39; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_40; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_41; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_42; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_43; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_44; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_45; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_46; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_47; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_48; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_49; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_50; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_51; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_52; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_53; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_54; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_55; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_56; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_57; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_58; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_59; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_60; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_61; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_62; // @[CompressedBitsBuffer.scala:141:28] wire remapVecValids_63; // @[CompressedBitsBuffer.scala:141:28] wire [7:0] _remap_idx_T = {1'h0, read_start_idx}; // @[CompressedBitsBuffer.scala:126:31, :144:26] wire [7:0] _GEN_184 = _remap_idx_T % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx = _GEN_184[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_0_T = remap_idx[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_0_T = remap_idx[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [63:0] _GEN_185 = {{bufVecData_63}, {bufVecData_62}, {bufVecData_61}, {bufVecData_60}, {bufVecData_59}, {bufVecData_58}, {bufVecData_57}, {bufVecData_56}, {bufVecData_55}, {bufVecData_54}, {bufVecData_53}, {bufVecData_52}, {bufVecData_51}, {bufVecData_50}, {bufVecData_49}, {bufVecData_48}, {bufVecData_47}, {bufVecData_46}, {bufVecData_45}, {bufVecData_44}, {bufVecData_43}, {bufVecData_42}, {bufVecData_41}, {bufVecData_40}, {bufVecData_39}, {bufVecData_38}, {bufVecData_37}, {bufVecData_36}, {bufVecData_35}, {bufVecData_34}, {bufVecData_33}, {bufVecData_32}, {bufVecData_31}, {bufVecData_30}, {bufVecData_29}, {bufVecData_28}, {bufVecData_27}, {bufVecData_26}, {bufVecData_25}, {bufVecData_24}, {bufVecData_23}, {bufVecData_22}, {bufVecData_21}, {bufVecData_20}, {bufVecData_19}, {bufVecData_18}, {bufVecData_17}, {bufVecData_16}, {bufVecData_15}, {bufVecData_14}, {bufVecData_13}, {bufVecData_12}, {bufVecData_11}, {bufVecData_10}, {bufVecData_9}, {bufVecData_8}, {bufVecData_7}, {bufVecData_6}, {bufVecData_5}, {bufVecData_4}, {bufVecData_3}, {bufVecData_2}, {bufVecData_1}, {bufVecData_0}}; // @[CompressedBitsBuffer.scala:128:24, :145:21] assign remapVecData_0 = _GEN_185[_remapVecData_0_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] wire [63:0] _GEN_186 = {{bufVecValids_63}, {bufVecValids_62}, {bufVecValids_61}, {bufVecValids_60}, {bufVecValids_59}, {bufVecValids_58}, {bufVecValids_57}, {bufVecValids_56}, {bufVecValids_55}, {bufVecValids_54}, {bufVecValids_53}, {bufVecValids_52}, {bufVecValids_51}, {bufVecValids_50}, {bufVecValids_49}, {bufVecValids_48}, {bufVecValids_47}, {bufVecValids_46}, {bufVecValids_45}, {bufVecValids_44}, {bufVecValids_43}, {bufVecValids_42}, {bufVecValids_41}, {bufVecValids_40}, {bufVecValids_39}, {bufVecValids_38}, {bufVecValids_37}, {bufVecValids_36}, {bufVecValids_35}, {bufVecValids_34}, {bufVecValids_33}, {bufVecValids_32}, {bufVecValids_31}, {bufVecValids_30}, {bufVecValids_29}, {bufVecValids_28}, {bufVecValids_27}, {bufVecValids_26}, {bufVecValids_25}, {bufVecValids_24}, {bufVecValids_23}, {bufVecValids_22}, {bufVecValids_21}, {bufVecValids_20}, {bufVecValids_19}, {bufVecValids_18}, {bufVecValids_17}, {bufVecValids_16}, {bufVecValids_15}, {bufVecValids_14}, {bufVecValids_13}, {bufVecValids_12}, {bufVecValids_11}, {bufVecValids_10}, {bufVecValids_9}, {bufVecValids_8}, {bufVecValids_7}, {bufVecValids_6}, {bufVecValids_5}, {bufVecValids_4}, {bufVecValids_3}, {bufVecValids_2}, {bufVecValids_1}, {bufVecValids_0}}; // @[CompressedBitsBuffer.scala:130:26, :146:23] assign remapVecValids_0 = _GEN_186[_remapVecValids_0_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_1 = _remap_idx_T + 8'h1; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_187 = _remap_idx_T_1 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_1 = _GEN_187[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_1_T = remap_idx_1[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_1_T = remap_idx_1[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_1 = _GEN_185[_remapVecData_1_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_1 = _GEN_186[_remapVecValids_1_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_2 = _remap_idx_T + 8'h2; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_188 = _remap_idx_T_2 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_2 = _GEN_188[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_2_T = remap_idx_2[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_2_T = remap_idx_2[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_2 = _GEN_185[_remapVecData_2_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_2 = _GEN_186[_remapVecValids_2_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_3 = _remap_idx_T + 8'h3; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_189 = _remap_idx_T_3 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_3 = _GEN_189[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_3_T = remap_idx_3[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_3_T = remap_idx_3[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_3 = _GEN_185[_remapVecData_3_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_3 = _GEN_186[_remapVecValids_3_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_4 = _remap_idx_T + 8'h4; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_190 = _remap_idx_T_4 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_4 = _GEN_190[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_4_T = remap_idx_4[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_4_T = remap_idx_4[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_4 = _GEN_185[_remapVecData_4_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_4 = _GEN_186[_remapVecValids_4_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_5 = _remap_idx_T + 8'h5; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_191 = _remap_idx_T_5 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_5 = _GEN_191[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_5_T = remap_idx_5[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_5_T = remap_idx_5[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_5 = _GEN_185[_remapVecData_5_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_5 = _GEN_186[_remapVecValids_5_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_6 = _remap_idx_T + 8'h6; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_192 = _remap_idx_T_6 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_6 = _GEN_192[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_6_T = remap_idx_6[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_6_T = remap_idx_6[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_6 = _GEN_185[_remapVecData_6_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_6 = _GEN_186[_remapVecValids_6_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_7 = _remap_idx_T + 8'h7; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_193 = _remap_idx_T_7 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_7 = _GEN_193[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_7_T = remap_idx_7[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_7_T = remap_idx_7[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_7 = _GEN_185[_remapVecData_7_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_7 = _GEN_186[_remapVecValids_7_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_8 = _remap_idx_T + 8'h8; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_194 = _remap_idx_T_8 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_8 = _GEN_194[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_8_T = remap_idx_8[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_8_T = remap_idx_8[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_8 = _GEN_185[_remapVecData_8_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_8 = _GEN_186[_remapVecValids_8_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_9 = _remap_idx_T + 8'h9; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_195 = _remap_idx_T_9 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_9 = _GEN_195[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_9_T = remap_idx_9[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_9_T = remap_idx_9[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_9 = _GEN_185[_remapVecData_9_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_9 = _GEN_186[_remapVecValids_9_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_10 = _remap_idx_T + 8'hA; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_196 = _remap_idx_T_10 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_10 = _GEN_196[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_10_T = remap_idx_10[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_10_T = remap_idx_10[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_10 = _GEN_185[_remapVecData_10_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_10 = _GEN_186[_remapVecValids_10_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_11 = _remap_idx_T + 8'hB; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_197 = _remap_idx_T_11 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_11 = _GEN_197[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_11_T = remap_idx_11[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_11_T = remap_idx_11[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_11 = _GEN_185[_remapVecData_11_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_11 = _GEN_186[_remapVecValids_11_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_12 = _remap_idx_T + 8'hC; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_198 = _remap_idx_T_12 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_12 = _GEN_198[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_12_T = remap_idx_12[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_12_T = remap_idx_12[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_12 = _GEN_185[_remapVecData_12_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_12 = _GEN_186[_remapVecValids_12_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_13 = _remap_idx_T + 8'hD; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_199 = _remap_idx_T_13 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_13 = _GEN_199[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_13_T = remap_idx_13[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_13_T = remap_idx_13[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_13 = _GEN_185[_remapVecData_13_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_13 = _GEN_186[_remapVecValids_13_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_14 = _remap_idx_T + 8'hE; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_200 = _remap_idx_T_14 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_14 = _GEN_200[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_14_T = remap_idx_14[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_14_T = remap_idx_14[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_14 = _GEN_185[_remapVecData_14_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_14 = _GEN_186[_remapVecValids_14_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_15 = _remap_idx_T + 8'hF; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_201 = _remap_idx_T_15 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_15 = _GEN_201[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_15_T = remap_idx_15[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_15_T = remap_idx_15[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_15 = _GEN_185[_remapVecData_15_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_15 = _GEN_186[_remapVecValids_15_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_16 = _remap_idx_T + 8'h10; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_202 = _remap_idx_T_16 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_16 = _GEN_202[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_16_T = remap_idx_16[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_16_T = remap_idx_16[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_16 = _GEN_185[_remapVecData_16_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_16 = _GEN_186[_remapVecValids_16_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_17 = _remap_idx_T + 8'h11; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_203 = _remap_idx_T_17 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_17 = _GEN_203[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_17_T = remap_idx_17[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_17_T = remap_idx_17[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_17 = _GEN_185[_remapVecData_17_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_17 = _GEN_186[_remapVecValids_17_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_18 = _remap_idx_T + 8'h12; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_204 = _remap_idx_T_18 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_18 = _GEN_204[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_18_T = remap_idx_18[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_18_T = remap_idx_18[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_18 = _GEN_185[_remapVecData_18_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_18 = _GEN_186[_remapVecValids_18_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_19 = _remap_idx_T + 8'h13; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_205 = _remap_idx_T_19 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_19 = _GEN_205[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_19_T = remap_idx_19[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_19_T = remap_idx_19[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_19 = _GEN_185[_remapVecData_19_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_19 = _GEN_186[_remapVecValids_19_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_20 = _remap_idx_T + 8'h14; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_206 = _remap_idx_T_20 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_20 = _GEN_206[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_20_T = remap_idx_20[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_20_T = remap_idx_20[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_20 = _GEN_185[_remapVecData_20_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_20 = _GEN_186[_remapVecValids_20_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_21 = _remap_idx_T + 8'h15; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_207 = _remap_idx_T_21 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_21 = _GEN_207[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_21_T = remap_idx_21[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_21_T = remap_idx_21[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_21 = _GEN_185[_remapVecData_21_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_21 = _GEN_186[_remapVecValids_21_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_22 = _remap_idx_T + 8'h16; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_208 = _remap_idx_T_22 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_22 = _GEN_208[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_22_T = remap_idx_22[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_22_T = remap_idx_22[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_22 = _GEN_185[_remapVecData_22_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_22 = _GEN_186[_remapVecValids_22_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_23 = _remap_idx_T + 8'h17; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_209 = _remap_idx_T_23 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_23 = _GEN_209[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_23_T = remap_idx_23[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_23_T = remap_idx_23[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_23 = _GEN_185[_remapVecData_23_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_23 = _GEN_186[_remapVecValids_23_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_24 = _remap_idx_T + 8'h18; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_210 = _remap_idx_T_24 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_24 = _GEN_210[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_24_T = remap_idx_24[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_24_T = remap_idx_24[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_24 = _GEN_185[_remapVecData_24_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_24 = _GEN_186[_remapVecValids_24_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_25 = _remap_idx_T + 8'h19; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_211 = _remap_idx_T_25 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_25 = _GEN_211[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_25_T = remap_idx_25[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_25_T = remap_idx_25[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_25 = _GEN_185[_remapVecData_25_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_25 = _GEN_186[_remapVecValids_25_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_26 = _remap_idx_T + 8'h1A; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_212 = _remap_idx_T_26 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_26 = _GEN_212[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_26_T = remap_idx_26[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_26_T = remap_idx_26[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_26 = _GEN_185[_remapVecData_26_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_26 = _GEN_186[_remapVecValids_26_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_27 = _remap_idx_T + 8'h1B; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_213 = _remap_idx_T_27 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_27 = _GEN_213[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_27_T = remap_idx_27[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_27_T = remap_idx_27[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_27 = _GEN_185[_remapVecData_27_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_27 = _GEN_186[_remapVecValids_27_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_28 = _remap_idx_T + 8'h1C; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_214 = _remap_idx_T_28 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_28 = _GEN_214[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_28_T = remap_idx_28[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_28_T = remap_idx_28[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_28 = _GEN_185[_remapVecData_28_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_28 = _GEN_186[_remapVecValids_28_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_29 = _remap_idx_T + 8'h1D; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_215 = _remap_idx_T_29 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_29 = _GEN_215[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_29_T = remap_idx_29[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_29_T = remap_idx_29[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_29 = _GEN_185[_remapVecData_29_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_29 = _GEN_186[_remapVecValids_29_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_30 = _remap_idx_T + 8'h1E; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_216 = _remap_idx_T_30 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_30 = _GEN_216[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_30_T = remap_idx_30[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_30_T = remap_idx_30[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_30 = _GEN_185[_remapVecData_30_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_30 = _GEN_186[_remapVecValids_30_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_31 = _remap_idx_T + 8'h1F; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_217 = _remap_idx_T_31 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_31 = _GEN_217[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_31_T = remap_idx_31[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_31_T = remap_idx_31[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_31 = _GEN_185[_remapVecData_31_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_31 = _GEN_186[_remapVecValids_31_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_32 = _remap_idx_T + 8'h20; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_218 = _remap_idx_T_32 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_32 = _GEN_218[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_32_T = remap_idx_32[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_32_T = remap_idx_32[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_32 = _GEN_185[_remapVecData_32_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_32 = _GEN_186[_remapVecValids_32_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_33 = _remap_idx_T + 8'h21; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_219 = _remap_idx_T_33 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_33 = _GEN_219[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_33_T = remap_idx_33[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_33_T = remap_idx_33[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_33 = _GEN_185[_remapVecData_33_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_33 = _GEN_186[_remapVecValids_33_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_34 = _remap_idx_T + 8'h22; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_220 = _remap_idx_T_34 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_34 = _GEN_220[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_34_T = remap_idx_34[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_34_T = remap_idx_34[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_34 = _GEN_185[_remapVecData_34_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_34 = _GEN_186[_remapVecValids_34_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_35 = _remap_idx_T + 8'h23; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_221 = _remap_idx_T_35 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_35 = _GEN_221[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_35_T = remap_idx_35[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_35_T = remap_idx_35[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_35 = _GEN_185[_remapVecData_35_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_35 = _GEN_186[_remapVecValids_35_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_36 = _remap_idx_T + 8'h24; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_222 = _remap_idx_T_36 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_36 = _GEN_222[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_36_T = remap_idx_36[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_36_T = remap_idx_36[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_36 = _GEN_185[_remapVecData_36_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_36 = _GEN_186[_remapVecValids_36_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_37 = _remap_idx_T + 8'h25; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_223 = _remap_idx_T_37 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_37 = _GEN_223[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_37_T = remap_idx_37[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_37_T = remap_idx_37[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_37 = _GEN_185[_remapVecData_37_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_37 = _GEN_186[_remapVecValids_37_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_38 = _remap_idx_T + 8'h26; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_224 = _remap_idx_T_38 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_38 = _GEN_224[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_38_T = remap_idx_38[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_38_T = remap_idx_38[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_38 = _GEN_185[_remapVecData_38_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_38 = _GEN_186[_remapVecValids_38_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_39 = _remap_idx_T + 8'h27; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_225 = _remap_idx_T_39 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_39 = _GEN_225[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_39_T = remap_idx_39[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_39_T = remap_idx_39[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_39 = _GEN_185[_remapVecData_39_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_39 = _GEN_186[_remapVecValids_39_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_40 = _remap_idx_T + 8'h28; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_226 = _remap_idx_T_40 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_40 = _GEN_226[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_40_T = remap_idx_40[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_40_T = remap_idx_40[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_40 = _GEN_185[_remapVecData_40_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_40 = _GEN_186[_remapVecValids_40_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_41 = _remap_idx_T + 8'h29; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_227 = _remap_idx_T_41 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_41 = _GEN_227[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_41_T = remap_idx_41[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_41_T = remap_idx_41[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_41 = _GEN_185[_remapVecData_41_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_41 = _GEN_186[_remapVecValids_41_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_42 = _remap_idx_T + 8'h2A; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_228 = _remap_idx_T_42 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_42 = _GEN_228[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_42_T = remap_idx_42[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_42_T = remap_idx_42[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_42 = _GEN_185[_remapVecData_42_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_42 = _GEN_186[_remapVecValids_42_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_43 = _remap_idx_T + 8'h2B; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_229 = _remap_idx_T_43 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_43 = _GEN_229[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_43_T = remap_idx_43[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_43_T = remap_idx_43[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_43 = _GEN_185[_remapVecData_43_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_43 = _GEN_186[_remapVecValids_43_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_44 = _remap_idx_T + 8'h2C; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_230 = _remap_idx_T_44 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_44 = _GEN_230[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_44_T = remap_idx_44[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_44_T = remap_idx_44[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_44 = _GEN_185[_remapVecData_44_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_44 = _GEN_186[_remapVecValids_44_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_45 = _remap_idx_T + 8'h2D; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_231 = _remap_idx_T_45 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_45 = _GEN_231[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_45_T = remap_idx_45[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_45_T = remap_idx_45[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_45 = _GEN_185[_remapVecData_45_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_45 = _GEN_186[_remapVecValids_45_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_46 = _remap_idx_T + 8'h2E; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_232 = _remap_idx_T_46 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_46 = _GEN_232[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_46_T = remap_idx_46[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_46_T = remap_idx_46[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_46 = _GEN_185[_remapVecData_46_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_46 = _GEN_186[_remapVecValids_46_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_47 = _remap_idx_T + 8'h2F; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_233 = _remap_idx_T_47 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_47 = _GEN_233[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_47_T = remap_idx_47[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_47_T = remap_idx_47[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_47 = _GEN_185[_remapVecData_47_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_47 = _GEN_186[_remapVecValids_47_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_48 = _remap_idx_T + 8'h30; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_234 = _remap_idx_T_48 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_48 = _GEN_234[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_48_T = remap_idx_48[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_48_T = remap_idx_48[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_48 = _GEN_185[_remapVecData_48_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_48 = _GEN_186[_remapVecValids_48_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_49 = _remap_idx_T + 8'h31; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_235 = _remap_idx_T_49 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_49 = _GEN_235[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_49_T = remap_idx_49[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_49_T = remap_idx_49[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_49 = _GEN_185[_remapVecData_49_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_49 = _GEN_186[_remapVecValids_49_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_50 = _remap_idx_T + 8'h32; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_236 = _remap_idx_T_50 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_50 = _GEN_236[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_50_T = remap_idx_50[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_50_T = remap_idx_50[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_50 = _GEN_185[_remapVecData_50_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_50 = _GEN_186[_remapVecValids_50_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_51 = _remap_idx_T + 8'h33; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_237 = _remap_idx_T_51 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_51 = _GEN_237[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_51_T = remap_idx_51[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_51_T = remap_idx_51[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_51 = _GEN_185[_remapVecData_51_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_51 = _GEN_186[_remapVecValids_51_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_52 = _remap_idx_T + 8'h34; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_238 = _remap_idx_T_52 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_52 = _GEN_238[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_52_T = remap_idx_52[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_52_T = remap_idx_52[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_52 = _GEN_185[_remapVecData_52_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_52 = _GEN_186[_remapVecValids_52_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_53 = _remap_idx_T + 8'h35; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_239 = _remap_idx_T_53 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_53 = _GEN_239[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_53_T = remap_idx_53[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_53_T = remap_idx_53[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_53 = _GEN_185[_remapVecData_53_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_53 = _GEN_186[_remapVecValids_53_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_54 = _remap_idx_T + 8'h36; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_240 = _remap_idx_T_54 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_54 = _GEN_240[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_54_T = remap_idx_54[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_54_T = remap_idx_54[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_54 = _GEN_185[_remapVecData_54_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_54 = _GEN_186[_remapVecValids_54_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_55 = _remap_idx_T + 8'h37; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_241 = _remap_idx_T_55 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_55 = _GEN_241[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_55_T = remap_idx_55[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_55_T = remap_idx_55[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_55 = _GEN_185[_remapVecData_55_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_55 = _GEN_186[_remapVecValids_55_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_56 = _remap_idx_T + 8'h38; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_242 = _remap_idx_T_56 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_56 = _GEN_242[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_56_T = remap_idx_56[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_56_T = remap_idx_56[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_56 = _GEN_185[_remapVecData_56_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_56 = _GEN_186[_remapVecValids_56_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_57 = _remap_idx_T + 8'h39; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_243 = _remap_idx_T_57 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_57 = _GEN_243[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_57_T = remap_idx_57[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_57_T = remap_idx_57[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_57 = _GEN_185[_remapVecData_57_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_57 = _GEN_186[_remapVecValids_57_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_58 = _remap_idx_T + 8'h3A; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_244 = _remap_idx_T_58 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_58 = _GEN_244[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_58_T = remap_idx_58[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_58_T = remap_idx_58[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_58 = _GEN_185[_remapVecData_58_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_58 = _GEN_186[_remapVecValids_58_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_59 = _remap_idx_T + 8'h3B; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_245 = _remap_idx_T_59 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_59 = _GEN_245[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_59_T = remap_idx_59[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_59_T = remap_idx_59[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_59 = _GEN_185[_remapVecData_59_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_59 = _GEN_186[_remapVecValids_59_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_60 = _remap_idx_T + 8'h3C; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_246 = _remap_idx_T_60 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_60 = _GEN_246[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_60_T = remap_idx_60[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_60_T = remap_idx_60[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_60 = _GEN_185[_remapVecData_60_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_60 = _GEN_186[_remapVecValids_60_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_61 = _remap_idx_T + 8'h3D; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_247 = _remap_idx_T_61 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_61 = _GEN_247[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_61_T = remap_idx_61[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_61_T = remap_idx_61[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_61 = _GEN_185[_remapVecData_61_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_61 = _GEN_186[_remapVecValids_61_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_62 = _remap_idx_T + 8'h3E; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_248 = _remap_idx_T_62 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_62 = _GEN_248[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_62_T = remap_idx_62[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_62_T = remap_idx_62[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_62 = _GEN_185[_remapVecData_62_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_62 = _GEN_186[_remapVecValids_62_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] wire [7:0] _remap_idx_T_63 = _remap_idx_T + 8'h3F; // @[CompressedBitsBuffer.scala:144:26] wire [7:0] _GEN_249 = _remap_idx_T_63 % 8'h40; // @[CompressedBitsBuffer.scala:144:{26,45}] wire [6:0] remap_idx_63 = _GEN_249[6:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecData_63_T = remap_idx_63[5:0]; // @[CompressedBitsBuffer.scala:144:45] wire [5:0] _remapVecValids_63_T = remap_idx_63[5:0]; // @[CompressedBitsBuffer.scala:144:45] assign remapVecData_63 = _GEN_185[_remapVecData_63_T]; // @[CompressedBitsBuffer.scala:139:26, :145:21] assign remapVecValids_63 = _GEN_186[_remapVecValids_63_T]; // @[CompressedBitsBuffer.scala:141:28, :146:23] assign bufVecReadys_0 = remap_idx_63[5:0] == 6'h0 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h0 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h0 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h0 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h0 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h0 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h0 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h0 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h0 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h0 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h0 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h0 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h0 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h0 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h0 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h0 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h0 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h0 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h0 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h0 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h0 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h0 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h0 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h0 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h0 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h0 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h0 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h0 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h0 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h0 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h0 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h0 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h0 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h0 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h0 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h0 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h0 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h0 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h0 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h0 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h0 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h0 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h0 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h0 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h0 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h0 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h0 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h0 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h0 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h0 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h0 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h0 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h0 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h0 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h0 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h0 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h0 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h0 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h0 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h0 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h0 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h0 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h0 ? remapVecReadys_1 : remap_idx[5:0] == 6'h0 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_1 = remap_idx_63[5:0] == 6'h1 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1 ? remapVecReadys_1 : remap_idx[5:0] == 6'h1 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_2 = remap_idx_63[5:0] == 6'h2 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2 ? remapVecReadys_1 : remap_idx[5:0] == 6'h2 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_3 = remap_idx_63[5:0] == 6'h3 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3 ? remapVecReadys_1 : remap_idx[5:0] == 6'h3 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_4 = remap_idx_63[5:0] == 6'h4 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h4 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h4 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h4 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h4 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h4 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h4 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h4 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h4 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h4 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h4 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h4 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h4 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h4 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h4 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h4 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h4 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h4 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h4 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h4 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h4 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h4 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h4 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h4 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h4 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h4 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h4 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h4 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h4 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h4 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h4 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h4 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h4 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h4 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h4 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h4 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h4 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h4 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h4 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h4 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h4 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h4 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h4 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h4 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h4 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h4 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h4 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h4 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h4 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h4 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h4 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h4 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h4 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h4 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h4 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h4 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h4 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h4 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h4 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h4 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h4 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h4 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h4 ? remapVecReadys_1 : remap_idx[5:0] == 6'h4 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_5 = remap_idx_63[5:0] == 6'h5 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h5 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h5 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h5 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h5 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h5 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h5 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h5 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h5 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h5 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h5 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h5 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h5 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h5 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h5 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h5 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h5 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h5 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h5 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h5 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h5 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h5 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h5 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h5 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h5 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h5 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h5 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h5 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h5 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h5 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h5 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h5 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h5 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h5 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h5 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h5 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h5 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h5 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h5 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h5 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h5 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h5 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h5 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h5 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h5 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h5 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h5 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h5 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h5 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h5 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h5 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h5 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h5 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h5 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h5 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h5 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h5 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h5 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h5 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h5 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h5 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h5 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h5 ? remapVecReadys_1 : remap_idx[5:0] == 6'h5 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_6 = remap_idx_63[5:0] == 6'h6 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h6 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h6 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h6 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h6 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h6 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h6 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h6 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h6 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h6 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h6 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h6 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h6 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h6 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h6 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h6 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h6 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h6 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h6 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h6 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h6 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h6 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h6 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h6 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h6 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h6 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h6 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h6 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h6 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h6 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h6 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h6 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h6 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h6 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h6 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h6 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h6 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h6 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h6 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h6 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h6 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h6 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h6 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h6 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h6 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h6 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h6 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h6 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h6 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h6 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h6 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h6 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h6 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h6 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h6 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h6 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h6 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h6 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h6 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h6 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h6 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h6 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h6 ? remapVecReadys_1 : remap_idx[5:0] == 6'h6 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_7 = remap_idx_63[5:0] == 6'h7 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h7 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h7 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h7 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h7 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h7 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h7 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h7 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h7 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h7 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h7 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h7 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h7 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h7 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h7 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h7 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h7 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h7 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h7 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h7 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h7 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h7 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h7 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h7 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h7 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h7 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h7 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h7 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h7 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h7 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h7 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h7 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h7 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h7 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h7 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h7 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h7 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h7 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h7 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h7 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h7 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h7 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h7 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h7 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h7 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h7 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h7 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h7 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h7 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h7 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h7 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h7 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h7 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h7 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h7 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h7 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h7 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h7 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h7 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h7 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h7 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h7 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h7 ? remapVecReadys_1 : remap_idx[5:0] == 6'h7 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_8 = remap_idx_63[5:0] == 6'h8 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h8 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h8 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h8 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h8 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h8 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h8 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h8 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h8 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h8 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h8 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h8 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h8 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h8 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h8 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h8 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h8 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h8 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h8 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h8 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h8 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h8 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h8 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h8 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h8 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h8 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h8 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h8 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h8 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h8 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h8 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h8 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h8 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h8 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h8 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h8 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h8 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h8 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h8 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h8 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h8 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h8 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h8 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h8 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h8 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h8 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h8 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h8 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h8 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h8 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h8 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h8 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h8 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h8 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h8 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h8 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h8 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h8 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h8 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h8 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h8 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h8 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h8 ? remapVecReadys_1 : remap_idx[5:0] == 6'h8 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_9 = remap_idx_63[5:0] == 6'h9 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h9 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h9 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h9 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h9 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h9 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h9 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h9 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h9 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h9 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h9 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h9 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h9 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h9 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h9 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h9 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h9 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h9 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h9 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h9 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h9 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h9 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h9 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h9 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h9 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h9 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h9 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h9 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h9 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h9 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h9 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h9 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h9 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h9 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h9 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h9 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h9 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h9 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h9 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h9 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h9 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h9 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h9 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h9 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h9 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h9 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h9 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h9 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h9 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h9 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h9 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h9 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h9 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h9 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h9 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h9 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h9 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h9 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h9 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h9 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h9 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h9 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h9 ? remapVecReadys_1 : remap_idx[5:0] == 6'h9 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_10 = remap_idx_63[5:0] == 6'hA ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hA ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hA ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hA ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hA ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hA ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hA ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hA ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hA ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hA ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hA ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hA ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hA ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hA ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hA ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hA ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hA ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hA ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hA ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hA ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hA ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hA ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hA ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hA ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hA ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hA ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hA ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hA ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hA ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hA ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hA ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hA ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hA ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hA ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hA ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hA ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hA ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hA ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hA ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hA ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hA ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hA ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hA ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hA ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hA ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hA ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hA ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hA ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hA ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hA ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hA ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hA ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hA ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hA ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hA ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hA ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hA ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hA ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hA ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hA ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hA ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hA ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hA ? remapVecReadys_1 : remap_idx[5:0] == 6'hA & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_11 = remap_idx_63[5:0] == 6'hB ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hB ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hB ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hB ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hB ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hB ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hB ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hB ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hB ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hB ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hB ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hB ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hB ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hB ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hB ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hB ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hB ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hB ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hB ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hB ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hB ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hB ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hB ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hB ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hB ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hB ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hB ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hB ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hB ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hB ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hB ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hB ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hB ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hB ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hB ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hB ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hB ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hB ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hB ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hB ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hB ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hB ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hB ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hB ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hB ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hB ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hB ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hB ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hB ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hB ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hB ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hB ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hB ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hB ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hB ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hB ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hB ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hB ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hB ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hB ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hB ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hB ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hB ? remapVecReadys_1 : remap_idx[5:0] == 6'hB & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_12 = remap_idx_63[5:0] == 6'hC ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hC ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hC ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hC ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hC ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hC ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hC ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hC ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hC ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hC ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hC ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hC ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hC ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hC ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hC ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hC ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hC ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hC ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hC ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hC ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hC ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hC ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hC ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hC ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hC ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hC ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hC ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hC ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hC ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hC ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hC ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hC ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hC ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hC ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hC ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hC ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hC ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hC ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hC ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hC ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hC ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hC ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hC ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hC ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hC ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hC ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hC ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hC ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hC ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hC ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hC ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hC ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hC ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hC ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hC ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hC ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hC ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hC ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hC ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hC ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hC ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hC ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hC ? remapVecReadys_1 : remap_idx[5:0] == 6'hC & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_13 = remap_idx_63[5:0] == 6'hD ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hD ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hD ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hD ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hD ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hD ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hD ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hD ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hD ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hD ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hD ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hD ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hD ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hD ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hD ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hD ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hD ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hD ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hD ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hD ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hD ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hD ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hD ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hD ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hD ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hD ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hD ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hD ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hD ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hD ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hD ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hD ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hD ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hD ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hD ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hD ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hD ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hD ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hD ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hD ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hD ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hD ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hD ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hD ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hD ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hD ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hD ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hD ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hD ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hD ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hD ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hD ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hD ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hD ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hD ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hD ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hD ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hD ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hD ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hD ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hD ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hD ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hD ? remapVecReadys_1 : remap_idx[5:0] == 6'hD & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_14 = remap_idx_63[5:0] == 6'hE ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hE ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hE ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hE ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hE ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hE ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hE ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hE ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hE ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hE ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hE ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hE ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hE ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hE ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hE ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hE ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hE ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hE ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hE ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hE ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hE ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hE ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hE ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hE ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hE ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hE ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hE ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hE ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hE ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hE ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hE ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hE ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hE ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hE ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hE ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hE ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hE ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hE ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hE ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hE ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hE ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hE ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hE ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hE ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hE ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hE ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hE ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hE ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hE ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hE ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hE ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hE ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hE ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hE ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hE ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hE ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hE ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hE ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hE ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hE ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hE ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hE ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hE ? remapVecReadys_1 : remap_idx[5:0] == 6'hE & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_15 = remap_idx_63[5:0] == 6'hF ? remapVecReadys_63 : remap_idx_62[5:0] == 6'hF ? remapVecReadys_62 : remap_idx_61[5:0] == 6'hF ? remapVecReadys_61 : remap_idx_60[5:0] == 6'hF ? remapVecReadys_60 : remap_idx_59[5:0] == 6'hF ? remapVecReadys_59 : remap_idx_58[5:0] == 6'hF ? remapVecReadys_58 : remap_idx_57[5:0] == 6'hF ? remapVecReadys_57 : remap_idx_56[5:0] == 6'hF ? remapVecReadys_56 : remap_idx_55[5:0] == 6'hF ? remapVecReadys_55 : remap_idx_54[5:0] == 6'hF ? remapVecReadys_54 : remap_idx_53[5:0] == 6'hF ? remapVecReadys_53 : remap_idx_52[5:0] == 6'hF ? remapVecReadys_52 : remap_idx_51[5:0] == 6'hF ? remapVecReadys_51 : remap_idx_50[5:0] == 6'hF ? remapVecReadys_50 : remap_idx_49[5:0] == 6'hF ? remapVecReadys_49 : remap_idx_48[5:0] == 6'hF ? remapVecReadys_48 : remap_idx_47[5:0] == 6'hF ? remapVecReadys_47 : remap_idx_46[5:0] == 6'hF ? remapVecReadys_46 : remap_idx_45[5:0] == 6'hF ? remapVecReadys_45 : remap_idx_44[5:0] == 6'hF ? remapVecReadys_44 : remap_idx_43[5:0] == 6'hF ? remapVecReadys_43 : remap_idx_42[5:0] == 6'hF ? remapVecReadys_42 : remap_idx_41[5:0] == 6'hF ? remapVecReadys_41 : remap_idx_40[5:0] == 6'hF ? remapVecReadys_40 : remap_idx_39[5:0] == 6'hF ? remapVecReadys_39 : remap_idx_38[5:0] == 6'hF ? remapVecReadys_38 : remap_idx_37[5:0] == 6'hF ? remapVecReadys_37 : remap_idx_36[5:0] == 6'hF ? remapVecReadys_36 : remap_idx_35[5:0] == 6'hF ? remapVecReadys_35 : remap_idx_34[5:0] == 6'hF ? remapVecReadys_34 : remap_idx_33[5:0] == 6'hF ? remapVecReadys_33 : remap_idx_32[5:0] == 6'hF ? remapVecReadys_32 : remap_idx_31[5:0] == 6'hF ? remapVecReadys_31 : remap_idx_30[5:0] == 6'hF ? remapVecReadys_30 : remap_idx_29[5:0] == 6'hF ? remapVecReadys_29 : remap_idx_28[5:0] == 6'hF ? remapVecReadys_28 : remap_idx_27[5:0] == 6'hF ? remapVecReadys_27 : remap_idx_26[5:0] == 6'hF ? remapVecReadys_26 : remap_idx_25[5:0] == 6'hF ? remapVecReadys_25 : remap_idx_24[5:0] == 6'hF ? remapVecReadys_24 : remap_idx_23[5:0] == 6'hF ? remapVecReadys_23 : remap_idx_22[5:0] == 6'hF ? remapVecReadys_22 : remap_idx_21[5:0] == 6'hF ? remapVecReadys_21 : remap_idx_20[5:0] == 6'hF ? remapVecReadys_20 : remap_idx_19[5:0] == 6'hF ? remapVecReadys_19 : remap_idx_18[5:0] == 6'hF ? remapVecReadys_18 : remap_idx_17[5:0] == 6'hF ? remapVecReadys_17 : remap_idx_16[5:0] == 6'hF ? remapVecReadys_16 : remap_idx_15[5:0] == 6'hF ? remapVecReadys_15 : remap_idx_14[5:0] == 6'hF ? remapVecReadys_14 : remap_idx_13[5:0] == 6'hF ? remapVecReadys_13 : remap_idx_12[5:0] == 6'hF ? remapVecReadys_12 : remap_idx_11[5:0] == 6'hF ? remapVecReadys_11 : remap_idx_10[5:0] == 6'hF ? remapVecReadys_10 : remap_idx_9[5:0] == 6'hF ? remapVecReadys_9 : remap_idx_8[5:0] == 6'hF ? remapVecReadys_8 : remap_idx_7[5:0] == 6'hF ? remapVecReadys_7 : remap_idx_6[5:0] == 6'hF ? remapVecReadys_6 : remap_idx_5[5:0] == 6'hF ? remapVecReadys_5 : remap_idx_4[5:0] == 6'hF ? remapVecReadys_4 : remap_idx_3[5:0] == 6'hF ? remapVecReadys_3 : remap_idx_2[5:0] == 6'hF ? remapVecReadys_2 : remap_idx_1[5:0] == 6'hF ? remapVecReadys_1 : remap_idx[5:0] == 6'hF & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_16 = remap_idx_63[5:0] == 6'h10 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h10 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h10 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h10 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h10 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h10 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h10 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h10 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h10 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h10 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h10 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h10 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h10 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h10 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h10 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h10 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h10 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h10 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h10 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h10 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h10 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h10 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h10 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h10 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h10 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h10 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h10 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h10 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h10 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h10 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h10 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h10 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h10 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h10 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h10 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h10 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h10 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h10 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h10 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h10 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h10 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h10 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h10 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h10 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h10 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h10 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h10 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h10 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h10 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h10 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h10 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h10 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h10 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h10 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h10 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h10 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h10 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h10 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h10 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h10 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h10 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h10 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h10 ? remapVecReadys_1 : remap_idx[5:0] == 6'h10 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_17 = remap_idx_63[5:0] == 6'h11 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h11 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h11 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h11 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h11 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h11 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h11 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h11 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h11 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h11 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h11 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h11 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h11 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h11 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h11 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h11 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h11 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h11 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h11 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h11 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h11 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h11 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h11 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h11 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h11 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h11 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h11 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h11 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h11 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h11 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h11 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h11 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h11 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h11 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h11 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h11 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h11 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h11 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h11 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h11 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h11 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h11 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h11 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h11 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h11 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h11 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h11 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h11 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h11 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h11 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h11 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h11 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h11 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h11 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h11 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h11 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h11 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h11 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h11 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h11 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h11 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h11 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h11 ? remapVecReadys_1 : remap_idx[5:0] == 6'h11 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_18 = remap_idx_63[5:0] == 6'h12 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h12 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h12 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h12 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h12 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h12 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h12 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h12 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h12 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h12 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h12 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h12 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h12 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h12 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h12 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h12 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h12 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h12 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h12 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h12 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h12 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h12 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h12 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h12 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h12 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h12 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h12 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h12 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h12 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h12 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h12 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h12 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h12 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h12 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h12 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h12 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h12 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h12 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h12 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h12 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h12 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h12 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h12 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h12 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h12 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h12 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h12 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h12 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h12 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h12 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h12 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h12 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h12 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h12 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h12 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h12 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h12 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h12 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h12 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h12 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h12 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h12 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h12 ? remapVecReadys_1 : remap_idx[5:0] == 6'h12 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_19 = remap_idx_63[5:0] == 6'h13 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h13 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h13 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h13 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h13 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h13 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h13 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h13 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h13 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h13 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h13 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h13 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h13 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h13 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h13 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h13 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h13 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h13 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h13 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h13 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h13 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h13 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h13 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h13 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h13 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h13 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h13 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h13 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h13 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h13 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h13 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h13 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h13 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h13 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h13 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h13 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h13 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h13 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h13 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h13 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h13 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h13 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h13 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h13 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h13 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h13 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h13 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h13 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h13 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h13 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h13 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h13 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h13 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h13 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h13 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h13 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h13 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h13 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h13 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h13 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h13 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h13 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h13 ? remapVecReadys_1 : remap_idx[5:0] == 6'h13 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_20 = remap_idx_63[5:0] == 6'h14 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h14 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h14 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h14 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h14 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h14 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h14 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h14 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h14 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h14 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h14 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h14 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h14 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h14 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h14 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h14 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h14 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h14 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h14 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h14 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h14 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h14 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h14 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h14 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h14 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h14 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h14 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h14 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h14 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h14 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h14 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h14 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h14 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h14 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h14 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h14 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h14 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h14 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h14 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h14 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h14 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h14 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h14 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h14 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h14 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h14 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h14 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h14 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h14 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h14 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h14 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h14 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h14 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h14 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h14 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h14 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h14 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h14 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h14 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h14 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h14 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h14 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h14 ? remapVecReadys_1 : remap_idx[5:0] == 6'h14 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_21 = remap_idx_63[5:0] == 6'h15 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h15 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h15 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h15 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h15 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h15 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h15 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h15 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h15 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h15 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h15 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h15 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h15 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h15 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h15 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h15 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h15 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h15 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h15 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h15 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h15 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h15 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h15 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h15 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h15 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h15 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h15 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h15 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h15 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h15 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h15 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h15 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h15 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h15 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h15 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h15 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h15 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h15 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h15 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h15 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h15 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h15 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h15 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h15 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h15 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h15 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h15 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h15 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h15 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h15 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h15 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h15 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h15 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h15 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h15 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h15 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h15 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h15 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h15 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h15 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h15 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h15 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h15 ? remapVecReadys_1 : remap_idx[5:0] == 6'h15 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_22 = remap_idx_63[5:0] == 6'h16 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h16 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h16 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h16 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h16 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h16 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h16 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h16 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h16 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h16 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h16 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h16 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h16 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h16 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h16 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h16 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h16 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h16 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h16 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h16 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h16 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h16 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h16 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h16 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h16 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h16 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h16 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h16 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h16 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h16 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h16 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h16 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h16 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h16 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h16 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h16 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h16 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h16 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h16 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h16 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h16 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h16 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h16 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h16 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h16 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h16 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h16 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h16 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h16 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h16 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h16 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h16 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h16 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h16 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h16 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h16 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h16 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h16 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h16 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h16 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h16 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h16 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h16 ? remapVecReadys_1 : remap_idx[5:0] == 6'h16 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_23 = remap_idx_63[5:0] == 6'h17 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h17 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h17 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h17 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h17 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h17 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h17 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h17 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h17 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h17 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h17 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h17 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h17 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h17 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h17 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h17 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h17 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h17 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h17 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h17 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h17 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h17 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h17 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h17 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h17 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h17 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h17 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h17 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h17 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h17 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h17 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h17 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h17 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h17 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h17 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h17 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h17 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h17 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h17 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h17 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h17 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h17 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h17 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h17 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h17 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h17 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h17 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h17 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h17 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h17 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h17 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h17 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h17 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h17 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h17 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h17 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h17 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h17 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h17 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h17 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h17 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h17 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h17 ? remapVecReadys_1 : remap_idx[5:0] == 6'h17 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_24 = remap_idx_63[5:0] == 6'h18 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h18 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h18 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h18 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h18 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h18 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h18 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h18 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h18 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h18 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h18 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h18 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h18 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h18 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h18 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h18 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h18 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h18 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h18 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h18 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h18 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h18 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h18 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h18 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h18 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h18 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h18 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h18 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h18 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h18 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h18 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h18 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h18 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h18 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h18 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h18 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h18 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h18 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h18 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h18 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h18 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h18 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h18 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h18 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h18 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h18 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h18 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h18 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h18 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h18 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h18 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h18 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h18 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h18 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h18 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h18 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h18 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h18 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h18 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h18 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h18 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h18 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h18 ? remapVecReadys_1 : remap_idx[5:0] == 6'h18 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_25 = remap_idx_63[5:0] == 6'h19 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h19 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h19 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h19 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h19 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h19 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h19 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h19 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h19 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h19 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h19 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h19 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h19 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h19 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h19 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h19 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h19 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h19 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h19 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h19 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h19 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h19 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h19 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h19 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h19 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h19 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h19 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h19 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h19 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h19 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h19 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h19 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h19 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h19 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h19 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h19 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h19 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h19 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h19 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h19 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h19 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h19 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h19 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h19 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h19 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h19 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h19 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h19 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h19 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h19 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h19 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h19 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h19 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h19 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h19 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h19 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h19 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h19 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h19 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h19 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h19 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h19 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h19 ? remapVecReadys_1 : remap_idx[5:0] == 6'h19 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_26 = remap_idx_63[5:0] == 6'h1A ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1A ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1A ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1A ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1A ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1A ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1A ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1A ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1A ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1A ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1A ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1A ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1A ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1A ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1A ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1A ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1A ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1A ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1A ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1A ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1A ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1A ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1A ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1A ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1A ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1A ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1A ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1A ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1A ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1A ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1A ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1A ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1A ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1A ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1A ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1A ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1A ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1A ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1A ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1A ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1A ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1A ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1A ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1A ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1A ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1A ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1A ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1A ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1A ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1A ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1A ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1A ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1A ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1A ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1A ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1A ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1A ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1A ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1A ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1A ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1A ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1A ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1A ? remapVecReadys_1 : remap_idx[5:0] == 6'h1A & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_27 = remap_idx_63[5:0] == 6'h1B ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1B ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1B ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1B ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1B ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1B ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1B ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1B ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1B ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1B ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1B ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1B ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1B ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1B ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1B ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1B ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1B ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1B ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1B ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1B ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1B ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1B ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1B ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1B ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1B ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1B ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1B ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1B ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1B ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1B ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1B ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1B ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1B ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1B ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1B ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1B ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1B ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1B ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1B ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1B ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1B ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1B ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1B ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1B ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1B ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1B ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1B ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1B ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1B ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1B ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1B ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1B ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1B ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1B ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1B ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1B ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1B ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1B ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1B ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1B ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1B ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1B ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1B ? remapVecReadys_1 : remap_idx[5:0] == 6'h1B & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_28 = remap_idx_63[5:0] == 6'h1C ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1C ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1C ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1C ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1C ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1C ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1C ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1C ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1C ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1C ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1C ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1C ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1C ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1C ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1C ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1C ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1C ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1C ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1C ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1C ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1C ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1C ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1C ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1C ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1C ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1C ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1C ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1C ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1C ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1C ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1C ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1C ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1C ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1C ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1C ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1C ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1C ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1C ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1C ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1C ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1C ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1C ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1C ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1C ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1C ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1C ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1C ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1C ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1C ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1C ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1C ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1C ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1C ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1C ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1C ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1C ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1C ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1C ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1C ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1C ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1C ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1C ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1C ? remapVecReadys_1 : remap_idx[5:0] == 6'h1C & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_29 = remap_idx_63[5:0] == 6'h1D ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1D ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1D ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1D ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1D ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1D ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1D ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1D ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1D ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1D ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1D ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1D ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1D ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1D ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1D ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1D ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1D ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1D ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1D ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1D ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1D ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1D ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1D ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1D ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1D ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1D ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1D ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1D ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1D ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1D ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1D ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1D ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1D ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1D ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1D ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1D ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1D ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1D ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1D ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1D ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1D ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1D ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1D ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1D ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1D ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1D ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1D ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1D ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1D ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1D ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1D ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1D ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1D ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1D ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1D ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1D ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1D ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1D ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1D ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1D ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1D ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1D ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1D ? remapVecReadys_1 : remap_idx[5:0] == 6'h1D & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_30 = remap_idx_63[5:0] == 6'h1E ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1E ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1E ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1E ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1E ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1E ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1E ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1E ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1E ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1E ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1E ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1E ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1E ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1E ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1E ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1E ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1E ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1E ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1E ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1E ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1E ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1E ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1E ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1E ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1E ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1E ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1E ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1E ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1E ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1E ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1E ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1E ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1E ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1E ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1E ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1E ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1E ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1E ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1E ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1E ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1E ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1E ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1E ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1E ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1E ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1E ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1E ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1E ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1E ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1E ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1E ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1E ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1E ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1E ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1E ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1E ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1E ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1E ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1E ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1E ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1E ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1E ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1E ? remapVecReadys_1 : remap_idx[5:0] == 6'h1E & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_31 = remap_idx_63[5:0] == 6'h1F ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h1F ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h1F ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h1F ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h1F ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h1F ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h1F ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h1F ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h1F ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h1F ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h1F ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h1F ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h1F ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h1F ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h1F ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h1F ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h1F ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h1F ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h1F ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h1F ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h1F ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h1F ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h1F ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h1F ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h1F ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h1F ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h1F ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h1F ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h1F ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h1F ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h1F ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h1F ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h1F ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h1F ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h1F ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h1F ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h1F ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h1F ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h1F ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h1F ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h1F ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h1F ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h1F ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h1F ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h1F ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h1F ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h1F ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h1F ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h1F ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h1F ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h1F ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h1F ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h1F ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h1F ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h1F ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h1F ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h1F ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h1F ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h1F ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h1F ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h1F ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h1F ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h1F ? remapVecReadys_1 : remap_idx[5:0] == 6'h1F & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_32 = remap_idx_63[5:0] == 6'h20 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h20 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h20 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h20 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h20 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h20 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h20 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h20 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h20 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h20 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h20 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h20 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h20 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h20 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h20 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h20 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h20 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h20 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h20 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h20 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h20 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h20 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h20 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h20 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h20 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h20 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h20 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h20 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h20 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h20 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h20 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h20 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h20 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h20 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h20 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h20 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h20 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h20 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h20 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h20 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h20 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h20 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h20 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h20 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h20 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h20 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h20 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h20 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h20 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h20 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h20 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h20 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h20 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h20 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h20 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h20 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h20 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h20 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h20 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h20 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h20 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h20 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h20 ? remapVecReadys_1 : remap_idx[5:0] == 6'h20 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_33 = remap_idx_63[5:0] == 6'h21 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h21 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h21 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h21 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h21 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h21 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h21 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h21 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h21 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h21 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h21 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h21 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h21 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h21 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h21 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h21 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h21 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h21 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h21 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h21 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h21 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h21 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h21 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h21 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h21 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h21 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h21 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h21 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h21 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h21 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h21 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h21 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h21 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h21 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h21 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h21 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h21 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h21 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h21 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h21 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h21 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h21 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h21 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h21 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h21 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h21 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h21 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h21 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h21 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h21 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h21 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h21 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h21 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h21 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h21 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h21 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h21 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h21 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h21 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h21 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h21 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h21 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h21 ? remapVecReadys_1 : remap_idx[5:0] == 6'h21 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_34 = remap_idx_63[5:0] == 6'h22 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h22 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h22 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h22 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h22 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h22 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h22 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h22 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h22 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h22 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h22 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h22 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h22 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h22 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h22 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h22 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h22 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h22 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h22 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h22 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h22 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h22 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h22 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h22 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h22 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h22 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h22 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h22 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h22 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h22 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h22 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h22 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h22 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h22 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h22 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h22 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h22 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h22 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h22 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h22 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h22 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h22 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h22 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h22 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h22 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h22 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h22 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h22 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h22 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h22 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h22 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h22 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h22 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h22 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h22 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h22 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h22 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h22 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h22 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h22 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h22 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h22 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h22 ? remapVecReadys_1 : remap_idx[5:0] == 6'h22 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_35 = remap_idx_63[5:0] == 6'h23 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h23 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h23 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h23 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h23 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h23 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h23 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h23 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h23 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h23 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h23 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h23 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h23 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h23 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h23 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h23 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h23 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h23 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h23 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h23 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h23 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h23 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h23 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h23 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h23 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h23 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h23 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h23 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h23 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h23 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h23 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h23 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h23 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h23 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h23 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h23 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h23 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h23 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h23 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h23 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h23 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h23 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h23 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h23 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h23 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h23 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h23 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h23 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h23 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h23 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h23 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h23 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h23 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h23 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h23 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h23 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h23 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h23 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h23 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h23 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h23 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h23 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h23 ? remapVecReadys_1 : remap_idx[5:0] == 6'h23 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_36 = remap_idx_63[5:0] == 6'h24 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h24 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h24 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h24 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h24 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h24 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h24 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h24 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h24 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h24 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h24 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h24 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h24 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h24 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h24 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h24 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h24 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h24 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h24 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h24 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h24 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h24 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h24 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h24 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h24 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h24 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h24 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h24 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h24 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h24 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h24 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h24 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h24 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h24 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h24 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h24 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h24 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h24 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h24 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h24 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h24 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h24 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h24 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h24 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h24 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h24 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h24 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h24 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h24 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h24 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h24 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h24 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h24 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h24 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h24 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h24 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h24 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h24 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h24 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h24 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h24 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h24 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h24 ? remapVecReadys_1 : remap_idx[5:0] == 6'h24 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_37 = remap_idx_63[5:0] == 6'h25 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h25 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h25 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h25 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h25 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h25 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h25 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h25 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h25 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h25 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h25 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h25 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h25 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h25 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h25 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h25 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h25 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h25 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h25 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h25 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h25 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h25 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h25 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h25 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h25 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h25 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h25 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h25 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h25 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h25 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h25 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h25 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h25 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h25 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h25 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h25 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h25 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h25 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h25 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h25 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h25 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h25 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h25 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h25 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h25 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h25 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h25 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h25 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h25 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h25 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h25 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h25 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h25 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h25 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h25 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h25 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h25 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h25 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h25 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h25 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h25 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h25 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h25 ? remapVecReadys_1 : remap_idx[5:0] == 6'h25 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_38 = remap_idx_63[5:0] == 6'h26 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h26 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h26 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h26 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h26 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h26 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h26 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h26 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h26 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h26 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h26 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h26 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h26 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h26 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h26 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h26 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h26 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h26 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h26 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h26 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h26 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h26 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h26 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h26 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h26 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h26 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h26 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h26 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h26 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h26 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h26 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h26 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h26 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h26 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h26 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h26 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h26 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h26 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h26 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h26 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h26 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h26 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h26 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h26 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h26 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h26 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h26 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h26 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h26 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h26 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h26 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h26 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h26 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h26 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h26 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h26 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h26 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h26 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h26 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h26 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h26 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h26 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h26 ? remapVecReadys_1 : remap_idx[5:0] == 6'h26 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_39 = remap_idx_63[5:0] == 6'h27 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h27 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h27 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h27 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h27 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h27 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h27 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h27 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h27 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h27 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h27 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h27 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h27 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h27 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h27 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h27 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h27 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h27 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h27 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h27 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h27 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h27 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h27 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h27 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h27 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h27 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h27 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h27 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h27 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h27 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h27 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h27 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h27 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h27 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h27 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h27 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h27 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h27 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h27 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h27 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h27 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h27 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h27 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h27 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h27 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h27 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h27 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h27 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h27 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h27 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h27 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h27 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h27 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h27 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h27 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h27 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h27 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h27 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h27 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h27 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h27 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h27 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h27 ? remapVecReadys_1 : remap_idx[5:0] == 6'h27 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_40 = remap_idx_63[5:0] == 6'h28 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h28 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h28 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h28 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h28 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h28 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h28 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h28 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h28 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h28 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h28 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h28 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h28 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h28 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h28 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h28 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h28 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h28 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h28 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h28 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h28 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h28 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h28 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h28 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h28 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h28 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h28 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h28 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h28 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h28 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h28 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h28 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h28 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h28 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h28 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h28 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h28 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h28 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h28 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h28 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h28 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h28 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h28 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h28 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h28 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h28 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h28 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h28 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h28 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h28 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h28 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h28 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h28 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h28 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h28 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h28 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h28 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h28 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h28 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h28 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h28 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h28 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h28 ? remapVecReadys_1 : remap_idx[5:0] == 6'h28 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_41 = remap_idx_63[5:0] == 6'h29 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h29 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h29 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h29 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h29 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h29 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h29 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h29 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h29 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h29 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h29 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h29 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h29 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h29 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h29 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h29 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h29 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h29 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h29 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h29 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h29 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h29 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h29 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h29 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h29 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h29 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h29 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h29 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h29 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h29 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h29 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h29 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h29 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h29 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h29 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h29 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h29 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h29 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h29 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h29 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h29 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h29 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h29 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h29 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h29 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h29 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h29 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h29 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h29 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h29 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h29 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h29 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h29 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h29 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h29 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h29 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h29 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h29 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h29 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h29 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h29 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h29 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h29 ? remapVecReadys_1 : remap_idx[5:0] == 6'h29 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_42 = remap_idx_63[5:0] == 6'h2A ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2A ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2A ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2A ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2A ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2A ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2A ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2A ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2A ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2A ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2A ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2A ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2A ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2A ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2A ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2A ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2A ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2A ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2A ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2A ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2A ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2A ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2A ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2A ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2A ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2A ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2A ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2A ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2A ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2A ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2A ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2A ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2A ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2A ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2A ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2A ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2A ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2A ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2A ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2A ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2A ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2A ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2A ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2A ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2A ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2A ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2A ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2A ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2A ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2A ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2A ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2A ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2A ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2A ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2A ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2A ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2A ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2A ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2A ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2A ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2A ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2A ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2A ? remapVecReadys_1 : remap_idx[5:0] == 6'h2A & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_43 = remap_idx_63[5:0] == 6'h2B ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2B ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2B ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2B ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2B ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2B ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2B ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2B ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2B ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2B ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2B ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2B ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2B ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2B ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2B ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2B ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2B ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2B ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2B ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2B ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2B ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2B ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2B ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2B ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2B ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2B ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2B ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2B ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2B ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2B ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2B ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2B ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2B ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2B ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2B ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2B ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2B ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2B ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2B ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2B ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2B ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2B ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2B ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2B ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2B ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2B ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2B ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2B ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2B ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2B ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2B ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2B ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2B ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2B ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2B ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2B ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2B ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2B ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2B ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2B ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2B ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2B ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2B ? remapVecReadys_1 : remap_idx[5:0] == 6'h2B & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_44 = remap_idx_63[5:0] == 6'h2C ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2C ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2C ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2C ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2C ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2C ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2C ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2C ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2C ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2C ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2C ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2C ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2C ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2C ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2C ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2C ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2C ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2C ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2C ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2C ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2C ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2C ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2C ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2C ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2C ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2C ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2C ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2C ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2C ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2C ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2C ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2C ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2C ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2C ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2C ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2C ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2C ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2C ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2C ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2C ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2C ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2C ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2C ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2C ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2C ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2C ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2C ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2C ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2C ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2C ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2C ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2C ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2C ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2C ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2C ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2C ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2C ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2C ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2C ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2C ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2C ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2C ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2C ? remapVecReadys_1 : remap_idx[5:0] == 6'h2C & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_45 = remap_idx_63[5:0] == 6'h2D ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2D ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2D ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2D ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2D ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2D ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2D ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2D ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2D ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2D ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2D ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2D ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2D ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2D ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2D ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2D ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2D ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2D ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2D ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2D ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2D ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2D ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2D ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2D ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2D ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2D ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2D ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2D ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2D ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2D ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2D ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2D ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2D ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2D ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2D ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2D ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2D ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2D ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2D ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2D ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2D ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2D ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2D ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2D ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2D ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2D ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2D ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2D ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2D ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2D ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2D ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2D ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2D ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2D ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2D ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2D ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2D ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2D ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2D ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2D ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2D ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2D ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2D ? remapVecReadys_1 : remap_idx[5:0] == 6'h2D & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_46 = remap_idx_63[5:0] == 6'h2E ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2E ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2E ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2E ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2E ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2E ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2E ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2E ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2E ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2E ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2E ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2E ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2E ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2E ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2E ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2E ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2E ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2E ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2E ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2E ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2E ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2E ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2E ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2E ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2E ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2E ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2E ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2E ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2E ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2E ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2E ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2E ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2E ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2E ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2E ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2E ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2E ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2E ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2E ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2E ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2E ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2E ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2E ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2E ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2E ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2E ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2E ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2E ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2E ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2E ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2E ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2E ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2E ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2E ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2E ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2E ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2E ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2E ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2E ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2E ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2E ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2E ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2E ? remapVecReadys_1 : remap_idx[5:0] == 6'h2E & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_47 = remap_idx_63[5:0] == 6'h2F ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h2F ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h2F ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h2F ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h2F ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h2F ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h2F ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h2F ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h2F ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h2F ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h2F ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h2F ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h2F ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h2F ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h2F ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h2F ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h2F ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h2F ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h2F ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h2F ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h2F ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h2F ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h2F ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h2F ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h2F ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h2F ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h2F ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h2F ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h2F ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h2F ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h2F ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h2F ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h2F ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h2F ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h2F ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h2F ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h2F ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h2F ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h2F ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h2F ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h2F ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h2F ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h2F ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h2F ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h2F ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h2F ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h2F ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h2F ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h2F ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h2F ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h2F ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h2F ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h2F ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h2F ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h2F ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h2F ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h2F ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h2F ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h2F ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h2F ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h2F ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h2F ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h2F ? remapVecReadys_1 : remap_idx[5:0] == 6'h2F & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_48 = remap_idx_63[5:0] == 6'h30 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h30 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h30 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h30 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h30 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h30 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h30 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h30 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h30 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h30 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h30 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h30 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h30 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h30 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h30 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h30 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h30 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h30 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h30 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h30 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h30 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h30 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h30 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h30 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h30 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h30 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h30 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h30 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h30 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h30 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h30 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h30 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h30 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h30 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h30 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h30 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h30 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h30 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h30 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h30 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h30 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h30 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h30 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h30 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h30 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h30 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h30 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h30 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h30 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h30 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h30 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h30 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h30 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h30 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h30 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h30 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h30 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h30 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h30 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h30 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h30 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h30 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h30 ? remapVecReadys_1 : remap_idx[5:0] == 6'h30 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_49 = remap_idx_63[5:0] == 6'h31 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h31 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h31 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h31 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h31 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h31 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h31 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h31 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h31 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h31 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h31 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h31 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h31 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h31 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h31 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h31 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h31 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h31 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h31 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h31 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h31 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h31 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h31 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h31 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h31 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h31 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h31 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h31 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h31 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h31 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h31 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h31 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h31 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h31 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h31 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h31 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h31 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h31 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h31 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h31 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h31 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h31 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h31 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h31 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h31 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h31 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h31 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h31 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h31 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h31 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h31 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h31 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h31 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h31 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h31 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h31 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h31 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h31 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h31 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h31 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h31 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h31 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h31 ? remapVecReadys_1 : remap_idx[5:0] == 6'h31 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_50 = remap_idx_63[5:0] == 6'h32 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h32 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h32 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h32 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h32 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h32 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h32 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h32 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h32 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h32 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h32 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h32 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h32 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h32 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h32 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h32 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h32 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h32 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h32 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h32 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h32 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h32 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h32 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h32 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h32 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h32 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h32 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h32 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h32 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h32 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h32 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h32 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h32 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h32 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h32 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h32 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h32 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h32 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h32 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h32 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h32 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h32 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h32 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h32 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h32 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h32 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h32 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h32 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h32 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h32 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h32 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h32 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h32 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h32 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h32 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h32 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h32 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h32 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h32 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h32 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h32 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h32 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h32 ? remapVecReadys_1 : remap_idx[5:0] == 6'h32 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_51 = remap_idx_63[5:0] == 6'h33 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h33 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h33 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h33 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h33 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h33 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h33 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h33 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h33 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h33 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h33 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h33 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h33 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h33 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h33 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h33 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h33 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h33 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h33 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h33 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h33 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h33 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h33 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h33 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h33 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h33 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h33 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h33 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h33 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h33 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h33 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h33 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h33 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h33 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h33 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h33 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h33 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h33 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h33 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h33 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h33 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h33 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h33 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h33 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h33 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h33 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h33 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h33 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h33 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h33 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h33 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h33 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h33 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h33 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h33 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h33 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h33 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h33 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h33 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h33 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h33 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h33 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h33 ? remapVecReadys_1 : remap_idx[5:0] == 6'h33 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_52 = remap_idx_63[5:0] == 6'h34 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h34 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h34 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h34 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h34 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h34 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h34 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h34 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h34 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h34 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h34 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h34 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h34 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h34 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h34 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h34 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h34 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h34 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h34 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h34 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h34 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h34 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h34 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h34 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h34 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h34 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h34 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h34 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h34 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h34 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h34 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h34 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h34 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h34 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h34 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h34 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h34 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h34 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h34 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h34 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h34 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h34 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h34 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h34 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h34 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h34 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h34 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h34 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h34 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h34 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h34 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h34 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h34 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h34 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h34 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h34 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h34 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h34 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h34 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h34 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h34 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h34 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h34 ? remapVecReadys_1 : remap_idx[5:0] == 6'h34 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_53 = remap_idx_63[5:0] == 6'h35 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h35 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h35 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h35 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h35 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h35 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h35 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h35 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h35 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h35 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h35 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h35 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h35 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h35 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h35 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h35 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h35 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h35 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h35 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h35 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h35 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h35 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h35 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h35 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h35 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h35 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h35 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h35 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h35 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h35 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h35 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h35 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h35 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h35 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h35 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h35 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h35 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h35 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h35 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h35 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h35 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h35 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h35 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h35 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h35 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h35 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h35 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h35 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h35 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h35 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h35 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h35 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h35 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h35 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h35 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h35 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h35 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h35 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h35 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h35 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h35 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h35 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h35 ? remapVecReadys_1 : remap_idx[5:0] == 6'h35 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_54 = remap_idx_63[5:0] == 6'h36 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h36 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h36 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h36 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h36 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h36 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h36 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h36 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h36 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h36 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h36 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h36 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h36 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h36 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h36 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h36 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h36 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h36 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h36 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h36 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h36 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h36 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h36 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h36 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h36 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h36 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h36 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h36 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h36 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h36 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h36 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h36 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h36 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h36 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h36 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h36 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h36 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h36 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h36 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h36 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h36 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h36 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h36 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h36 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h36 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h36 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h36 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h36 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h36 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h36 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h36 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h36 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h36 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h36 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h36 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h36 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h36 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h36 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h36 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h36 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h36 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h36 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h36 ? remapVecReadys_1 : remap_idx[5:0] == 6'h36 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_55 = remap_idx_63[5:0] == 6'h37 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h37 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h37 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h37 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h37 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h37 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h37 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h37 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h37 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h37 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h37 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h37 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h37 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h37 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h37 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h37 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h37 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h37 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h37 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h37 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h37 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h37 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h37 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h37 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h37 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h37 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h37 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h37 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h37 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h37 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h37 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h37 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h37 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h37 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h37 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h37 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h37 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h37 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h37 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h37 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h37 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h37 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h37 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h37 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h37 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h37 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h37 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h37 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h37 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h37 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h37 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h37 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h37 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h37 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h37 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h37 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h37 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h37 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h37 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h37 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h37 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h37 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h37 ? remapVecReadys_1 : remap_idx[5:0] == 6'h37 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_56 = remap_idx_63[5:0] == 6'h38 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h38 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h38 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h38 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h38 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h38 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h38 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h38 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h38 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h38 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h38 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h38 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h38 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h38 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h38 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h38 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h38 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h38 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h38 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h38 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h38 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h38 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h38 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h38 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h38 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h38 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h38 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h38 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h38 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h38 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h38 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h38 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h38 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h38 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h38 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h38 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h38 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h38 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h38 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h38 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h38 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h38 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h38 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h38 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h38 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h38 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h38 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h38 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h38 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h38 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h38 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h38 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h38 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h38 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h38 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h38 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h38 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h38 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h38 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h38 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h38 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h38 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h38 ? remapVecReadys_1 : remap_idx[5:0] == 6'h38 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_57 = remap_idx_63[5:0] == 6'h39 ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h39 ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h39 ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h39 ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h39 ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h39 ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h39 ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h39 ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h39 ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h39 ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h39 ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h39 ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h39 ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h39 ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h39 ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h39 ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h39 ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h39 ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h39 ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h39 ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h39 ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h39 ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h39 ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h39 ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h39 ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h39 ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h39 ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h39 ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h39 ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h39 ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h39 ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h39 ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h39 ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h39 ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h39 ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h39 ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h39 ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h39 ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h39 ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h39 ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h39 ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h39 ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h39 ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h39 ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h39 ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h39 ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h39 ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h39 ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h39 ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h39 ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h39 ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h39 ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h39 ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h39 ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h39 ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h39 ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h39 ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h39 ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h39 ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h39 ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h39 ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h39 ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h39 ? remapVecReadys_1 : remap_idx[5:0] == 6'h39 & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_58 = remap_idx_63[5:0] == 6'h3A ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3A ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3A ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3A ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3A ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3A ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3A ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3A ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3A ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3A ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3A ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3A ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3A ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3A ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3A ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3A ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3A ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3A ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3A ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3A ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3A ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3A ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3A ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3A ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3A ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3A ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3A ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3A ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3A ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3A ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3A ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3A ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3A ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3A ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3A ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3A ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3A ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3A ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3A ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3A ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3A ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3A ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3A ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3A ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3A ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3A ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3A ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3A ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3A ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3A ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3A ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3A ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3A ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3A ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3A ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3A ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3A ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3A ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3A ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3A ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3A ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3A ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3A ? remapVecReadys_1 : remap_idx[5:0] == 6'h3A & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_59 = remap_idx_63[5:0] == 6'h3B ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3B ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3B ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3B ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3B ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3B ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3B ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3B ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3B ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3B ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3B ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3B ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3B ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3B ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3B ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3B ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3B ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3B ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3B ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3B ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3B ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3B ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3B ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3B ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3B ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3B ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3B ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3B ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3B ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3B ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3B ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3B ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3B ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3B ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3B ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3B ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3B ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3B ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3B ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3B ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3B ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3B ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3B ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3B ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3B ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3B ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3B ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3B ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3B ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3B ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3B ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3B ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3B ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3B ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3B ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3B ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3B ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3B ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3B ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3B ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3B ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3B ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3B ? remapVecReadys_1 : remap_idx[5:0] == 6'h3B & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_60 = remap_idx_63[5:0] == 6'h3C ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3C ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3C ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3C ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3C ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3C ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3C ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3C ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3C ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3C ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3C ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3C ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3C ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3C ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3C ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3C ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3C ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3C ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3C ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3C ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3C ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3C ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3C ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3C ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3C ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3C ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3C ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3C ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3C ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3C ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3C ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3C ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3C ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3C ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3C ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3C ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3C ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3C ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3C ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3C ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3C ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3C ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3C ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3C ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3C ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3C ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3C ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3C ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3C ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3C ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3C ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3C ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3C ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3C ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3C ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3C ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3C ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3C ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3C ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3C ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3C ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3C ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3C ? remapVecReadys_1 : remap_idx[5:0] == 6'h3C & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_61 = remap_idx_63[5:0] == 6'h3D ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3D ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3D ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3D ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3D ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3D ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3D ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3D ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3D ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3D ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3D ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3D ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3D ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3D ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3D ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3D ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3D ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3D ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3D ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3D ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3D ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3D ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3D ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3D ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3D ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3D ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3D ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3D ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3D ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3D ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3D ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3D ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3D ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3D ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3D ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3D ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3D ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3D ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3D ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3D ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3D ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3D ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3D ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3D ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3D ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3D ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3D ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3D ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3D ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3D ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3D ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3D ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3D ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3D ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3D ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3D ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3D ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3D ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3D ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3D ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3D ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3D ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3D ? remapVecReadys_1 : remap_idx[5:0] == 6'h3D & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_62 = remap_idx_63[5:0] == 6'h3E ? remapVecReadys_63 : remap_idx_62[5:0] == 6'h3E ? remapVecReadys_62 : remap_idx_61[5:0] == 6'h3E ? remapVecReadys_61 : remap_idx_60[5:0] == 6'h3E ? remapVecReadys_60 : remap_idx_59[5:0] == 6'h3E ? remapVecReadys_59 : remap_idx_58[5:0] == 6'h3E ? remapVecReadys_58 : remap_idx_57[5:0] == 6'h3E ? remapVecReadys_57 : remap_idx_56[5:0] == 6'h3E ? remapVecReadys_56 : remap_idx_55[5:0] == 6'h3E ? remapVecReadys_55 : remap_idx_54[5:0] == 6'h3E ? remapVecReadys_54 : remap_idx_53[5:0] == 6'h3E ? remapVecReadys_53 : remap_idx_52[5:0] == 6'h3E ? remapVecReadys_52 : remap_idx_51[5:0] == 6'h3E ? remapVecReadys_51 : remap_idx_50[5:0] == 6'h3E ? remapVecReadys_50 : remap_idx_49[5:0] == 6'h3E ? remapVecReadys_49 : remap_idx_48[5:0] == 6'h3E ? remapVecReadys_48 : remap_idx_47[5:0] == 6'h3E ? remapVecReadys_47 : remap_idx_46[5:0] == 6'h3E ? remapVecReadys_46 : remap_idx_45[5:0] == 6'h3E ? remapVecReadys_45 : remap_idx_44[5:0] == 6'h3E ? remapVecReadys_44 : remap_idx_43[5:0] == 6'h3E ? remapVecReadys_43 : remap_idx_42[5:0] == 6'h3E ? remapVecReadys_42 : remap_idx_41[5:0] == 6'h3E ? remapVecReadys_41 : remap_idx_40[5:0] == 6'h3E ? remapVecReadys_40 : remap_idx_39[5:0] == 6'h3E ? remapVecReadys_39 : remap_idx_38[5:0] == 6'h3E ? remapVecReadys_38 : remap_idx_37[5:0] == 6'h3E ? remapVecReadys_37 : remap_idx_36[5:0] == 6'h3E ? remapVecReadys_36 : remap_idx_35[5:0] == 6'h3E ? remapVecReadys_35 : remap_idx_34[5:0] == 6'h3E ? remapVecReadys_34 : remap_idx_33[5:0] == 6'h3E ? remapVecReadys_33 : remap_idx_32[5:0] == 6'h3E ? remapVecReadys_32 : remap_idx_31[5:0] == 6'h3E ? remapVecReadys_31 : remap_idx_30[5:0] == 6'h3E ? remapVecReadys_30 : remap_idx_29[5:0] == 6'h3E ? remapVecReadys_29 : remap_idx_28[5:0] == 6'h3E ? remapVecReadys_28 : remap_idx_27[5:0] == 6'h3E ? remapVecReadys_27 : remap_idx_26[5:0] == 6'h3E ? remapVecReadys_26 : remap_idx_25[5:0] == 6'h3E ? remapVecReadys_25 : remap_idx_24[5:0] == 6'h3E ? remapVecReadys_24 : remap_idx_23[5:0] == 6'h3E ? remapVecReadys_23 : remap_idx_22[5:0] == 6'h3E ? remapVecReadys_22 : remap_idx_21[5:0] == 6'h3E ? remapVecReadys_21 : remap_idx_20[5:0] == 6'h3E ? remapVecReadys_20 : remap_idx_19[5:0] == 6'h3E ? remapVecReadys_19 : remap_idx_18[5:0] == 6'h3E ? remapVecReadys_18 : remap_idx_17[5:0] == 6'h3E ? remapVecReadys_17 : remap_idx_16[5:0] == 6'h3E ? remapVecReadys_16 : remap_idx_15[5:0] == 6'h3E ? remapVecReadys_15 : remap_idx_14[5:0] == 6'h3E ? remapVecReadys_14 : remap_idx_13[5:0] == 6'h3E ? remapVecReadys_13 : remap_idx_12[5:0] == 6'h3E ? remapVecReadys_12 : remap_idx_11[5:0] == 6'h3E ? remapVecReadys_11 : remap_idx_10[5:0] == 6'h3E ? remapVecReadys_10 : remap_idx_9[5:0] == 6'h3E ? remapVecReadys_9 : remap_idx_8[5:0] == 6'h3E ? remapVecReadys_8 : remap_idx_7[5:0] == 6'h3E ? remapVecReadys_7 : remap_idx_6[5:0] == 6'h3E ? remapVecReadys_6 : remap_idx_5[5:0] == 6'h3E ? remapVecReadys_5 : remap_idx_4[5:0] == 6'h3E ? remapVecReadys_4 : remap_idx_3[5:0] == 6'h3E ? remapVecReadys_3 : remap_idx_2[5:0] == 6'h3E ? remapVecReadys_2 : remap_idx_1[5:0] == 6'h3E ? remapVecReadys_1 : remap_idx[5:0] == 6'h3E & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] assign bufVecReadys_63 = (&(remap_idx_63[5:0])) ? remapVecReadys_63 : (&(remap_idx_62[5:0])) ? remapVecReadys_62 : (&(remap_idx_61[5:0])) ? remapVecReadys_61 : (&(remap_idx_60[5:0])) ? remapVecReadys_60 : (&(remap_idx_59[5:0])) ? remapVecReadys_59 : (&(remap_idx_58[5:0])) ? remapVecReadys_58 : (&(remap_idx_57[5:0])) ? remapVecReadys_57 : (&(remap_idx_56[5:0])) ? remapVecReadys_56 : (&(remap_idx_55[5:0])) ? remapVecReadys_55 : (&(remap_idx_54[5:0])) ? remapVecReadys_54 : (&(remap_idx_53[5:0])) ? remapVecReadys_53 : (&(remap_idx_52[5:0])) ? remapVecReadys_52 : (&(remap_idx_51[5:0])) ? remapVecReadys_51 : (&(remap_idx_50[5:0])) ? remapVecReadys_50 : (&(remap_idx_49[5:0])) ? remapVecReadys_49 : (&(remap_idx_48[5:0])) ? remapVecReadys_48 : (&(remap_idx_47[5:0])) ? remapVecReadys_47 : (&(remap_idx_46[5:0])) ? remapVecReadys_46 : (&(remap_idx_45[5:0])) ? remapVecReadys_45 : (&(remap_idx_44[5:0])) ? remapVecReadys_44 : (&(remap_idx_43[5:0])) ? remapVecReadys_43 : (&(remap_idx_42[5:0])) ? remapVecReadys_42 : (&(remap_idx_41[5:0])) ? remapVecReadys_41 : (&(remap_idx_40[5:0])) ? remapVecReadys_40 : (&(remap_idx_39[5:0])) ? remapVecReadys_39 : (&(remap_idx_38[5:0])) ? remapVecReadys_38 : (&(remap_idx_37[5:0])) ? remapVecReadys_37 : (&(remap_idx_36[5:0])) ? remapVecReadys_36 : (&(remap_idx_35[5:0])) ? remapVecReadys_35 : (&(remap_idx_34[5:0])) ? remapVecReadys_34 : (&(remap_idx_33[5:0])) ? remapVecReadys_33 : (&(remap_idx_32[5:0])) ? remapVecReadys_32 : (&(remap_idx_31[5:0])) ? remapVecReadys_31 : (&(remap_idx_30[5:0])) ? remapVecReadys_30 : (&(remap_idx_29[5:0])) ? remapVecReadys_29 : (&(remap_idx_28[5:0])) ? remapVecReadys_28 : (&(remap_idx_27[5:0])) ? remapVecReadys_27 : (&(remap_idx_26[5:0])) ? remapVecReadys_26 : (&(remap_idx_25[5:0])) ? remapVecReadys_25 : (&(remap_idx_24[5:0])) ? remapVecReadys_24 : (&(remap_idx_23[5:0])) ? remapVecReadys_23 : (&(remap_idx_22[5:0])) ? remapVecReadys_22 : (&(remap_idx_21[5:0])) ? remapVecReadys_21 : (&(remap_idx_20[5:0])) ? remapVecReadys_20 : (&(remap_idx_19[5:0])) ? remapVecReadys_19 : (&(remap_idx_18[5:0])) ? remapVecReadys_18 : (&(remap_idx_17[5:0])) ? remapVecReadys_17 : (&(remap_idx_16[5:0])) ? remapVecReadys_16 : (&(remap_idx_15[5:0])) ? remapVecReadys_15 : (&(remap_idx_14[5:0])) ? remapVecReadys_14 : (&(remap_idx_13[5:0])) ? remapVecReadys_13 : (&(remap_idx_12[5:0])) ? remapVecReadys_12 : (&(remap_idx_11[5:0])) ? remapVecReadys_11 : (&(remap_idx_10[5:0])) ? remapVecReadys_10 : (&(remap_idx_9[5:0])) ? remapVecReadys_9 : (&(remap_idx_8[5:0])) ? remapVecReadys_8 : (&(remap_idx_7[5:0])) ? remapVecReadys_7 : (&(remap_idx_6[5:0])) ? remapVecReadys_6 : (&(remap_idx_5[5:0])) ? remapVecReadys_5 : (&(remap_idx_4[5:0])) ? remapVecReadys_4 : (&(remap_idx_3[5:0])) ? remapVecReadys_3 : (&(remap_idx_2[5:0])) ? remapVecReadys_2 : (&(remap_idx_1[5:0])) ? remapVecReadys_1 : (&(remap_idx[5:0])) & remapVecReadys_0; // @[CompressedBitsBuffer.scala:129:26, :131:31, :140:28, :144:45, :147:29] wire [1:0] _count_valid_bits_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [2:0] _count_valid_bits_T_1 = {1'h0, _count_valid_bits_T} + {2'h0, remapVecValids_2}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [3:0] _count_valid_bits_T_2 = {1'h0, _count_valid_bits_T_1} + {3'h0, remapVecValids_3}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [4:0] _count_valid_bits_T_3 = {1'h0, _count_valid_bits_T_2} + {4'h0, remapVecValids_4}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [5:0] _count_valid_bits_T_4 = {1'h0, _count_valid_bits_T_3} + {5'h0, remapVecValids_5}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [6:0] _count_valid_bits_T_5 = {1'h0, _count_valid_bits_T_4} + {6'h0, remapVecValids_6}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [7:0] _count_valid_bits_T_6 = {1'h0, _count_valid_bits_T_5} + {7'h0, remapVecValids_7}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [8:0] _count_valid_bits_T_7 = {1'h0, _count_valid_bits_T_6} + {8'h0, remapVecValids_8}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [9:0] _count_valid_bits_T_8 = {1'h0, _count_valid_bits_T_7} + {9'h0, remapVecValids_9}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [10:0] _count_valid_bits_T_9 = {1'h0, _count_valid_bits_T_8} + {10'h0, remapVecValids_10}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [11:0] _count_valid_bits_T_10 = {1'h0, _count_valid_bits_T_9} + {11'h0, remapVecValids_11}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [12:0] _count_valid_bits_T_11 = {1'h0, _count_valid_bits_T_10} + {12'h0, remapVecValids_12}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [13:0] _count_valid_bits_T_12 = {1'h0, _count_valid_bits_T_11} + {13'h0, remapVecValids_13}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [14:0] _count_valid_bits_T_13 = {1'h0, _count_valid_bits_T_12} + {14'h0, remapVecValids_14}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [15:0] _count_valid_bits_T_14 = {1'h0, _count_valid_bits_T_13} + {15'h0, remapVecValids_15}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [16:0] _count_valid_bits_T_15 = {1'h0, _count_valid_bits_T_14} + {16'h0, remapVecValids_16}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [17:0] _count_valid_bits_T_16 = {1'h0, _count_valid_bits_T_15} + {17'h0, remapVecValids_17}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [18:0] _count_valid_bits_T_17 = {1'h0, _count_valid_bits_T_16} + {18'h0, remapVecValids_18}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [19:0] _count_valid_bits_T_18 = {1'h0, _count_valid_bits_T_17} + {19'h0, remapVecValids_19}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [20:0] _count_valid_bits_T_19 = {1'h0, _count_valid_bits_T_18} + {20'h0, remapVecValids_20}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [21:0] _count_valid_bits_T_20 = {1'h0, _count_valid_bits_T_19} + {21'h0, remapVecValids_21}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [22:0] _count_valid_bits_T_21 = {1'h0, _count_valid_bits_T_20} + {22'h0, remapVecValids_22}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [23:0] _count_valid_bits_T_22 = {1'h0, _count_valid_bits_T_21} + {23'h0, remapVecValids_23}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [24:0] _count_valid_bits_T_23 = {1'h0, _count_valid_bits_T_22} + {24'h0, remapVecValids_24}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [25:0] _count_valid_bits_T_24 = {1'h0, _count_valid_bits_T_23} + {25'h0, remapVecValids_25}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [26:0] _count_valid_bits_T_25 = {1'h0, _count_valid_bits_T_24} + {26'h0, remapVecValids_26}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [27:0] _count_valid_bits_T_26 = {1'h0, _count_valid_bits_T_25} + {27'h0, remapVecValids_27}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [28:0] _count_valid_bits_T_27 = {1'h0, _count_valid_bits_T_26} + {28'h0, remapVecValids_28}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [29:0] _count_valid_bits_T_28 = {1'h0, _count_valid_bits_T_27} + {29'h0, remapVecValids_29}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [30:0] _count_valid_bits_T_29 = {1'h0, _count_valid_bits_T_28} + {30'h0, remapVecValids_30}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [31:0] _count_valid_bits_T_30 = {1'h0, _count_valid_bits_T_29} + {31'h0, remapVecValids_31}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [32:0] _count_valid_bits_T_31 = {1'h0, _count_valid_bits_T_30} + {32'h0, remapVecValids_32}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [33:0] _count_valid_bits_T_32 = {1'h0, _count_valid_bits_T_31} + {33'h0, remapVecValids_33}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [34:0] _count_valid_bits_T_33 = {1'h0, _count_valid_bits_T_32} + {34'h0, remapVecValids_34}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [35:0] _count_valid_bits_T_34 = {1'h0, _count_valid_bits_T_33} + {35'h0, remapVecValids_35}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [36:0] _count_valid_bits_T_35 = {1'h0, _count_valid_bits_T_34} + {36'h0, remapVecValids_36}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [37:0] _count_valid_bits_T_36 = {1'h0, _count_valid_bits_T_35} + {37'h0, remapVecValids_37}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [38:0] _count_valid_bits_T_37 = {1'h0, _count_valid_bits_T_36} + {38'h0, remapVecValids_38}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [39:0] _count_valid_bits_T_38 = {1'h0, _count_valid_bits_T_37} + {39'h0, remapVecValids_39}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [40:0] _count_valid_bits_T_39 = {1'h0, _count_valid_bits_T_38} + {40'h0, remapVecValids_40}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [41:0] _count_valid_bits_T_40 = {1'h0, _count_valid_bits_T_39} + {41'h0, remapVecValids_41}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [42:0] _count_valid_bits_T_41 = {1'h0, _count_valid_bits_T_40} + {42'h0, remapVecValids_42}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [43:0] _count_valid_bits_T_42 = {1'h0, _count_valid_bits_T_41} + {43'h0, remapVecValids_43}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [44:0] _count_valid_bits_T_43 = {1'h0, _count_valid_bits_T_42} + {44'h0, remapVecValids_44}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [45:0] _count_valid_bits_T_44 = {1'h0, _count_valid_bits_T_43} + {45'h0, remapVecValids_45}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [46:0] _count_valid_bits_T_45 = {1'h0, _count_valid_bits_T_44} + {46'h0, remapVecValids_46}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [47:0] _count_valid_bits_T_46 = {1'h0, _count_valid_bits_T_45} + {47'h0, remapVecValids_47}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [48:0] _count_valid_bits_T_47 = {1'h0, _count_valid_bits_T_46} + {48'h0, remapVecValids_48}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [49:0] _count_valid_bits_T_48 = {1'h0, _count_valid_bits_T_47} + {49'h0, remapVecValids_49}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [50:0] _count_valid_bits_T_49 = {1'h0, _count_valid_bits_T_48} + {50'h0, remapVecValids_50}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [51:0] _count_valid_bits_T_50 = {1'h0, _count_valid_bits_T_49} + {51'h0, remapVecValids_51}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [52:0] _count_valid_bits_T_51 = {1'h0, _count_valid_bits_T_50} + {52'h0, remapVecValids_52}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [53:0] _count_valid_bits_T_52 = {1'h0, _count_valid_bits_T_51} + {53'h0, remapVecValids_53}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [54:0] _count_valid_bits_T_53 = {1'h0, _count_valid_bits_T_52} + {54'h0, remapVecValids_54}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [55:0] _count_valid_bits_T_54 = {1'h0, _count_valid_bits_T_53} + {55'h0, remapVecValids_55}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [56:0] _count_valid_bits_T_55 = {1'h0, _count_valid_bits_T_54} + {56'h0, remapVecValids_56}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [57:0] _count_valid_bits_T_56 = {1'h0, _count_valid_bits_T_55} + {57'h0, remapVecValids_57}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [58:0] _count_valid_bits_T_57 = {1'h0, _count_valid_bits_T_56} + {58'h0, remapVecValids_58}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [59:0] _count_valid_bits_T_58 = {1'h0, _count_valid_bits_T_57} + {59'h0, remapVecValids_59}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [60:0] _count_valid_bits_T_59 = {1'h0, _count_valid_bits_T_58} + {60'h0, remapVecValids_60}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [61:0] _count_valid_bits_T_60 = {1'h0, _count_valid_bits_T_59} + {61'h0, remapVecValids_61}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [62:0] _count_valid_bits_T_61 = {1'h0, _count_valid_bits_T_60} + {62'h0, remapVecValids_62}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [63:0] count_valid_bits = {1'h0, _count_valid_bits_T_61} + {63'h0, remapVecValids_63}; // @[CompressedBitsBuffer.scala:141:28, :150:64] wire [63:0] count_valid_bytes = {3'h0, count_valid_bits[63:3]}; // @[CompressedBitsBuffer.scala:150:64, :151:44] wire [66:0] _remain_valid_bits_T = {count_valid_bytes, 3'h0}; // @[CompressedBitsBuffer.scala:151:44, :152:65] wire [67:0] _remain_valid_bits_T_1 = {4'h0, count_valid_bits} - {1'h0, _remain_valid_bits_T}; // @[CompressedBitsBuffer.scala:150:64, :152:{44,65}] wire [66:0] remain_valid_bits = _remain_valid_bits_T_1[66:0]; // @[CompressedBitsBuffer.scala:152:44] wire byte_aligned = remain_valid_bits == 67'h0; // @[CompressedBitsBuffer.scala:152:44, :153:41] reg [63:0] len_already_consumed; // @[CompressedBitsBuffer.scala:155:37] wire [64:0] _GEN_250 = {1'h0, len_already_consumed}; // @[CompressedBitsBuffer.scala:155:37, :156:55] wire [64:0] _unconsumed_bits_so_far_T = {1'h0, _buf_lens_q_io_deq_bits} - _GEN_250; // @[CompressedBitsBuffer.scala:65:26, :156:55] wire [63:0] unconsumed_bits_so_far = _unconsumed_bits_so_far_T[63:0]; // @[CompressedBitsBuffer.scala:156:55] wire _last_chunk_T = unconsumed_bits_so_far < 64'h41; // @[CompressedBitsBuffer.scala:156:55, :157:71] assign last_chunk = _buf_lens_q_io_deq_valid & _last_chunk_T; // @[CompressedBitsBuffer.scala:65:26, :157:{44,71}] assign io_consumer_last_chunk_0 = last_chunk; // @[CompressedBitsBuffer.scala:38:7, :157:44] wire _avail_bytes_T = ~byte_aligned; // @[CompressedBitsBuffer.scala:153:41, :159:40] wire _avail_bytes_T_1 = last_chunk & _avail_bytes_T; // @[CompressedBitsBuffer.scala:157:44, :159:{37,40}] wire [64:0] _avail_bytes_T_2 = {1'h0, count_valid_bytes} + 65'h1; // @[CompressedBitsBuffer.scala:151:44, :160:51] wire [63:0] _avail_bytes_T_3 = _avail_bytes_T_2[63:0]; // @[CompressedBitsBuffer.scala:160:51] wire [63:0] avail_bytes = _avail_bytes_T_1 ? _avail_bytes_T_3 : count_valid_bytes; // @[CompressedBitsBuffer.scala:151:44, :159:{24,37}, :160:51] assign enough_data = |avail_bytes; // @[CompressedBitsBuffer.scala:159:24, :162:33] assign io_consumer_valid_0 = enough_data; // @[CompressedBitsBuffer.scala:38:7, :162:33] wire [7:0] count_valid_bits_u8; // @[CompressedBitsBuffer.scala:164:33] assign count_valid_bits_u8 = count_valid_bits[7:0]; // @[CompressedBitsBuffer.scala:150:64, :164:33, :165:23] wire [255:0] _valid_bit_mask_T = 256'h1 << count_valid_bits_u8; // @[CompressedBitsBuffer.scala:164:33, :166:29] wire [256:0] _valid_bit_mask_T_1 = {1'h0, _valid_bit_mask_T} - 257'h1; // @[CompressedBitsBuffer.scala:166:{29,53}] wire [255:0] valid_bit_mask = _valid_bit_mask_T_1[255:0]; // @[CompressedBitsBuffer.scala:166:53] wire [1:0] io_consumer_data_lo_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_lo_lo_lo = {io_consumer_data_lo_lo_lo_lo_hi, io_consumer_data_lo_lo_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_lo_lo_hi = {io_consumer_data_lo_lo_lo_hi_hi, io_consumer_data_lo_lo_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_lo_lo_lo = {io_consumer_data_lo_lo_lo_hi, io_consumer_data_lo_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_lo_hi_lo = {io_consumer_data_lo_lo_hi_lo_hi, io_consumer_data_lo_lo_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_lo_hi_hi = {io_consumer_data_lo_lo_hi_hi_hi, io_consumer_data_lo_lo_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_lo_lo_hi = {io_consumer_data_lo_lo_hi_hi, io_consumer_data_lo_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [15:0] io_consumer_data_lo_lo = {io_consumer_data_lo_lo_hi, io_consumer_data_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_hi_lo_lo = {io_consumer_data_lo_hi_lo_lo_hi, io_consumer_data_lo_hi_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_hi_lo_hi = {io_consumer_data_lo_hi_lo_hi_hi, io_consumer_data_lo_hi_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_lo_hi_lo = {io_consumer_data_lo_hi_lo_hi, io_consumer_data_lo_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_hi_hi_lo = {io_consumer_data_lo_hi_hi_lo_hi, io_consumer_data_lo_hi_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_lo_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_lo_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_lo_hi_hi_hi = {io_consumer_data_lo_hi_hi_hi_hi, io_consumer_data_lo_hi_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_lo_hi_hi = {io_consumer_data_lo_hi_hi_hi, io_consumer_data_lo_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [15:0] io_consumer_data_lo_hi = {io_consumer_data_lo_hi_hi, io_consumer_data_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [31:0] io_consumer_data_lo = {io_consumer_data_lo_hi, io_consumer_data_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_lo_lo_lo_lo = {remapVecData_33, remapVecData_32}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_lo_lo_lo_hi = {remapVecData_35, remapVecData_34}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_lo_lo_lo = {io_consumer_data_hi_lo_lo_lo_hi, io_consumer_data_hi_lo_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_lo_lo_hi_lo = {remapVecData_37, remapVecData_36}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_lo_lo_hi_hi = {remapVecData_39, remapVecData_38}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_lo_lo_hi = {io_consumer_data_hi_lo_lo_hi_hi, io_consumer_data_hi_lo_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_hi_lo_lo = {io_consumer_data_hi_lo_lo_hi, io_consumer_data_hi_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_lo_hi_lo_lo = {remapVecData_41, remapVecData_40}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_lo_hi_lo_hi = {remapVecData_43, remapVecData_42}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_lo_hi_lo = {io_consumer_data_hi_lo_hi_lo_hi, io_consumer_data_hi_lo_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_lo_hi_hi_lo = {remapVecData_45, remapVecData_44}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_lo_hi_hi_hi = {remapVecData_47, remapVecData_46}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_lo_hi_hi = {io_consumer_data_hi_lo_hi_hi_hi, io_consumer_data_hi_lo_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_hi_lo_hi = {io_consumer_data_hi_lo_hi_hi, io_consumer_data_hi_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [15:0] io_consumer_data_hi_lo = {io_consumer_data_hi_lo_hi, io_consumer_data_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_hi_lo_lo_lo = {remapVecData_49, remapVecData_48}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_hi_lo_lo_hi = {remapVecData_51, remapVecData_50}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_hi_lo_lo = {io_consumer_data_hi_hi_lo_lo_hi, io_consumer_data_hi_hi_lo_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_hi_lo_hi_lo = {remapVecData_53, remapVecData_52}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_hi_lo_hi_hi = {remapVecData_55, remapVecData_54}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_hi_lo_hi = {io_consumer_data_hi_hi_lo_hi_hi, io_consumer_data_hi_hi_lo_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_hi_hi_lo = {io_consumer_data_hi_hi_lo_hi, io_consumer_data_hi_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_hi_hi_lo_lo = {remapVecData_57, remapVecData_56}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_hi_hi_lo_hi = {remapVecData_59, remapVecData_58}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_hi_hi_lo = {io_consumer_data_hi_hi_hi_lo_hi, io_consumer_data_hi_hi_hi_lo_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [1:0] io_consumer_data_hi_hi_hi_hi_lo = {remapVecData_61, remapVecData_60}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [1:0] io_consumer_data_hi_hi_hi_hi_hi = {remapVecData_63, remapVecData_62}; // @[CompressedBitsBuffer.scala:139:26, :168:26] wire [3:0] io_consumer_data_hi_hi_hi_hi = {io_consumer_data_hi_hi_hi_hi_hi, io_consumer_data_hi_hi_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [7:0] io_consumer_data_hi_hi_hi = {io_consumer_data_hi_hi_hi_hi, io_consumer_data_hi_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [15:0] io_consumer_data_hi_hi = {io_consumer_data_hi_hi_hi, io_consumer_data_hi_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [31:0] io_consumer_data_hi = {io_consumer_data_hi_hi, io_consumer_data_hi_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [63:0] _io_consumer_data_T = {io_consumer_data_hi, io_consumer_data_lo}; // @[CompressedBitsBuffer.scala:168:26] wire [255:0] _io_consumer_data_T_1 = {192'h0, valid_bit_mask[63:0] & _io_consumer_data_T}; // @[CompressedBitsBuffer.scala:166:53, :168:{26,49}] assign io_consumer_data_0 = _io_consumer_data_T_1[63:0]; // @[CompressedBitsBuffer.scala:38:7, :168:{20,49}] assign io_consumer_avail_bytes_0 = avail_bytes[6:0]; // @[CompressedBitsBuffer.scala:38:7, :159:24, :169:27] wire [9:0] consumed_bits_wide = {io_consumer_consumed_bytes_0, 3'h0}; // @[CompressedBitsBuffer.scala:38:7, :178:55] wire [63:0] _GEN_251 = {54'h0, consumed_bits_wide}; // @[CompressedBitsBuffer.scala:178:55, :179:51] wire consumed_bits_overflow = _GEN_251 > count_valid_bits; // @[CompressedBitsBuffer.scala:150:64, :179:51] wire _consumed_bits_T = ~byte_aligned; // @[CompressedBitsBuffer.scala:153:41, :159:40, :180:41] wire _consumed_bits_T_1 = last_chunk & _consumed_bits_T; // @[CompressedBitsBuffer.scala:157:44, :180:{38,41}] wire _consumed_bits_T_2 = _consumed_bits_T_1 & consumed_bits_overflow; // @[CompressedBitsBuffer.scala:179:51, :180:{38,55}] wire [63:0] consumed_bits = _consumed_bits_T_2 ? count_valid_bits : _GEN_251; // @[CompressedBitsBuffer.scala:150:64, :179:51, :180:{26,55}] wire [64:0] _GEN_252 = {1'h0, consumed_bits}; // @[CompressedBitsBuffer.scala:180:26, :184:95] wire [64:0] _GEN_253 = _GEN_250 + _GEN_252; // @[CompressedBitsBuffer.scala:156:55, :184:95] wire [64:0] _buf_last_T; // @[CompressedBitsBuffer.scala:184:95] assign _buf_last_T = _GEN_253; // @[CompressedBitsBuffer.scala:184:95] wire [64:0] _nxt_len_already_consumed_T; // @[CompressedBitsBuffer.scala:185:74] assign _nxt_len_already_consumed_T = _GEN_253; // @[CompressedBitsBuffer.scala:184:95, :185:74] wire [63:0] _buf_last_T_1 = _buf_last_T[63:0]; // @[CompressedBitsBuffer.scala:184:95] wire _buf_last_T_2 = _buf_lens_q_io_deq_bits == _buf_last_T_1; // @[CompressedBitsBuffer.scala:65:26, :184:{69,95}] wire buf_last = _buf_lens_q_io_deq_valid & _buf_last_T_2; // @[CompressedBitsBuffer.scala:65:26, :184:{42,69}] wire [63:0] _nxt_len_already_consumed_T_1 = _nxt_len_already_consumed_T[63:0]; // @[CompressedBitsBuffer.scala:185:74] wire [63:0] nxt_len_already_consumed = buf_last ? 64'h0 : _nxt_len_already_consumed_T_1; // @[CompressedBitsBuffer.scala:184:42, :185:{37,74}] wire _T_337 = io_consumer_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_32_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_32_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_33_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_33_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_34_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_34_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_35_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_35_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_36_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_36_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_37_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_37_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_38_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_38_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_39_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_39_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_40_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_40_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_41_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_41_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_42_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_42_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_43_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_43_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_44_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_44_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_45_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_45_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_46_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_46_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_47_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_47_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_48_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_48_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_49_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_49_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_50_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_50_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_51_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_51_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_52_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_52_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_53_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_53_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_54_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_54_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_55_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_55_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_56_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_56_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_57_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_57_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_58_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_58_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_59_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_59_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_60_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_60_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_61_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_61_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_62_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_62_T_1 = _T_337; // @[Misc.scala:29:18] wire _remapVecReadys_63_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_63_T_1 = _T_337; // @[Misc.scala:29:18] wire _buf_lens_q_io_deq_ready_T; // @[Misc.scala:29:18] assign _buf_lens_q_io_deq_ready_T = _T_337; // @[Misc.scala:29:18] wire [64:0] _read_start_idx_T = {58'h0, read_start_idx} + _GEN_252; // @[CompressedBitsBuffer.scala:126:31, :184:95, :187:39] wire [64:0] _GEN_254 = _read_start_idx_T % 65'h40; // @[CompressedBitsBuffer.scala:187:{39,57}] wire [6:0] _read_start_idx_T_1 = _GEN_254[6:0]; // @[CompressedBitsBuffer.scala:187:57] wire _remapVecReadys_0_T = |consumed_bits; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_0_T_2 = _remapVecReadys_0_T & _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign remapVecReadys_0 = _remapVecReadys_0_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_1_T = |(consumed_bits[63:1]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_1_T_2 = _remapVecReadys_1_T & _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign remapVecReadys_1 = _remapVecReadys_1_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_2_T = consumed_bits > 64'h2; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_2_T_2 = _remapVecReadys_2_T & _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign remapVecReadys_2 = _remapVecReadys_2_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_3_T = |(consumed_bits[63:2]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_3_T_2 = _remapVecReadys_3_T & _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign remapVecReadys_3 = _remapVecReadys_3_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_4_T = consumed_bits > 64'h4; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_4_T_2 = _remapVecReadys_4_T & _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign remapVecReadys_4 = _remapVecReadys_4_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_5_T = consumed_bits > 64'h5; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_5_T_2 = _remapVecReadys_5_T & _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign remapVecReadys_5 = _remapVecReadys_5_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_6_T = consumed_bits > 64'h6; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_6_T_2 = _remapVecReadys_6_T & _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign remapVecReadys_6 = _remapVecReadys_6_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_7_T = |(consumed_bits[63:3]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_7_T_2 = _remapVecReadys_7_T & _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign remapVecReadys_7 = _remapVecReadys_7_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_8_T = consumed_bits > 64'h8; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_8_T_2 = _remapVecReadys_8_T & _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign remapVecReadys_8 = _remapVecReadys_8_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_9_T = consumed_bits > 64'h9; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_9_T_2 = _remapVecReadys_9_T & _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign remapVecReadys_9 = _remapVecReadys_9_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_10_T = consumed_bits > 64'hA; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_10_T_2 = _remapVecReadys_10_T & _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign remapVecReadys_10 = _remapVecReadys_10_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_11_T = consumed_bits > 64'hB; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_11_T_2 = _remapVecReadys_11_T & _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign remapVecReadys_11 = _remapVecReadys_11_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_12_T = consumed_bits > 64'hC; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_12_T_2 = _remapVecReadys_12_T & _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign remapVecReadys_12 = _remapVecReadys_12_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_13_T = consumed_bits > 64'hD; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_13_T_2 = _remapVecReadys_13_T & _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign remapVecReadys_13 = _remapVecReadys_13_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_14_T = consumed_bits > 64'hE; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_14_T_2 = _remapVecReadys_14_T & _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign remapVecReadys_14 = _remapVecReadys_14_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_15_T = |(consumed_bits[63:4]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_15_T_2 = _remapVecReadys_15_T & _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign remapVecReadys_15 = _remapVecReadys_15_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_16_T = consumed_bits > 64'h10; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_16_T_2 = _remapVecReadys_16_T & _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign remapVecReadys_16 = _remapVecReadys_16_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_17_T = consumed_bits > 64'h11; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_17_T_2 = _remapVecReadys_17_T & _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign remapVecReadys_17 = _remapVecReadys_17_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_18_T = consumed_bits > 64'h12; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_18_T_2 = _remapVecReadys_18_T & _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign remapVecReadys_18 = _remapVecReadys_18_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_19_T = consumed_bits > 64'h13; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_19_T_2 = _remapVecReadys_19_T & _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign remapVecReadys_19 = _remapVecReadys_19_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_20_T = consumed_bits > 64'h14; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_20_T_2 = _remapVecReadys_20_T & _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign remapVecReadys_20 = _remapVecReadys_20_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_21_T = consumed_bits > 64'h15; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_21_T_2 = _remapVecReadys_21_T & _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign remapVecReadys_21 = _remapVecReadys_21_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_22_T = consumed_bits > 64'h16; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_22_T_2 = _remapVecReadys_22_T & _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign remapVecReadys_22 = _remapVecReadys_22_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_23_T = consumed_bits > 64'h17; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_23_T_2 = _remapVecReadys_23_T & _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign remapVecReadys_23 = _remapVecReadys_23_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_24_T = consumed_bits > 64'h18; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_24_T_2 = _remapVecReadys_24_T & _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign remapVecReadys_24 = _remapVecReadys_24_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_25_T = consumed_bits > 64'h19; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_25_T_2 = _remapVecReadys_25_T & _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign remapVecReadys_25 = _remapVecReadys_25_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_26_T = consumed_bits > 64'h1A; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_26_T_2 = _remapVecReadys_26_T & _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign remapVecReadys_26 = _remapVecReadys_26_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_27_T = consumed_bits > 64'h1B; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_27_T_2 = _remapVecReadys_27_T & _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign remapVecReadys_27 = _remapVecReadys_27_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_28_T = consumed_bits > 64'h1C; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_28_T_2 = _remapVecReadys_28_T & _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign remapVecReadys_28 = _remapVecReadys_28_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_29_T = consumed_bits > 64'h1D; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_29_T_2 = _remapVecReadys_29_T & _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign remapVecReadys_29 = _remapVecReadys_29_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_30_T = consumed_bits > 64'h1E; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_30_T_2 = _remapVecReadys_30_T & _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign remapVecReadys_30 = _remapVecReadys_30_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_31_T = |(consumed_bits[63:5]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_31_T_2 = _remapVecReadys_31_T & _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign remapVecReadys_31 = _remapVecReadys_31_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_32_T = consumed_bits > 64'h20; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_32_T_2 = _remapVecReadys_32_T & _remapVecReadys_32_T_1; // @[Misc.scala:29:18] assign remapVecReadys_32 = _remapVecReadys_32_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_33_T = consumed_bits > 64'h21; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_33_T_2 = _remapVecReadys_33_T & _remapVecReadys_33_T_1; // @[Misc.scala:29:18] assign remapVecReadys_33 = _remapVecReadys_33_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_34_T = consumed_bits > 64'h22; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_34_T_2 = _remapVecReadys_34_T & _remapVecReadys_34_T_1; // @[Misc.scala:29:18] assign remapVecReadys_34 = _remapVecReadys_34_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_35_T = consumed_bits > 64'h23; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_35_T_2 = _remapVecReadys_35_T & _remapVecReadys_35_T_1; // @[Misc.scala:29:18] assign remapVecReadys_35 = _remapVecReadys_35_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_36_T = consumed_bits > 64'h24; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_36_T_2 = _remapVecReadys_36_T & _remapVecReadys_36_T_1; // @[Misc.scala:29:18] assign remapVecReadys_36 = _remapVecReadys_36_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_37_T = consumed_bits > 64'h25; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_37_T_2 = _remapVecReadys_37_T & _remapVecReadys_37_T_1; // @[Misc.scala:29:18] assign remapVecReadys_37 = _remapVecReadys_37_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_38_T = consumed_bits > 64'h26; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_38_T_2 = _remapVecReadys_38_T & _remapVecReadys_38_T_1; // @[Misc.scala:29:18] assign remapVecReadys_38 = _remapVecReadys_38_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_39_T = consumed_bits > 64'h27; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_39_T_2 = _remapVecReadys_39_T & _remapVecReadys_39_T_1; // @[Misc.scala:29:18] assign remapVecReadys_39 = _remapVecReadys_39_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_40_T = consumed_bits > 64'h28; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_40_T_2 = _remapVecReadys_40_T & _remapVecReadys_40_T_1; // @[Misc.scala:29:18] assign remapVecReadys_40 = _remapVecReadys_40_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_41_T = consumed_bits > 64'h29; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_41_T_2 = _remapVecReadys_41_T & _remapVecReadys_41_T_1; // @[Misc.scala:29:18] assign remapVecReadys_41 = _remapVecReadys_41_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_42_T = consumed_bits > 64'h2A; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_42_T_2 = _remapVecReadys_42_T & _remapVecReadys_42_T_1; // @[Misc.scala:29:18] assign remapVecReadys_42 = _remapVecReadys_42_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_43_T = consumed_bits > 64'h2B; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_43_T_2 = _remapVecReadys_43_T & _remapVecReadys_43_T_1; // @[Misc.scala:29:18] assign remapVecReadys_43 = _remapVecReadys_43_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_44_T = consumed_bits > 64'h2C; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_44_T_2 = _remapVecReadys_44_T & _remapVecReadys_44_T_1; // @[Misc.scala:29:18] assign remapVecReadys_44 = _remapVecReadys_44_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_45_T = consumed_bits > 64'h2D; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_45_T_2 = _remapVecReadys_45_T & _remapVecReadys_45_T_1; // @[Misc.scala:29:18] assign remapVecReadys_45 = _remapVecReadys_45_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_46_T = consumed_bits > 64'h2E; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_46_T_2 = _remapVecReadys_46_T & _remapVecReadys_46_T_1; // @[Misc.scala:29:18] assign remapVecReadys_46 = _remapVecReadys_46_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_47_T = consumed_bits > 64'h2F; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_47_T_2 = _remapVecReadys_47_T & _remapVecReadys_47_T_1; // @[Misc.scala:29:18] assign remapVecReadys_47 = _remapVecReadys_47_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_48_T = consumed_bits > 64'h30; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_48_T_2 = _remapVecReadys_48_T & _remapVecReadys_48_T_1; // @[Misc.scala:29:18] assign remapVecReadys_48 = _remapVecReadys_48_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_49_T = consumed_bits > 64'h31; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_49_T_2 = _remapVecReadys_49_T & _remapVecReadys_49_T_1; // @[Misc.scala:29:18] assign remapVecReadys_49 = _remapVecReadys_49_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_50_T = consumed_bits > 64'h32; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_50_T_2 = _remapVecReadys_50_T & _remapVecReadys_50_T_1; // @[Misc.scala:29:18] assign remapVecReadys_50 = _remapVecReadys_50_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_51_T = consumed_bits > 64'h33; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_51_T_2 = _remapVecReadys_51_T & _remapVecReadys_51_T_1; // @[Misc.scala:29:18] assign remapVecReadys_51 = _remapVecReadys_51_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_52_T = consumed_bits > 64'h34; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_52_T_2 = _remapVecReadys_52_T & _remapVecReadys_52_T_1; // @[Misc.scala:29:18] assign remapVecReadys_52 = _remapVecReadys_52_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_53_T = consumed_bits > 64'h35; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_53_T_2 = _remapVecReadys_53_T & _remapVecReadys_53_T_1; // @[Misc.scala:29:18] assign remapVecReadys_53 = _remapVecReadys_53_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_54_T = consumed_bits > 64'h36; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_54_T_2 = _remapVecReadys_54_T & _remapVecReadys_54_T_1; // @[Misc.scala:29:18] assign remapVecReadys_54 = _remapVecReadys_54_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_55_T = consumed_bits > 64'h37; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_55_T_2 = _remapVecReadys_55_T & _remapVecReadys_55_T_1; // @[Misc.scala:29:18] assign remapVecReadys_55 = _remapVecReadys_55_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_56_T = consumed_bits > 64'h38; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_56_T_2 = _remapVecReadys_56_T & _remapVecReadys_56_T_1; // @[Misc.scala:29:18] assign remapVecReadys_56 = _remapVecReadys_56_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_57_T = consumed_bits > 64'h39; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_57_T_2 = _remapVecReadys_57_T & _remapVecReadys_57_T_1; // @[Misc.scala:29:18] assign remapVecReadys_57 = _remapVecReadys_57_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_58_T = consumed_bits > 64'h3A; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_58_T_2 = _remapVecReadys_58_T & _remapVecReadys_58_T_1; // @[Misc.scala:29:18] assign remapVecReadys_58 = _remapVecReadys_58_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_59_T = consumed_bits > 64'h3B; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_59_T_2 = _remapVecReadys_59_T & _remapVecReadys_59_T_1; // @[Misc.scala:29:18] assign remapVecReadys_59 = _remapVecReadys_59_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_60_T = consumed_bits > 64'h3C; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_60_T_2 = _remapVecReadys_60_T & _remapVecReadys_60_T_1; // @[Misc.scala:29:18] assign remapVecReadys_60 = _remapVecReadys_60_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_61_T = consumed_bits > 64'h3D; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_61_T_2 = _remapVecReadys_61_T & _remapVecReadys_61_T_1; // @[Misc.scala:29:18] assign remapVecReadys_61 = _remapVecReadys_61_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_62_T = consumed_bits > 64'h3E; // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_62_T_2 = _remapVecReadys_62_T & _remapVecReadys_62_T_1; // @[Misc.scala:29:18] assign remapVecReadys_62 = _remapVecReadys_62_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _remapVecReadys_63_T = |(consumed_bits[63:6]); // @[CompressedBitsBuffer.scala:180:26, :197:31] assign _remapVecReadys_63_T_2 = _remapVecReadys_63_T & _remapVecReadys_63_T_1; // @[Misc.scala:29:18] assign remapVecReadys_63 = _remapVecReadys_63_T_2; // @[CompressedBitsBuffer.scala:140:28, :197:48] wire _buf_lens_q_io_deq_ready_T_1 = _buf_lens_q_io_deq_ready_T & buf_last; // @[Misc.scala:29:18] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_43; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_86 = {1'h0, loginfo_cycles_43} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_87 = _loginfo_cycles_T_86[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_44; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_88 = {1'h0, loginfo_cycles_44} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_89 = _loginfo_cycles_T_88[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_45; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_90 = {1'h0, loginfo_cycles_45} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_91 = _loginfo_cycles_T_90[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_46; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_92 = {1'h0, loginfo_cycles_46} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_93 = _loginfo_cycles_T_92[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_47; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_94 = {1'h0, loginfo_cycles_47} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_95 = _loginfo_cycles_T_94[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_48; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_96 = {1'h0, loginfo_cycles_48} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_97 = _loginfo_cycles_T_96[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_49; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_98 = {1'h0, loginfo_cycles_49} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_99 = _loginfo_cycles_T_98[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_50; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_100 = {1'h0, loginfo_cycles_50} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_101 = _loginfo_cycles_T_100[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_51; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_102 = {1'h0, loginfo_cycles_51} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_103 = _loginfo_cycles_T_102[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_52; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_104 = {1'h0, loginfo_cycles_52} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_105 = _loginfo_cycles_T_104[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_53; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_106 = {1'h0, loginfo_cycles_53} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_107 = _loginfo_cycles_T_106[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_54; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_108 = {1'h0, loginfo_cycles_54} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_109 = _loginfo_cycles_T_108[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_55; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_110 = {1'h0, loginfo_cycles_55} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_111 = _loginfo_cycles_T_110[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_56; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_112 = {1'h0, loginfo_cycles_56} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_113 = _loginfo_cycles_T_112[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_57; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_114 = {1'h0, loginfo_cycles_57} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_115 = _loginfo_cycles_T_114[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_58; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_116 = {1'h0, loginfo_cycles_58} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_117 = _loginfo_cycles_T_116[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_59; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_118 = {1'h0, loginfo_cycles_59} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_119 = _loginfo_cycles_T_118[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_60; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_120 = {1'h0, loginfo_cycles_60} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_121 = _loginfo_cycles_T_120[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_61; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_122 = {1'h0, loginfo_cycles_61} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_123 = _loginfo_cycles_T_122[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_62; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_124 = {1'h0, loginfo_cycles_62} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_125 = _loginfo_cycles_T_124[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_63; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_126 = {1'h0, loginfo_cycles_63} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_127 = _loginfo_cycles_T_126[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_64; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_128 = {1'h0, loginfo_cycles_64} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_129 = _loginfo_cycles_T_128[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_65; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_130 = {1'h0, loginfo_cycles_65} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_131 = _loginfo_cycles_T_130[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_66; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_132 = {1'h0, loginfo_cycles_66} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_133 = _loginfo_cycles_T_132[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_67; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_134 = {1'h0, loginfo_cycles_67} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_135 = _loginfo_cycles_T_134[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_68; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_136 = {1'h0, loginfo_cycles_68} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_137 = _loginfo_cycles_T_136[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_69; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_138 = {1'h0, loginfo_cycles_69} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_139 = _loginfo_cycles_T_138[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_70; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_140 = {1'h0, loginfo_cycles_70} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_141 = _loginfo_cycles_T_140[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_71; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_142 = {1'h0, loginfo_cycles_71} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_143 = _loginfo_cycles_T_142[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_72; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_144 = {1'h0, loginfo_cycles_72} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_145 = _loginfo_cycles_T_144[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_73; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_146 = {1'h0, loginfo_cycles_73} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_147 = _loginfo_cycles_T_146[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_74; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_148 = {1'h0, loginfo_cycles_74} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_149 = _loginfo_cycles_T_148[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_75; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_150 = {1'h0, loginfo_cycles_75} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_151 = _loginfo_cycles_T_150[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_76; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_152 = {1'h0, loginfo_cycles_76} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_153 = _loginfo_cycles_T_152[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_77; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_154 = {1'h0, loginfo_cycles_77} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_155 = _loginfo_cycles_T_154[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_78; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_156 = {1'h0, loginfo_cycles_78} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_157 = _loginfo_cycles_T_156[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_79; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_158 = {1'h0, loginfo_cycles_79} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_159 = _loginfo_cycles_T_158[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_80; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_160 = {1'h0, loginfo_cycles_80} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_161 = _loginfo_cycles_T_160[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_81; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_162 = {1'h0, loginfo_cycles_81} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_163 = _loginfo_cycles_T_162[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_82; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_164 = {1'h0, loginfo_cycles_82} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_165 = _loginfo_cycles_T_164[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_83; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_166 = {1'h0, loginfo_cycles_83} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_167 = _loginfo_cycles_T_166[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_84; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_168 = {1'h0, loginfo_cycles_84} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_169 = _loginfo_cycles_T_168[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_85; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_170 = {1'h0, loginfo_cycles_85} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_171 = _loginfo_cycles_T_170[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_86; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_172 = {1'h0, loginfo_cycles_86} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_173 = _loginfo_cycles_T_172[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_87; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_174 = {1'h0, loginfo_cycles_87} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_175 = _loginfo_cycles_T_174[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_88; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_176 = {1'h0, loginfo_cycles_88} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_177 = _loginfo_cycles_T_176[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_89; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_178 = {1'h0, loginfo_cycles_89} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_179 = _loginfo_cycles_T_178[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_90; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_180 = {1'h0, loginfo_cycles_90} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_181 = _loginfo_cycles_T_180[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_91; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_182 = {1'h0, loginfo_cycles_91} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_183 = _loginfo_cycles_T_182[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_92; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_184 = {1'h0, loginfo_cycles_92} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_185 = _loginfo_cycles_T_184[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_93; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_186 = {1'h0, loginfo_cycles_93} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_187 = _loginfo_cycles_T_186[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_94; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_188 = {1'h0, loginfo_cycles_94} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_189 = _loginfo_cycles_T_188[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_95; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_190 = {1'h0, loginfo_cycles_95} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_191 = _loginfo_cycles_T_190[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_96; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_192 = {1'h0, loginfo_cycles_96} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_193 = _loginfo_cycles_T_192[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_97; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_194 = {1'h0, loginfo_cycles_97} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_195 = _loginfo_cycles_T_194[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_98; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_196 = {1'h0, loginfo_cycles_98} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_197 = _loginfo_cycles_T_196[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_99; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_198 = {1'h0, loginfo_cycles_99} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_199 = _loginfo_cycles_T_198[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_100; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_200 = {1'h0, loginfo_cycles_100} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_201 = _loginfo_cycles_T_200[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_101; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_202 = {1'h0, loginfo_cycles_101} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_203 = _loginfo_cycles_T_202[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_102; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_204 = {1'h0, loginfo_cycles_102} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_205 = _loginfo_cycles_T_204[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_103; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_206 = {1'h0, loginfo_cycles_103} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_207 = _loginfo_cycles_T_206[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_104; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_208 = {1'h0, loginfo_cycles_104} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_209 = _loginfo_cycles_T_208[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_105; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_210 = {1'h0, loginfo_cycles_105} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_211 = _loginfo_cycles_T_210[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_106; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_212 = {1'h0, loginfo_cycles_106} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_213 = _loginfo_cycles_T_212[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_107; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_214 = {1'h0, loginfo_cycles_107} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_215 = _loginfo_cycles_T_214[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_108; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_216 = {1'h0, loginfo_cycles_108} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_217 = _loginfo_cycles_T_216[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_109; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_218 = {1'h0, loginfo_cycles_109} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_219 = _loginfo_cycles_T_218[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_110; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_220 = {1'h0, loginfo_cycles_110} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_221 = _loginfo_cycles_T_220[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_111; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_222 = {1'h0, loginfo_cycles_111} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_223 = _loginfo_cycles_T_222[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_112; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_224 = {1'h0, loginfo_cycles_112} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_225 = _loginfo_cycles_T_224[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_113; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_226 = {1'h0, loginfo_cycles_113} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_227 = _loginfo_cycles_T_226[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_114; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_228 = {1'h0, loginfo_cycles_114} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_229 = _loginfo_cycles_T_228[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_115; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_230 = {1'h0, loginfo_cycles_115} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_231 = _loginfo_cycles_T_230[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_116; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_232 = {1'h0, loginfo_cycles_116} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_233 = _loginfo_cycles_T_232[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_117; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_234 = {1'h0, loginfo_cycles_117} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_235 = _loginfo_cycles_T_234[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_118; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_236 = {1'h0, loginfo_cycles_118} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_237 = _loginfo_cycles_T_236[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_119; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_238 = {1'h0, loginfo_cycles_119} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_239 = _loginfo_cycles_T_238[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_120; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_240 = {1'h0, loginfo_cycles_120} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_241 = _loginfo_cycles_T_240[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_121; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_242 = {1'h0, loginfo_cycles_121} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_243 = _loginfo_cycles_T_242[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_122; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_244 = {1'h0, loginfo_cycles_122} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_245 = _loginfo_cycles_T_244[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_123; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_246 = {1'h0, loginfo_cycles_123} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_247 = _loginfo_cycles_T_246[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_124; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_248 = {1'h0, loginfo_cycles_124} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_249 = _loginfo_cycles_T_248[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_125; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_250 = {1'h0, loginfo_cycles_125} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_251 = _loginfo_cycles_T_250[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_126; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_252 = {1'h0, loginfo_cycles_126} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_253 = _loginfo_cycles_T_252[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_127; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_254 = {1'h0, loginfo_cycles_127} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_255 = _loginfo_cycles_T_254[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_128; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_256 = {1'h0, loginfo_cycles_128} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_257 = _loginfo_cycles_T_256[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_129; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_258 = {1'h0, loginfo_cycles_129} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_259 = _loginfo_cycles_T_258[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_130; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_260 = {1'h0, loginfo_cycles_130} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_261 = _loginfo_cycles_T_260[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_131; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_262 = {1'h0, loginfo_cycles_131} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_263 = _loginfo_cycles_T_262[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_132; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_264 = {1'h0, loginfo_cycles_132} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_265 = _loginfo_cycles_T_264[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_133; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_266 = {1'h0, loginfo_cycles_133} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_267 = _loginfo_cycles_T_266[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_134; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_268 = {1'h0, loginfo_cycles_134} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_269 = _loginfo_cycles_T_268[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_135; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_270 = {1'h0, loginfo_cycles_135} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_271 = _loginfo_cycles_T_270[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_136; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_272 = {1'h0, loginfo_cycles_136} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_273 = _loginfo_cycles_T_272[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_137; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_274 = {1'h0, loginfo_cycles_137} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_275 = _loginfo_cycles_T_274[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_138; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_276 = {1'h0, loginfo_cycles_138} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_277 = _loginfo_cycles_T_276[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_139; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_278 = {1'h0, loginfo_cycles_139} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_279 = _loginfo_cycles_T_278[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_140; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_280 = {1'h0, loginfo_cycles_140} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_281 = _loginfo_cycles_T_280[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_141; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_282 = {1'h0, loginfo_cycles_141} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_283 = _loginfo_cycles_T_282[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_142; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_284 = {1'h0, loginfo_cycles_142} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_285 = _loginfo_cycles_T_284[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_143; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_286 = {1'h0, loginfo_cycles_143} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_287 = _loginfo_cycles_T_286[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_144; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_288 = {1'h0, loginfo_cycles_144} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_289 = _loginfo_cycles_T_288[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_145; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_290 = {1'h0, loginfo_cycles_145} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_291 = _loginfo_cycles_T_290[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_146; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_292 = {1'h0, loginfo_cycles_146} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_293 = _loginfo_cycles_T_292[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_147; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_294 = {1'h0, loginfo_cycles_147} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_295 = _loginfo_cycles_T_294[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_148; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_296 = {1'h0, loginfo_cycles_148} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_297 = _loginfo_cycles_T_296[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_149; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_298 = {1'h0, loginfo_cycles_149} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_299 = _loginfo_cycles_T_298[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_150; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_300 = {1'h0, loginfo_cycles_150} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_301 = _loginfo_cycles_T_300[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_151; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_302 = {1'h0, loginfo_cycles_151} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_303 = _loginfo_cycles_T_302[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_152; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_304 = {1'h0, loginfo_cycles_152} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_305 = _loginfo_cycles_T_304[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_153; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_306 = {1'h0, loginfo_cycles_153} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_307 = _loginfo_cycles_T_306[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_154; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_308 = {1'h0, loginfo_cycles_154} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_309 = _loginfo_cycles_T_308[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_155; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_310 = {1'h0, loginfo_cycles_155} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_311 = _loginfo_cycles_T_310[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_156; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_312 = {1'h0, loginfo_cycles_156} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_313 = _loginfo_cycles_T_312[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_157; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_314 = {1'h0, loginfo_cycles_157} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_315 = _loginfo_cycles_T_314[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_158; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_316 = {1'h0, loginfo_cycles_158} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_317 = _loginfo_cycles_T_316[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_159; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_318 = {1'h0, loginfo_cycles_159} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_319 = _loginfo_cycles_T_318[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_160; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_320 = {1'h0, loginfo_cycles_160} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_321 = _loginfo_cycles_T_320[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_161; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_322 = {1'h0, loginfo_cycles_161} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_323 = _loginfo_cycles_T_322[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_162; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_324 = {1'h0, loginfo_cycles_162} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_325 = _loginfo_cycles_T_324[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_163; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_326 = {1'h0, loginfo_cycles_163} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_327 = _loginfo_cycles_T_326[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_164; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_328 = {1'h0, loginfo_cycles_164} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_329 = _loginfo_cycles_T_328[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_165; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_330 = {1'h0, loginfo_cycles_165} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_331 = _loginfo_cycles_T_330[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_166; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_332 = {1'h0, loginfo_cycles_166} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_333 = _loginfo_cycles_T_332[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_167; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_334 = {1'h0, loginfo_cycles_167} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_335 = _loginfo_cycles_T_334[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_168; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_336 = {1'h0, loginfo_cycles_168} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_337 = _loginfo_cycles_T_336[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_169; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_338 = {1'h0, loginfo_cycles_169} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_339 = _loginfo_cycles_T_338[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_170; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_340 = {1'h0, loginfo_cycles_170} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_341 = _loginfo_cycles_T_340[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_171; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_342 = {1'h0, loginfo_cycles_171} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_343 = _loginfo_cycles_T_342[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_172; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_344 = {1'h0, loginfo_cycles_172} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_345 = _loginfo_cycles_T_344[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_173; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_346 = {1'h0, loginfo_cycles_173} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_347 = _loginfo_cycles_T_346[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_174; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_348 = {1'h0, loginfo_cycles_174} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_349 = _loginfo_cycles_T_348[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_175; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_350 = {1'h0, loginfo_cycles_175} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_351 = _loginfo_cycles_T_350[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_176; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_352 = {1'h0, loginfo_cycles_176} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_353 = _loginfo_cycles_T_352[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_177; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_354 = {1'h0, loginfo_cycles_177} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_355 = _loginfo_cycles_T_354[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_178; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_356 = {1'h0, loginfo_cycles_178} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_357 = _loginfo_cycles_T_356[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_179; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_358 = {1'h0, loginfo_cycles_179} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_359 = _loginfo_cycles_T_358[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_180; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_360 = {1'h0, loginfo_cycles_180} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_361 = _loginfo_cycles_T_360[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_181; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_362 = {1'h0, loginfo_cycles_181} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_363 = _loginfo_cycles_T_362[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_182; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_364 = {1'h0, loginfo_cycles_182} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_365 = _loginfo_cycles_T_364[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_183; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_366 = {1'h0, loginfo_cycles_183} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_367 = _loginfo_cycles_T_366[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_184; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_368 = {1'h0, loginfo_cycles_184} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_369 = _loginfo_cycles_T_368[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_185; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_370 = {1'h0, loginfo_cycles_185} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_371 = _loginfo_cycles_T_370[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_186; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_372 = {1'h0, loginfo_cycles_186} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_373 = _loginfo_cycles_T_372[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_187; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_374 = {1'h0, loginfo_cycles_187} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_375 = _loginfo_cycles_T_374[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_188; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_376 = {1'h0, loginfo_cycles_188} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_377 = _loginfo_cycles_T_376[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_189; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_378 = {1'h0, loginfo_cycles_189} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_379 = _loginfo_cycles_T_378[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_190; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_380 = {1'h0, loginfo_cycles_190} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_381 = _loginfo_cycles_T_380[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_191; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_382 = {1'h0, loginfo_cycles_191} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_383 = _loginfo_cycles_T_382[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_192; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_384 = {1'h0, loginfo_cycles_192} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_385 = _loginfo_cycles_T_384[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_193; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_386 = {1'h0, loginfo_cycles_193} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_387 = _loginfo_cycles_T_386[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_194; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_388 = {1'h0, loginfo_cycles_194} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_389 = _loginfo_cycles_T_388[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_195; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_390 = {1'h0, loginfo_cycles_195} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_391 = _loginfo_cycles_T_390[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_196; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_392 = {1'h0, loginfo_cycles_196} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_393 = _loginfo_cycles_T_392[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_197; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_394 = {1'h0, loginfo_cycles_197} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_395 = _loginfo_cycles_T_394[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_198; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_396 = {1'h0, loginfo_cycles_198} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_397 = _loginfo_cycles_T_396[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_199; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_398 = {1'h0, loginfo_cycles_199} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_399 = _loginfo_cycles_T_398[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_200; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_400 = {1'h0, loginfo_cycles_200} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_401 = _loginfo_cycles_T_400[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_201; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_402 = {1'h0, loginfo_cycles_201} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_403 = _loginfo_cycles_T_402[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_202; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_404 = {1'h0, loginfo_cycles_202} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_405 = _loginfo_cycles_T_404[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_203; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_406 = {1'h0, loginfo_cycles_203} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_407 = _loginfo_cycles_T_406[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_204; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_408 = {1'h0, loginfo_cycles_204} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_409 = _loginfo_cycles_T_408[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_205; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_410 = {1'h0, loginfo_cycles_205} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_411 = _loginfo_cycles_T_410[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_206; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_412 = {1'h0, loginfo_cycles_206} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_413 = _loginfo_cycles_T_412[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_207; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_414 = {1'h0, loginfo_cycles_207} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_415 = _loginfo_cycles_T_414[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_208; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_416 = {1'h0, loginfo_cycles_208} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_417 = _loginfo_cycles_T_416[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_209; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_418 = {1'h0, loginfo_cycles_209} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_419 = _loginfo_cycles_T_418[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_210; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_420 = {1'h0, loginfo_cycles_210} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_421 = _loginfo_cycles_T_420[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_211; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_422 = {1'h0, loginfo_cycles_211} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_423 = _loginfo_cycles_T_422[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_212; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_424 = {1'h0, loginfo_cycles_212} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_425 = _loginfo_cycles_T_424[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_213; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_426 = {1'h0, loginfo_cycles_213} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_427 = _loginfo_cycles_T_426[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_214; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_428 = {1'h0, loginfo_cycles_214} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_429 = _loginfo_cycles_T_428[63:0]; // @[Util.scala:19:38]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_217( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [15:0] c_sizes_set = 16'h0; // @[Monitor.scala:741:34] wire [7:0] c_opcodes_set = 8'h0; // @[Monitor.scala:740:34] wire [1:0] c_set = 2'h0; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready = 2'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _T_1357 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1357; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1357; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1430 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1430; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1430; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1430; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1357 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1283 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1283 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1283 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1283 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1283 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1329 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1329 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_1298 = _T_1430 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1298 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1298 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1298 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1401 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1401 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_1383 = _T_1430 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1383 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1383 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1383 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }

module NoCMonitor_3( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1)) }) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf || io.b.isInf val notNaN_isZeroOut = io.a.isZero || io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN || io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }

module MulRecFN_29( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_29 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_96 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_149( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_166 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncQueue( // @[AsyncQueue.scala:226:7] input io_enq_clock, // @[AsyncQueue.scala:227:14] input io_enq_reset, // @[AsyncQueue.scala:227:14] output io_enq_ready, // @[AsyncQueue.scala:227:14] input io_enq_valid, // @[AsyncQueue.scala:227:14] input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:227:14] input io_deq_clock, // @[AsyncQueue.scala:227:14] input io_deq_reset, // @[AsyncQueue.scala:227:14] input io_deq_ready, // @[AsyncQueue.scala:227:14] output io_deq_valid, // @[AsyncQueue.scala:227:14] output [31:0] io_deq_bits_phit // @[AsyncQueue.scala:227:14] ); wire [3:0] _sink_io_async_ridx; // @[AsyncQueue.scala:229:70] wire _sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala:229:70] wire _sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala:229:70] wire [31:0] _source_io_async_mem_0_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_1_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_2_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_3_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_4_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_5_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_6_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_7_phit; // @[AsyncQueue.scala:228:70] wire [3:0] _source_io_async_widx; // @[AsyncQueue.scala:228:70] wire _source_io_async_safe_widx_valid; // @[AsyncQueue.scala:228:70] wire _source_io_async_safe_source_reset_n; // @[AsyncQueue.scala:228:70] AsyncQueueSource_Phit source ( // @[AsyncQueue.scala:228:70] .clock (io_enq_clock), .reset (io_enq_reset), .io_enq_ready (io_enq_ready), .io_enq_valid (io_enq_valid), .io_enq_bits_phit (io_enq_bits_phit), .io_async_mem_0_phit (_source_io_async_mem_0_phit), .io_async_mem_1_phit (_source_io_async_mem_1_phit), .io_async_mem_2_phit (_source_io_async_mem_2_phit), .io_async_mem_3_phit (_source_io_async_mem_3_phit), .io_async_mem_4_phit (_source_io_async_mem_4_phit), .io_async_mem_5_phit (_source_io_async_mem_5_phit), .io_async_mem_6_phit (_source_io_async_mem_6_phit), .io_async_mem_7_phit (_source_io_async_mem_7_phit), .io_async_ridx (_sink_io_async_ridx), // @[AsyncQueue.scala:229:70] .io_async_widx (_source_io_async_widx), .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), // @[AsyncQueue.scala:229:70] .io_async_safe_widx_valid (_source_io_async_safe_widx_valid), .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) // @[AsyncQueue.scala:229:70] ); // @[AsyncQueue.scala:228:70] AsyncQueueSink_Phit sink ( // @[AsyncQueue.scala:229:70] .clock (io_deq_clock), .reset (io_deq_reset), .io_deq_ready (io_deq_ready), .io_deq_valid (io_deq_valid), .io_deq_bits_phit (io_deq_bits_phit), .io_async_mem_0_phit (_source_io_async_mem_0_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_1_phit (_source_io_async_mem_1_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_2_phit (_source_io_async_mem_2_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_3_phit (_source_io_async_mem_3_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_4_phit (_source_io_async_mem_4_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_5_phit (_source_io_async_mem_5_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_6_phit (_source_io_async_mem_6_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_7_phit (_source_io_async_mem_7_phit), // @[AsyncQueue.scala:228:70] .io_async_ridx (_sink_io_async_ridx), .io_async_widx (_source_io_async_widx), // @[AsyncQueue.scala:228:70] .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), .io_async_safe_widx_valid (_source_io_async_safe_widx_valid), // @[AsyncQueue.scala:228:70] .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), // @[AsyncQueue.scala:228:70] .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) ); // @[AsyncQueue.scala:229:70] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_34( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_38 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid || io.clear || io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 || rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_||_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_||_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_||_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready || agen_ready || dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }

module IssueSlot_93( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }

module TLXbar_MasterXbar_BoomTile_i2_o1_a32d64s3k3z4c( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire [2:0] out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [2:0] in_0_c_bits_source; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_ready_0 = auto_anon_in_0_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_valid_0 = auto_anon_in_0_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_opcode_0 = auto_anon_in_0_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_param_0 = auto_anon_in_0_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_c_bits_size_0 = auto_anon_in_0_c_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_c_bits_source_0 = auto_anon_in_0_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_c_bits_address_0 = auto_anon_in_0_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_c_bits_data_0 = auto_anon_in_0_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_valid_0 = auto_anon_in_0_e_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_e_bits_sink_0 = auto_anon_in_0_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_b_valid_0 = auto_anon_out_b_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_b_bits_opcode_0 = auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_b_bits_param_0 = auto_anon_out_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_b_bits_size_0 = auto_anon_out_b_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_b_bits_source_0 = auto_anon_out_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_b_bits_address_0 = auto_anon_out_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_b_bits_mask_0 = auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_b_bits_data_0 = auto_anon_out_b_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_b_bits_corrupt_0 = auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_c_ready_0 = auto_anon_out_c_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_e_ready_0 = auto_anon_out_e_ready; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = 3'h4; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_source = 3'h4; // @[Xbar.scala:159:18] wire [2:0] _in_1_a_bits_source_T = 3'h4; // @[Xbar.scala:166:55] wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h4; // @[Xbar.scala:352:24] wire [2:0] portsAOI_filtered_1_0_bits_source = 3'h4; // @[Xbar.scala:352:24] wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_b_bits_source = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_source = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_e_bits_sink = 3'h0; // @[Xbar.scala:159:18] wire [2:0] _requestEIO_uncommonBits_T_1 = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestEIO_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_source = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_1_0_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_anon_in_1_a_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] in_1_a_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24] wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_valid = 1'h0; // @[Xbar.scala:159:18] wire out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire beatsAI_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _out_0_a_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire [7:0] auto_anon_in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:74:9] wire [7:0] anonIn_1_a_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:159:18] wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24] wire [63:0] auto_anon_in_1_a_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_a_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] in_1_a_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] in_1_b_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] in_1_c_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] portsAOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _out_0_a_bits_T_4 = 64'h0; // @[Mux.scala:30:73] wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire in_1_b_ready = 1'h1; // @[Xbar.scala:159:18] wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _beatsAI_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [8:0] beatsAI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69] wire [31:0] in_1_b_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] in_1_c_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [3:0] in_1_b_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_1_c_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [8:0] beatsAI_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] _beatsAI_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _beatsAI_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [7:0] in_1_b_bits_mask = 8'h0; // @[Xbar.scala:159:18] wire [1:0] in_1_b_bits_param = 2'h0; // @[Xbar.scala:159:18] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_b_ready = auto_anon_in_0_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_c_ready; // @[MixedNode.scala:551:17] wire anonIn_c_valid = auto_anon_in_0_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_opcode = auto_anon_in_0_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_param = auto_anon_in_0_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_c_bits_size = auto_anon_in_0_c_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_c_bits_source = auto_anon_in_0_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_c_bits_address = auto_anon_in_0_c_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_c_bits_data = auto_anon_in_0_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_e_ready; // @[MixedNode.scala:551:17] wire anonIn_e_valid = auto_anon_in_0_e_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_e_bits_sink = auto_anon_in_0_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_b_ready; // @[MixedNode.scala:542:17] wire anonOut_b_valid = auto_anon_out_b_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_b_bits_opcode = auto_anon_out_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_b_bits_param = auto_anon_out_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_b_bits_size = auto_anon_out_b_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_b_bits_source = auto_anon_out_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonOut_b_bits_address = auto_anon_out_b_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonOut_b_bits_mask = auto_anon_out_b_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_b_bits_data = auto_anon_out_b_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_b_bits_corrupt = auto_anon_out_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_c_ready = auto_anon_out_c_ready_0; // @[Xbar.scala:74:9] wire anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_e_ready = auto_anon_out_e_ready_0; // @[Xbar.scala:74:9] wire anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_b_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_b_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_b_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_b_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_b_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_c_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_c_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_c_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_c_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_e_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_out_e_valid_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [1:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_b_ready = anonIn_b_ready; // @[Xbar.scala:159:18] wire in_0_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_valid_0 = anonIn_b_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_b_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_opcode_0 = anonIn_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_param_0 = anonIn_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_b_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_size_0 = anonIn_b_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_b_bits_source_0 = anonIn_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_0_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_address_0 = anonIn_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_0_b_bits_mask; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_mask_0 = anonIn_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_0_b_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_data_0 = anonIn_b_bits_data; // @[Xbar.scala:74:9] wire in_0_b_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_corrupt_0 = anonIn_b_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_c_ready_0 = anonIn_c_ready; // @[Xbar.scala:74:9] wire in_0_c_valid = anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_opcode = anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_param = anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_c_bits_size = anonIn_c_bits_size; // @[Xbar.scala:159:18] wire [1:0] _in_0_c_bits_source_T = anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] in_0_c_bits_address = anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [63:0] in_0_c_bits_data = anonIn_c_bits_data; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_e_ready_0 = anonIn_e_ready; // @[Xbar.scala:74:9] wire in_0_e_valid = anonIn_e_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_e_bits_sink = anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_b_ready; // @[Xbar.scala:216:19] assign auto_anon_out_b_ready_0 = anonOut_b_ready; // @[Xbar.scala:74:9] wire out_0_b_valid = anonOut_b_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_b_bits_opcode = anonOut_b_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_b_bits_param = anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_b_bits_size = anonOut_b_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_0_b_bits_source = anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] out_0_b_bits_address = anonOut_b_bits_address; // @[Xbar.scala:216:19] wire [7:0] out_0_b_bits_mask = anonOut_b_bits_mask; // @[Xbar.scala:216:19] wire [63:0] out_0_b_bits_data = anonOut_b_bits_data; // @[Xbar.scala:216:19] wire out_0_b_bits_corrupt = anonOut_b_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_c_ready = anonOut_c_ready; // @[Xbar.scala:216:19] wire out_0_c_valid; // @[Xbar.scala:216:19] assign auto_anon_out_c_valid_0 = anonOut_c_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_opcode_0 = anonOut_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_param_0 = anonOut_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_c_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_size_0 = anonOut_c_bits_size; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_source_0 = anonOut_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_c_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_address_0 = anonOut_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] out_0_c_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_data_0 = anonOut_c_bits_data; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_e_ready = anonOut_e_ready; // @[Xbar.scala:216:19] wire out_0_e_valid; // @[Xbar.scala:216:19] assign auto_anon_out_e_valid_0 = anonOut_e_valid; // @[Xbar.scala:74:9] wire [2:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign auto_anon_out_e_bits_sink_0 = anonOut_e_bits_sink; // @[Xbar.scala:74:9] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_ready = in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_b_valid = in_0_b_valid; // @[Xbar.scala:159:18] wire [2:0] portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_b_bits_opcode = in_0_b_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_b_bits_param = in_0_b_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_b_bits_size = in_0_b_bits_size; // @[Xbar.scala:159:18] wire [2:0] portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign anonIn_b_bits_address = in_0_b_bits_address; // @[Xbar.scala:159:18] wire [7:0] portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24] assign anonIn_b_bits_mask = in_0_b_bits_mask; // @[Xbar.scala:159:18] wire [63:0] portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_b_bits_data = in_0_b_bits_data; // @[Xbar.scala:159:18] wire portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_b_bits_corrupt = in_0_b_bits_corrupt; // @[Xbar.scala:159:18] wire portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_c_ready = in_0_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_1 = in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_0_bits_opcode = in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_0_bits_param = in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_0_bits_size = in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_0_bits_source = in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T = in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_0_bits_address = in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsCOI_filtered_0_bits_data = in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [2:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsEOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_e_ready = in_0_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_0_valid_T_1 = in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] _requestEIO_uncommonBits_T = in_0_e_bits_sink; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_0_bits_sink = in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire [2:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire [2:0] in_0_b_bits_source; // @[Xbar.scala:159:18] wire [2:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [2:0] in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_b_bits_source_T = in_0_b_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign in_0_c_bits_source = {1'h0, _in_0_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_b_ready = out_0_b_ready; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsBIO_filtered_1_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsBIO_filtered_1_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [2:0] _requestBOI_uncommonBits_T = out_0_b_bits_source; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsBIO_filtered_1_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsBIO_filtered_1_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] wire [7:0] portsBIO_filtered_1_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsBIO_filtered_1_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsBIO_filtered_1_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_ready = out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_c_valid = out_0_c_valid; // @[Xbar.scala:216:19] assign anonOut_c_bits_opcode = out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_c_bits_param = out_0_c_bits_param; // @[Xbar.scala:216:19] assign anonOut_c_bits_size = out_0_c_bits_size; // @[Xbar.scala:216:19] assign anonOut_c_bits_source = out_0_c_bits_source; // @[Xbar.scala:216:19] assign anonOut_c_bits_address = out_0_c_bits_address; // @[Xbar.scala:216:19] assign anonOut_c_bits_data = out_0_c_bits_data; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [2:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_ready = out_0_e_ready; // @[Xbar.scala:216:19, :352:24] wire portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_e_valid = out_0_e_valid; // @[Xbar.scala:216:19] assign _anonOut_e_bits_sink_T = out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_1 = {1'h0, _requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire [1:0] requestBOI_uncommonBits = _requestBOI_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T = out_0_b_bits_source[2]; // @[Xbar.scala:216:19] wire _requestBOI_T_1 = ~_requestBOI_T; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_3 = _requestBOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestBOI_0_0 = _requestBOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_0_valid_T = requestBOI_0_0; // @[Xbar.scala:355:54] wire requestBOI_0_1 = out_0_b_bits_source == 3'h4; // @[Xbar.scala:216:19] wire _portsBIO_filtered_1_valid_T = requestBOI_0_1; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[2]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = out_0_d_bits_source == 3'h4; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73] wire [2:0] requestEIO_uncommonBits = _requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsBO_decode_T = 27'hFFF << out_0_b_bits_size; // @[package.scala:243:71] wire [11:0] _beatsBO_decode_T_1 = _beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsBO_decode_T_2 = ~_beatsBO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsBO_decode = _beatsBO_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsBO_opdata_T = out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19] wire beatsBO_opdata = ~_beatsBO_opdata_T; // @[Edges.scala:97:{28,37}] wire [26:0] _beatsCI_decode_T = 27'hFFF << in_0_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_1 = _beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_2 = ~_beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsCI_decode = _beatsCI_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsCI_opdata = in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [8:0] beatsCI_0 = beatsCI_opdata ? beatsCI_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_b_valid = portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_opcode = portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_param = portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_size = portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_source = portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_address = portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_mask = portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_data = portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_corrupt = portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsBIO_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsBIO_filtered_0_valid_T_1 = out_0_b_valid & _portsBIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_0_valid = _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_1_valid_T_1 = out_0_b_valid & _portsBIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_valid = _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_out_0_b_ready_T = requestBOI_0_0 & portsBIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_2 = _portsBIO_out_0_b_ready_T; // @[Mux.scala:30:73] assign _portsBIO_out_0_b_ready_WIRE = _portsBIO_out_0_b_ready_T_2; // @[Mux.scala:30:73] assign out_0_b_ready = _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign in_0_c_ready = portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_c_valid = portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_opcode = portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_param = portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_size = portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_source = portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_address = portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_data = portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_valid = _portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign in_0_e_ready = portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_e_valid = portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_e_bits_sink = portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_valid = _portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_451( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_444( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }

module PriorityQueueStage_66( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops }

module BranchKillableQueue_7( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [39:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [7:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [39:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [7:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:463:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:463:14] input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:463:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:463:14] input io_brupdate_b2_uop_is_rvc, // @[util.scala:463:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_0, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_1, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_2, // @[util.scala:463:14] input io_brupdate_b2_uop_iq_type_3, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_0, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_1, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_2, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_3, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_4, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_5, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_6, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_7, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_8, // @[util.scala:463:14] input io_brupdate_b2_uop_fu_code_9, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_issued, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:463:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:463:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:463:14] input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:463:14] input io_brupdate_b2_uop_is_sfb, // @[util.scala:463:14] input io_brupdate_b2_uop_is_fence, // @[util.scala:463:14] input io_brupdate_b2_uop_is_fencei, // @[util.scala:463:14] input io_brupdate_b2_uop_is_sfence, // @[util.scala:463:14] input io_brupdate_b2_uop_is_amo, // @[util.scala:463:14] input io_brupdate_b2_uop_is_eret, // @[util.scala:463:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_brupdate_b2_uop_is_rocc, // @[util.scala:463:14] input io_brupdate_b2_uop_is_mov, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:463:14] input io_brupdate_b2_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:463:14] input io_brupdate_b2_uop_taken, // @[util.scala:463:14] input io_brupdate_b2_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:463:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:463:14] input io_brupdate_b2_uop_prs1_busy, // @[util.scala:463:14] input io_brupdate_b2_uop_prs2_busy, // @[util.scala:463:14] input io_brupdate_b2_uop_prs3_busy, // @[util.scala:463:14] input io_brupdate_b2_uop_ppred_busy, // @[util.scala:463:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:463:14] input io_brupdate_b2_uop_exception, // @[util.scala:463:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:463:14] input io_brupdate_b2_uop_mem_signed, // @[util.scala:463:14] input io_brupdate_b2_uop_uses_ldq, // @[util.scala:463:14] input io_brupdate_b2_uop_uses_stq, // @[util.scala:463:14] input io_brupdate_b2_uop_is_unique, // @[util.scala:463:14] input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:463:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:463:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:463:14] input io_brupdate_b2_uop_frs3_en, // @[util.scala:463:14] input io_brupdate_b2_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:463:14] input io_brupdate_b2_uop_fp_val, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:463:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:463:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:463:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:463:14] input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:463:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:463:14] input io_brupdate_b2_mispredict, // @[util.scala:463:14] input io_brupdate_b2_taken, // @[util.scala:463:14] input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:463:14] input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:463:14] input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:463:14] input [20:0] io_brupdate_b2_target_offset, // @[util.scala:463:14] input io_flush, // @[util.scala:463:14] output io_empty // @[util.scala:463:14] ); wire _main_io_deq_valid; // @[util.scala:476:22] wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22] wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22] wire [39:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22] wire [15:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22] wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22] wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22] wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22] wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22] wire [6:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22] wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22] wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22] wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22] wire [39:0] _main_io_deq_bits_addr; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22] wire _main_io_deq_bits_is_hella; // @[util.scala:476:22] wire _main_io_deq_bits_tag_match; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22] wire [19:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22] wire [7:0] _main_io_deq_bits_way_en; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22] wire _main_io_empty; // @[util.scala:476:22] wire [3:0] _main_io_count; // @[util.scala:476:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [7:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:458:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:458:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:458:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:458:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:458:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:458:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:458:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:458:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:458:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:458:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:458:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:458:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:458:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:458:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:458:7] wire io_flush_0 = io_flush; // @[util.scala:458:7] wire _io_empty_T_1; // @[util.scala:484:31] wire [3:0] _io_count_T_1; // @[util.scala:485:31] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [39:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [7:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count; // @[util.scala:458:7] reg [31:0] out_reg_uop_inst; // @[util.scala:477:22] reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22] reg out_reg_uop_is_rvc; // @[util.scala:477:22] reg [39:0] out_reg_uop_debug_pc; // @[util.scala:477:22] reg out_reg_uop_iq_type_0; // @[util.scala:477:22] reg out_reg_uop_iq_type_1; // @[util.scala:477:22] reg out_reg_uop_iq_type_2; // @[util.scala:477:22] reg out_reg_uop_iq_type_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_0; // @[util.scala:477:22] reg out_reg_uop_fu_code_1; // @[util.scala:477:22] reg out_reg_uop_fu_code_2; // @[util.scala:477:22] reg out_reg_uop_fu_code_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_4; // @[util.scala:477:22] reg out_reg_uop_fu_code_5; // @[util.scala:477:22] reg out_reg_uop_fu_code_6; // @[util.scala:477:22] reg out_reg_uop_fu_code_7; // @[util.scala:477:22] reg out_reg_uop_fu_code_8; // @[util.scala:477:22] reg out_reg_uop_fu_code_9; // @[util.scala:477:22] reg out_reg_uop_iw_issued; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22] reg [2:0] out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22] reg [2:0] out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22] reg [2:0] out_reg_uop_dis_col_sel; // @[util.scala:477:22] reg [15:0] out_reg_uop_br_mask; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_tag; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22] reg out_reg_uop_is_sfb; // @[util.scala:477:22] reg out_reg_uop_is_fence; // @[util.scala:477:22] reg out_reg_uop_is_fencei; // @[util.scala:477:22] reg out_reg_uop_is_sfence; // @[util.scala:477:22] reg out_reg_uop_is_amo; // @[util.scala:477:22] reg out_reg_uop_is_eret; // @[util.scala:477:22] reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22] reg out_reg_uop_is_rocc; // @[util.scala:477:22] reg out_reg_uop_is_mov; // @[util.scala:477:22] reg [4:0] out_reg_uop_ftq_idx; // @[util.scala:477:22] reg out_reg_uop_edge_inst; // @[util.scala:477:22] reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22] reg out_reg_uop_taken; // @[util.scala:477:22] reg out_reg_uop_imm_rename; // @[util.scala:477:22] reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22] reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22] reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22] reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22] reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22] reg [6:0] out_reg_uop_rob_idx; // @[util.scala:477:22] reg [4:0] out_reg_uop_ldq_idx; // @[util.scala:477:22] reg [4:0] out_reg_uop_stq_idx; // @[util.scala:477:22] reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22] reg [6:0] out_reg_uop_pdst; // @[util.scala:477:22] reg [6:0] out_reg_uop_prs1; // @[util.scala:477:22] reg [6:0] out_reg_uop_prs2; // @[util.scala:477:22] reg [6:0] out_reg_uop_prs3; // @[util.scala:477:22] reg [4:0] out_reg_uop_ppred; // @[util.scala:477:22] reg out_reg_uop_prs1_busy; // @[util.scala:477:22] reg out_reg_uop_prs2_busy; // @[util.scala:477:22] reg out_reg_uop_prs3_busy; // @[util.scala:477:22] reg out_reg_uop_ppred_busy; // @[util.scala:477:22] reg [6:0] out_reg_uop_stale_pdst; // @[util.scala:477:22] reg out_reg_uop_exception; // @[util.scala:477:22] reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22] reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22] reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22] reg out_reg_uop_mem_signed; // @[util.scala:477:22] reg out_reg_uop_uses_ldq; // @[util.scala:477:22] reg out_reg_uop_uses_stq; // @[util.scala:477:22] reg out_reg_uop_is_unique; // @[util.scala:477:22] reg out_reg_uop_flush_on_commit; // @[util.scala:477:22] reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22] reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22] reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22] reg out_reg_uop_frs3_en; // @[util.scala:477:22] reg out_reg_uop_fcn_dw; // @[util.scala:477:22] reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22] reg out_reg_uop_fp_val; // @[util.scala:477:22] reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22] reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22] reg out_reg_uop_bp_debug_if; // @[util.scala:477:22] reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22] reg [39:0] out_reg_addr; // @[util.scala:477:22] assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22] reg [63:0] out_reg_data; // @[util.scala:477:22] assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22] reg out_reg_is_hella; // @[util.scala:477:22] assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22] reg out_reg_tag_match; // @[util.scala:477:22] assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22] assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22] reg [19:0] out_reg_old_meta_tag; // @[util.scala:477:22] assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22] reg [7:0] out_reg_way_en; // @[util.scala:477:22] assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22] reg [4:0] out_reg_sdq_id; // @[util.scala:477:22] assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22] reg out_valid; // @[util.scala:478:28] assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28] reg [31:0] out_uop_inst; // @[util.scala:479:22] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22] reg [31:0] out_uop_debug_inst; // @[util.scala:479:22] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22] reg out_uop_is_rvc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22] reg [39:0] out_uop_debug_pc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22] wire [39:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_0; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_1; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_2; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_3; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_0; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_1; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_2; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_3; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_4; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_5; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_6; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_7; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_8; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_9; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_iw_p1_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_iw_p2_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_dis_col_sel; // @[util.scala:479:22] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22] reg [15:0] out_uop_br_mask; // @[util.scala:479:22] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22] reg [3:0] out_uop_br_tag; // @[util.scala:479:22] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_type; // @[util.scala:479:22] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22] reg out_uop_is_sfb; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22] reg out_uop_is_fence; // @[util.scala:479:22] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22] reg out_uop_is_fencei; // @[util.scala:479:22] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22] reg out_uop_is_sfence; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22] reg out_uop_is_amo; // @[util.scala:479:22] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22] wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22] reg out_uop_is_eret; // @[util.scala:479:22] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22] wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22] reg out_uop_is_sys_pc2epc; // @[util.scala:479:22] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22] reg out_uop_is_rocc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22] reg out_uop_is_mov; // @[util.scala:479:22] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22] wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_ftq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22] reg out_uop_edge_inst; // @[util.scala:479:22] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22] wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pc_lob; // @[util.scala:479:22] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22] reg out_uop_taken; // @[util.scala:479:22] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22] wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22] reg out_uop_imm_rename; // @[util.scala:479:22] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22] wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_imm_sel; // @[util.scala:479:22] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_pimm; // @[util.scala:479:22] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22] reg [19:0] out_uop_imm_packed; // @[util.scala:479:22] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22] wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_op1_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_op2_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wen; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_toint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fma; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_div; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_vec; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_rob_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_ldq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_stq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_prs1; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_prs2; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_prs3; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_ppred; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22] reg out_uop_prs1_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs2_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs3_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22] reg out_uop_ppred_busy; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22] reg [6:0] out_uop_stale_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22] wire [6:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22] reg out_uop_exception; // @[util.scala:479:22] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22] wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22] reg [63:0] out_uop_exc_cause; // @[util.scala:479:22] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22] wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_mem_size; // @[util.scala:479:22] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22] reg out_uop_mem_signed; // @[util.scala:479:22] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22] wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22] reg out_uop_uses_ldq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22] reg out_uop_uses_stq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22] reg out_uop_is_unique; // @[util.scala:479:22] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22] wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22] reg out_uop_flush_on_commit; // @[util.scala:479:22] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22] wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22] reg out_uop_ldst_is_rs1; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22] wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs1; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs2; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs3; // @[util.scala:479:22] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22] reg out_uop_frs3_en; // @[util.scala:479:22] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22] wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22] reg out_uop_fcn_dw; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22] wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_fcn_op; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22] reg out_uop_fp_val; // @[util.scala:479:22] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_fp_rm; // @[util.scala:479:22] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_typ; // @[util.scala:479:22] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_pf_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ae_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ma_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_debug_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_xcpt_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22] wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34] assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31] wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:476:22, :478:28, :485:31] assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31] assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31] wire [15:0] _out_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [15:0] out_uop_out_br_mask; // @[util.scala:104:23] wire [15:0] _out_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :458:7] assign _out_uop_out_br_mask_T_1 = out_uop_br_mask & _out_uop_out_br_mask_T; // @[util.scala:93:{25,27}, :479:22] assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire [15:0] _out_valid_T = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:126:51, :458:7, :479:22] wire _out_valid_T_1 = |_out_valid_T; // @[util.scala:126:{51,59}] wire _out_valid_T_2 = _out_valid_T_1; // @[util.scala:61:61, :126:59] wire _out_valid_T_3 = ~_out_valid_T_2; // @[util.scala:61:61, :492:31] wire _out_valid_T_4 = out_valid & _out_valid_T_3; // @[util.scala:478:28, :492:{28,31}] wire _out_valid_T_5 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:458:7, :479:22, :492:94] wire _out_valid_T_6 = ~_out_valid_T_5; // @[util.scala:492:{83,94}] wire _out_valid_T_7 = _out_valid_T_4 & _out_valid_T_6; // @[util.scala:492:{28,80,83}] wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 | ~out_valid; // @[Decoupled.scala:51:35] wire [15:0] _out_valid_T_8 = io_brupdate_b1_mispredict_mask_0 & _main_io_deq_bits_uop_br_mask; // @[util.scala:126:51, :458:7, :476:22] wire _out_valid_T_9 = |_out_valid_T_8; // @[util.scala:126:{51,59}] wire _out_valid_T_10 = _out_valid_T_9; // @[util.scala:61:61, :126:59] wire _out_valid_T_11 = ~_out_valid_T_10; // @[util.scala:61:61, :496:41] wire _out_valid_T_12 = _main_io_deq_valid & _out_valid_T_11; // @[util.scala:476:22, :496:{38,41}] wire _out_valid_T_13 = io_flush_0 & _main_io_deq_bits_uop_uses_ldq; // @[util.scala:458:7, :476:22, :496:117] wire _out_valid_T_14 = ~_out_valid_T_13; // @[util.scala:496:{106,117}] wire _out_valid_T_15 = _out_valid_T_12 & _out_valid_T_14; // @[util.scala:496:{38,103,106}] wire [15:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25] wire out_uop_out_1_iq_type_0; // @[util.scala:104:23] wire out_uop_out_1_iq_type_1; // @[util.scala:104:23] wire out_uop_out_1_iq_type_2; // @[util.scala:104:23] wire out_uop_out_1_iq_type_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_0; // @[util.scala:104:23] wire out_uop_out_1_fu_code_1; // @[util.scala:104:23] wire out_uop_out_1_fu_code_2; // @[util.scala:104:23] wire out_uop_out_1_fu_code_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_4; // @[util.scala:104:23] wire out_uop_out_1_fu_code_5; // @[util.scala:104:23] wire out_uop_out_1_fu_code_6; // @[util.scala:104:23] wire out_uop_out_1_fu_code_7; // @[util.scala:104:23] wire out_uop_out_1_fu_code_8; // @[util.scala:104:23] wire out_uop_out_1_fu_code_9; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23] wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23] wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23] wire out_uop_out_1_is_rvc; // @[util.scala:104:23] wire [39:0] out_uop_out_1_debug_pc; // @[util.scala:104:23] wire out_uop_out_1_iw_issued; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23] wire [2:0] out_uop_out_1_dis_col_sel; // @[util.scala:104:23] wire [15:0] out_uop_out_1_br_mask; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_tag; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23] wire out_uop_out_1_is_sfb; // @[util.scala:104:23] wire out_uop_out_1_is_fence; // @[util.scala:104:23] wire out_uop_out_1_is_fencei; // @[util.scala:104:23] wire out_uop_out_1_is_sfence; // @[util.scala:104:23] wire out_uop_out_1_is_amo; // @[util.scala:104:23] wire out_uop_out_1_is_eret; // @[util.scala:104:23] wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23] wire out_uop_out_1_is_rocc; // @[util.scala:104:23] wire out_uop_out_1_is_mov; // @[util.scala:104:23] wire [4:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23] wire out_uop_out_1_edge_inst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23] wire out_uop_out_1_taken; // @[util.scala:104:23] wire out_uop_out_1_imm_rename; // @[util.scala:104:23] wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23] wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23] wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23] wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23] wire [6:0] out_uop_out_1_rob_idx; // @[util.scala:104:23] wire [4:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23] wire [4:0] out_uop_out_1_stq_idx; // @[util.scala:104:23] wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23] wire [6:0] out_uop_out_1_pdst; // @[util.scala:104:23] wire [6:0] out_uop_out_1_prs1; // @[util.scala:104:23] wire [6:0] out_uop_out_1_prs2; // @[util.scala:104:23] wire [6:0] out_uop_out_1_prs3; // @[util.scala:104:23] wire [4:0] out_uop_out_1_ppred; // @[util.scala:104:23] wire out_uop_out_1_prs1_busy; // @[util.scala:104:23] wire out_uop_out_1_prs2_busy; // @[util.scala:104:23] wire out_uop_out_1_prs3_busy; // @[util.scala:104:23] wire out_uop_out_1_ppred_busy; // @[util.scala:104:23] wire [6:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23] wire out_uop_out_1_exception; // @[util.scala:104:23] wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23] wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23] wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23] wire out_uop_out_1_mem_signed; // @[util.scala:104:23] wire out_uop_out_1_uses_ldq; // @[util.scala:104:23] wire out_uop_out_1_uses_stq; // @[util.scala:104:23] wire out_uop_out_1_is_unique; // @[util.scala:104:23] wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23] wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23] wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23] wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23] wire out_uop_out_1_frs3_en; // @[util.scala:104:23] wire out_uop_out_1_fcn_dw; // @[util.scala:104:23] wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23] wire out_uop_out_1_fp_val; // @[util.scala:104:23] wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23] wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23] wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23] wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23] wire [15:0] _out_uop_out_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :458:7] assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask & _out_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}, :476:22] assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] always @(posedge clock) begin // @[util.scala:458:7] if (main_io_deq_ready) begin // @[util.scala:495:23] out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22] out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22] out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22] out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22] out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22] out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22] out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22] out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22] out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22] out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22] out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22] out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22] out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22] out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22] out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22] out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22] out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22] out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22] out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22] out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22] out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22] out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22] out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22] out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22] out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22] out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22] out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22] out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22] out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22] out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22] out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22] out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22] out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22] out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22] out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22] out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22] out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22] out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22] out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22] out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22] out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22] out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22] out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22] out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22] out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22] out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22] out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22] out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22] out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22] out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22] out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22] out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22] out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22] end out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] if (reset) // @[util.scala:458:7] out_valid <= 1'h0; // @[util.scala:478:28] else // @[util.scala:458:7] out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}] always @(posedge) BranchKillableQueue_6 main ( // @[util.scala:476:22] .clock (clock), .reset (reset), .io_enq_ready (io_enq_ready_0), .io_enq_valid (io_enq_valid_0), // @[util.scala:458:7] .io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7] .io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7] .io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7] .io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7] .io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7] .io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7] .io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7] .io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7] .io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7] .io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7] .io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7] .io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7] .io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7] .io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7] .io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7] .io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7] .io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7] .io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7] .io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7] .io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7] .io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7] .io_deq_ready (main_io_deq_ready), // @[util.scala:495:23] .io_deq_valid (_main_io_deq_valid), .io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst), .io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst), .io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc), .io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc), .io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0), .io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1), .io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2), .io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3), .io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0), .io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1), .io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2), .io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3), .io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4), .io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5), .io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6), .io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7), .io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8), .io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9), .io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued), .io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen), .io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen), .io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child), .io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child), .io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint), .io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint), .io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint), .io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel), .io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask), .io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag), .io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type), .io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb), .io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence), .io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei), .io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence), .io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo), .io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret), .io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc), .io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc), .io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov), .io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx), .io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst), .io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob), .io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken), .io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename), .io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel), .io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm), .io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed), .io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel), .io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel), .io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst), .io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen), .io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1), .io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2), .io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3), .io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12), .io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23), .io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn), .io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut), .io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint), .io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint), .io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe), .io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma), .io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div), .io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt), .io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags), .io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec), .io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx), .io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx), .io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx), .io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx), .io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst), .io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1), .io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2), .io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3), .io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred), .io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy), .io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy), .io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy), .io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy), .io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst), .io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception), .io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause), .io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd), .io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size), .io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed), .io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq), .io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq), .io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique), .io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit), .io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd), .io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1), .io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst), .io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1), .io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2), .io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3), .io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype), .io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype), .io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype), .io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en), .io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw), .io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op), .io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val), .io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm), .io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ), .io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if), .io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if), .io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if), .io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if), .io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if), .io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc), .io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc), .io_deq_bits_addr (_main_io_deq_bits_addr), .io_deq_bits_data (_main_io_deq_bits_data), .io_deq_bits_is_hella (_main_io_deq_bits_is_hella), .io_deq_bits_tag_match (_main_io_deq_bits_tag_match), .io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state), .io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag), .io_deq_bits_way_en (_main_io_deq_bits_way_en), .io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id), .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask_0), // @[util.scala:458:7] .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask_0), // @[util.scala:458:7] .io_brupdate_b2_uop_inst (io_brupdate_b2_uop_inst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_debug_inst (io_brupdate_b2_uop_debug_inst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_rvc (io_brupdate_b2_uop_is_rvc_0), // @[util.scala:458:7] .io_brupdate_b2_uop_debug_pc (io_brupdate_b2_uop_debug_pc_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iq_type_0 (io_brupdate_b2_uop_iq_type_0_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iq_type_1 (io_brupdate_b2_uop_iq_type_1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iq_type_2 (io_brupdate_b2_uop_iq_type_2_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iq_type_3 (io_brupdate_b2_uop_iq_type_3_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_0 (io_brupdate_b2_uop_fu_code_0_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_1 (io_brupdate_b2_uop_fu_code_1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_2 (io_brupdate_b2_uop_fu_code_2_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_3 (io_brupdate_b2_uop_fu_code_3_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_4 (io_brupdate_b2_uop_fu_code_4_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_5 (io_brupdate_b2_uop_fu_code_5_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_6 (io_brupdate_b2_uop_fu_code_6_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_7 (io_brupdate_b2_uop_fu_code_7_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_8 (io_brupdate_b2_uop_fu_code_8_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fu_code_9 (io_brupdate_b2_uop_fu_code_9_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_issued (io_brupdate_b2_uop_iw_issued_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_issued_partial_agen (io_brupdate_b2_uop_iw_issued_partial_agen_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_issued_partial_dgen (io_brupdate_b2_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_p1_speculative_child (io_brupdate_b2_uop_iw_p1_speculative_child_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_p2_speculative_child (io_brupdate_b2_uop_iw_p2_speculative_child_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_p1_bypass_hint (io_brupdate_b2_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_p2_bypass_hint (io_brupdate_b2_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7] .io_brupdate_b2_uop_iw_p3_bypass_hint (io_brupdate_b2_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7] .io_brupdate_b2_uop_dis_col_sel (io_brupdate_b2_uop_dis_col_sel_0), // @[util.scala:458:7] .io_brupdate_b2_uop_br_mask (io_brupdate_b2_uop_br_mask_0), // @[util.scala:458:7] .io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag_0), // @[util.scala:458:7] .io_brupdate_b2_uop_br_type (io_brupdate_b2_uop_br_type_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_sfb (io_brupdate_b2_uop_is_sfb_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_fence (io_brupdate_b2_uop_is_fence_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_fencei (io_brupdate_b2_uop_is_fencei_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_sfence (io_brupdate_b2_uop_is_sfence_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_amo (io_brupdate_b2_uop_is_amo_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_eret (io_brupdate_b2_uop_is_eret_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_sys_pc2epc (io_brupdate_b2_uop_is_sys_pc2epc_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_rocc (io_brupdate_b2_uop_is_rocc_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_mov (io_brupdate_b2_uop_is_mov_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ftq_idx (io_brupdate_b2_uop_ftq_idx_0), // @[util.scala:458:7] .io_brupdate_b2_uop_edge_inst (io_brupdate_b2_uop_edge_inst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_pc_lob (io_brupdate_b2_uop_pc_lob_0), // @[util.scala:458:7] .io_brupdate_b2_uop_taken (io_brupdate_b2_uop_taken_0), // @[util.scala:458:7] .io_brupdate_b2_uop_imm_rename (io_brupdate_b2_uop_imm_rename_0), // @[util.scala:458:7] .io_brupdate_b2_uop_imm_sel (io_brupdate_b2_uop_imm_sel_0), // @[util.scala:458:7] .io_brupdate_b2_uop_pimm (io_brupdate_b2_uop_pimm_0), // @[util.scala:458:7] .io_brupdate_b2_uop_imm_packed (io_brupdate_b2_uop_imm_packed_0), // @[util.scala:458:7] .io_brupdate_b2_uop_op1_sel (io_brupdate_b2_uop_op1_sel_0), // @[util.scala:458:7] .io_brupdate_b2_uop_op2_sel (io_brupdate_b2_uop_op2_sel_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_ldst (io_brupdate_b2_uop_fp_ctrl_ldst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_wen (io_brupdate_b2_uop_fp_ctrl_wen_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_ren1 (io_brupdate_b2_uop_fp_ctrl_ren1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_ren2 (io_brupdate_b2_uop_fp_ctrl_ren2_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_ren3 (io_brupdate_b2_uop_fp_ctrl_ren3_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_swap12 (io_brupdate_b2_uop_fp_ctrl_swap12_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_swap23 (io_brupdate_b2_uop_fp_ctrl_swap23_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_typeTagIn (io_brupdate_b2_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_typeTagOut (io_brupdate_b2_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_fromint (io_brupdate_b2_uop_fp_ctrl_fromint_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_toint (io_brupdate_b2_uop_fp_ctrl_toint_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_fastpipe (io_brupdate_b2_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_fma (io_brupdate_b2_uop_fp_ctrl_fma_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_div (io_brupdate_b2_uop_fp_ctrl_div_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_sqrt (io_brupdate_b2_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_wflags (io_brupdate_b2_uop_fp_ctrl_wflags_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_ctrl_vec (io_brupdate_b2_uop_fp_ctrl_vec_0), // @[util.scala:458:7] .io_brupdate_b2_uop_rob_idx (io_brupdate_b2_uop_rob_idx_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ldq_idx (io_brupdate_b2_uop_ldq_idx_0), // @[util.scala:458:7] .io_brupdate_b2_uop_stq_idx (io_brupdate_b2_uop_stq_idx_0), // @[util.scala:458:7] .io_brupdate_b2_uop_rxq_idx (io_brupdate_b2_uop_rxq_idx_0), // @[util.scala:458:7] .io_brupdate_b2_uop_pdst (io_brupdate_b2_uop_pdst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs1 (io_brupdate_b2_uop_prs1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs2 (io_brupdate_b2_uop_prs2_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs3 (io_brupdate_b2_uop_prs3_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ppred (io_brupdate_b2_uop_ppred_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs1_busy (io_brupdate_b2_uop_prs1_busy_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs2_busy (io_brupdate_b2_uop_prs2_busy_0), // @[util.scala:458:7] .io_brupdate_b2_uop_prs3_busy (io_brupdate_b2_uop_prs3_busy_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ppred_busy (io_brupdate_b2_uop_ppred_busy_0), // @[util.scala:458:7] .io_brupdate_b2_uop_stale_pdst (io_brupdate_b2_uop_stale_pdst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_exception (io_brupdate_b2_uop_exception_0), // @[util.scala:458:7] .io_brupdate_b2_uop_exc_cause (io_brupdate_b2_uop_exc_cause_0), // @[util.scala:458:7] .io_brupdate_b2_uop_mem_cmd (io_brupdate_b2_uop_mem_cmd_0), // @[util.scala:458:7] .io_brupdate_b2_uop_mem_size (io_brupdate_b2_uop_mem_size_0), // @[util.scala:458:7] .io_brupdate_b2_uop_mem_signed (io_brupdate_b2_uop_mem_signed_0), // @[util.scala:458:7] .io_brupdate_b2_uop_uses_ldq (io_brupdate_b2_uop_uses_ldq_0), // @[util.scala:458:7] .io_brupdate_b2_uop_uses_stq (io_brupdate_b2_uop_uses_stq_0), // @[util.scala:458:7] .io_brupdate_b2_uop_is_unique (io_brupdate_b2_uop_is_unique_0), // @[util.scala:458:7] .io_brupdate_b2_uop_flush_on_commit (io_brupdate_b2_uop_flush_on_commit_0), // @[util.scala:458:7] .io_brupdate_b2_uop_csr_cmd (io_brupdate_b2_uop_csr_cmd_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ldst_is_rs1 (io_brupdate_b2_uop_ldst_is_rs1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_ldst (io_brupdate_b2_uop_ldst_0), // @[util.scala:458:7] .io_brupdate_b2_uop_lrs1 (io_brupdate_b2_uop_lrs1_0), // @[util.scala:458:7] .io_brupdate_b2_uop_lrs2 (io_brupdate_b2_uop_lrs2_0), // @[util.scala:458:7] .io_brupdate_b2_uop_lrs3 (io_brupdate_b2_uop_lrs3_0), // @[util.scala:458:7] .io_brupdate_b2_uop_dst_rtype (io_brupdate_b2_uop_dst_rtype_0), // @[util.scala:458:7] .io_brupdate_b2_uop_lrs1_rtype (io_brupdate_b2_uop_lrs1_rtype_0), // @[util.scala:458:7] .io_brupdate_b2_uop_lrs2_rtype (io_brupdate_b2_uop_lrs2_rtype_0), // @[util.scala:458:7] .io_brupdate_b2_uop_frs3_en (io_brupdate_b2_uop_frs3_en_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fcn_dw (io_brupdate_b2_uop_fcn_dw_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fcn_op (io_brupdate_b2_uop_fcn_op_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_val (io_brupdate_b2_uop_fp_val_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_rm (io_brupdate_b2_uop_fp_rm_0), // @[util.scala:458:7] .io_brupdate_b2_uop_fp_typ (io_brupdate_b2_uop_fp_typ_0), // @[util.scala:458:7] .io_brupdate_b2_uop_xcpt_pf_if (io_brupdate_b2_uop_xcpt_pf_if_0), // @[util.scala:458:7] .io_brupdate_b2_uop_xcpt_ae_if (io_brupdate_b2_uop_xcpt_ae_if_0), // @[util.scala:458:7] .io_brupdate_b2_uop_xcpt_ma_if (io_brupdate_b2_uop_xcpt_ma_if_0), // @[util.scala:458:7] .io_brupdate_b2_uop_bp_debug_if (io_brupdate_b2_uop_bp_debug_if_0), // @[util.scala:458:7] .io_brupdate_b2_uop_bp_xcpt_if (io_brupdate_b2_uop_bp_xcpt_if_0), // @[util.scala:458:7] .io_brupdate_b2_uop_debug_fsrc (io_brupdate_b2_uop_debug_fsrc_0), // @[util.scala:458:7] .io_brupdate_b2_uop_debug_tsrc (io_brupdate_b2_uop_debug_tsrc_0), // @[util.scala:458:7] .io_brupdate_b2_mispredict (io_brupdate_b2_mispredict_0), // @[util.scala:458:7] .io_brupdate_b2_taken (io_brupdate_b2_taken_0), // @[util.scala:458:7] .io_brupdate_b2_cfi_type (io_brupdate_b2_cfi_type_0), // @[util.scala:458:7] .io_brupdate_b2_pc_sel (io_brupdate_b2_pc_sel_0), // @[util.scala:458:7] .io_brupdate_b2_jalr_target (io_brupdate_b2_jalr_target_0), // @[util.scala:458:7] .io_brupdate_b2_target_offset (io_brupdate_b2_target_offset_0), // @[util.scala:458:7] .io_flush (io_flush_0), // @[util.scala:458:7] .io_empty (_main_io_empty), .io_count (_main_io_count) ); // @[util.scala:476:22] assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22] assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22] assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22] assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_144( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_248 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }

module NoCMonitor_52( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26]

Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File rawFloatFromIN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }

module INToRecFN_i64_e5_s11( // @[INToRecFN.scala:43:7] input io_signedIn, // @[INToRecFN.scala:46:16] input [63:0] io_in, // @[INToRecFN.scala:46:16] input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16] output [16:0] io_out, // @[INToRecFN.scala:46:16] output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16] ); wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7] wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7] wire [16:0] io_out_0; // @[INToRecFN.scala:43:7] wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7] wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34] wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}] wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23] wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31] wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31] wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44] wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}] wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53] wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70] wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}] wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23] wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72] wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23] wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23] wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28] assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}] assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23] wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}] wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}] assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}] assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72] assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20] RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23] .io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23] .io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23] .io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23] .io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[INToRecFN.scala:60:15] assign io_out = io_out_0; // @[INToRecFN.scala:43:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_20 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_21 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_22 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_27 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_28 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire _source_ok_T_49 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_29 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_72 = _source_ok_T_71 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_77 | _source_ok_WIRE_29; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_79 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire _source_ok_T_103 = io_in_d_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_103; // @[Parameters.scala:1138:31] wire _source_ok_T_104 = io_in_d_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire _source_ok_T_105 = io_in_d_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_105; // @[Parameters.scala:1138:31] wire _source_ok_T_106 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_106; // @[Parameters.scala:1138:31] wire _source_ok_T_107 = io_in_d_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_107; // @[Parameters.scala:1138:31] wire _source_ok_T_108 = io_in_d_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_112; // @[Parameters.scala:1138:31] wire _source_ok_T_113 = io_in_d_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_113; // @[Parameters.scala:1138:31] wire _source_ok_T_114 = io_in_d_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire _source_ok_T_115 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_115; // @[Parameters.scala:1138:31] wire _source_ok_T_116 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire _source_ok_T_118 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_20 = _source_ok_T_118; // @[Parameters.scala:1138:31] wire _source_ok_T_119 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_21 = _source_ok_T_119; // @[Parameters.scala:1138:31] wire _source_ok_T_120 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_22 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire _source_ok_T_121 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_121; // @[Parameters.scala:1138:31] wire _source_ok_T_122 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_122; // @[Parameters.scala:1138:31] wire _source_ok_T_123 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_123; // @[Parameters.scala:1138:31] wire _source_ok_T_124 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_124; // @[Parameters.scala:1138:31] wire _source_ok_T_125 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_27 = _source_ok_T_125; // @[Parameters.scala:1138:31] wire _source_ok_T_126 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_28 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire _source_ok_T_127 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_29 = _source_ok_T_127; // @[Parameters.scala:1138:31] wire _source_ok_T_128 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_129 = _source_ok_T_128 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_130 = _source_ok_T_129 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_131 = _source_ok_T_130 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_132 = _source_ok_T_131 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_133 = _source_ok_T_132 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_134 = _source_ok_T_133 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_135 = _source_ok_T_134 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_1_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_1_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_155 | _source_ok_WIRE_1_29; // @[Parameters.scala:1138:31, :1139:46] wire _T_1766 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1766; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1766; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_1839 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1839; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1839; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1839; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1692 = _T_1766 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1692 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1692 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1692 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1692 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1692 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1738 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1738 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1707 = _T_1839 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1707 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1707 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1707 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1810 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1810 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1792 = _T_1839 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1792 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1792 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1792 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle

module MSHR_35( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire excluded_client = 1'h0; // @[MSHR.scala:279:28] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53] wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module MacUnit_52( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn || noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }

module test_router_32ClockSinkDomain( // @[ClockDomain.scala:14:9] output [4:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_27 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid), .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head), .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail), .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload), .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id), .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return), .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid), .auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head), .auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail), .auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload), .auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return), .auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundRawFNToRecFN_e8_s24_13( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_13 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_421( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops }

module BranchKillableQueue_32( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty, // @[util.scala:463:14] output [3:0] io_count // @[util.scala:463:14] ); wire [130:0] _ram_ext_R0_data; // @[util.scala:503:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _do_enq_T_4 = 1'h1; // @[util.scala:514:42] wire _do_enq_T_7 = 1'h1; // @[util.scala:514:102] wire _valids_0_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_0_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_1_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_1_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_2_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_2_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_3_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_3_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_4_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_4_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_5_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_5_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_6_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_6_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_7_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_7_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_8_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_8_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_9_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_9_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_10_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_10_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_11_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_11_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_12_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_12_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_13_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_13_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_14_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_14_T_6 = 1'h1; // @[util.scala:520:83] wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_8 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_9 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_10 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_11 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_12 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_13 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_14 = 1'h0; // @[util.scala:504:34] wire _do_enq_T_2 = 1'h0; // @[util.scala:126:59] wire _do_enq_T_3 = 1'h0; // @[util.scala:61:61] wire _do_enq_T_6 = 1'h0; // @[util.scala:514:113] wire _valids_0_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_0_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_0_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_1_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_1_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_1_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_2_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_2_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_2_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_3_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_3_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_3_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_4_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_4_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_4_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_5_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_5_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_5_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_6_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_6_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_6_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_7_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_7_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_7_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_8_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_8_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_8_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_9_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_9_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_9_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_10_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_10_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_10_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_11_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_11_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_11_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_12_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_12_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_12_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_13_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_13_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_13_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_14_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_14_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_14_T_5 = 1'h0; // @[util.scala:520:94] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:458:7] wire [3:0] _do_enq_T_1 = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_0_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_1_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_2_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_3_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_4_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_5_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_6_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_7_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_8_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_9_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_10_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_11_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_12_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_13_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_14_T = 4'h0; // @[util.scala:126:51] wire _io_enq_ready_T; // @[util.scala:543:21] wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:93:25, :458:7] wire _io_deq_valid_T_1; // @[util.scala:548:42] wire [31:0] out_uop_inst; // @[util.scala:545:19] wire [31:0] out_uop_debug_inst; // @[util.scala:545:19] wire out_uop_is_rvc; // @[util.scala:545:19] wire [33:0] out_uop_debug_pc; // @[util.scala:545:19] wire out_uop_iq_type_0; // @[util.scala:545:19] wire out_uop_iq_type_1; // @[util.scala:545:19] wire out_uop_iq_type_2; // @[util.scala:545:19] wire out_uop_iq_type_3; // @[util.scala:545:19] wire out_uop_fu_code_0; // @[util.scala:545:19] wire out_uop_fu_code_1; // @[util.scala:545:19] wire out_uop_fu_code_2; // @[util.scala:545:19] wire out_uop_fu_code_3; // @[util.scala:545:19] wire out_uop_fu_code_4; // @[util.scala:545:19] wire out_uop_fu_code_5; // @[util.scala:545:19] wire out_uop_fu_code_6; // @[util.scala:545:19] wire out_uop_fu_code_7; // @[util.scala:545:19] wire out_uop_fu_code_8; // @[util.scala:545:19] wire out_uop_fu_code_9; // @[util.scala:545:19] wire out_uop_iw_issued; // @[util.scala:545:19] wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19] wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19] wire out_uop_iw_p1_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p2_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19] wire out_uop_dis_col_sel; // @[util.scala:545:19] wire [3:0] out_uop_br_mask; // @[util.scala:545:19] wire [1:0] out_uop_br_tag; // @[util.scala:545:19] wire [3:0] out_uop_br_type; // @[util.scala:545:19] wire out_uop_is_sfb; // @[util.scala:545:19] wire out_uop_is_fence; // @[util.scala:545:19] wire out_uop_is_fencei; // @[util.scala:545:19] wire out_uop_is_sfence; // @[util.scala:545:19] wire out_uop_is_amo; // @[util.scala:545:19] wire out_uop_is_eret; // @[util.scala:545:19] wire out_uop_is_sys_pc2epc; // @[util.scala:545:19] wire out_uop_is_rocc; // @[util.scala:545:19] wire out_uop_is_mov; // @[util.scala:545:19] wire [3:0] out_uop_ftq_idx; // @[util.scala:545:19] wire out_uop_edge_inst; // @[util.scala:545:19] wire [5:0] out_uop_pc_lob; // @[util.scala:545:19] wire out_uop_taken; // @[util.scala:545:19] wire out_uop_imm_rename; // @[util.scala:545:19] wire [2:0] out_uop_imm_sel; // @[util.scala:545:19] wire [4:0] out_uop_pimm; // @[util.scala:545:19] wire [19:0] out_uop_imm_packed; // @[util.scala:545:19] wire [1:0] out_uop_op1_sel; // @[util.scala:545:19] wire [2:0] out_uop_op2_sel; // @[util.scala:545:19] wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19] wire out_uop_fp_ctrl_wen; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19] wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19] wire out_uop_fp_ctrl_toint; // @[util.scala:545:19] wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19] wire out_uop_fp_ctrl_fma; // @[util.scala:545:19] wire out_uop_fp_ctrl_div; // @[util.scala:545:19] wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19] wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19] wire out_uop_fp_ctrl_vec; // @[util.scala:545:19] wire [4:0] out_uop_rob_idx; // @[util.scala:545:19] wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19] wire [3:0] out_uop_stq_idx; // @[util.scala:545:19] wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19] wire [5:0] out_uop_pdst; // @[util.scala:545:19] wire [5:0] out_uop_prs1; // @[util.scala:545:19] wire [5:0] out_uop_prs2; // @[util.scala:545:19] wire [5:0] out_uop_prs3; // @[util.scala:545:19] wire [3:0] out_uop_ppred; // @[util.scala:545:19] wire out_uop_prs1_busy; // @[util.scala:545:19] wire out_uop_prs2_busy; // @[util.scala:545:19] wire out_uop_prs3_busy; // @[util.scala:545:19] wire out_uop_ppred_busy; // @[util.scala:545:19] wire [5:0] out_uop_stale_pdst; // @[util.scala:545:19] wire out_uop_exception; // @[util.scala:545:19] wire [63:0] out_uop_exc_cause; // @[util.scala:545:19] wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19] wire [1:0] out_uop_mem_size; // @[util.scala:545:19] wire out_uop_mem_signed; // @[util.scala:545:19] wire out_uop_uses_ldq; // @[util.scala:545:19] wire out_uop_uses_stq; // @[util.scala:545:19] wire out_uop_is_unique; // @[util.scala:545:19] wire out_uop_flush_on_commit; // @[util.scala:545:19] wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19] wire out_uop_ldst_is_rs1; // @[util.scala:545:19] wire [5:0] out_uop_ldst; // @[util.scala:545:19] wire [5:0] out_uop_lrs1; // @[util.scala:545:19] wire [5:0] out_uop_lrs2; // @[util.scala:545:19] wire [5:0] out_uop_lrs3; // @[util.scala:545:19] wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19] wire out_uop_frs3_en; // @[util.scala:545:19] wire out_uop_fcn_dw; // @[util.scala:545:19] wire [4:0] out_uop_fcn_op; // @[util.scala:545:19] wire out_uop_fp_val; // @[util.scala:545:19] wire [2:0] out_uop_fp_rm; // @[util.scala:545:19] wire [1:0] out_uop_fp_typ; // @[util.scala:545:19] wire out_uop_xcpt_pf_if; // @[util.scala:545:19] wire out_uop_xcpt_ae_if; // @[util.scala:545:19] wire out_uop_xcpt_ma_if; // @[util.scala:545:19] wire out_uop_bp_debug_if; // @[util.scala:545:19] wire out_uop_bp_xcpt_if; // @[util.scala:545:19] wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19] wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19] wire [33:0] out_addr; // @[util.scala:545:19] wire [63:0] out_data; // @[util.scala:545:19] wire out_is_hella; // @[util.scala:545:19] wire out_tag_match; // @[util.scala:545:19] wire [1:0] out_old_meta_coh_state; // @[util.scala:545:19] wire [21:0] out_old_meta_tag; // @[util.scala:545:19] wire [1:0] out_way_en; // @[util.scala:545:19] wire [4:0] out_sdq_id; // @[util.scala:545:19] wire _io_empty_T_1; // @[util.scala:512:27] wire [3:0] _io_count_T_5; // @[util.scala:556:22] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count_0; // @[util.scala:458:7] assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:503:22, :545:19] assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:503:22, :545:19] assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:503:22, :545:19] assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:503:22, :545:19] assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:503:22, :545:19] assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:503:22, :545:19] assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:503:22, :545:19] assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:503:22, :545:19] reg valids_0; // @[util.scala:504:26] wire _valids_0_T_4 = valids_0; // @[util.scala:504:26, :520:31] reg valids_1; // @[util.scala:504:26] wire _valids_1_T_4 = valids_1; // @[util.scala:504:26, :520:31] reg valids_2; // @[util.scala:504:26] wire _valids_2_T_4 = valids_2; // @[util.scala:504:26, :520:31] reg valids_3; // @[util.scala:504:26] wire _valids_3_T_4 = valids_3; // @[util.scala:504:26, :520:31] reg valids_4; // @[util.scala:504:26] wire _valids_4_T_4 = valids_4; // @[util.scala:504:26, :520:31] reg valids_5; // @[util.scala:504:26] wire _valids_5_T_4 = valids_5; // @[util.scala:504:26, :520:31] reg valids_6; // @[util.scala:504:26] wire _valids_6_T_4 = valids_6; // @[util.scala:504:26, :520:31] reg valids_7; // @[util.scala:504:26] wire _valids_7_T_4 = valids_7; // @[util.scala:504:26, :520:31] reg valids_8; // @[util.scala:504:26] wire _valids_8_T_4 = valids_8; // @[util.scala:504:26, :520:31] reg valids_9; // @[util.scala:504:26] wire _valids_9_T_4 = valids_9; // @[util.scala:504:26, :520:31] reg valids_10; // @[util.scala:504:26] wire _valids_10_T_4 = valids_10; // @[util.scala:504:26, :520:31] reg valids_11; // @[util.scala:504:26] wire _valids_11_T_4 = valids_11; // @[util.scala:504:26, :520:31] reg valids_12; // @[util.scala:504:26] wire _valids_12_T_4 = valids_12; // @[util.scala:504:26, :520:31] reg valids_13; // @[util.scala:504:26] wire _valids_13_T_4 = valids_13; // @[util.scala:504:26, :520:31] reg valids_14; // @[util.scala:504:26] wire _valids_14_T_4 = valids_14; // @[util.scala:504:26, :520:31] reg [31:0] uops_0_inst; // @[util.scala:505:22] reg [31:0] uops_0_debug_inst; // @[util.scala:505:22] reg uops_0_is_rvc; // @[util.scala:505:22] reg [33:0] uops_0_debug_pc; // @[util.scala:505:22] reg uops_0_iq_type_0; // @[util.scala:505:22] reg uops_0_iq_type_1; // @[util.scala:505:22] reg uops_0_iq_type_2; // @[util.scala:505:22] reg uops_0_iq_type_3; // @[util.scala:505:22] reg uops_0_fu_code_0; // @[util.scala:505:22] reg uops_0_fu_code_1; // @[util.scala:505:22] reg uops_0_fu_code_2; // @[util.scala:505:22] reg uops_0_fu_code_3; // @[util.scala:505:22] reg uops_0_fu_code_4; // @[util.scala:505:22] reg uops_0_fu_code_5; // @[util.scala:505:22] reg uops_0_fu_code_6; // @[util.scala:505:22] reg uops_0_fu_code_7; // @[util.scala:505:22] reg uops_0_fu_code_8; // @[util.scala:505:22] reg uops_0_fu_code_9; // @[util.scala:505:22] reg uops_0_iw_issued; // @[util.scala:505:22] reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_0_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_0_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_0_br_mask; // @[util.scala:505:22] wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_0_br_tag; // @[util.scala:505:22] reg [3:0] uops_0_br_type; // @[util.scala:505:22] reg uops_0_is_sfb; // @[util.scala:505:22] reg uops_0_is_fence; // @[util.scala:505:22] reg uops_0_is_fencei; // @[util.scala:505:22] reg uops_0_is_sfence; // @[util.scala:505:22] reg uops_0_is_amo; // @[util.scala:505:22] reg uops_0_is_eret; // @[util.scala:505:22] reg uops_0_is_sys_pc2epc; // @[util.scala:505:22] reg uops_0_is_rocc; // @[util.scala:505:22] reg uops_0_is_mov; // @[util.scala:505:22] reg [3:0] uops_0_ftq_idx; // @[util.scala:505:22] reg uops_0_edge_inst; // @[util.scala:505:22] reg [5:0] uops_0_pc_lob; // @[util.scala:505:22] reg uops_0_taken; // @[util.scala:505:22] reg uops_0_imm_rename; // @[util.scala:505:22] reg [2:0] uops_0_imm_sel; // @[util.scala:505:22] reg [4:0] uops_0_pimm; // @[util.scala:505:22] reg [19:0] uops_0_imm_packed; // @[util.scala:505:22] reg [1:0] uops_0_op1_sel; // @[util.scala:505:22] reg [2:0] uops_0_op2_sel; // @[util.scala:505:22] reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_0_fp_ctrl_wen; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_0_fp_ctrl_toint; // @[util.scala:505:22] reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_0_fp_ctrl_fma; // @[util.scala:505:22] reg uops_0_fp_ctrl_div; // @[util.scala:505:22] reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_0_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_0_rob_idx; // @[util.scala:505:22] reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_0_stq_idx; // @[util.scala:505:22] reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_0_pdst; // @[util.scala:505:22] reg [5:0] uops_0_prs1; // @[util.scala:505:22] reg [5:0] uops_0_prs2; // @[util.scala:505:22] reg [5:0] uops_0_prs3; // @[util.scala:505:22] reg [3:0] uops_0_ppred; // @[util.scala:505:22] reg uops_0_prs1_busy; // @[util.scala:505:22] reg uops_0_prs2_busy; // @[util.scala:505:22] reg uops_0_prs3_busy; // @[util.scala:505:22] reg uops_0_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_0_stale_pdst; // @[util.scala:505:22] reg uops_0_exception; // @[util.scala:505:22] reg [63:0] uops_0_exc_cause; // @[util.scala:505:22] reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_0_mem_size; // @[util.scala:505:22] reg uops_0_mem_signed; // @[util.scala:505:22] reg uops_0_uses_ldq; // @[util.scala:505:22] reg uops_0_uses_stq; // @[util.scala:505:22] reg uops_0_is_unique; // @[util.scala:505:22] reg uops_0_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22] reg uops_0_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_0_ldst; // @[util.scala:505:22] reg [5:0] uops_0_lrs1; // @[util.scala:505:22] reg [5:0] uops_0_lrs2; // @[util.scala:505:22] reg [5:0] uops_0_lrs3; // @[util.scala:505:22] reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22] reg uops_0_frs3_en; // @[util.scala:505:22] reg uops_0_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_0_fcn_op; // @[util.scala:505:22] reg uops_0_fp_val; // @[util.scala:505:22] reg [2:0] uops_0_fp_rm; // @[util.scala:505:22] reg [1:0] uops_0_fp_typ; // @[util.scala:505:22] reg uops_0_xcpt_pf_if; // @[util.scala:505:22] reg uops_0_xcpt_ae_if; // @[util.scala:505:22] reg uops_0_xcpt_ma_if; // @[util.scala:505:22] reg uops_0_bp_debug_if; // @[util.scala:505:22] reg uops_0_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_1_inst; // @[util.scala:505:22] reg [31:0] uops_1_debug_inst; // @[util.scala:505:22] reg uops_1_is_rvc; // @[util.scala:505:22] reg [33:0] uops_1_debug_pc; // @[util.scala:505:22] reg uops_1_iq_type_0; // @[util.scala:505:22] reg uops_1_iq_type_1; // @[util.scala:505:22] reg uops_1_iq_type_2; // @[util.scala:505:22] reg uops_1_iq_type_3; // @[util.scala:505:22] reg uops_1_fu_code_0; // @[util.scala:505:22] reg uops_1_fu_code_1; // @[util.scala:505:22] reg uops_1_fu_code_2; // @[util.scala:505:22] reg uops_1_fu_code_3; // @[util.scala:505:22] reg uops_1_fu_code_4; // @[util.scala:505:22] reg uops_1_fu_code_5; // @[util.scala:505:22] reg uops_1_fu_code_6; // @[util.scala:505:22] reg uops_1_fu_code_7; // @[util.scala:505:22] reg uops_1_fu_code_8; // @[util.scala:505:22] reg uops_1_fu_code_9; // @[util.scala:505:22] reg uops_1_iw_issued; // @[util.scala:505:22] reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_1_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_1_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_1_br_mask; // @[util.scala:505:22] wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_1_br_tag; // @[util.scala:505:22] reg [3:0] uops_1_br_type; // @[util.scala:505:22] reg uops_1_is_sfb; // @[util.scala:505:22] reg uops_1_is_fence; // @[util.scala:505:22] reg uops_1_is_fencei; // @[util.scala:505:22] reg uops_1_is_sfence; // @[util.scala:505:22] reg uops_1_is_amo; // @[util.scala:505:22] reg uops_1_is_eret; // @[util.scala:505:22] reg uops_1_is_sys_pc2epc; // @[util.scala:505:22] reg uops_1_is_rocc; // @[util.scala:505:22] reg uops_1_is_mov; // @[util.scala:505:22] reg [3:0] uops_1_ftq_idx; // @[util.scala:505:22] reg uops_1_edge_inst; // @[util.scala:505:22] reg [5:0] uops_1_pc_lob; // @[util.scala:505:22] reg uops_1_taken; // @[util.scala:505:22] reg uops_1_imm_rename; // @[util.scala:505:22] reg [2:0] uops_1_imm_sel; // @[util.scala:505:22] reg [4:0] uops_1_pimm; // @[util.scala:505:22] reg [19:0] uops_1_imm_packed; // @[util.scala:505:22] reg [1:0] uops_1_op1_sel; // @[util.scala:505:22] reg [2:0] uops_1_op2_sel; // @[util.scala:505:22] reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_1_fp_ctrl_wen; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_1_fp_ctrl_toint; // @[util.scala:505:22] reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_1_fp_ctrl_fma; // @[util.scala:505:22] reg uops_1_fp_ctrl_div; // @[util.scala:505:22] reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_1_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_1_rob_idx; // @[util.scala:505:22] reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_1_stq_idx; // @[util.scala:505:22] reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_1_pdst; // @[util.scala:505:22] reg [5:0] uops_1_prs1; // @[util.scala:505:22] reg [5:0] uops_1_prs2; // @[util.scala:505:22] reg [5:0] uops_1_prs3; // @[util.scala:505:22] reg [3:0] uops_1_ppred; // @[util.scala:505:22] reg uops_1_prs1_busy; // @[util.scala:505:22] reg uops_1_prs2_busy; // @[util.scala:505:22] reg uops_1_prs3_busy; // @[util.scala:505:22] reg uops_1_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_1_stale_pdst; // @[util.scala:505:22] reg uops_1_exception; // @[util.scala:505:22] reg [63:0] uops_1_exc_cause; // @[util.scala:505:22] reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_1_mem_size; // @[util.scala:505:22] reg uops_1_mem_signed; // @[util.scala:505:22] reg uops_1_uses_ldq; // @[util.scala:505:22] reg uops_1_uses_stq; // @[util.scala:505:22] reg uops_1_is_unique; // @[util.scala:505:22] reg uops_1_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22] reg uops_1_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_1_ldst; // @[util.scala:505:22] reg [5:0] uops_1_lrs1; // @[util.scala:505:22] reg [5:0] uops_1_lrs2; // @[util.scala:505:22] reg [5:0] uops_1_lrs3; // @[util.scala:505:22] reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22] reg uops_1_frs3_en; // @[util.scala:505:22] reg uops_1_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_1_fcn_op; // @[util.scala:505:22] reg uops_1_fp_val; // @[util.scala:505:22] reg [2:0] uops_1_fp_rm; // @[util.scala:505:22] reg [1:0] uops_1_fp_typ; // @[util.scala:505:22] reg uops_1_xcpt_pf_if; // @[util.scala:505:22] reg uops_1_xcpt_ae_if; // @[util.scala:505:22] reg uops_1_xcpt_ma_if; // @[util.scala:505:22] reg uops_1_bp_debug_if; // @[util.scala:505:22] reg uops_1_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_2_inst; // @[util.scala:505:22] reg [31:0] uops_2_debug_inst; // @[util.scala:505:22] reg uops_2_is_rvc; // @[util.scala:505:22] reg [33:0] uops_2_debug_pc; // @[util.scala:505:22] reg uops_2_iq_type_0; // @[util.scala:505:22] reg uops_2_iq_type_1; // @[util.scala:505:22] reg uops_2_iq_type_2; // @[util.scala:505:22] reg uops_2_iq_type_3; // @[util.scala:505:22] reg uops_2_fu_code_0; // @[util.scala:505:22] reg uops_2_fu_code_1; // @[util.scala:505:22] reg uops_2_fu_code_2; // @[util.scala:505:22] reg uops_2_fu_code_3; // @[util.scala:505:22] reg uops_2_fu_code_4; // @[util.scala:505:22] reg uops_2_fu_code_5; // @[util.scala:505:22] reg uops_2_fu_code_6; // @[util.scala:505:22] reg uops_2_fu_code_7; // @[util.scala:505:22] reg uops_2_fu_code_8; // @[util.scala:505:22] reg uops_2_fu_code_9; // @[util.scala:505:22] reg uops_2_iw_issued; // @[util.scala:505:22] reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_2_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_2_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_2_br_mask; // @[util.scala:505:22] wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_2_br_tag; // @[util.scala:505:22] reg [3:0] uops_2_br_type; // @[util.scala:505:22] reg uops_2_is_sfb; // @[util.scala:505:22] reg uops_2_is_fence; // @[util.scala:505:22] reg uops_2_is_fencei; // @[util.scala:505:22] reg uops_2_is_sfence; // @[util.scala:505:22] reg uops_2_is_amo; // @[util.scala:505:22] reg uops_2_is_eret; // @[util.scala:505:22] reg uops_2_is_sys_pc2epc; // @[util.scala:505:22] reg uops_2_is_rocc; // @[util.scala:505:22] reg uops_2_is_mov; // @[util.scala:505:22] reg [3:0] uops_2_ftq_idx; // @[util.scala:505:22] reg uops_2_edge_inst; // @[util.scala:505:22] reg [5:0] uops_2_pc_lob; // @[util.scala:505:22] reg uops_2_taken; // @[util.scala:505:22] reg uops_2_imm_rename; // @[util.scala:505:22] reg [2:0] uops_2_imm_sel; // @[util.scala:505:22] reg [4:0] uops_2_pimm; // @[util.scala:505:22] reg [19:0] uops_2_imm_packed; // @[util.scala:505:22] reg [1:0] uops_2_op1_sel; // @[util.scala:505:22] reg [2:0] uops_2_op2_sel; // @[util.scala:505:22] reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_2_fp_ctrl_wen; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_2_fp_ctrl_toint; // @[util.scala:505:22] reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_2_fp_ctrl_fma; // @[util.scala:505:22] reg uops_2_fp_ctrl_div; // @[util.scala:505:22] reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_2_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_2_rob_idx; // @[util.scala:505:22] reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_2_stq_idx; // @[util.scala:505:22] reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_2_pdst; // @[util.scala:505:22] reg [5:0] uops_2_prs1; // @[util.scala:505:22] reg [5:0] uops_2_prs2; // @[util.scala:505:22] reg [5:0] uops_2_prs3; // @[util.scala:505:22] reg [3:0] uops_2_ppred; // @[util.scala:505:22] reg uops_2_prs1_busy; // @[util.scala:505:22] reg uops_2_prs2_busy; // @[util.scala:505:22] reg uops_2_prs3_busy; // @[util.scala:505:22] reg uops_2_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_2_stale_pdst; // @[util.scala:505:22] reg uops_2_exception; // @[util.scala:505:22] reg [63:0] uops_2_exc_cause; // @[util.scala:505:22] reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_2_mem_size; // @[util.scala:505:22] reg uops_2_mem_signed; // @[util.scala:505:22] reg uops_2_uses_ldq; // @[util.scala:505:22] reg uops_2_uses_stq; // @[util.scala:505:22] reg uops_2_is_unique; // @[util.scala:505:22] reg uops_2_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22] reg uops_2_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_2_ldst; // @[util.scala:505:22] reg [5:0] uops_2_lrs1; // @[util.scala:505:22] reg [5:0] uops_2_lrs2; // @[util.scala:505:22] reg [5:0] uops_2_lrs3; // @[util.scala:505:22] reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22] reg uops_2_frs3_en; // @[util.scala:505:22] reg uops_2_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_2_fcn_op; // @[util.scala:505:22] reg uops_2_fp_val; // @[util.scala:505:22] reg [2:0] uops_2_fp_rm; // @[util.scala:505:22] reg [1:0] uops_2_fp_typ; // @[util.scala:505:22] reg uops_2_xcpt_pf_if; // @[util.scala:505:22] reg uops_2_xcpt_ae_if; // @[util.scala:505:22] reg uops_2_xcpt_ma_if; // @[util.scala:505:22] reg uops_2_bp_debug_if; // @[util.scala:505:22] reg uops_2_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_3_inst; // @[util.scala:505:22] reg [31:0] uops_3_debug_inst; // @[util.scala:505:22] reg uops_3_is_rvc; // @[util.scala:505:22] reg [33:0] uops_3_debug_pc; // @[util.scala:505:22] reg uops_3_iq_type_0; // @[util.scala:505:22] reg uops_3_iq_type_1; // @[util.scala:505:22] reg uops_3_iq_type_2; // @[util.scala:505:22] reg uops_3_iq_type_3; // @[util.scala:505:22] reg uops_3_fu_code_0; // @[util.scala:505:22] reg uops_3_fu_code_1; // @[util.scala:505:22] reg uops_3_fu_code_2; // @[util.scala:505:22] reg uops_3_fu_code_3; // @[util.scala:505:22] reg uops_3_fu_code_4; // @[util.scala:505:22] reg uops_3_fu_code_5; // @[util.scala:505:22] reg uops_3_fu_code_6; // @[util.scala:505:22] reg uops_3_fu_code_7; // @[util.scala:505:22] reg uops_3_fu_code_8; // @[util.scala:505:22] reg uops_3_fu_code_9; // @[util.scala:505:22] reg uops_3_iw_issued; // @[util.scala:505:22] reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_3_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_3_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_3_br_mask; // @[util.scala:505:22] wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_3_br_tag; // @[util.scala:505:22] reg [3:0] uops_3_br_type; // @[util.scala:505:22] reg uops_3_is_sfb; // @[util.scala:505:22] reg uops_3_is_fence; // @[util.scala:505:22] reg uops_3_is_fencei; // @[util.scala:505:22] reg uops_3_is_sfence; // @[util.scala:505:22] reg uops_3_is_amo; // @[util.scala:505:22] reg uops_3_is_eret; // @[util.scala:505:22] reg uops_3_is_sys_pc2epc; // @[util.scala:505:22] reg uops_3_is_rocc; // @[util.scala:505:22] reg uops_3_is_mov; // @[util.scala:505:22] reg [3:0] uops_3_ftq_idx; // @[util.scala:505:22] reg uops_3_edge_inst; // @[util.scala:505:22] reg [5:0] uops_3_pc_lob; // @[util.scala:505:22] reg uops_3_taken; // @[util.scala:505:22] reg uops_3_imm_rename; // @[util.scala:505:22] reg [2:0] uops_3_imm_sel; // @[util.scala:505:22] reg [4:0] uops_3_pimm; // @[util.scala:505:22] reg [19:0] uops_3_imm_packed; // @[util.scala:505:22] reg [1:0] uops_3_op1_sel; // @[util.scala:505:22] reg [2:0] uops_3_op2_sel; // @[util.scala:505:22] reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_3_fp_ctrl_wen; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_3_fp_ctrl_toint; // @[util.scala:505:22] reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_3_fp_ctrl_fma; // @[util.scala:505:22] reg uops_3_fp_ctrl_div; // @[util.scala:505:22] reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_3_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_3_rob_idx; // @[util.scala:505:22] reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_3_stq_idx; // @[util.scala:505:22] reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_3_pdst; // @[util.scala:505:22] reg [5:0] uops_3_prs1; // @[util.scala:505:22] reg [5:0] uops_3_prs2; // @[util.scala:505:22] reg [5:0] uops_3_prs3; // @[util.scala:505:22] reg [3:0] uops_3_ppred; // @[util.scala:505:22] reg uops_3_prs1_busy; // @[util.scala:505:22] reg uops_3_prs2_busy; // @[util.scala:505:22] reg uops_3_prs3_busy; // @[util.scala:505:22] reg uops_3_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_3_stale_pdst; // @[util.scala:505:22] reg uops_3_exception; // @[util.scala:505:22] reg [63:0] uops_3_exc_cause; // @[util.scala:505:22] reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_3_mem_size; // @[util.scala:505:22] reg uops_3_mem_signed; // @[util.scala:505:22] reg uops_3_uses_ldq; // @[util.scala:505:22] reg uops_3_uses_stq; // @[util.scala:505:22] reg uops_3_is_unique; // @[util.scala:505:22] reg uops_3_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22] reg uops_3_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_3_ldst; // @[util.scala:505:22] reg [5:0] uops_3_lrs1; // @[util.scala:505:22] reg [5:0] uops_3_lrs2; // @[util.scala:505:22] reg [5:0] uops_3_lrs3; // @[util.scala:505:22] reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22] reg uops_3_frs3_en; // @[util.scala:505:22] reg uops_3_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_3_fcn_op; // @[util.scala:505:22] reg uops_3_fp_val; // @[util.scala:505:22] reg [2:0] uops_3_fp_rm; // @[util.scala:505:22] reg [1:0] uops_3_fp_typ; // @[util.scala:505:22] reg uops_3_xcpt_pf_if; // @[util.scala:505:22] reg uops_3_xcpt_ae_if; // @[util.scala:505:22] reg uops_3_xcpt_ma_if; // @[util.scala:505:22] reg uops_3_bp_debug_if; // @[util.scala:505:22] reg uops_3_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_4_inst; // @[util.scala:505:22] reg [31:0] uops_4_debug_inst; // @[util.scala:505:22] reg uops_4_is_rvc; // @[util.scala:505:22] reg [33:0] uops_4_debug_pc; // @[util.scala:505:22] reg uops_4_iq_type_0; // @[util.scala:505:22] reg uops_4_iq_type_1; // @[util.scala:505:22] reg uops_4_iq_type_2; // @[util.scala:505:22] reg uops_4_iq_type_3; // @[util.scala:505:22] reg uops_4_fu_code_0; // @[util.scala:505:22] reg uops_4_fu_code_1; // @[util.scala:505:22] reg uops_4_fu_code_2; // @[util.scala:505:22] reg uops_4_fu_code_3; // @[util.scala:505:22] reg uops_4_fu_code_4; // @[util.scala:505:22] reg uops_4_fu_code_5; // @[util.scala:505:22] reg uops_4_fu_code_6; // @[util.scala:505:22] reg uops_4_fu_code_7; // @[util.scala:505:22] reg uops_4_fu_code_8; // @[util.scala:505:22] reg uops_4_fu_code_9; // @[util.scala:505:22] reg uops_4_iw_issued; // @[util.scala:505:22] reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_4_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_4_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_4_br_mask; // @[util.scala:505:22] wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_4_br_tag; // @[util.scala:505:22] reg [3:0] uops_4_br_type; // @[util.scala:505:22] reg uops_4_is_sfb; // @[util.scala:505:22] reg uops_4_is_fence; // @[util.scala:505:22] reg uops_4_is_fencei; // @[util.scala:505:22] reg uops_4_is_sfence; // @[util.scala:505:22] reg uops_4_is_amo; // @[util.scala:505:22] reg uops_4_is_eret; // @[util.scala:505:22] reg uops_4_is_sys_pc2epc; // @[util.scala:505:22] reg uops_4_is_rocc; // @[util.scala:505:22] reg uops_4_is_mov; // @[util.scala:505:22] reg [3:0] uops_4_ftq_idx; // @[util.scala:505:22] reg uops_4_edge_inst; // @[util.scala:505:22] reg [5:0] uops_4_pc_lob; // @[util.scala:505:22] reg uops_4_taken; // @[util.scala:505:22] reg uops_4_imm_rename; // @[util.scala:505:22] reg [2:0] uops_4_imm_sel; // @[util.scala:505:22] reg [4:0] uops_4_pimm; // @[util.scala:505:22] reg [19:0] uops_4_imm_packed; // @[util.scala:505:22] reg [1:0] uops_4_op1_sel; // @[util.scala:505:22] reg [2:0] uops_4_op2_sel; // @[util.scala:505:22] reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_4_fp_ctrl_wen; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_4_fp_ctrl_toint; // @[util.scala:505:22] reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_4_fp_ctrl_fma; // @[util.scala:505:22] reg uops_4_fp_ctrl_div; // @[util.scala:505:22] reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_4_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_4_rob_idx; // @[util.scala:505:22] reg [3:0] uops_4_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_4_stq_idx; // @[util.scala:505:22] reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_4_pdst; // @[util.scala:505:22] reg [5:0] uops_4_prs1; // @[util.scala:505:22] reg [5:0] uops_4_prs2; // @[util.scala:505:22] reg [5:0] uops_4_prs3; // @[util.scala:505:22] reg [3:0] uops_4_ppred; // @[util.scala:505:22] reg uops_4_prs1_busy; // @[util.scala:505:22] reg uops_4_prs2_busy; // @[util.scala:505:22] reg uops_4_prs3_busy; // @[util.scala:505:22] reg uops_4_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_4_stale_pdst; // @[util.scala:505:22] reg uops_4_exception; // @[util.scala:505:22] reg [63:0] uops_4_exc_cause; // @[util.scala:505:22] reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_4_mem_size; // @[util.scala:505:22] reg uops_4_mem_signed; // @[util.scala:505:22] reg uops_4_uses_ldq; // @[util.scala:505:22] reg uops_4_uses_stq; // @[util.scala:505:22] reg uops_4_is_unique; // @[util.scala:505:22] reg uops_4_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22] reg uops_4_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_4_ldst; // @[util.scala:505:22] reg [5:0] uops_4_lrs1; // @[util.scala:505:22] reg [5:0] uops_4_lrs2; // @[util.scala:505:22] reg [5:0] uops_4_lrs3; // @[util.scala:505:22] reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22] reg uops_4_frs3_en; // @[util.scala:505:22] reg uops_4_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_4_fcn_op; // @[util.scala:505:22] reg uops_4_fp_val; // @[util.scala:505:22] reg [2:0] uops_4_fp_rm; // @[util.scala:505:22] reg [1:0] uops_4_fp_typ; // @[util.scala:505:22] reg uops_4_xcpt_pf_if; // @[util.scala:505:22] reg uops_4_xcpt_ae_if; // @[util.scala:505:22] reg uops_4_xcpt_ma_if; // @[util.scala:505:22] reg uops_4_bp_debug_if; // @[util.scala:505:22] reg uops_4_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_5_inst; // @[util.scala:505:22] reg [31:0] uops_5_debug_inst; // @[util.scala:505:22] reg uops_5_is_rvc; // @[util.scala:505:22] reg [33:0] uops_5_debug_pc; // @[util.scala:505:22] reg uops_5_iq_type_0; // @[util.scala:505:22] reg uops_5_iq_type_1; // @[util.scala:505:22] reg uops_5_iq_type_2; // @[util.scala:505:22] reg uops_5_iq_type_3; // @[util.scala:505:22] reg uops_5_fu_code_0; // @[util.scala:505:22] reg uops_5_fu_code_1; // @[util.scala:505:22] reg uops_5_fu_code_2; // @[util.scala:505:22] reg uops_5_fu_code_3; // @[util.scala:505:22] reg uops_5_fu_code_4; // @[util.scala:505:22] reg uops_5_fu_code_5; // @[util.scala:505:22] reg uops_5_fu_code_6; // @[util.scala:505:22] reg uops_5_fu_code_7; // @[util.scala:505:22] reg uops_5_fu_code_8; // @[util.scala:505:22] reg uops_5_fu_code_9; // @[util.scala:505:22] reg uops_5_iw_issued; // @[util.scala:505:22] reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_5_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_5_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_5_br_mask; // @[util.scala:505:22] wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_5_br_tag; // @[util.scala:505:22] reg [3:0] uops_5_br_type; // @[util.scala:505:22] reg uops_5_is_sfb; // @[util.scala:505:22] reg uops_5_is_fence; // @[util.scala:505:22] reg uops_5_is_fencei; // @[util.scala:505:22] reg uops_5_is_sfence; // @[util.scala:505:22] reg uops_5_is_amo; // @[util.scala:505:22] reg uops_5_is_eret; // @[util.scala:505:22] reg uops_5_is_sys_pc2epc; // @[util.scala:505:22] reg uops_5_is_rocc; // @[util.scala:505:22] reg uops_5_is_mov; // @[util.scala:505:22] reg [3:0] uops_5_ftq_idx; // @[util.scala:505:22] reg uops_5_edge_inst; // @[util.scala:505:22] reg [5:0] uops_5_pc_lob; // @[util.scala:505:22] reg uops_5_taken; // @[util.scala:505:22] reg uops_5_imm_rename; // @[util.scala:505:22] reg [2:0] uops_5_imm_sel; // @[util.scala:505:22] reg [4:0] uops_5_pimm; // @[util.scala:505:22] reg [19:0] uops_5_imm_packed; // @[util.scala:505:22] reg [1:0] uops_5_op1_sel; // @[util.scala:505:22] reg [2:0] uops_5_op2_sel; // @[util.scala:505:22] reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_5_fp_ctrl_wen; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_5_fp_ctrl_toint; // @[util.scala:505:22] reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_5_fp_ctrl_fma; // @[util.scala:505:22] reg uops_5_fp_ctrl_div; // @[util.scala:505:22] reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_5_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_5_rob_idx; // @[util.scala:505:22] reg [3:0] uops_5_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_5_stq_idx; // @[util.scala:505:22] reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_5_pdst; // @[util.scala:505:22] reg [5:0] uops_5_prs1; // @[util.scala:505:22] reg [5:0] uops_5_prs2; // @[util.scala:505:22] reg [5:0] uops_5_prs3; // @[util.scala:505:22] reg [3:0] uops_5_ppred; // @[util.scala:505:22] reg uops_5_prs1_busy; // @[util.scala:505:22] reg uops_5_prs2_busy; // @[util.scala:505:22] reg uops_5_prs3_busy; // @[util.scala:505:22] reg uops_5_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_5_stale_pdst; // @[util.scala:505:22] reg uops_5_exception; // @[util.scala:505:22] reg [63:0] uops_5_exc_cause; // @[util.scala:505:22] reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_5_mem_size; // @[util.scala:505:22] reg uops_5_mem_signed; // @[util.scala:505:22] reg uops_5_uses_ldq; // @[util.scala:505:22] reg uops_5_uses_stq; // @[util.scala:505:22] reg uops_5_is_unique; // @[util.scala:505:22] reg uops_5_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22] reg uops_5_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_5_ldst; // @[util.scala:505:22] reg [5:0] uops_5_lrs1; // @[util.scala:505:22] reg [5:0] uops_5_lrs2; // @[util.scala:505:22] reg [5:0] uops_5_lrs3; // @[util.scala:505:22] reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22] reg uops_5_frs3_en; // @[util.scala:505:22] reg uops_5_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_5_fcn_op; // @[util.scala:505:22] reg uops_5_fp_val; // @[util.scala:505:22] reg [2:0] uops_5_fp_rm; // @[util.scala:505:22] reg [1:0] uops_5_fp_typ; // @[util.scala:505:22] reg uops_5_xcpt_pf_if; // @[util.scala:505:22] reg uops_5_xcpt_ae_if; // @[util.scala:505:22] reg uops_5_xcpt_ma_if; // @[util.scala:505:22] reg uops_5_bp_debug_if; // @[util.scala:505:22] reg uops_5_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_6_inst; // @[util.scala:505:22] reg [31:0] uops_6_debug_inst; // @[util.scala:505:22] reg uops_6_is_rvc; // @[util.scala:505:22] reg [33:0] uops_6_debug_pc; // @[util.scala:505:22] reg uops_6_iq_type_0; // @[util.scala:505:22] reg uops_6_iq_type_1; // @[util.scala:505:22] reg uops_6_iq_type_2; // @[util.scala:505:22] reg uops_6_iq_type_3; // @[util.scala:505:22] reg uops_6_fu_code_0; // @[util.scala:505:22] reg uops_6_fu_code_1; // @[util.scala:505:22] reg uops_6_fu_code_2; // @[util.scala:505:22] reg uops_6_fu_code_3; // @[util.scala:505:22] reg uops_6_fu_code_4; // @[util.scala:505:22] reg uops_6_fu_code_5; // @[util.scala:505:22] reg uops_6_fu_code_6; // @[util.scala:505:22] reg uops_6_fu_code_7; // @[util.scala:505:22] reg uops_6_fu_code_8; // @[util.scala:505:22] reg uops_6_fu_code_9; // @[util.scala:505:22] reg uops_6_iw_issued; // @[util.scala:505:22] reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_6_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_6_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_6_br_mask; // @[util.scala:505:22] wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_6_br_tag; // @[util.scala:505:22] reg [3:0] uops_6_br_type; // @[util.scala:505:22] reg uops_6_is_sfb; // @[util.scala:505:22] reg uops_6_is_fence; // @[util.scala:505:22] reg uops_6_is_fencei; // @[util.scala:505:22] reg uops_6_is_sfence; // @[util.scala:505:22] reg uops_6_is_amo; // @[util.scala:505:22] reg uops_6_is_eret; // @[util.scala:505:22] reg uops_6_is_sys_pc2epc; // @[util.scala:505:22] reg uops_6_is_rocc; // @[util.scala:505:22] reg uops_6_is_mov; // @[util.scala:505:22] reg [3:0] uops_6_ftq_idx; // @[util.scala:505:22] reg uops_6_edge_inst; // @[util.scala:505:22] reg [5:0] uops_6_pc_lob; // @[util.scala:505:22] reg uops_6_taken; // @[util.scala:505:22] reg uops_6_imm_rename; // @[util.scala:505:22] reg [2:0] uops_6_imm_sel; // @[util.scala:505:22] reg [4:0] uops_6_pimm; // @[util.scala:505:22] reg [19:0] uops_6_imm_packed; // @[util.scala:505:22] reg [1:0] uops_6_op1_sel; // @[util.scala:505:22] reg [2:0] uops_6_op2_sel; // @[util.scala:505:22] reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_6_fp_ctrl_wen; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_6_fp_ctrl_toint; // @[util.scala:505:22] reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_6_fp_ctrl_fma; // @[util.scala:505:22] reg uops_6_fp_ctrl_div; // @[util.scala:505:22] reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_6_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_6_rob_idx; // @[util.scala:505:22] reg [3:0] uops_6_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_6_stq_idx; // @[util.scala:505:22] reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_6_pdst; // @[util.scala:505:22] reg [5:0] uops_6_prs1; // @[util.scala:505:22] reg [5:0] uops_6_prs2; // @[util.scala:505:22] reg [5:0] uops_6_prs3; // @[util.scala:505:22] reg [3:0] uops_6_ppred; // @[util.scala:505:22] reg uops_6_prs1_busy; // @[util.scala:505:22] reg uops_6_prs2_busy; // @[util.scala:505:22] reg uops_6_prs3_busy; // @[util.scala:505:22] reg uops_6_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_6_stale_pdst; // @[util.scala:505:22] reg uops_6_exception; // @[util.scala:505:22] reg [63:0] uops_6_exc_cause; // @[util.scala:505:22] reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_6_mem_size; // @[util.scala:505:22] reg uops_6_mem_signed; // @[util.scala:505:22] reg uops_6_uses_ldq; // @[util.scala:505:22] reg uops_6_uses_stq; // @[util.scala:505:22] reg uops_6_is_unique; // @[util.scala:505:22] reg uops_6_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22] reg uops_6_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_6_ldst; // @[util.scala:505:22] reg [5:0] uops_6_lrs1; // @[util.scala:505:22] reg [5:0] uops_6_lrs2; // @[util.scala:505:22] reg [5:0] uops_6_lrs3; // @[util.scala:505:22] reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22] reg uops_6_frs3_en; // @[util.scala:505:22] reg uops_6_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_6_fcn_op; // @[util.scala:505:22] reg uops_6_fp_val; // @[util.scala:505:22] reg [2:0] uops_6_fp_rm; // @[util.scala:505:22] reg [1:0] uops_6_fp_typ; // @[util.scala:505:22] reg uops_6_xcpt_pf_if; // @[util.scala:505:22] reg uops_6_xcpt_ae_if; // @[util.scala:505:22] reg uops_6_xcpt_ma_if; // @[util.scala:505:22] reg uops_6_bp_debug_if; // @[util.scala:505:22] reg uops_6_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_7_inst; // @[util.scala:505:22] reg [31:0] uops_7_debug_inst; // @[util.scala:505:22] reg uops_7_is_rvc; // @[util.scala:505:22] reg [33:0] uops_7_debug_pc; // @[util.scala:505:22] reg uops_7_iq_type_0; // @[util.scala:505:22] reg uops_7_iq_type_1; // @[util.scala:505:22] reg uops_7_iq_type_2; // @[util.scala:505:22] reg uops_7_iq_type_3; // @[util.scala:505:22] reg uops_7_fu_code_0; // @[util.scala:505:22] reg uops_7_fu_code_1; // @[util.scala:505:22] reg uops_7_fu_code_2; // @[util.scala:505:22] reg uops_7_fu_code_3; // @[util.scala:505:22] reg uops_7_fu_code_4; // @[util.scala:505:22] reg uops_7_fu_code_5; // @[util.scala:505:22] reg uops_7_fu_code_6; // @[util.scala:505:22] reg uops_7_fu_code_7; // @[util.scala:505:22] reg uops_7_fu_code_8; // @[util.scala:505:22] reg uops_7_fu_code_9; // @[util.scala:505:22] reg uops_7_iw_issued; // @[util.scala:505:22] reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_7_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_7_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_7_br_mask; // @[util.scala:505:22] wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_7_br_tag; // @[util.scala:505:22] reg [3:0] uops_7_br_type; // @[util.scala:505:22] reg uops_7_is_sfb; // @[util.scala:505:22] reg uops_7_is_fence; // @[util.scala:505:22] reg uops_7_is_fencei; // @[util.scala:505:22] reg uops_7_is_sfence; // @[util.scala:505:22] reg uops_7_is_amo; // @[util.scala:505:22] reg uops_7_is_eret; // @[util.scala:505:22] reg uops_7_is_sys_pc2epc; // @[util.scala:505:22] reg uops_7_is_rocc; // @[util.scala:505:22] reg uops_7_is_mov; // @[util.scala:505:22] reg [3:0] uops_7_ftq_idx; // @[util.scala:505:22] reg uops_7_edge_inst; // @[util.scala:505:22] reg [5:0] uops_7_pc_lob; // @[util.scala:505:22] reg uops_7_taken; // @[util.scala:505:22] reg uops_7_imm_rename; // @[util.scala:505:22] reg [2:0] uops_7_imm_sel; // @[util.scala:505:22] reg [4:0] uops_7_pimm; // @[util.scala:505:22] reg [19:0] uops_7_imm_packed; // @[util.scala:505:22] reg [1:0] uops_7_op1_sel; // @[util.scala:505:22] reg [2:0] uops_7_op2_sel; // @[util.scala:505:22] reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_7_fp_ctrl_wen; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_7_fp_ctrl_toint; // @[util.scala:505:22] reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_7_fp_ctrl_fma; // @[util.scala:505:22] reg uops_7_fp_ctrl_div; // @[util.scala:505:22] reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_7_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_7_rob_idx; // @[util.scala:505:22] reg [3:0] uops_7_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_7_stq_idx; // @[util.scala:505:22] reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_7_pdst; // @[util.scala:505:22] reg [5:0] uops_7_prs1; // @[util.scala:505:22] reg [5:0] uops_7_prs2; // @[util.scala:505:22] reg [5:0] uops_7_prs3; // @[util.scala:505:22] reg [3:0] uops_7_ppred; // @[util.scala:505:22] reg uops_7_prs1_busy; // @[util.scala:505:22] reg uops_7_prs2_busy; // @[util.scala:505:22] reg uops_7_prs3_busy; // @[util.scala:505:22] reg uops_7_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_7_stale_pdst; // @[util.scala:505:22] reg uops_7_exception; // @[util.scala:505:22] reg [63:0] uops_7_exc_cause; // @[util.scala:505:22] reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_7_mem_size; // @[util.scala:505:22] reg uops_7_mem_signed; // @[util.scala:505:22] reg uops_7_uses_ldq; // @[util.scala:505:22] reg uops_7_uses_stq; // @[util.scala:505:22] reg uops_7_is_unique; // @[util.scala:505:22] reg uops_7_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22] reg uops_7_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_7_ldst; // @[util.scala:505:22] reg [5:0] uops_7_lrs1; // @[util.scala:505:22] reg [5:0] uops_7_lrs2; // @[util.scala:505:22] reg [5:0] uops_7_lrs3; // @[util.scala:505:22] reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22] reg uops_7_frs3_en; // @[util.scala:505:22] reg uops_7_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_7_fcn_op; // @[util.scala:505:22] reg uops_7_fp_val; // @[util.scala:505:22] reg [2:0] uops_7_fp_rm; // @[util.scala:505:22] reg [1:0] uops_7_fp_typ; // @[util.scala:505:22] reg uops_7_xcpt_pf_if; // @[util.scala:505:22] reg uops_7_xcpt_ae_if; // @[util.scala:505:22] reg uops_7_xcpt_ma_if; // @[util.scala:505:22] reg uops_7_bp_debug_if; // @[util.scala:505:22] reg uops_7_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_8_inst; // @[util.scala:505:22] reg [31:0] uops_8_debug_inst; // @[util.scala:505:22] reg uops_8_is_rvc; // @[util.scala:505:22] reg [33:0] uops_8_debug_pc; // @[util.scala:505:22] reg uops_8_iq_type_0; // @[util.scala:505:22] reg uops_8_iq_type_1; // @[util.scala:505:22] reg uops_8_iq_type_2; // @[util.scala:505:22] reg uops_8_iq_type_3; // @[util.scala:505:22] reg uops_8_fu_code_0; // @[util.scala:505:22] reg uops_8_fu_code_1; // @[util.scala:505:22] reg uops_8_fu_code_2; // @[util.scala:505:22] reg uops_8_fu_code_3; // @[util.scala:505:22] reg uops_8_fu_code_4; // @[util.scala:505:22] reg uops_8_fu_code_5; // @[util.scala:505:22] reg uops_8_fu_code_6; // @[util.scala:505:22] reg uops_8_fu_code_7; // @[util.scala:505:22] reg uops_8_fu_code_8; // @[util.scala:505:22] reg uops_8_fu_code_9; // @[util.scala:505:22] reg uops_8_iw_issued; // @[util.scala:505:22] reg uops_8_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_8_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_8_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_8_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_8_br_mask; // @[util.scala:505:22] wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_8_br_tag; // @[util.scala:505:22] reg [3:0] uops_8_br_type; // @[util.scala:505:22] reg uops_8_is_sfb; // @[util.scala:505:22] reg uops_8_is_fence; // @[util.scala:505:22] reg uops_8_is_fencei; // @[util.scala:505:22] reg uops_8_is_sfence; // @[util.scala:505:22] reg uops_8_is_amo; // @[util.scala:505:22] reg uops_8_is_eret; // @[util.scala:505:22] reg uops_8_is_sys_pc2epc; // @[util.scala:505:22] reg uops_8_is_rocc; // @[util.scala:505:22] reg uops_8_is_mov; // @[util.scala:505:22] reg [3:0] uops_8_ftq_idx; // @[util.scala:505:22] reg uops_8_edge_inst; // @[util.scala:505:22] reg [5:0] uops_8_pc_lob; // @[util.scala:505:22] reg uops_8_taken; // @[util.scala:505:22] reg uops_8_imm_rename; // @[util.scala:505:22] reg [2:0] uops_8_imm_sel; // @[util.scala:505:22] reg [4:0] uops_8_pimm; // @[util.scala:505:22] reg [19:0] uops_8_imm_packed; // @[util.scala:505:22] reg [1:0] uops_8_op1_sel; // @[util.scala:505:22] reg [2:0] uops_8_op2_sel; // @[util.scala:505:22] reg uops_8_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_8_fp_ctrl_wen; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_8_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_8_fp_ctrl_toint; // @[util.scala:505:22] reg uops_8_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_8_fp_ctrl_fma; // @[util.scala:505:22] reg uops_8_fp_ctrl_div; // @[util.scala:505:22] reg uops_8_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_8_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_8_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_8_rob_idx; // @[util.scala:505:22] reg [3:0] uops_8_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_8_stq_idx; // @[util.scala:505:22] reg [1:0] uops_8_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_8_pdst; // @[util.scala:505:22] reg [5:0] uops_8_prs1; // @[util.scala:505:22] reg [5:0] uops_8_prs2; // @[util.scala:505:22] reg [5:0] uops_8_prs3; // @[util.scala:505:22] reg [3:0] uops_8_ppred; // @[util.scala:505:22] reg uops_8_prs1_busy; // @[util.scala:505:22] reg uops_8_prs2_busy; // @[util.scala:505:22] reg uops_8_prs3_busy; // @[util.scala:505:22] reg uops_8_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_8_stale_pdst; // @[util.scala:505:22] reg uops_8_exception; // @[util.scala:505:22] reg [63:0] uops_8_exc_cause; // @[util.scala:505:22] reg [4:0] uops_8_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_8_mem_size; // @[util.scala:505:22] reg uops_8_mem_signed; // @[util.scala:505:22] reg uops_8_uses_ldq; // @[util.scala:505:22] reg uops_8_uses_stq; // @[util.scala:505:22] reg uops_8_is_unique; // @[util.scala:505:22] reg uops_8_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_8_csr_cmd; // @[util.scala:505:22] reg uops_8_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_8_ldst; // @[util.scala:505:22] reg [5:0] uops_8_lrs1; // @[util.scala:505:22] reg [5:0] uops_8_lrs2; // @[util.scala:505:22] reg [5:0] uops_8_lrs3; // @[util.scala:505:22] reg [1:0] uops_8_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:505:22] reg uops_8_frs3_en; // @[util.scala:505:22] reg uops_8_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_8_fcn_op; // @[util.scala:505:22] reg uops_8_fp_val; // @[util.scala:505:22] reg [2:0] uops_8_fp_rm; // @[util.scala:505:22] reg [1:0] uops_8_fp_typ; // @[util.scala:505:22] reg uops_8_xcpt_pf_if; // @[util.scala:505:22] reg uops_8_xcpt_ae_if; // @[util.scala:505:22] reg uops_8_xcpt_ma_if; // @[util.scala:505:22] reg uops_8_bp_debug_if; // @[util.scala:505:22] reg uops_8_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_8_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_8_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_9_inst; // @[util.scala:505:22] reg [31:0] uops_9_debug_inst; // @[util.scala:505:22] reg uops_9_is_rvc; // @[util.scala:505:22] reg [33:0] uops_9_debug_pc; // @[util.scala:505:22] reg uops_9_iq_type_0; // @[util.scala:505:22] reg uops_9_iq_type_1; // @[util.scala:505:22] reg uops_9_iq_type_2; // @[util.scala:505:22] reg uops_9_iq_type_3; // @[util.scala:505:22] reg uops_9_fu_code_0; // @[util.scala:505:22] reg uops_9_fu_code_1; // @[util.scala:505:22] reg uops_9_fu_code_2; // @[util.scala:505:22] reg uops_9_fu_code_3; // @[util.scala:505:22] reg uops_9_fu_code_4; // @[util.scala:505:22] reg uops_9_fu_code_5; // @[util.scala:505:22] reg uops_9_fu_code_6; // @[util.scala:505:22] reg uops_9_fu_code_7; // @[util.scala:505:22] reg uops_9_fu_code_8; // @[util.scala:505:22] reg uops_9_fu_code_9; // @[util.scala:505:22] reg uops_9_iw_issued; // @[util.scala:505:22] reg uops_9_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_9_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_9_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_9_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_9_br_mask; // @[util.scala:505:22] wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_9_br_tag; // @[util.scala:505:22] reg [3:0] uops_9_br_type; // @[util.scala:505:22] reg uops_9_is_sfb; // @[util.scala:505:22] reg uops_9_is_fence; // @[util.scala:505:22] reg uops_9_is_fencei; // @[util.scala:505:22] reg uops_9_is_sfence; // @[util.scala:505:22] reg uops_9_is_amo; // @[util.scala:505:22] reg uops_9_is_eret; // @[util.scala:505:22] reg uops_9_is_sys_pc2epc; // @[util.scala:505:22] reg uops_9_is_rocc; // @[util.scala:505:22] reg uops_9_is_mov; // @[util.scala:505:22] reg [3:0] uops_9_ftq_idx; // @[util.scala:505:22] reg uops_9_edge_inst; // @[util.scala:505:22] reg [5:0] uops_9_pc_lob; // @[util.scala:505:22] reg uops_9_taken; // @[util.scala:505:22] reg uops_9_imm_rename; // @[util.scala:505:22] reg [2:0] uops_9_imm_sel; // @[util.scala:505:22] reg [4:0] uops_9_pimm; // @[util.scala:505:22] reg [19:0] uops_9_imm_packed; // @[util.scala:505:22] reg [1:0] uops_9_op1_sel; // @[util.scala:505:22] reg [2:0] uops_9_op2_sel; // @[util.scala:505:22] reg uops_9_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_9_fp_ctrl_wen; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_9_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_9_fp_ctrl_toint; // @[util.scala:505:22] reg uops_9_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_9_fp_ctrl_fma; // @[util.scala:505:22] reg uops_9_fp_ctrl_div; // @[util.scala:505:22] reg uops_9_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_9_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_9_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_9_rob_idx; // @[util.scala:505:22] reg [3:0] uops_9_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_9_stq_idx; // @[util.scala:505:22] reg [1:0] uops_9_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_9_pdst; // @[util.scala:505:22] reg [5:0] uops_9_prs1; // @[util.scala:505:22] reg [5:0] uops_9_prs2; // @[util.scala:505:22] reg [5:0] uops_9_prs3; // @[util.scala:505:22] reg [3:0] uops_9_ppred; // @[util.scala:505:22] reg uops_9_prs1_busy; // @[util.scala:505:22] reg uops_9_prs2_busy; // @[util.scala:505:22] reg uops_9_prs3_busy; // @[util.scala:505:22] reg uops_9_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_9_stale_pdst; // @[util.scala:505:22] reg uops_9_exception; // @[util.scala:505:22] reg [63:0] uops_9_exc_cause; // @[util.scala:505:22] reg [4:0] uops_9_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_9_mem_size; // @[util.scala:505:22] reg uops_9_mem_signed; // @[util.scala:505:22] reg uops_9_uses_ldq; // @[util.scala:505:22] reg uops_9_uses_stq; // @[util.scala:505:22] reg uops_9_is_unique; // @[util.scala:505:22] reg uops_9_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_9_csr_cmd; // @[util.scala:505:22] reg uops_9_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_9_ldst; // @[util.scala:505:22] reg [5:0] uops_9_lrs1; // @[util.scala:505:22] reg [5:0] uops_9_lrs2; // @[util.scala:505:22] reg [5:0] uops_9_lrs3; // @[util.scala:505:22] reg [1:0] uops_9_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:505:22] reg uops_9_frs3_en; // @[util.scala:505:22] reg uops_9_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_9_fcn_op; // @[util.scala:505:22] reg uops_9_fp_val; // @[util.scala:505:22] reg [2:0] uops_9_fp_rm; // @[util.scala:505:22] reg [1:0] uops_9_fp_typ; // @[util.scala:505:22] reg uops_9_xcpt_pf_if; // @[util.scala:505:22] reg uops_9_xcpt_ae_if; // @[util.scala:505:22] reg uops_9_xcpt_ma_if; // @[util.scala:505:22] reg uops_9_bp_debug_if; // @[util.scala:505:22] reg uops_9_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_9_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_9_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_10_inst; // @[util.scala:505:22] reg [31:0] uops_10_debug_inst; // @[util.scala:505:22] reg uops_10_is_rvc; // @[util.scala:505:22] reg [33:0] uops_10_debug_pc; // @[util.scala:505:22] reg uops_10_iq_type_0; // @[util.scala:505:22] reg uops_10_iq_type_1; // @[util.scala:505:22] reg uops_10_iq_type_2; // @[util.scala:505:22] reg uops_10_iq_type_3; // @[util.scala:505:22] reg uops_10_fu_code_0; // @[util.scala:505:22] reg uops_10_fu_code_1; // @[util.scala:505:22] reg uops_10_fu_code_2; // @[util.scala:505:22] reg uops_10_fu_code_3; // @[util.scala:505:22] reg uops_10_fu_code_4; // @[util.scala:505:22] reg uops_10_fu_code_5; // @[util.scala:505:22] reg uops_10_fu_code_6; // @[util.scala:505:22] reg uops_10_fu_code_7; // @[util.scala:505:22] reg uops_10_fu_code_8; // @[util.scala:505:22] reg uops_10_fu_code_9; // @[util.scala:505:22] reg uops_10_iw_issued; // @[util.scala:505:22] reg uops_10_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_10_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_10_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_10_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_10_br_mask; // @[util.scala:505:22] wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_10_br_tag; // @[util.scala:505:22] reg [3:0] uops_10_br_type; // @[util.scala:505:22] reg uops_10_is_sfb; // @[util.scala:505:22] reg uops_10_is_fence; // @[util.scala:505:22] reg uops_10_is_fencei; // @[util.scala:505:22] reg uops_10_is_sfence; // @[util.scala:505:22] reg uops_10_is_amo; // @[util.scala:505:22] reg uops_10_is_eret; // @[util.scala:505:22] reg uops_10_is_sys_pc2epc; // @[util.scala:505:22] reg uops_10_is_rocc; // @[util.scala:505:22] reg uops_10_is_mov; // @[util.scala:505:22] reg [3:0] uops_10_ftq_idx; // @[util.scala:505:22] reg uops_10_edge_inst; // @[util.scala:505:22] reg [5:0] uops_10_pc_lob; // @[util.scala:505:22] reg uops_10_taken; // @[util.scala:505:22] reg uops_10_imm_rename; // @[util.scala:505:22] reg [2:0] uops_10_imm_sel; // @[util.scala:505:22] reg [4:0] uops_10_pimm; // @[util.scala:505:22] reg [19:0] uops_10_imm_packed; // @[util.scala:505:22] reg [1:0] uops_10_op1_sel; // @[util.scala:505:22] reg [2:0] uops_10_op2_sel; // @[util.scala:505:22] reg uops_10_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_10_fp_ctrl_wen; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_10_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_10_fp_ctrl_toint; // @[util.scala:505:22] reg uops_10_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_10_fp_ctrl_fma; // @[util.scala:505:22] reg uops_10_fp_ctrl_div; // @[util.scala:505:22] reg uops_10_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_10_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_10_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_10_rob_idx; // @[util.scala:505:22] reg [3:0] uops_10_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_10_stq_idx; // @[util.scala:505:22] reg [1:0] uops_10_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_10_pdst; // @[util.scala:505:22] reg [5:0] uops_10_prs1; // @[util.scala:505:22] reg [5:0] uops_10_prs2; // @[util.scala:505:22] reg [5:0] uops_10_prs3; // @[util.scala:505:22] reg [3:0] uops_10_ppred; // @[util.scala:505:22] reg uops_10_prs1_busy; // @[util.scala:505:22] reg uops_10_prs2_busy; // @[util.scala:505:22] reg uops_10_prs3_busy; // @[util.scala:505:22] reg uops_10_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_10_stale_pdst; // @[util.scala:505:22] reg uops_10_exception; // @[util.scala:505:22] reg [63:0] uops_10_exc_cause; // @[util.scala:505:22] reg [4:0] uops_10_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_10_mem_size; // @[util.scala:505:22] reg uops_10_mem_signed; // @[util.scala:505:22] reg uops_10_uses_ldq; // @[util.scala:505:22] reg uops_10_uses_stq; // @[util.scala:505:22] reg uops_10_is_unique; // @[util.scala:505:22] reg uops_10_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_10_csr_cmd; // @[util.scala:505:22] reg uops_10_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_10_ldst; // @[util.scala:505:22] reg [5:0] uops_10_lrs1; // @[util.scala:505:22] reg [5:0] uops_10_lrs2; // @[util.scala:505:22] reg [5:0] uops_10_lrs3; // @[util.scala:505:22] reg [1:0] uops_10_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:505:22] reg uops_10_frs3_en; // @[util.scala:505:22] reg uops_10_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_10_fcn_op; // @[util.scala:505:22] reg uops_10_fp_val; // @[util.scala:505:22] reg [2:0] uops_10_fp_rm; // @[util.scala:505:22] reg [1:0] uops_10_fp_typ; // @[util.scala:505:22] reg uops_10_xcpt_pf_if; // @[util.scala:505:22] reg uops_10_xcpt_ae_if; // @[util.scala:505:22] reg uops_10_xcpt_ma_if; // @[util.scala:505:22] reg uops_10_bp_debug_if; // @[util.scala:505:22] reg uops_10_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_10_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_10_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_11_inst; // @[util.scala:505:22] reg [31:0] uops_11_debug_inst; // @[util.scala:505:22] reg uops_11_is_rvc; // @[util.scala:505:22] reg [33:0] uops_11_debug_pc; // @[util.scala:505:22] reg uops_11_iq_type_0; // @[util.scala:505:22] reg uops_11_iq_type_1; // @[util.scala:505:22] reg uops_11_iq_type_2; // @[util.scala:505:22] reg uops_11_iq_type_3; // @[util.scala:505:22] reg uops_11_fu_code_0; // @[util.scala:505:22] reg uops_11_fu_code_1; // @[util.scala:505:22] reg uops_11_fu_code_2; // @[util.scala:505:22] reg uops_11_fu_code_3; // @[util.scala:505:22] reg uops_11_fu_code_4; // @[util.scala:505:22] reg uops_11_fu_code_5; // @[util.scala:505:22] reg uops_11_fu_code_6; // @[util.scala:505:22] reg uops_11_fu_code_7; // @[util.scala:505:22] reg uops_11_fu_code_8; // @[util.scala:505:22] reg uops_11_fu_code_9; // @[util.scala:505:22] reg uops_11_iw_issued; // @[util.scala:505:22] reg uops_11_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_11_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_11_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_11_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_11_br_mask; // @[util.scala:505:22] wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_11_br_tag; // @[util.scala:505:22] reg [3:0] uops_11_br_type; // @[util.scala:505:22] reg uops_11_is_sfb; // @[util.scala:505:22] reg uops_11_is_fence; // @[util.scala:505:22] reg uops_11_is_fencei; // @[util.scala:505:22] reg uops_11_is_sfence; // @[util.scala:505:22] reg uops_11_is_amo; // @[util.scala:505:22] reg uops_11_is_eret; // @[util.scala:505:22] reg uops_11_is_sys_pc2epc; // @[util.scala:505:22] reg uops_11_is_rocc; // @[util.scala:505:22] reg uops_11_is_mov; // @[util.scala:505:22] reg [3:0] uops_11_ftq_idx; // @[util.scala:505:22] reg uops_11_edge_inst; // @[util.scala:505:22] reg [5:0] uops_11_pc_lob; // @[util.scala:505:22] reg uops_11_taken; // @[util.scala:505:22] reg uops_11_imm_rename; // @[util.scala:505:22] reg [2:0] uops_11_imm_sel; // @[util.scala:505:22] reg [4:0] uops_11_pimm; // @[util.scala:505:22] reg [19:0] uops_11_imm_packed; // @[util.scala:505:22] reg [1:0] uops_11_op1_sel; // @[util.scala:505:22] reg [2:0] uops_11_op2_sel; // @[util.scala:505:22] reg uops_11_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_11_fp_ctrl_wen; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_11_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_11_fp_ctrl_toint; // @[util.scala:505:22] reg uops_11_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_11_fp_ctrl_fma; // @[util.scala:505:22] reg uops_11_fp_ctrl_div; // @[util.scala:505:22] reg uops_11_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_11_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_11_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_11_rob_idx; // @[util.scala:505:22] reg [3:0] uops_11_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_11_stq_idx; // @[util.scala:505:22] reg [1:0] uops_11_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_11_pdst; // @[util.scala:505:22] reg [5:0] uops_11_prs1; // @[util.scala:505:22] reg [5:0] uops_11_prs2; // @[util.scala:505:22] reg [5:0] uops_11_prs3; // @[util.scala:505:22] reg [3:0] uops_11_ppred; // @[util.scala:505:22] reg uops_11_prs1_busy; // @[util.scala:505:22] reg uops_11_prs2_busy; // @[util.scala:505:22] reg uops_11_prs3_busy; // @[util.scala:505:22] reg uops_11_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_11_stale_pdst; // @[util.scala:505:22] reg uops_11_exception; // @[util.scala:505:22] reg [63:0] uops_11_exc_cause; // @[util.scala:505:22] reg [4:0] uops_11_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_11_mem_size; // @[util.scala:505:22] reg uops_11_mem_signed; // @[util.scala:505:22] reg uops_11_uses_ldq; // @[util.scala:505:22] reg uops_11_uses_stq; // @[util.scala:505:22] reg uops_11_is_unique; // @[util.scala:505:22] reg uops_11_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_11_csr_cmd; // @[util.scala:505:22] reg uops_11_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_11_ldst; // @[util.scala:505:22] reg [5:0] uops_11_lrs1; // @[util.scala:505:22] reg [5:0] uops_11_lrs2; // @[util.scala:505:22] reg [5:0] uops_11_lrs3; // @[util.scala:505:22] reg [1:0] uops_11_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:505:22] reg uops_11_frs3_en; // @[util.scala:505:22] reg uops_11_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_11_fcn_op; // @[util.scala:505:22] reg uops_11_fp_val; // @[util.scala:505:22] reg [2:0] uops_11_fp_rm; // @[util.scala:505:22] reg [1:0] uops_11_fp_typ; // @[util.scala:505:22] reg uops_11_xcpt_pf_if; // @[util.scala:505:22] reg uops_11_xcpt_ae_if; // @[util.scala:505:22] reg uops_11_xcpt_ma_if; // @[util.scala:505:22] reg uops_11_bp_debug_if; // @[util.scala:505:22] reg uops_11_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_11_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_11_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_12_inst; // @[util.scala:505:22] reg [31:0] uops_12_debug_inst; // @[util.scala:505:22] reg uops_12_is_rvc; // @[util.scala:505:22] reg [33:0] uops_12_debug_pc; // @[util.scala:505:22] reg uops_12_iq_type_0; // @[util.scala:505:22] reg uops_12_iq_type_1; // @[util.scala:505:22] reg uops_12_iq_type_2; // @[util.scala:505:22] reg uops_12_iq_type_3; // @[util.scala:505:22] reg uops_12_fu_code_0; // @[util.scala:505:22] reg uops_12_fu_code_1; // @[util.scala:505:22] reg uops_12_fu_code_2; // @[util.scala:505:22] reg uops_12_fu_code_3; // @[util.scala:505:22] reg uops_12_fu_code_4; // @[util.scala:505:22] reg uops_12_fu_code_5; // @[util.scala:505:22] reg uops_12_fu_code_6; // @[util.scala:505:22] reg uops_12_fu_code_7; // @[util.scala:505:22] reg uops_12_fu_code_8; // @[util.scala:505:22] reg uops_12_fu_code_9; // @[util.scala:505:22] reg uops_12_iw_issued; // @[util.scala:505:22] reg uops_12_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_12_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_12_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_12_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_12_br_mask; // @[util.scala:505:22] wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_12_br_tag; // @[util.scala:505:22] reg [3:0] uops_12_br_type; // @[util.scala:505:22] reg uops_12_is_sfb; // @[util.scala:505:22] reg uops_12_is_fence; // @[util.scala:505:22] reg uops_12_is_fencei; // @[util.scala:505:22] reg uops_12_is_sfence; // @[util.scala:505:22] reg uops_12_is_amo; // @[util.scala:505:22] reg uops_12_is_eret; // @[util.scala:505:22] reg uops_12_is_sys_pc2epc; // @[util.scala:505:22] reg uops_12_is_rocc; // @[util.scala:505:22] reg uops_12_is_mov; // @[util.scala:505:22] reg [3:0] uops_12_ftq_idx; // @[util.scala:505:22] reg uops_12_edge_inst; // @[util.scala:505:22] reg [5:0] uops_12_pc_lob; // @[util.scala:505:22] reg uops_12_taken; // @[util.scala:505:22] reg uops_12_imm_rename; // @[util.scala:505:22] reg [2:0] uops_12_imm_sel; // @[util.scala:505:22] reg [4:0] uops_12_pimm; // @[util.scala:505:22] reg [19:0] uops_12_imm_packed; // @[util.scala:505:22] reg [1:0] uops_12_op1_sel; // @[util.scala:505:22] reg [2:0] uops_12_op2_sel; // @[util.scala:505:22] reg uops_12_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_12_fp_ctrl_wen; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_12_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_12_fp_ctrl_toint; // @[util.scala:505:22] reg uops_12_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_12_fp_ctrl_fma; // @[util.scala:505:22] reg uops_12_fp_ctrl_div; // @[util.scala:505:22] reg uops_12_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_12_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_12_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_12_rob_idx; // @[util.scala:505:22] reg [3:0] uops_12_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_12_stq_idx; // @[util.scala:505:22] reg [1:0] uops_12_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_12_pdst; // @[util.scala:505:22] reg [5:0] uops_12_prs1; // @[util.scala:505:22] reg [5:0] uops_12_prs2; // @[util.scala:505:22] reg [5:0] uops_12_prs3; // @[util.scala:505:22] reg [3:0] uops_12_ppred; // @[util.scala:505:22] reg uops_12_prs1_busy; // @[util.scala:505:22] reg uops_12_prs2_busy; // @[util.scala:505:22] reg uops_12_prs3_busy; // @[util.scala:505:22] reg uops_12_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_12_stale_pdst; // @[util.scala:505:22] reg uops_12_exception; // @[util.scala:505:22] reg [63:0] uops_12_exc_cause; // @[util.scala:505:22] reg [4:0] uops_12_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_12_mem_size; // @[util.scala:505:22] reg uops_12_mem_signed; // @[util.scala:505:22] reg uops_12_uses_ldq; // @[util.scala:505:22] reg uops_12_uses_stq; // @[util.scala:505:22] reg uops_12_is_unique; // @[util.scala:505:22] reg uops_12_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_12_csr_cmd; // @[util.scala:505:22] reg uops_12_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_12_ldst; // @[util.scala:505:22] reg [5:0] uops_12_lrs1; // @[util.scala:505:22] reg [5:0] uops_12_lrs2; // @[util.scala:505:22] reg [5:0] uops_12_lrs3; // @[util.scala:505:22] reg [1:0] uops_12_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:505:22] reg uops_12_frs3_en; // @[util.scala:505:22] reg uops_12_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_12_fcn_op; // @[util.scala:505:22] reg uops_12_fp_val; // @[util.scala:505:22] reg [2:0] uops_12_fp_rm; // @[util.scala:505:22] reg [1:0] uops_12_fp_typ; // @[util.scala:505:22] reg uops_12_xcpt_pf_if; // @[util.scala:505:22] reg uops_12_xcpt_ae_if; // @[util.scala:505:22] reg uops_12_xcpt_ma_if; // @[util.scala:505:22] reg uops_12_bp_debug_if; // @[util.scala:505:22] reg uops_12_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_12_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_12_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_13_inst; // @[util.scala:505:22] reg [31:0] uops_13_debug_inst; // @[util.scala:505:22] reg uops_13_is_rvc; // @[util.scala:505:22] reg [33:0] uops_13_debug_pc; // @[util.scala:505:22] reg uops_13_iq_type_0; // @[util.scala:505:22] reg uops_13_iq_type_1; // @[util.scala:505:22] reg uops_13_iq_type_2; // @[util.scala:505:22] reg uops_13_iq_type_3; // @[util.scala:505:22] reg uops_13_fu_code_0; // @[util.scala:505:22] reg uops_13_fu_code_1; // @[util.scala:505:22] reg uops_13_fu_code_2; // @[util.scala:505:22] reg uops_13_fu_code_3; // @[util.scala:505:22] reg uops_13_fu_code_4; // @[util.scala:505:22] reg uops_13_fu_code_5; // @[util.scala:505:22] reg uops_13_fu_code_6; // @[util.scala:505:22] reg uops_13_fu_code_7; // @[util.scala:505:22] reg uops_13_fu_code_8; // @[util.scala:505:22] reg uops_13_fu_code_9; // @[util.scala:505:22] reg uops_13_iw_issued; // @[util.scala:505:22] reg uops_13_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_13_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_13_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_13_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_13_br_mask; // @[util.scala:505:22] wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_13_br_tag; // @[util.scala:505:22] reg [3:0] uops_13_br_type; // @[util.scala:505:22] reg uops_13_is_sfb; // @[util.scala:505:22] reg uops_13_is_fence; // @[util.scala:505:22] reg uops_13_is_fencei; // @[util.scala:505:22] reg uops_13_is_sfence; // @[util.scala:505:22] reg uops_13_is_amo; // @[util.scala:505:22] reg uops_13_is_eret; // @[util.scala:505:22] reg uops_13_is_sys_pc2epc; // @[util.scala:505:22] reg uops_13_is_rocc; // @[util.scala:505:22] reg uops_13_is_mov; // @[util.scala:505:22] reg [3:0] uops_13_ftq_idx; // @[util.scala:505:22] reg uops_13_edge_inst; // @[util.scala:505:22] reg [5:0] uops_13_pc_lob; // @[util.scala:505:22] reg uops_13_taken; // @[util.scala:505:22] reg uops_13_imm_rename; // @[util.scala:505:22] reg [2:0] uops_13_imm_sel; // @[util.scala:505:22] reg [4:0] uops_13_pimm; // @[util.scala:505:22] reg [19:0] uops_13_imm_packed; // @[util.scala:505:22] reg [1:0] uops_13_op1_sel; // @[util.scala:505:22] reg [2:0] uops_13_op2_sel; // @[util.scala:505:22] reg uops_13_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_13_fp_ctrl_wen; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_13_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_13_fp_ctrl_toint; // @[util.scala:505:22] reg uops_13_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_13_fp_ctrl_fma; // @[util.scala:505:22] reg uops_13_fp_ctrl_div; // @[util.scala:505:22] reg uops_13_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_13_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_13_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_13_rob_idx; // @[util.scala:505:22] reg [3:0] uops_13_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_13_stq_idx; // @[util.scala:505:22] reg [1:0] uops_13_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_13_pdst; // @[util.scala:505:22] reg [5:0] uops_13_prs1; // @[util.scala:505:22] reg [5:0] uops_13_prs2; // @[util.scala:505:22] reg [5:0] uops_13_prs3; // @[util.scala:505:22] reg [3:0] uops_13_ppred; // @[util.scala:505:22] reg uops_13_prs1_busy; // @[util.scala:505:22] reg uops_13_prs2_busy; // @[util.scala:505:22] reg uops_13_prs3_busy; // @[util.scala:505:22] reg uops_13_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_13_stale_pdst; // @[util.scala:505:22] reg uops_13_exception; // @[util.scala:505:22] reg [63:0] uops_13_exc_cause; // @[util.scala:505:22] reg [4:0] uops_13_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_13_mem_size; // @[util.scala:505:22] reg uops_13_mem_signed; // @[util.scala:505:22] reg uops_13_uses_ldq; // @[util.scala:505:22] reg uops_13_uses_stq; // @[util.scala:505:22] reg uops_13_is_unique; // @[util.scala:505:22] reg uops_13_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_13_csr_cmd; // @[util.scala:505:22] reg uops_13_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_13_ldst; // @[util.scala:505:22] reg [5:0] uops_13_lrs1; // @[util.scala:505:22] reg [5:0] uops_13_lrs2; // @[util.scala:505:22] reg [5:0] uops_13_lrs3; // @[util.scala:505:22] reg [1:0] uops_13_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:505:22] reg uops_13_frs3_en; // @[util.scala:505:22] reg uops_13_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_13_fcn_op; // @[util.scala:505:22] reg uops_13_fp_val; // @[util.scala:505:22] reg [2:0] uops_13_fp_rm; // @[util.scala:505:22] reg [1:0] uops_13_fp_typ; // @[util.scala:505:22] reg uops_13_xcpt_pf_if; // @[util.scala:505:22] reg uops_13_xcpt_ae_if; // @[util.scala:505:22] reg uops_13_xcpt_ma_if; // @[util.scala:505:22] reg uops_13_bp_debug_if; // @[util.scala:505:22] reg uops_13_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_13_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_13_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_14_inst; // @[util.scala:505:22] reg [31:0] uops_14_debug_inst; // @[util.scala:505:22] reg uops_14_is_rvc; // @[util.scala:505:22] reg [33:0] uops_14_debug_pc; // @[util.scala:505:22] reg uops_14_iq_type_0; // @[util.scala:505:22] reg uops_14_iq_type_1; // @[util.scala:505:22] reg uops_14_iq_type_2; // @[util.scala:505:22] reg uops_14_iq_type_3; // @[util.scala:505:22] reg uops_14_fu_code_0; // @[util.scala:505:22] reg uops_14_fu_code_1; // @[util.scala:505:22] reg uops_14_fu_code_2; // @[util.scala:505:22] reg uops_14_fu_code_3; // @[util.scala:505:22] reg uops_14_fu_code_4; // @[util.scala:505:22] reg uops_14_fu_code_5; // @[util.scala:505:22] reg uops_14_fu_code_6; // @[util.scala:505:22] reg uops_14_fu_code_7; // @[util.scala:505:22] reg uops_14_fu_code_8; // @[util.scala:505:22] reg uops_14_fu_code_9; // @[util.scala:505:22] reg uops_14_iw_issued; // @[util.scala:505:22] reg uops_14_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_14_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_14_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_14_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_14_br_mask; // @[util.scala:505:22] wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_14_br_tag; // @[util.scala:505:22] reg [3:0] uops_14_br_type; // @[util.scala:505:22] reg uops_14_is_sfb; // @[util.scala:505:22] reg uops_14_is_fence; // @[util.scala:505:22] reg uops_14_is_fencei; // @[util.scala:505:22] reg uops_14_is_sfence; // @[util.scala:505:22] reg uops_14_is_amo; // @[util.scala:505:22] reg uops_14_is_eret; // @[util.scala:505:22] reg uops_14_is_sys_pc2epc; // @[util.scala:505:22] reg uops_14_is_rocc; // @[util.scala:505:22] reg uops_14_is_mov; // @[util.scala:505:22] reg [3:0] uops_14_ftq_idx; // @[util.scala:505:22] reg uops_14_edge_inst; // @[util.scala:505:22] reg [5:0] uops_14_pc_lob; // @[util.scala:505:22] reg uops_14_taken; // @[util.scala:505:22] reg uops_14_imm_rename; // @[util.scala:505:22] reg [2:0] uops_14_imm_sel; // @[util.scala:505:22] reg [4:0] uops_14_pimm; // @[util.scala:505:22] reg [19:0] uops_14_imm_packed; // @[util.scala:505:22] reg [1:0] uops_14_op1_sel; // @[util.scala:505:22] reg [2:0] uops_14_op2_sel; // @[util.scala:505:22] reg uops_14_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_14_fp_ctrl_wen; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_14_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_14_fp_ctrl_toint; // @[util.scala:505:22] reg uops_14_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_14_fp_ctrl_fma; // @[util.scala:505:22] reg uops_14_fp_ctrl_div; // @[util.scala:505:22] reg uops_14_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_14_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_14_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_14_rob_idx; // @[util.scala:505:22] reg [3:0] uops_14_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_14_stq_idx; // @[util.scala:505:22] reg [1:0] uops_14_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_14_pdst; // @[util.scala:505:22] reg [5:0] uops_14_prs1; // @[util.scala:505:22] reg [5:0] uops_14_prs2; // @[util.scala:505:22] reg [5:0] uops_14_prs3; // @[util.scala:505:22] reg [3:0] uops_14_ppred; // @[util.scala:505:22] reg uops_14_prs1_busy; // @[util.scala:505:22] reg uops_14_prs2_busy; // @[util.scala:505:22] reg uops_14_prs3_busy; // @[util.scala:505:22] reg uops_14_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_14_stale_pdst; // @[util.scala:505:22] reg uops_14_exception; // @[util.scala:505:22] reg [63:0] uops_14_exc_cause; // @[util.scala:505:22] reg [4:0] uops_14_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_14_mem_size; // @[util.scala:505:22] reg uops_14_mem_signed; // @[util.scala:505:22] reg uops_14_uses_ldq; // @[util.scala:505:22] reg uops_14_uses_stq; // @[util.scala:505:22] reg uops_14_is_unique; // @[util.scala:505:22] reg uops_14_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_14_csr_cmd; // @[util.scala:505:22] reg uops_14_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_14_ldst; // @[util.scala:505:22] reg [5:0] uops_14_lrs1; // @[util.scala:505:22] reg [5:0] uops_14_lrs2; // @[util.scala:505:22] reg [5:0] uops_14_lrs3; // @[util.scala:505:22] reg [1:0] uops_14_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:505:22] reg uops_14_frs3_en; // @[util.scala:505:22] reg uops_14_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_14_fcn_op; // @[util.scala:505:22] reg uops_14_fp_val; // @[util.scala:505:22] reg [2:0] uops_14_fp_rm; // @[util.scala:505:22] reg [1:0] uops_14_fp_typ; // @[util.scala:505:22] reg uops_14_xcpt_pf_if; // @[util.scala:505:22] reg uops_14_xcpt_ae_if; // @[util.scala:505:22] reg uops_14_xcpt_ma_if; // @[util.scala:505:22] reg uops_14_bp_debug_if; // @[util.scala:505:22] reg uops_14_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_14_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_14_debug_tsrc; // @[util.scala:505:22] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:509:29] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :512:27] wire full = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _do_enq_T_5 = _do_enq_T; // @[Decoupled.scala:51:35] wire _do_enq_T_8 = _do_enq_T_5; // @[util.scala:514:{39,99}] wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}] wire [15:0] _GEN = {{valids_0}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44] wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_0; // @[util.scala:515:44] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:458:7, :515:71] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}] wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}] wire _valids_0_T_7 = _valids_0_T_4; // @[util.scala:520:{31,80}] wire _valids_1_T_7 = _valids_1_T_4; // @[util.scala:520:{31,80}] wire _valids_2_T_7 = _valids_2_T_4; // @[util.scala:520:{31,80}] wire _valids_3_T_7 = _valids_3_T_4; // @[util.scala:520:{31,80}] wire _valids_4_T_7 = _valids_4_T_4; // @[util.scala:520:{31,80}] wire _valids_5_T_7 = _valids_5_T_4; // @[util.scala:520:{31,80}] wire _valids_6_T_7 = _valids_6_T_4; // @[util.scala:520:{31,80}] wire _valids_7_T_7 = _valids_7_T_4; // @[util.scala:520:{31,80}] wire _valids_8_T_7 = _valids_8_T_4; // @[util.scala:520:{31,80}] wire _valids_9_T_7 = _valids_9_T_4; // @[util.scala:520:{31,80}] wire _valids_10_T_7 = _valids_10_T_4; // @[util.scala:520:{31,80}] wire _valids_11_T_7 = _valids_11_T_4; // @[util.scala:520:{31,80}] wire _valids_12_T_7 = _valids_12_T_4; // @[util.scala:520:{31,80}] wire _valids_13_T_7 = _valids_13_T_4; // @[util.scala:520:{31,80}] wire _valids_14_T_7 = _valids_14_T_4; // @[util.scala:520:{31,80}] wire wrap = enq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_1 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = deq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:458:7, :545:19] assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:458:7, :545:19] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_way_en_0 = out_way_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:458:7, :545:19] wire [15:0][31:0] _GEN_3 = {{uops_0_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_inst = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_4 = {{uops_0_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_5 = {{uops_0_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rvc = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][33:0] _GEN_6 = {{uops_0_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_pc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_0_iq_type_0}, {uops_14_iq_type_0}, {uops_13_iq_type_0}, {uops_12_iq_type_0}, {uops_11_iq_type_0}, {uops_10_iq_type_0}, {uops_9_iq_type_0}, {uops_8_iq_type_0}, {uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_0 = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_8 = {{uops_0_iq_type_1}, {uops_14_iq_type_1}, {uops_13_iq_type_1}, {uops_12_iq_type_1}, {uops_11_iq_type_1}, {uops_10_iq_type_1}, {uops_9_iq_type_1}, {uops_8_iq_type_1}, {uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_1 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_9 = {{uops_0_iq_type_2}, {uops_14_iq_type_2}, {uops_13_iq_type_2}, {uops_12_iq_type_2}, {uops_11_iq_type_2}, {uops_10_iq_type_2}, {uops_9_iq_type_2}, {uops_8_iq_type_2}, {uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_2 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_10 = {{uops_0_iq_type_3}, {uops_14_iq_type_3}, {uops_13_iq_type_3}, {uops_12_iq_type_3}, {uops_11_iq_type_3}, {uops_10_iq_type_3}, {uops_9_iq_type_3}, {uops_8_iq_type_3}, {uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_3 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_11 = {{uops_0_fu_code_0}, {uops_14_fu_code_0}, {uops_13_fu_code_0}, {uops_12_fu_code_0}, {uops_11_fu_code_0}, {uops_10_fu_code_0}, {uops_9_fu_code_0}, {uops_8_fu_code_0}, {uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_0 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_12 = {{uops_0_fu_code_1}, {uops_14_fu_code_1}, {uops_13_fu_code_1}, {uops_12_fu_code_1}, {uops_11_fu_code_1}, {uops_10_fu_code_1}, {uops_9_fu_code_1}, {uops_8_fu_code_1}, {uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_1 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_13 = {{uops_0_fu_code_2}, {uops_14_fu_code_2}, {uops_13_fu_code_2}, {uops_12_fu_code_2}, {uops_11_fu_code_2}, {uops_10_fu_code_2}, {uops_9_fu_code_2}, {uops_8_fu_code_2}, {uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_2 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_14 = {{uops_0_fu_code_3}, {uops_14_fu_code_3}, {uops_13_fu_code_3}, {uops_12_fu_code_3}, {uops_11_fu_code_3}, {uops_10_fu_code_3}, {uops_9_fu_code_3}, {uops_8_fu_code_3}, {uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_3 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_15 = {{uops_0_fu_code_4}, {uops_14_fu_code_4}, {uops_13_fu_code_4}, {uops_12_fu_code_4}, {uops_11_fu_code_4}, {uops_10_fu_code_4}, {uops_9_fu_code_4}, {uops_8_fu_code_4}, {uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_4 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_0_fu_code_5}, {uops_14_fu_code_5}, {uops_13_fu_code_5}, {uops_12_fu_code_5}, {uops_11_fu_code_5}, {uops_10_fu_code_5}, {uops_9_fu_code_5}, {uops_8_fu_code_5}, {uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_5 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_17 = {{uops_0_fu_code_6}, {uops_14_fu_code_6}, {uops_13_fu_code_6}, {uops_12_fu_code_6}, {uops_11_fu_code_6}, {uops_10_fu_code_6}, {uops_9_fu_code_6}, {uops_8_fu_code_6}, {uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_6 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_0_fu_code_7}, {uops_14_fu_code_7}, {uops_13_fu_code_7}, {uops_12_fu_code_7}, {uops_11_fu_code_7}, {uops_10_fu_code_7}, {uops_9_fu_code_7}, {uops_8_fu_code_7}, {uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_7 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_0_fu_code_8}, {uops_14_fu_code_8}, {uops_13_fu_code_8}, {uops_12_fu_code_8}, {uops_11_fu_code_8}, {uops_10_fu_code_8}, {uops_9_fu_code_8}, {uops_8_fu_code_8}, {uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_8 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_0_fu_code_9}, {uops_14_fu_code_9}, {uops_13_fu_code_9}, {uops_12_fu_code_9}, {uops_11_fu_code_9}, {uops_10_fu_code_9}, {uops_9_fu_code_9}, {uops_8_fu_code_9}, {uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_9 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_21 = {{uops_0_iw_issued}, {uops_14_iw_issued}, {uops_13_iw_issued}, {uops_12_iw_issued}, {uops_11_iw_issued}, {uops_10_iw_issued}, {uops_9_iw_issued}, {uops_8_iw_issued}, {uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_0_iw_issued_partial_agen}, {uops_14_iw_issued_partial_agen}, {uops_13_iw_issued_partial_agen}, {uops_12_iw_issued_partial_agen}, {uops_11_iw_issued_partial_agen}, {uops_10_iw_issued_partial_agen}, {uops_9_iw_issued_partial_agen}, {uops_8_iw_issued_partial_agen}, {uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_agen = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_0_iw_issued_partial_dgen}, {uops_14_iw_issued_partial_dgen}, {uops_13_iw_issued_partial_dgen}, {uops_12_iw_issued_partial_dgen}, {uops_11_iw_issued_partial_dgen}, {uops_10_iw_issued_partial_dgen}, {uops_9_iw_issued_partial_dgen}, {uops_8_iw_issued_partial_dgen}, {uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_dgen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_0_iw_p1_speculative_child}, {uops_14_iw_p1_speculative_child}, {uops_13_iw_p1_speculative_child}, {uops_12_iw_p1_speculative_child}, {uops_11_iw_p1_speculative_child}, {uops_10_iw_p1_speculative_child}, {uops_9_iw_p1_speculative_child}, {uops_8_iw_p1_speculative_child}, {uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_speculative_child = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_0_iw_p2_speculative_child}, {uops_14_iw_p2_speculative_child}, {uops_13_iw_p2_speculative_child}, {uops_12_iw_p2_speculative_child}, {uops_11_iw_p2_speculative_child}, {uops_10_iw_p2_speculative_child}, {uops_9_iw_p2_speculative_child}, {uops_8_iw_p2_speculative_child}, {uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_0_iw_p1_bypass_hint}, {uops_14_iw_p1_bypass_hint}, {uops_13_iw_p1_bypass_hint}, {uops_12_iw_p1_bypass_hint}, {uops_11_iw_p1_bypass_hint}, {uops_10_iw_p1_bypass_hint}, {uops_9_iw_p1_bypass_hint}, {uops_8_iw_p1_bypass_hint}, {uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_bypass_hint = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_0_iw_p2_bypass_hint}, {uops_14_iw_p2_bypass_hint}, {uops_13_iw_p2_bypass_hint}, {uops_12_iw_p2_bypass_hint}, {uops_11_iw_p2_bypass_hint}, {uops_10_iw_p2_bypass_hint}, {uops_9_iw_p2_bypass_hint}, {uops_8_iw_p2_bypass_hint}, {uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_28 = {{uops_0_iw_p3_bypass_hint}, {uops_14_iw_p3_bypass_hint}, {uops_13_iw_p3_bypass_hint}, {uops_12_iw_p3_bypass_hint}, {uops_11_iw_p3_bypass_hint}, {uops_10_iw_p3_bypass_hint}, {uops_9_iw_p3_bypass_hint}, {uops_8_iw_p3_bypass_hint}, {uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p3_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_29 = {{uops_0_dis_col_sel}, {uops_14_dis_col_sel}, {uops_13_dis_col_sel}, {uops_12_dis_col_sel}, {uops_11_dis_col_sel}, {uops_10_dis_col_sel}, {uops_9_dis_col_sel}, {uops_8_dis_col_sel}, {uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_dis_col_sel = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_30 = {{uops_0_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21] assign out_uop_br_mask = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_31 = {{uops_0_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21] assign out_uop_br_tag = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_32 = {{uops_0_br_type}, {uops_14_br_type}, {uops_13_br_type}, {uops_12_br_type}, {uops_11_br_type}, {uops_10_br_type}, {uops_9_br_type}, {uops_8_br_type}, {uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21] assign out_uop_br_type = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_0_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfb = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_34 = {{uops_0_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fence = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_35 = {{uops_0_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fencei = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_36 = {{uops_0_is_sfence}, {uops_14_is_sfence}, {uops_13_is_sfence}, {uops_12_is_sfence}, {uops_11_is_sfence}, {uops_10_is_sfence}, {uops_9_is_sfence}, {uops_8_is_sfence}, {uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfence = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_37 = {{uops_0_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21] assign out_uop_is_amo = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_38 = {{uops_0_is_eret}, {uops_14_is_eret}, {uops_13_is_eret}, {uops_12_is_eret}, {uops_11_is_eret}, {uops_10_is_eret}, {uops_9_is_eret}, {uops_8_is_eret}, {uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21] assign out_uop_is_eret = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_39 = {{uops_0_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sys_pc2epc = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_40 = {{uops_0_is_rocc}, {uops_14_is_rocc}, {uops_13_is_rocc}, {uops_12_is_rocc}, {uops_11_is_rocc}, {uops_10_is_rocc}, {uops_9_is_rocc}, {uops_8_is_rocc}, {uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rocc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_41 = {{uops_0_is_mov}, {uops_14_is_mov}, {uops_13_is_mov}, {uops_12_is_mov}, {uops_11_is_mov}, {uops_10_is_mov}, {uops_9_is_mov}, {uops_8_is_mov}, {uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21] assign out_uop_is_mov = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_42 = {{uops_0_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ftq_idx = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_43 = {{uops_0_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_edge_inst = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_44 = {{uops_0_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21] assign out_uop_pc_lob = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_0_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21] assign out_uop_taken = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_0_imm_rename}, {uops_14_imm_rename}, {uops_13_imm_rename}, {uops_12_imm_rename}, {uops_11_imm_rename}, {uops_10_imm_rename}, {uops_9_imm_rename}, {uops_8_imm_rename}, {uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_rename = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_47 = {{uops_0_imm_sel}, {uops_14_imm_sel}, {uops_13_imm_sel}, {uops_12_imm_sel}, {uops_11_imm_sel}, {uops_10_imm_sel}, {uops_9_imm_sel}, {uops_8_imm_sel}, {uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_sel = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_48 = {{uops_0_pimm}, {uops_14_pimm}, {uops_13_pimm}, {uops_12_pimm}, {uops_11_pimm}, {uops_10_pimm}, {uops_9_pimm}, {uops_8_pimm}, {uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21] assign out_uop_pimm = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_49 = {{uops_0_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_packed = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_50 = {{uops_0_op1_sel}, {uops_14_op1_sel}, {uops_13_op1_sel}, {uops_12_op1_sel}, {uops_11_op1_sel}, {uops_10_op1_sel}, {uops_9_op1_sel}, {uops_8_op1_sel}, {uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op1_sel = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_51 = {{uops_0_op2_sel}, {uops_14_op2_sel}, {uops_13_op2_sel}, {uops_12_op2_sel}, {uops_11_op2_sel}, {uops_10_op2_sel}, {uops_9_op2_sel}, {uops_8_op2_sel}, {uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op2_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_0_fp_ctrl_ldst}, {uops_14_fp_ctrl_ldst}, {uops_13_fp_ctrl_ldst}, {uops_12_fp_ctrl_ldst}, {uops_11_fp_ctrl_ldst}, {uops_10_fp_ctrl_ldst}, {uops_9_fp_ctrl_ldst}, {uops_8_fp_ctrl_ldst}, {uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ldst = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_53 = {{uops_0_fp_ctrl_wen}, {uops_14_fp_ctrl_wen}, {uops_13_fp_ctrl_wen}, {uops_12_fp_ctrl_wen}, {uops_11_fp_ctrl_wen}, {uops_10_fp_ctrl_wen}, {uops_9_fp_ctrl_wen}, {uops_8_fp_ctrl_wen}, {uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wen = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_54 = {{uops_0_fp_ctrl_ren1}, {uops_14_fp_ctrl_ren1}, {uops_13_fp_ctrl_ren1}, {uops_12_fp_ctrl_ren1}, {uops_11_fp_ctrl_ren1}, {uops_10_fp_ctrl_ren1}, {uops_9_fp_ctrl_ren1}, {uops_8_fp_ctrl_ren1}, {uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren1 = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_0_fp_ctrl_ren2}, {uops_14_fp_ctrl_ren2}, {uops_13_fp_ctrl_ren2}, {uops_12_fp_ctrl_ren2}, {uops_11_fp_ctrl_ren2}, {uops_10_fp_ctrl_ren2}, {uops_9_fp_ctrl_ren2}, {uops_8_fp_ctrl_ren2}, {uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren2 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_0_fp_ctrl_ren3}, {uops_14_fp_ctrl_ren3}, {uops_13_fp_ctrl_ren3}, {uops_12_fp_ctrl_ren3}, {uops_11_fp_ctrl_ren3}, {uops_10_fp_ctrl_ren3}, {uops_9_fp_ctrl_ren3}, {uops_8_fp_ctrl_ren3}, {uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren3 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_0_fp_ctrl_swap12}, {uops_14_fp_ctrl_swap12}, {uops_13_fp_ctrl_swap12}, {uops_12_fp_ctrl_swap12}, {uops_11_fp_ctrl_swap12}, {uops_10_fp_ctrl_swap12}, {uops_9_fp_ctrl_swap12}, {uops_8_fp_ctrl_swap12}, {uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap12 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_0_fp_ctrl_swap23}, {uops_14_fp_ctrl_swap23}, {uops_13_fp_ctrl_swap23}, {uops_12_fp_ctrl_swap23}, {uops_11_fp_ctrl_swap23}, {uops_10_fp_ctrl_swap23}, {uops_9_fp_ctrl_swap23}, {uops_8_fp_ctrl_swap23}, {uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap23 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_59 = {{uops_0_fp_ctrl_typeTagIn}, {uops_14_fp_ctrl_typeTagIn}, {uops_13_fp_ctrl_typeTagIn}, {uops_12_fp_ctrl_typeTagIn}, {uops_11_fp_ctrl_typeTagIn}, {uops_10_fp_ctrl_typeTagIn}, {uops_9_fp_ctrl_typeTagIn}, {uops_8_fp_ctrl_typeTagIn}, {uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagIn = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_60 = {{uops_0_fp_ctrl_typeTagOut}, {uops_14_fp_ctrl_typeTagOut}, {uops_13_fp_ctrl_typeTagOut}, {uops_12_fp_ctrl_typeTagOut}, {uops_11_fp_ctrl_typeTagOut}, {uops_10_fp_ctrl_typeTagOut}, {uops_9_fp_ctrl_typeTagOut}, {uops_8_fp_ctrl_typeTagOut}, {uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagOut = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_0_fp_ctrl_fromint}, {uops_14_fp_ctrl_fromint}, {uops_13_fp_ctrl_fromint}, {uops_12_fp_ctrl_fromint}, {uops_11_fp_ctrl_fromint}, {uops_10_fp_ctrl_fromint}, {uops_9_fp_ctrl_fromint}, {uops_8_fp_ctrl_fromint}, {uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fromint = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_0_fp_ctrl_toint}, {uops_14_fp_ctrl_toint}, {uops_13_fp_ctrl_toint}, {uops_12_fp_ctrl_toint}, {uops_11_fp_ctrl_toint}, {uops_10_fp_ctrl_toint}, {uops_9_fp_ctrl_toint}, {uops_8_fp_ctrl_toint}, {uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_toint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_0_fp_ctrl_fastpipe}, {uops_14_fp_ctrl_fastpipe}, {uops_13_fp_ctrl_fastpipe}, {uops_12_fp_ctrl_fastpipe}, {uops_11_fp_ctrl_fastpipe}, {uops_10_fp_ctrl_fastpipe}, {uops_9_fp_ctrl_fastpipe}, {uops_8_fp_ctrl_fastpipe}, {uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fastpipe = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_0_fp_ctrl_fma}, {uops_14_fp_ctrl_fma}, {uops_13_fp_ctrl_fma}, {uops_12_fp_ctrl_fma}, {uops_11_fp_ctrl_fma}, {uops_10_fp_ctrl_fma}, {uops_9_fp_ctrl_fma}, {uops_8_fp_ctrl_fma}, {uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fma = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_65 = {{uops_0_fp_ctrl_div}, {uops_14_fp_ctrl_div}, {uops_13_fp_ctrl_div}, {uops_12_fp_ctrl_div}, {uops_11_fp_ctrl_div}, {uops_10_fp_ctrl_div}, {uops_9_fp_ctrl_div}, {uops_8_fp_ctrl_div}, {uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_div = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_66 = {{uops_0_fp_ctrl_sqrt}, {uops_14_fp_ctrl_sqrt}, {uops_13_fp_ctrl_sqrt}, {uops_12_fp_ctrl_sqrt}, {uops_11_fp_ctrl_sqrt}, {uops_10_fp_ctrl_sqrt}, {uops_9_fp_ctrl_sqrt}, {uops_8_fp_ctrl_sqrt}, {uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_sqrt = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_67 = {{uops_0_fp_ctrl_wflags}, {uops_14_fp_ctrl_wflags}, {uops_13_fp_ctrl_wflags}, {uops_12_fp_ctrl_wflags}, {uops_11_fp_ctrl_wflags}, {uops_10_fp_ctrl_wflags}, {uops_9_fp_ctrl_wflags}, {uops_8_fp_ctrl_wflags}, {uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wflags = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_68 = {{uops_0_fp_ctrl_vec}, {uops_14_fp_ctrl_vec}, {uops_13_fp_ctrl_vec}, {uops_12_fp_ctrl_vec}, {uops_11_fp_ctrl_vec}, {uops_10_fp_ctrl_vec}, {uops_9_fp_ctrl_vec}, {uops_8_fp_ctrl_vec}, {uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_vec = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_69 = {{uops_0_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rob_idx = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_70 = {{uops_0_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ldq_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_71 = {{uops_0_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_stq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_0_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rxq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_73 = {{uops_0_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_pdst = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_74 = {{uops_0_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1 = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_75 = {{uops_0_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_76 = {{uops_0_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_77 = {{uops_0_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_0_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1_busy = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_0_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_0_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_81 = {{uops_0_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_82 = {{uops_0_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_stale_pdst = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_83 = {{uops_0_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21] assign out_uop_exception = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_84 = {{uops_0_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21] assign out_uop_exc_cause = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_85 = {{uops_0_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_cmd = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_86 = {{uops_0_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_size = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_87 = {{uops_0_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_signed = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_88 = {{uops_0_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_ldq = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_89 = {{uops_0_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_stq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_90 = {{uops_0_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21] assign out_uop_is_unique = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_91 = {{uops_0_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21] assign out_uop_flush_on_commit = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_92 = {{uops_0_csr_cmd}, {uops_14_csr_cmd}, {uops_13_csr_cmd}, {uops_12_csr_cmd}, {uops_11_csr_cmd}, {uops_10_csr_cmd}, {uops_9_csr_cmd}, {uops_8_csr_cmd}, {uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_csr_cmd = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_93 = {{uops_0_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst_is_rs1 = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_94 = {{uops_0_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_95 = {{uops_0_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1 = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_96 = {{uops_0_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_97 = {{uops_0_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs3 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_98 = {{uops_0_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_dst_rtype = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_99 = {{uops_0_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_100 = {{uops_0_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_101 = {{uops_0_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21] assign out_uop_frs3_en = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_102 = {{uops_0_fcn_dw}, {uops_14_fcn_dw}, {uops_13_fcn_dw}, {uops_12_fcn_dw}, {uops_11_fcn_dw}, {uops_10_fcn_dw}, {uops_9_fcn_dw}, {uops_8_fcn_dw}, {uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_dw = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_103 = {{uops_0_fcn_op}, {uops_14_fcn_op}, {uops_13_fcn_op}, {uops_12_fcn_op}, {uops_11_fcn_op}, {uops_10_fcn_op}, {uops_9_fcn_op}, {uops_8_fcn_op}, {uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_op = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_104 = {{uops_0_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_val = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_105 = {{uops_0_fp_rm}, {uops_14_fp_rm}, {uops_13_fp_rm}, {uops_12_fp_rm}, {uops_11_fp_rm}, {uops_10_fp_rm}, {uops_9_fp_rm}, {uops_8_fp_rm}, {uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_rm = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_106 = {{uops_0_fp_typ}, {uops_14_fp_typ}, {uops_13_fp_typ}, {uops_12_fp_typ}, {uops_11_fp_typ}, {uops_10_fp_typ}, {uops_9_fp_typ}, {uops_8_fp_typ}, {uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_typ = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_107 = {{uops_0_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_pf_if = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_108 = {{uops_0_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ae_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_109 = {{uops_0_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ma_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_110 = {{uops_0_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_debug_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_111 = {{uops_0_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_xcpt_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_112 = {{uops_0_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_fsrc = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_113 = {{uops_0_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_tsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:458:7, :515:71, :548:32] assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:515:44, :548:{32,42}] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42] wire [4:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:551:34] wire [3:0] _io_count_T = {4{maybe_full}}; // @[util.scala:509:29, :557:12] wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40] wire [4:0] _io_count_T_2 = {1'h0, ptr_diff} + 5'hF; // @[util.scala:551:34, :560:26] wire [3:0] _io_count_T_3 = _io_count_T_2[3:0]; // @[util.scala:560:26] wire [3:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:551:34, :559:{12,27}, :560:26] assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:511:35, :556:22, :557:12, :559:12] assign io_count_0 = _io_count_T_5; // @[util.scala:458:7, :556:22] wire _GEN_114 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_115 = do_enq & _GEN_114; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_116 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_117 = do_enq & _GEN_116; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_118 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_119 = do_enq & _GEN_118; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_120 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_121 = do_enq & _GEN_120; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_122 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_123 = do_enq & _GEN_122; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_124 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_125 = do_enq & _GEN_124; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_126 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_127 = do_enq & _GEN_126; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_128 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_129 = do_enq & _GEN_128; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_130 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_131 = do_enq & _GEN_130; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_132 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_133 = do_enq & _GEN_132; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_134 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_135 = do_enq & _GEN_134; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_136 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_137 = do_enq & _GEN_136; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_138 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_139 = do_enq & _GEN_138; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_140 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_141 = do_enq & _GEN_140; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_142 = do_enq & wrap; // @[Counter.scala:73:24] always @(posedge clock) begin // @[util.scala:458:7] if (reset) begin // @[util.scala:458:7] valids_0 <= 1'h0; // @[util.scala:504:26] valids_1 <= 1'h0; // @[util.scala:504:26] valids_2 <= 1'h0; // @[util.scala:504:26] valids_3 <= 1'h0; // @[util.scala:504:26] valids_4 <= 1'h0; // @[util.scala:504:26] valids_5 <= 1'h0; // @[util.scala:504:26] valids_6 <= 1'h0; // @[util.scala:504:26] valids_7 <= 1'h0; // @[util.scala:504:26] valids_8 <= 1'h0; // @[util.scala:504:26] valids_9 <= 1'h0; // @[util.scala:504:26] valids_10 <= 1'h0; // @[util.scala:504:26] valids_11 <= 1'h0; // @[util.scala:504:26] valids_12 <= 1'h0; // @[util.scala:504:26] valids_13 <= 1'h0; // @[util.scala:504:26] valids_14 <= 1'h0; // @[util.scala:504:26] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:509:29] end else begin // @[util.scala:458:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_115 | _valids_0_T_7); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_117 | _valids_1_T_7); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_119 | _valids_2_T_7); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_121 | _valids_3_T_7); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_123 | _valids_4_T_7); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_125 | _valids_5_T_7); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_127 | _valids_6_T_7); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_129 | _valids_7_T_7); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_131 | _valids_8_T_7); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_133 | _valids_9_T_7); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_135 | _valids_10_T_7); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_137 | _valids_11_T_7); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_139 | _valids_12_T_7); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_141 | _valids_13_T_7); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & wrap_1) & (_GEN_142 | _valids_14_T_7); // @[Counter.scala:73:24] if (do_enq) // @[util.scala:514:26] enq_ptr_value <= wrap ? 4'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (do_deq) // @[util.scala:515:26] deq_ptr_value <= wrap_1 ? 4'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18] maybe_full <= do_enq; // @[util.scala:509:29, :514:26] end if (_GEN_115) begin // @[util.scala:520:18, :526:19, :528:35] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_114) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_0) // @[util.scala:504:26] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_117) begin // @[util.scala:520:18, :526:19, :528:35] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_116) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_1) // @[util.scala:504:26] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_119) begin // @[util.scala:520:18, :526:19, :528:35] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_118) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_2) // @[util.scala:504:26] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_120) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_3) // @[util.scala:504:26] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_123) begin // @[util.scala:520:18, :526:19, :528:35] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_122) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_4) // @[util.scala:504:26] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_125) begin // @[util.scala:520:18, :526:19, :528:35] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_124) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_5) // @[util.scala:504:26] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_127) begin // @[util.scala:520:18, :526:19, :528:35] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_126) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_6) // @[util.scala:504:26] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_128) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_7) // @[util.scala:504:26] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_131) begin // @[util.scala:520:18, :526:19, :528:35] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_8_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_8_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_8_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_8_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_8_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_8_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_8_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_8_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_8_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_8_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_8_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_8_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_8_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_8_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_8_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_130) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_8) // @[util.scala:504:26] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_133) begin // @[util.scala:520:18, :526:19, :528:35] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_9_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_9_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_9_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_9_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_9_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_9_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_9_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_9_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_9_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_9_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_9_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_9_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_9_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_9_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_9_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_132) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_9) // @[util.scala:504:26] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_135) begin // @[util.scala:520:18, :526:19, :528:35] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_10_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_10_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_10_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_10_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_10_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_10_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_10_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_10_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_10_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_10_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_10_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_10_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_10_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_10_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_10_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_134) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_10) // @[util.scala:504:26] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_137) begin // @[util.scala:520:18, :526:19, :528:35] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_11_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_11_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_11_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_11_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_11_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_11_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_11_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_11_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_11_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_11_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_11_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_11_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_11_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_11_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_11_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_136) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_11) // @[util.scala:504:26] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_139) begin // @[util.scala:520:18, :526:19, :528:35] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_12_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_12_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_12_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_12_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_12_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_12_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_12_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_12_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_12_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_12_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_12_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_12_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_12_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_12_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_12_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_138) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_12) // @[util.scala:504:26] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_141) begin // @[util.scala:520:18, :526:19, :528:35] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_13_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_13_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_13_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_13_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_13_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_13_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_13_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_13_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_13_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_13_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_13_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_13_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_13_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_13_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_13_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_140) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_13) // @[util.scala:504:26] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_142) begin // @[util.scala:520:18, :526:19, :528:35] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_14_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_14_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_14_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_14_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_14_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_14_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_14_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_14_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_14_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_14_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_14_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_14_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_14_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_14_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_14_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & wrap) // @[Counter.scala:73:24] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_14) // @[util.scala:504:26] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:97:21, :505:22] always @(posedge) ram_15x131 ram_ext ( // @[util.scala:503:22] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:514:26] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:458:7, :503:22] ); // @[util.scala:503:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] assign io_count = io_count_0; // @[util.scala:458:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [19:0] inflight; // @[Monitor.scala:614:27] reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [31:0] _GEN_0 = {27'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [31:0] _GEN_3 = {27'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [19:0] inflight_1; // @[Monitor.scala:726:35] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File ToAXI4.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField} import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp} import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1} import freechips.rocketchip.util.DataToAugmentedData class AXI4TLStateBundle(val sourceBits: Int) extends Bundle { val size = UInt(4.W) val source = UInt((sourceBits max 1).W) } case object AXI4TLState extends ControlKey[AXI4TLStateBundle]("tl_state") case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBundle](AXI4TLState, Output(new AXI4TLStateBundle(sourceBits)), x => { x.size := 0.U x.source := 0.U }) /** TLtoAXI4IdMap serves as a record for the translation performed between id spaces. * * Its member [axi4Masters] is used as the new AXI4MasterParameters in diplomacy. * Its member [mapping] is used as the template for the circuit generated in TLToAXI4Node.module. */ class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapEntry] { val tlMasters = tlPort.masters.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType) private val axi4IdSize = tlMasters.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size } private val axi4IdStart = axi4IdSize.scanLeft(0)(_+_).init val axi4Masters = axi4IdStart.zip(axi4IdSize).zip(tlMasters).map { case ((start, size), tl) => AXI4MasterParameters( name = tl.name, id = IdRange(start, start+size), aligned = true, maxFlight = Some(if (tl.requestFifo) tl.sourceId.size else 1), nodePath = tl.nodePath) } private val axi4IdEnd = axi4Masters.map(_.id.end).max private val axiDigits = String.valueOf(axi4IdEnd-1).length() private val tlDigits = String.valueOf(tlPort.endSourceId-1).length() protected val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s" val mapping: Seq[TLToAXI4IdMapEntry] = tlMasters.zip(axi4Masters).map { case (tl, axi) => TLToAXI4IdMapEntry(axi.id, tl.sourceId, tl.name, tl.supports.probe, tl.requestFifo) } } case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = axi4Id val maxTransactionsInFlight = Some(tlId.size) } case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)( dFn = { p => AXI4MasterPortParameters( masters = (new TLtoAXI4IdMap(p)).axi4Masters, requestFields = (if (wcorrupt) Seq(AMBACorruptField()) else Seq()) ++ p.requestFields.filter(!_.isInstanceOf[AMBAProtField]), echoFields = AXI4TLStateField(log2Ceil(p.endSourceId)) +: p.echoFields, responseKeys = p.responseKeys) }, uFn = { p => TLSlavePortParameters.v1( managers = p.slaves.map { case s => TLSlaveParameters.v1( address = s.address, resources = s.resources, regionType = s.regionType, executable = s.executable, nodePath = s.nodePath, supportsGet = s.supportsRead, supportsPutFull = s.supportsWrite, supportsPutPartial = s.supportsWrite, fifoId = Some(0), mayDenyPut = true, mayDenyGet = true)}, beatBytes = p.beatBytes, minLatency = p.minLatency, responseFields = p.responseFields, requestKeys = AMBAProt +: p.requestKeys) }) // wcorrupt alone is not enough; a slave must include AMBACorrupt in the slave port's requestKeys class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0, val wcorrupt: Boolean = true)(implicit p: Parameters) extends LazyModule { require(stripBits == 0, "stripBits > 0 is no longer supported on TLToAXI4") val node = TLToAXI4Node(wcorrupt) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val slaves = edgeOut.slave.slaves // All pairs of slaves must promise that they will never interleave data require (slaves(0).interleavedId.isDefined) slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) } // Construct the source=>ID mapping table val map = new TLtoAXI4IdMap(edgeIn.client) val sourceStall = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(false.B)) val sourceTable = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(0.U.asTypeOf(out.aw.bits.id))) val idStall = WireDefault(VecInit.fill(edgeOut.master.endId)(false.B)) var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] } map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) => for (i <- 0 until tlId.size) { val id = axi4Id.start + (if (fifo) 0 else i) sourceStall(tlId.start + i) := idStall(id) sourceTable(tlId.start + i) := id.U } if (fifo) { idCount(axi4Id.start) = Some(tlId.size) } } adapterName.foreach { n => println(s"$n AXI4-ID <= TL-Source mapping:\n${map.pretty}\n") ElaborationArtefacts.add(s"$n.axi4.json", s"""{"mapping":[${map.mapping.mkString(",")}]}""") } // We need to keep the following state from A => D: (size, source) // All of those fields could potentially require 0 bits (argh. Chisel.) // We will pack all of that extra information into the echo bits. require (log2Ceil(edgeIn.maxLgSize+1) <= 4) val a_address = edgeIn.address(in.a.bits) val a_source = in.a.bits.source val a_size = edgeIn.size(in.a.bits) val a_isPut = edgeIn.hasData(in.a.bits) val (a_first, a_last, _) = edgeIn.firstlast(in.a) val r_state = out.r.bits.echo(AXI4TLState) val r_source = r_state.source val r_size = r_state.size val b_state = out.b.bits.echo(AXI4TLState) val b_source = b_state.source val b_size = b_state.size // We need these Queues because AXI4 queues are irrevocable val depth = if (combinational) 1 else 2 val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params))) val out_w = Wire(chiselTypeOf(out.w)) out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational) val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational) // Fan out the ARW channel to AR and AW out.ar.bits := queue_arw.bits out.aw.bits := queue_arw.bits out.ar.valid := queue_arw.valid && !queue_arw.bits.wen out.aw.valid := queue_arw.valid && queue_arw.bits.wen queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready) val beatBytes = edgeIn.manager.beatBytes val maxSize = log2Ceil(beatBytes).U val doneAW = RegInit(false.B) when (in.a.fire) { doneAW := !a_last } val arw = out_arw.bits arw.wen := a_isPut arw.id := sourceTable(a_source) arw.addr := a_address arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes) arw.size := Mux(a_size >= maxSize, maxSize, a_size) arw.burst := AXI4Parameters.BURST_INCR arw.lock := 0.U // not exclusive (LR/SC unsupported b/c no forward progress guarantee) arw.cache := 0.U // do not allow AXI to modify our transactions arw.prot := AXI4Parameters.PROT_PRIVILEGED arw.qos := 0.U // no QoS Connectable.waiveUnmatched(arw.user, in.a.bits.user) match { case (lhs, rhs) => lhs :<= rhs } Connectable.waiveUnmatched(arw.echo, in.a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = arw.echo(AXI4TLState) a_extra.source := a_source a_extra.size := a_size in.a.bits.user.lift(AMBAProt).foreach { x => val prot = Wire(Vec(3, Bool())) val cache = Wire(Vec(4, Bool())) prot(0) := x.privileged prot(1) := !x.secure prot(2) := x.fetch cache(0) := x.bufferable cache(1) := x.modifiable cache(2) := x.readalloc cache(3) := x.writealloc arw.prot := Cat(prot.reverse) arw.cache := Cat(cache.reverse) } val stall = sourceStall(in.a.bits.source) && a_first in.a.ready := !stall && Mux(a_isPut, (doneAW || out_arw.ready) && out_w.ready, out_arw.ready) out_arw.valid := !stall && in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, true.B) out_w.valid := !stall && in.a.valid && a_isPut && (doneAW || out_arw.ready) out_w.bits.data := in.a.bits.data out_w.bits.strb := in.a.bits.mask out_w.bits.last := a_last out_w.bits.user.lift(AMBACorrupt).foreach { _ := in.a.bits.corrupt } // R and B => D arbitration val r_holds_d = RegInit(false.B) when (out.r.fire) { r_holds_d := !out.r.bits.last } // Give R higher priority than B, unless B has been delayed for 8 cycles val b_delay = Reg(UInt(3.W)) when (out.b.valid && !out.b.ready) { b_delay := b_delay + 1.U } .otherwise { b_delay := 0.U } val r_wins = (out.r.valid && b_delay =/= 7.U) || r_holds_d out.r.ready := in.d.ready && r_wins out.b.ready := in.d.ready && !r_wins in.d.valid := Mux(r_wins, out.r.valid, out.b.valid) // If the first beat of the AXI RRESP is RESP_DECERR, treat this as a denied // request. We must pulse extend this value as AXI is allowed to change the // value of RRESP on every beat, and ChipLink may not. val r_first = RegInit(true.B) when (out.r.fire) { r_first := out.r.bits.last } val r_denied = out.r.bits.resp === AXI4Parameters.RESP_DECERR holdUnless r_first val r_corrupt = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY val b_denied = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY val r_d = edgeIn.AccessAck(r_source, r_size, 0.U, denied = r_denied, corrupt = r_corrupt || r_denied) val b_d = edgeIn.AccessAck(b_source, b_size, denied = b_denied) Connectable.waiveUnmatched(r_d.user, out.r.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(r_d.echo, out.r.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.user, out.b.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.echo, out.b.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } in.d.bits := Mux(r_wins, r_d, b_d) in.d.bits.data := out.r.bits.data // avoid a costly Mux // We need to track if any reads or writes are inflight for a given ID. // If the opposite type arrives, we must stall until it completes. val a_sel = UIntToOH(arw.id, edgeOut.master.endId).asBools val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).asBools val d_last = Mux(r_wins, out.r.bits.last, true.B) // If FIFO was requested, ensure that R+W ordering is preserved (a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) => // AXI does not guarantee read vs. write ordering. In particular, if we // are in the middle of receiving a read burst and then issue a write, // the write might affect the read burst. This violates FIFO behaviour. // To solve this, we must wait until the last beat of a burst, but this // means that a TileLink master which performs early source reuse can // have one more transaction inflight than we promised AXI; stall it too. val maxCount = n.getOrElse(1) val count = RegInit(0.U(log2Ceil(maxCount + 1).W)) val write = Reg(Bool()) val idle = count === 0.U val inc = as && out_arw.fire val dec = ds && d_last && in.d.fire count := count + inc.asUInt - dec.asUInt assert (!dec || count =/= 0.U) // underflow assert (!inc || count =/= maxCount.U) // overflow when (inc) { write := arw.wen } // If only one transaction can be inflight, it can't mismatch val mismatch = if (maxCount > 1) { write =/= arw.wen } else { false.B } s := (!idle && mismatch) || (count === maxCount.U) } // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B } } } object TLToAXI4 { def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0, wcorrupt: Boolean = true)(implicit p: Parameters) = { val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits, wcorrupt)) tl2axi4.node } def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = { if ( a.supports.probe && !b.supports.probe) return false if (!a.supports.probe && b.supports.probe) return true if ( a.requestFifo && !b.requestFifo ) return false if (!a.requestFifo && b.requestFifo ) return true return false } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLToAXI4( // @[ToAXI4.scala:103:9] input clock, // @[ToAXI4.scala:103:9] input reset, // @[ToAXI4.scala:103:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire [5:0] out_arw_bits_id; // @[ToAXI4.scala:153:25] wire auto_in_a_valid_0 = auto_in_a_valid; // @[ToAXI4.scala:103:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[ToAXI4.scala:103:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[ToAXI4.scala:103:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[ToAXI4.scala:103:9] wire [5:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[ToAXI4.scala:103:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[ToAXI4.scala:103:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[ToAXI4.scala:103:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[ToAXI4.scala:103:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[ToAXI4.scala:103:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[ToAXI4.scala:103:9] wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[ToAXI4.scala:103:9] wire auto_out_w_ready_0 = auto_out_w_ready; // @[ToAXI4.scala:103:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[ToAXI4.scala:103:9] wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_b_bits_echo_tl_state_size_0 = auto_out_b_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_b_bits_echo_tl_state_source_0 = auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9] wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[ToAXI4.scala:103:9] wire auto_out_r_valid_0 = auto_out_r_valid; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[ToAXI4.scala:103:9] wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[ToAXI4.scala:103:9] wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_r_bits_echo_tl_state_size_0 = auto_out_r_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_r_bits_echo_tl_state_source_0 = auto_out_r_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9] wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[ToAXI4.scala:103:9] wire [63:0][5:0] _GEN = '{6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h27, 6'h26, 6'h25, 6'h24, 6'h23, 6'h22, 6'h21, 6'h20, 6'h1F, 6'h1E, 6'h1D, 6'h1C, 6'h1B, 6'h1A, 6'h19, 6'h18, 6'h17, 6'h16, 6'h15, 6'h14, 6'h13, 6'h12, 6'h11, 6'h10, 6'hF, 6'hE, 6'hD, 6'hC, 6'hB, 6'hA, 6'h9, 6'h8, 6'h7, 6'h6, 6'h5, 6'h4, 6'h3, 6'h2, 6'h1, 6'h0}; wire [1:0] auto_in_d_bits_param = 2'h0; // @[ToAXI4.scala:103:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] r_d_param = 2'h0; // @[Edges.scala:810:17] wire [1:0] b_d_param = 2'h0; // @[Edges.scala:792:17] wire [1:0] _nodeIn_d_bits_T_param = 2'h0; // @[ToAXI4.scala:255:23] wire auto_in_d_bits_sink = 1'h0; // @[ToAXI4.scala:103:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire _sourceStall_WIRE_0 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_1 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_2 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_3 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_4 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_5 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_6 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_7 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_8 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_9 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_10 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_11 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_12 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_13 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_14 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_15 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_16 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_17 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_18 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_19 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_20 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_21 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_22 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_23 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_24 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_25 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_26 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_27 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_28 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_29 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_30 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_31 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_32 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_33 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_34 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_35 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_36 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_37 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_38 = 1'h0; // @[ToAXI4.scala:113:76] wire _sourceStall_WIRE_39 = 1'h0; // @[ToAXI4.scala:113:76] wire _idStall_WIRE_0 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_1 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_2 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_3 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_4 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_5 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_6 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_7 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_8 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_9 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_10 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_11 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_12 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_13 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_14 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_15 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_16 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_17 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_18 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_19 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_20 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_21 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_22 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_23 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_24 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_25 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_26 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_27 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_28 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_29 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_30 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_31 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_32 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_33 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_34 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_35 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_36 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_37 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_38 = 1'h0; // @[ToAXI4.scala:115:67] wire _idStall_WIRE_39 = 1'h0; // @[ToAXI4.scala:115:67] wire out_arw_bits_lock = 1'h0; // @[ToAXI4.scala:153:25] wire r_d_sink = 1'h0; // @[Edges.scala:810:17] wire b_d_sink = 1'h0; // @[Edges.scala:792:17] wire b_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire _nodeIn_d_bits_T_sink = 1'h0; // @[ToAXI4.scala:255:23] wire _idStall_0_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_1_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_2_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_3_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_4_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_5_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_6_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_7_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_8_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_9_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_10_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_11_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_12_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_13_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_14_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_15_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_16_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_17_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_18_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_19_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_20_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_21_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_22_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_23_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_24_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_25_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_26_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_27_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_28_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_29_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_30_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_31_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_32_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_33_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_34_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_35_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_36_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_37_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_38_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire _idStall_39_T_1 = 1'h0; // @[ToAXI4.scala:286:21] wire [63:0] r_d_data = 64'h0; // @[Edges.scala:810:17] wire [63:0] b_d_data = 64'h0; // @[Edges.scala:792:17] wire [63:0] _nodeIn_d_bits_T_data = 64'h0; // @[ToAXI4.scala:255:23] wire [2:0] b_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [2:0] out_arw_bits_prot = 3'h1; // @[ToAXI4.scala:153:25] wire [2:0] r_d_opcode = 3'h1; // @[Edges.scala:810:17] wire [3:0] out_arw_bits_cache = 4'h0; // @[ToAXI4.scala:153:25] wire [3:0] out_arw_bits_qos = 4'h0; // @[ToAXI4.scala:153:25] wire [1:0] out_arw_bits_burst = 2'h1; // @[ToAXI4.scala:153:25] wire [5:0] sourceTable_39 = 6'h27; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_38 = 6'h26; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_37 = 6'h25; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_36 = 6'h24; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_35 = 6'h23; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_34 = 6'h22; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_33 = 6'h21; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_32 = 6'h20; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_31 = 6'h1F; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_30 = 6'h1E; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_29 = 6'h1D; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_28 = 6'h1C; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_27 = 6'h1B; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_26 = 6'h1A; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_25 = 6'h19; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_24 = 6'h18; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_23 = 6'h17; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_22 = 6'h16; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_21 = 6'h15; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_20 = 6'h14; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_19 = 6'h13; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_18 = 6'h12; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_17 = 6'h11; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_16 = 6'h10; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_15 = 6'hF; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_14 = 6'hE; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_13 = 6'hD; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_12 = 6'hC; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_11 = 6'hB; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_10 = 6'hA; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_9 = 6'h9; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_8 = 6'h8; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_7 = 6'h7; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_6 = 6'h6; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_5 = 6'h5; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_4 = 6'h4; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_3 = 6'h3; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_2 = 6'h2; // @[ToAXI4.scala:114:36] wire [5:0] sourceTable_1 = 6'h1; // @[ToAXI4.scala:114:36] wire [5:0] _sourceTable_WIRE = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_1 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_2 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_3 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_4 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_5 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_6 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_7 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_8 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_9 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_10 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_11 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_12 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_13 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_14 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_15 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_16 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_17 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_18 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_19 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_20 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_21 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_22 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_23 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_24 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_25 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_26 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_27 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_28 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_29 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_30 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_31 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_32 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_33 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_34 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_35 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_36 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_37 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_38 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_39 = 6'h0; // @[ToAXI4.scala:114:89] wire [5:0] _sourceTable_WIRE_40_0 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_1 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_2 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_3 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_4 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_5 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_6 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_7 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_8 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_9 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_10 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_11 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_12 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_13 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_14 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_15 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_16 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_17 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_18 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_19 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_20 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_21 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_22 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_23 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_24 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_25 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_26 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_27 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_28 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_29 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_30 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_31 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_32 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_33 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_34 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_35 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_36 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_37 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_38 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] _sourceTable_WIRE_40_39 = 6'h0; // @[ToAXI4.scala:114:76] wire [5:0] sourceTable_0 = 6'h0; // @[ToAXI4.scala:114:36] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[ToAXI4.scala:103:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[ToAXI4.scala:103:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[ToAXI4.scala:103:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[ToAXI4.scala:103:9] wire [5:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[ToAXI4.scala:103:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[ToAXI4.scala:103:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[ToAXI4.scala:103:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[ToAXI4.scala:103:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[ToAXI4.scala:103:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[ToAXI4.scala:103:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[ToAXI4.scala:103:9] wire nodeOut_aw_valid; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_aw_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_w_ready = auto_out_w_ready_0; // @[ToAXI4.scala:103:9] wire nodeOut_w_valid; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17] wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[ToAXI4.scala:103:9] wire [5:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[ToAXI4.scala:103:9] wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[ToAXI4.scala:103:9] wire [3:0] nodeOut_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9] wire [5:0] nodeOut_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9] wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[ToAXI4.scala:103:9] wire nodeOut_ar_valid; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_ar_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_r_ready; // @[MixedNode.scala:542:17] wire nodeOut_r_valid = auto_out_r_valid_0; // @[ToAXI4.scala:103:9] wire [5:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[ToAXI4.scala:103:9] wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[ToAXI4.scala:103:9] wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[ToAXI4.scala:103:9] wire [3:0] nodeOut_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9] wire [5:0] nodeOut_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9] wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[ToAXI4.scala:103:9] wire auto_in_a_ready_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_in_d_bits_opcode_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_in_d_bits_size_0; // @[ToAXI4.scala:103:9] wire [5:0] auto_in_d_bits_source_0; // @[ToAXI4.scala:103:9] wire auto_in_d_bits_denied_0; // @[ToAXI4.scala:103:9] wire [63:0] auto_in_d_bits_data_0; // @[ToAXI4.scala:103:9] wire auto_in_d_bits_corrupt_0; // @[ToAXI4.scala:103:9] wire auto_in_d_valid_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_aw_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_aw_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_aw_bits_id_0; // @[ToAXI4.scala:103:9] wire [31:0] auto_out_aw_bits_addr_0; // @[ToAXI4.scala:103:9] wire [7:0] auto_out_aw_bits_len_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_out_aw_bits_size_0; // @[ToAXI4.scala:103:9] wire [1:0] auto_out_aw_bits_burst_0; // @[ToAXI4.scala:103:9] wire auto_out_aw_bits_lock_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_aw_bits_cache_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_out_aw_bits_prot_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_aw_bits_qos_0; // @[ToAXI4.scala:103:9] wire auto_out_aw_valid_0; // @[ToAXI4.scala:103:9] wire [63:0] auto_out_w_bits_data_0; // @[ToAXI4.scala:103:9] wire [7:0] auto_out_w_bits_strb_0; // @[ToAXI4.scala:103:9] wire auto_out_w_bits_last_0; // @[ToAXI4.scala:103:9] wire auto_out_w_valid_0; // @[ToAXI4.scala:103:9] wire auto_out_b_ready_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_ar_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_ar_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9] wire [5:0] auto_out_ar_bits_id_0; // @[ToAXI4.scala:103:9] wire [31:0] auto_out_ar_bits_addr_0; // @[ToAXI4.scala:103:9] wire [7:0] auto_out_ar_bits_len_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_out_ar_bits_size_0; // @[ToAXI4.scala:103:9] wire [1:0] auto_out_ar_bits_burst_0; // @[ToAXI4.scala:103:9] wire auto_out_ar_bits_lock_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_ar_bits_cache_0; // @[ToAXI4.scala:103:9] wire [2:0] auto_out_ar_bits_prot_0; // @[ToAXI4.scala:103:9] wire [3:0] auto_out_ar_bits_qos_0; // @[ToAXI4.scala:103:9] wire auto_out_ar_valid_0; // @[ToAXI4.scala:103:9] wire auto_out_r_ready_0; // @[ToAXI4.scala:103:9] wire _nodeIn_a_ready_T_4; // @[ToAXI4.scala:206:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[ToAXI4.scala:103:9] wire [5:0] out_arw_bits_echo_tl_state_source = nodeIn_a_bits_source; // @[ToAXI4.scala:153:25] wire [31:0] out_arw_bits_addr = nodeIn_a_bits_address; // @[ToAXI4.scala:153:25] wire [7:0] out_w_bits_strb = nodeIn_a_bits_mask; // @[ToAXI4.scala:154:23] wire [63:0] out_w_bits_data = nodeIn_a_bits_data; // @[ToAXI4.scala:154:23] wire _nodeIn_d_valid_T; // @[ToAXI4.scala:229:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[ToAXI4.scala:103:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[ToAXI4.scala:255:23] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[ToAXI4.scala:103:9] wire [2:0] _nodeIn_d_bits_T_size; // @[ToAXI4.scala:255:23] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[ToAXI4.scala:103:9] wire [5:0] _nodeIn_d_bits_T_source; // @[ToAXI4.scala:255:23] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[ToAXI4.scala:103:9] wire _nodeIn_d_bits_T_denied; // @[ToAXI4.scala:255:23] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[ToAXI4.scala:103:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[ToAXI4.scala:103:9] wire _nodeIn_d_bits_T_corrupt; // @[ToAXI4.scala:255:23] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[ToAXI4.scala:103:9] wire _nodeOut_aw_valid_T; // @[ToAXI4.scala:162:39] assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[ToAXI4.scala:103:9] wire [5:0] queue_arw_bits_id; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[ToAXI4.scala:103:9] wire [31:0] queue_arw_bits_addr; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[ToAXI4.scala:103:9] wire [7:0] queue_arw_bits_len; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[ToAXI4.scala:103:9] wire [2:0] queue_arw_bits_size; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[ToAXI4.scala:103:9] wire [1:0] queue_arw_bits_burst; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[ToAXI4.scala:103:9] wire queue_arw_bits_lock; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[ToAXI4.scala:103:9] wire [3:0] queue_arw_bits_cache; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[ToAXI4.scala:103:9] wire [2:0] queue_arw_bits_prot; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[ToAXI4.scala:103:9] wire [3:0] queue_arw_bits_qos; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[ToAXI4.scala:103:9] wire [3:0] queue_arw_bits_echo_tl_state_size; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_echo_tl_state_size_0 = nodeOut_aw_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9] wire [5:0] queue_arw_bits_echo_tl_state_source; // @[Decoupled.scala:401:19] assign auto_out_aw_bits_echo_tl_state_source_0 = nodeOut_aw_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9] wire nodeOut_w_irr_ready = nodeOut_w_ready; // @[Decoupled.scala:401:19] wire nodeOut_w_irr_valid; // @[Decoupled.scala:401:19] assign auto_out_w_valid_0 = nodeOut_w_valid; // @[ToAXI4.scala:103:9] wire [63:0] nodeOut_w_irr_bits_data; // @[Decoupled.scala:401:19] assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[ToAXI4.scala:103:9] wire [7:0] nodeOut_w_irr_bits_strb; // @[Decoupled.scala:401:19] assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[ToAXI4.scala:103:9] wire nodeOut_w_irr_bits_last; // @[Decoupled.scala:401:19] assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[ToAXI4.scala:103:9] wire _nodeOut_b_ready_T_1; // @[ToAXI4.scala:228:33] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[ToAXI4.scala:103:9] wire [5:0] b_d_source = nodeOut_b_bits_echo_tl_state_source; // @[Edges.scala:792:17] wire _nodeOut_ar_valid_T_1; // @[ToAXI4.scala:161:39] assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_echo_tl_state_size_0 = nodeOut_ar_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9] assign auto_out_ar_bits_echo_tl_state_source_0 = nodeOut_ar_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9] wire _nodeOut_r_ready_T; // @[ToAXI4.scala:227:33] assign auto_out_r_ready_0 = nodeOut_r_ready; // @[ToAXI4.scala:103:9] assign nodeIn_d_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [5:0] r_d_source = nodeOut_r_bits_echo_tl_state_source; // @[Edges.scala:810:17] wire idStall_0; // @[ToAXI4.scala:115:32] wire idStall_1; // @[ToAXI4.scala:115:32] wire idStall_2; // @[ToAXI4.scala:115:32] wire idStall_3; // @[ToAXI4.scala:115:32] wire idStall_4; // @[ToAXI4.scala:115:32] wire idStall_5; // @[ToAXI4.scala:115:32] wire idStall_6; // @[ToAXI4.scala:115:32] wire idStall_7; // @[ToAXI4.scala:115:32] wire idStall_8; // @[ToAXI4.scala:115:32] wire idStall_9; // @[ToAXI4.scala:115:32] wire idStall_10; // @[ToAXI4.scala:115:32] wire idStall_11; // @[ToAXI4.scala:115:32] wire idStall_12; // @[ToAXI4.scala:115:32] wire idStall_13; // @[ToAXI4.scala:115:32] wire idStall_14; // @[ToAXI4.scala:115:32] wire idStall_15; // @[ToAXI4.scala:115:32] wire idStall_16; // @[ToAXI4.scala:115:32] wire idStall_17; // @[ToAXI4.scala:115:32] wire idStall_18; // @[ToAXI4.scala:115:32] wire idStall_19; // @[ToAXI4.scala:115:32] wire idStall_20; // @[ToAXI4.scala:115:32] wire idStall_21; // @[ToAXI4.scala:115:32] wire idStall_22; // @[ToAXI4.scala:115:32] wire idStall_23; // @[ToAXI4.scala:115:32] wire idStall_24; // @[ToAXI4.scala:115:32] wire idStall_25; // @[ToAXI4.scala:115:32] wire idStall_26; // @[ToAXI4.scala:115:32] wire idStall_27; // @[ToAXI4.scala:115:32] wire idStall_28; // @[ToAXI4.scala:115:32] wire idStall_29; // @[ToAXI4.scala:115:32] wire idStall_30; // @[ToAXI4.scala:115:32] wire idStall_31; // @[ToAXI4.scala:115:32] wire idStall_32; // @[ToAXI4.scala:115:32] wire idStall_33; // @[ToAXI4.scala:115:32] wire idStall_34; // @[ToAXI4.scala:115:32] wire idStall_35; // @[ToAXI4.scala:115:32] wire idStall_36; // @[ToAXI4.scala:115:32] wire idStall_37; // @[ToAXI4.scala:115:32] wire idStall_38; // @[ToAXI4.scala:115:32] wire idStall_39; // @[ToAXI4.scala:115:32] wire sourceStall_0; // @[ToAXI4.scala:113:36] wire sourceStall_1; // @[ToAXI4.scala:113:36] wire sourceStall_2; // @[ToAXI4.scala:113:36] wire sourceStall_3; // @[ToAXI4.scala:113:36] wire sourceStall_4; // @[ToAXI4.scala:113:36] wire sourceStall_5; // @[ToAXI4.scala:113:36] wire sourceStall_6; // @[ToAXI4.scala:113:36] wire sourceStall_7; // @[ToAXI4.scala:113:36] wire sourceStall_8; // @[ToAXI4.scala:113:36] wire sourceStall_9; // @[ToAXI4.scala:113:36] wire sourceStall_10; // @[ToAXI4.scala:113:36] wire sourceStall_11; // @[ToAXI4.scala:113:36] wire sourceStall_12; // @[ToAXI4.scala:113:36] wire sourceStall_13; // @[ToAXI4.scala:113:36] wire sourceStall_14; // @[ToAXI4.scala:113:36] wire sourceStall_15; // @[ToAXI4.scala:113:36] wire sourceStall_16; // @[ToAXI4.scala:113:36] wire sourceStall_17; // @[ToAXI4.scala:113:36] wire sourceStall_18; // @[ToAXI4.scala:113:36] wire sourceStall_19; // @[ToAXI4.scala:113:36] wire sourceStall_20; // @[ToAXI4.scala:113:36] wire sourceStall_21; // @[ToAXI4.scala:113:36] wire sourceStall_22; // @[ToAXI4.scala:113:36] wire sourceStall_23; // @[ToAXI4.scala:113:36] wire sourceStall_24; // @[ToAXI4.scala:113:36] wire sourceStall_25; // @[ToAXI4.scala:113:36] wire sourceStall_26; // @[ToAXI4.scala:113:36] wire sourceStall_27; // @[ToAXI4.scala:113:36] wire sourceStall_28; // @[ToAXI4.scala:113:36] wire sourceStall_29; // @[ToAXI4.scala:113:36] wire sourceStall_30; // @[ToAXI4.scala:113:36] wire sourceStall_31; // @[ToAXI4.scala:113:36] wire sourceStall_32; // @[ToAXI4.scala:113:36] wire sourceStall_33; // @[ToAXI4.scala:113:36] wire sourceStall_34; // @[ToAXI4.scala:113:36] wire sourceStall_35; // @[ToAXI4.scala:113:36] wire sourceStall_36; // @[ToAXI4.scala:113:36] wire sourceStall_37; // @[ToAXI4.scala:113:36] wire sourceStall_38; // @[ToAXI4.scala:113:36] wire sourceStall_39; // @[ToAXI4.scala:113:36] wire _idStall_0_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_0 = idStall_0; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_1_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_1 = idStall_1; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_2_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_2 = idStall_2; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_3_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_3 = idStall_3; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_4_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_4 = idStall_4; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_5_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_5 = idStall_5; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_6_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_6 = idStall_6; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_7_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_7 = idStall_7; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_8_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_8 = idStall_8; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_9_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_9 = idStall_9; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_10_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_10 = idStall_10; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_11_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_11 = idStall_11; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_12_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_12 = idStall_12; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_13_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_13 = idStall_13; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_14_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_14 = idStall_14; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_15_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_15 = idStall_15; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_16_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_16 = idStall_16; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_17_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_17 = idStall_17; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_18_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_18 = idStall_18; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_19_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_19 = idStall_19; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_20_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_20 = idStall_20; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_21_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_21 = idStall_21; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_22_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_22 = idStall_22; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_23_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_23 = idStall_23; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_24_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_24 = idStall_24; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_25_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_25 = idStall_25; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_26_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_26 = idStall_26; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_27_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_27 = idStall_27; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_28_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_28 = idStall_28; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_29_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_29 = idStall_29; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_30_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_30 = idStall_30; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_31_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_31 = idStall_31; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_32_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_32 = idStall_32; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_33_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_33 = idStall_33; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_34_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_34 = idStall_34; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_35_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_35 = idStall_35; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_36_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_36 = idStall_36; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_37_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_37 = idStall_37; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_38_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_38 = idStall_38; // @[ToAXI4.scala:113:36, :115:32] wire _idStall_39_T_3; // @[ToAXI4.scala:286:34] assign sourceStall_39 = idStall_39; // @[ToAXI4.scala:113:36, :115:32] wire _a_isPut_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire a_isPut = ~_a_isPut_opdata_T; // @[Edges.scala:92:{28,37}] wire out_arw_bits_wen = a_isPut; // @[ToAXI4.scala:153:25] wire _T_1 = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire [12:0] _r_beats1_decode_T = 13'h3F << nodeIn_a_bits_size; // @[package.scala:243:71] wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] r_beats1_decode = _r_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] r_counter; // @[Edges.scala:229:27] wire [3:0] _r_counter1_T = {1'h0, r_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] r_counter1 = _r_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = r_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire out_w_bits_last = a_last; // @[ToAXI4.scala:154:23] wire r_3 = a_last & _T_1; // @[Decoupled.scala:51:35] wire [2:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _r_counter_T = a_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _out_arw_valid_T_5; // @[ToAXI4.scala:207:45] wire [5:0] a_sel_shiftAmount = out_arw_bits_id; // @[OneHot.scala:64:49] wire [7:0] _out_arw_bits_len_T_3; // @[ToAXI4.scala:174:84] wire [2:0] _out_arw_bits_size_T_1; // @[ToAXI4.scala:175:23] wire [3:0] out_arw_bits_echo_tl_state_size; // @[ToAXI4.scala:153:25] wire [7:0] out_arw_bits_len; // @[ToAXI4.scala:153:25] wire [2:0] out_arw_bits_size; // @[ToAXI4.scala:153:25] wire out_arw_ready; // @[ToAXI4.scala:153:25] wire out_arw_valid; // @[ToAXI4.scala:153:25] wire _out_w_valid_T_4; // @[ToAXI4.scala:209:54] wire out_w_ready; // @[ToAXI4.scala:154:23] wire out_w_valid; // @[ToAXI4.scala:154:23] assign nodeOut_w_valid = nodeOut_w_irr_valid; // @[Decoupled.scala:401:19] assign nodeOut_w_bits_data = nodeOut_w_irr_bits_data; // @[Decoupled.scala:401:19] assign nodeOut_w_bits_strb = nodeOut_w_irr_bits_strb; // @[Decoupled.scala:401:19] assign nodeOut_w_bits_last = nodeOut_w_irr_bits_last; // @[Decoupled.scala:401:19] wire _queue_arw_ready_T; // @[ToAXI4.scala:163:29] assign nodeOut_aw_bits_id = queue_arw_bits_id; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_id = queue_arw_bits_id; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_addr = queue_arw_bits_addr; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_addr = queue_arw_bits_addr; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_len = queue_arw_bits_len; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_len = queue_arw_bits_len; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_size = queue_arw_bits_size; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_size = queue_arw_bits_size; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_burst = queue_arw_bits_burst; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_burst = queue_arw_bits_burst; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_lock = queue_arw_bits_lock; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_lock = queue_arw_bits_lock; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_cache = queue_arw_bits_cache; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_cache = queue_arw_bits_cache; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_prot = queue_arw_bits_prot; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_prot = queue_arw_bits_prot; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_qos = queue_arw_bits_qos; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_qos = queue_arw_bits_qos; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_echo_tl_state_size = queue_arw_bits_echo_tl_state_size; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_echo_tl_state_size = queue_arw_bits_echo_tl_state_size; // @[Decoupled.scala:401:19] assign nodeOut_aw_bits_echo_tl_state_source = queue_arw_bits_echo_tl_state_source; // @[Decoupled.scala:401:19] assign nodeOut_ar_bits_echo_tl_state_source = queue_arw_bits_echo_tl_state_source; // @[Decoupled.scala:401:19] wire queue_arw_bits_wen; // @[Decoupled.scala:401:19] wire queue_arw_ready; // @[Decoupled.scala:401:19] wire queue_arw_valid; // @[Decoupled.scala:401:19] wire _nodeOut_ar_valid_T = ~queue_arw_bits_wen; // @[Decoupled.scala:401:19] assign _nodeOut_ar_valid_T_1 = queue_arw_valid & _nodeOut_ar_valid_T; // @[Decoupled.scala:401:19] assign nodeOut_ar_valid = _nodeOut_ar_valid_T_1; // @[ToAXI4.scala:161:39] assign _nodeOut_aw_valid_T = queue_arw_valid & queue_arw_bits_wen; // @[Decoupled.scala:401:19] assign nodeOut_aw_valid = _nodeOut_aw_valid_T; // @[ToAXI4.scala:162:39] assign _queue_arw_ready_T = queue_arw_bits_wen ? nodeOut_aw_ready : nodeOut_ar_ready; // @[Decoupled.scala:401:19] assign queue_arw_ready = _queue_arw_ready_T; // @[Decoupled.scala:401:19] reg doneAW; // @[ToAXI4.scala:167:30] wire _doneAW_T = ~a_last; // @[ToAXI4.scala:168:36] assign out_arw_bits_id = _GEN[nodeIn_a_bits_source]; // @[ToAXI4.scala:153:25, :172:17] wire [17:0] _out_arw_bits_len_T = 18'h7FF << nodeIn_a_bits_size; // @[package.scala:243:71] wire [10:0] _out_arw_bits_len_T_1 = _out_arw_bits_len_T[10:0]; // @[package.scala:243:{71,76}] wire [10:0] _out_arw_bits_len_T_2 = ~_out_arw_bits_len_T_1; // @[package.scala:243:{46,76}] assign _out_arw_bits_len_T_3 = _out_arw_bits_len_T_2[10:3]; // @[package.scala:243:46] assign out_arw_bits_len = _out_arw_bits_len_T_3; // @[ToAXI4.scala:153:25, :174:84] wire _out_arw_bits_size_T = nodeIn_a_bits_size > 3'h2; // @[ToAXI4.scala:175:31] assign _out_arw_bits_size_T_1 = _out_arw_bits_size_T ? 3'h3 : nodeIn_a_bits_size; // @[ToAXI4.scala:175:{23,31}] assign out_arw_bits_size = _out_arw_bits_size_T_1; // @[ToAXI4.scala:153:25, :175:23] assign out_arw_bits_echo_tl_state_size = {1'h0, nodeIn_a_bits_size}; // @[ToAXI4.scala:153:25, :189:22] wire [63:0] _GEN_0 = {{sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_0}, {sourceStall_39}, {sourceStall_38}, {sourceStall_37}, {sourceStall_36}, {sourceStall_35}, {sourceStall_34}, {sourceStall_33}, {sourceStall_32}, {sourceStall_31}, {sourceStall_30}, {sourceStall_29}, {sourceStall_28}, {sourceStall_27}, {sourceStall_26}, {sourceStall_25}, {sourceStall_24}, {sourceStall_23}, {sourceStall_22}, {sourceStall_21}, {sourceStall_20}, {sourceStall_19}, {sourceStall_18}, {sourceStall_17}, {sourceStall_16}, {sourceStall_15}, {sourceStall_14}, {sourceStall_13}, {sourceStall_12}, {sourceStall_11}, {sourceStall_10}, {sourceStall_9}, {sourceStall_8}, {sourceStall_7}, {sourceStall_6}, {sourceStall_5}, {sourceStall_4}, {sourceStall_3}, {sourceStall_2}, {sourceStall_1}, {sourceStall_0}}; // @[ToAXI4.scala:113:36, :205:49] wire stall = _GEN_0[nodeIn_a_bits_source] & a_first; // @[ToAXI4.scala:205:49] wire _nodeIn_a_ready_T = ~stall; // @[ToAXI4.scala:205:49, :206:21] wire _GEN_1 = doneAW | out_arw_ready; // @[ToAXI4.scala:153:25, :167:30, :206:52] wire _nodeIn_a_ready_T_1; // @[ToAXI4.scala:206:52] assign _nodeIn_a_ready_T_1 = _GEN_1; // @[ToAXI4.scala:206:52] wire _out_w_valid_T_3; // @[ToAXI4.scala:209:65] assign _out_w_valid_T_3 = _GEN_1; // @[ToAXI4.scala:206:52, :209:65] wire _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T_1 & out_w_ready; // @[ToAXI4.scala:154:23, :206:{52,70}] wire _nodeIn_a_ready_T_3 = a_isPut ? _nodeIn_a_ready_T_2 : out_arw_ready; // @[ToAXI4.scala:153:25, :206:{34,70}] assign _nodeIn_a_ready_T_4 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_3; // @[ToAXI4.scala:206:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_4; // @[ToAXI4.scala:206:28] wire _out_arw_valid_T = ~stall; // @[ToAXI4.scala:205:49, :206:21, :207:24] wire _out_arw_valid_T_1 = _out_arw_valid_T & nodeIn_a_valid; // @[ToAXI4.scala:207:{24,31}] wire _out_arw_valid_T_2 = ~doneAW; // @[ToAXI4.scala:167:30, :207:61] wire _out_arw_valid_T_3 = _out_arw_valid_T_2 & out_w_ready; // @[ToAXI4.scala:154:23, :207:{61,69}] wire _out_arw_valid_T_4 = ~a_isPut | _out_arw_valid_T_3; // @[ToAXI4.scala:207:{51,69}] assign _out_arw_valid_T_5 = _out_arw_valid_T_1 & _out_arw_valid_T_4; // @[ToAXI4.scala:207:{31,45,51}] assign out_arw_valid = _out_arw_valid_T_5; // @[ToAXI4.scala:153:25, :207:45] wire _out_w_valid_T = ~stall; // @[ToAXI4.scala:205:49, :206:21, :209:22] wire _out_w_valid_T_1 = _out_w_valid_T & nodeIn_a_valid; // @[ToAXI4.scala:209:{22,29}] wire _out_w_valid_T_2 = _out_w_valid_T_1 & a_isPut; // @[ToAXI4.scala:209:{29,43}] assign _out_w_valid_T_4 = _out_w_valid_T_2 & _out_w_valid_T_3; // @[ToAXI4.scala:209:{43,54,65}] assign out_w_valid = _out_w_valid_T_4; // @[ToAXI4.scala:154:23, :209:54] reg r_holds_d; // @[ToAXI4.scala:216:30] wire _r_holds_d_T = ~nodeOut_r_bits_last; // @[ToAXI4.scala:217:40] reg [2:0] b_delay; // @[ToAXI4.scala:219:24] wire [3:0] _b_delay_T = {1'h0, b_delay} + 4'h1; // @[ToAXI4.scala:219:24, :221:28] wire [2:0] _b_delay_T_1 = _b_delay_T[2:0]; // @[ToAXI4.scala:221:28] wire _r_wins_T = b_delay != 3'h7; // @[ToAXI4.scala:219:24, :225:44] wire _r_wins_T_1 = nodeOut_r_valid & _r_wins_T; // @[ToAXI4.scala:225:{33,44}] wire r_wins = _r_wins_T_1 | r_holds_d; // @[ToAXI4.scala:216:30, :225:{33,53}] assign _nodeOut_r_ready_T = nodeIn_d_ready & r_wins; // @[ToAXI4.scala:225:53, :227:33] assign nodeOut_r_ready = _nodeOut_r_ready_T; // @[ToAXI4.scala:227:33] wire _nodeOut_b_ready_T = ~r_wins; // @[ToAXI4.scala:225:53, :228:36] assign _nodeOut_b_ready_T_1 = nodeIn_d_ready & _nodeOut_b_ready_T; // @[ToAXI4.scala:228:{33,36}] assign nodeOut_b_ready = _nodeOut_b_ready_T_1; // @[ToAXI4.scala:228:33] assign _nodeIn_d_valid_T = r_wins ? nodeOut_r_valid : nodeOut_b_valid; // @[ToAXI4.scala:225:53, :229:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[ToAXI4.scala:229:24] reg r_first; // @[ToAXI4.scala:234:28] wire _r_denied_T = &nodeOut_r_bits_resp; // @[ToAXI4.scala:236:39] reg r_denied_r; // @[package.scala:88:63] wire r_denied = r_first ? _r_denied_T : r_denied_r; // @[package.scala:88:{42,63}] wire r_d_denied = r_denied; // @[package.scala:88:42] wire r_corrupt = |nodeOut_r_bits_resp; // @[ToAXI4.scala:237:39] wire b_denied = |nodeOut_b_bits_resp; // @[ToAXI4.scala:238:39] wire b_d_denied = b_denied; // @[ToAXI4.scala:238:39] wire _r_d_T = r_corrupt | r_denied; // @[package.scala:88:42] wire r_d_corrupt = _r_d_T; // @[ToAXI4.scala:240:96] wire [2:0] r_d_size; // @[Edges.scala:810:17] assign r_d_size = nodeOut_r_bits_echo_tl_state_size[2:0]; // @[Edges.scala:810:17, :813:15] wire [2:0] b_d_size; // @[Edges.scala:792:17] assign b_d_size = nodeOut_b_bits_echo_tl_state_size[2:0]; // @[Edges.scala:792:17, :795:15] assign _nodeIn_d_bits_T_opcode = {2'h0, r_wins}; // @[ToAXI4.scala:225:53, :255:23] assign _nodeIn_d_bits_T_size = r_wins ? r_d_size : b_d_size; // @[ToAXI4.scala:225:53, :255:23] assign _nodeIn_d_bits_T_source = r_wins ? r_d_source : b_d_source; // @[ToAXI4.scala:225:53, :255:23] assign _nodeIn_d_bits_T_denied = r_wins ? r_d_denied : b_d_denied; // @[ToAXI4.scala:225:53, :255:23] assign _nodeIn_d_bits_T_corrupt = r_wins & r_d_corrupt; // @[ToAXI4.scala:225:53, :255:23] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[ToAXI4.scala:255:23] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[ToAXI4.scala:255:23] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[ToAXI4.scala:255:23] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[ToAXI4.scala:255:23] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[ToAXI4.scala:255:23] wire [63:0] _a_sel_T = 64'h1 << a_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _a_sel_T_1 = _a_sel_T[39:0]; // @[OneHot.scala:65:{12,27}] wire a_sel_0 = _a_sel_T_1[0]; // @[OneHot.scala:65:27] wire a_sel_1 = _a_sel_T_1[1]; // @[OneHot.scala:65:27] wire a_sel_2 = _a_sel_T_1[2]; // @[OneHot.scala:65:27] wire a_sel_3 = _a_sel_T_1[3]; // @[OneHot.scala:65:27] wire a_sel_4 = _a_sel_T_1[4]; // @[OneHot.scala:65:27] wire a_sel_5 = _a_sel_T_1[5]; // @[OneHot.scala:65:27] wire a_sel_6 = _a_sel_T_1[6]; // @[OneHot.scala:65:27] wire a_sel_7 = _a_sel_T_1[7]; // @[OneHot.scala:65:27] wire a_sel_8 = _a_sel_T_1[8]; // @[OneHot.scala:65:27] wire a_sel_9 = _a_sel_T_1[9]; // @[OneHot.scala:65:27] wire a_sel_10 = _a_sel_T_1[10]; // @[OneHot.scala:65:27] wire a_sel_11 = _a_sel_T_1[11]; // @[OneHot.scala:65:27] wire a_sel_12 = _a_sel_T_1[12]; // @[OneHot.scala:65:27] wire a_sel_13 = _a_sel_T_1[13]; // @[OneHot.scala:65:27] wire a_sel_14 = _a_sel_T_1[14]; // @[OneHot.scala:65:27] wire a_sel_15 = _a_sel_T_1[15]; // @[OneHot.scala:65:27] wire a_sel_16 = _a_sel_T_1[16]; // @[OneHot.scala:65:27] wire a_sel_17 = _a_sel_T_1[17]; // @[OneHot.scala:65:27] wire a_sel_18 = _a_sel_T_1[18]; // @[OneHot.scala:65:27] wire a_sel_19 = _a_sel_T_1[19]; // @[OneHot.scala:65:27] wire a_sel_20 = _a_sel_T_1[20]; // @[OneHot.scala:65:27] wire a_sel_21 = _a_sel_T_1[21]; // @[OneHot.scala:65:27] wire a_sel_22 = _a_sel_T_1[22]; // @[OneHot.scala:65:27] wire a_sel_23 = _a_sel_T_1[23]; // @[OneHot.scala:65:27] wire a_sel_24 = _a_sel_T_1[24]; // @[OneHot.scala:65:27] wire a_sel_25 = _a_sel_T_1[25]; // @[OneHot.scala:65:27] wire a_sel_26 = _a_sel_T_1[26]; // @[OneHot.scala:65:27] wire a_sel_27 = _a_sel_T_1[27]; // @[OneHot.scala:65:27] wire a_sel_28 = _a_sel_T_1[28]; // @[OneHot.scala:65:27] wire a_sel_29 = _a_sel_T_1[29]; // @[OneHot.scala:65:27] wire a_sel_30 = _a_sel_T_1[30]; // @[OneHot.scala:65:27] wire a_sel_31 = _a_sel_T_1[31]; // @[OneHot.scala:65:27] wire a_sel_32 = _a_sel_T_1[32]; // @[OneHot.scala:65:27] wire a_sel_33 = _a_sel_T_1[33]; // @[OneHot.scala:65:27] wire a_sel_34 = _a_sel_T_1[34]; // @[OneHot.scala:65:27] wire a_sel_35 = _a_sel_T_1[35]; // @[OneHot.scala:65:27] wire a_sel_36 = _a_sel_T_1[36]; // @[OneHot.scala:65:27] wire a_sel_37 = _a_sel_T_1[37]; // @[OneHot.scala:65:27] wire a_sel_38 = _a_sel_T_1[38]; // @[OneHot.scala:65:27] wire a_sel_39 = _a_sel_T_1[39]; // @[OneHot.scala:65:27] wire [5:0] _d_sel_T = r_wins ? nodeOut_r_bits_id : nodeOut_b_bits_id; // @[ToAXI4.scala:225:53, :261:31] wire [5:0] d_sel_shiftAmount = _d_sel_T; // @[OneHot.scala:64:49] wire [63:0] _d_sel_T_1 = 64'h1 << d_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _d_sel_T_2 = _d_sel_T_1[39:0]; // @[OneHot.scala:65:{12,27}] wire d_sel_0 = _d_sel_T_2[0]; // @[OneHot.scala:65:27] wire d_sel_1 = _d_sel_T_2[1]; // @[OneHot.scala:65:27] wire d_sel_2 = _d_sel_T_2[2]; // @[OneHot.scala:65:27] wire d_sel_3 = _d_sel_T_2[3]; // @[OneHot.scala:65:27] wire d_sel_4 = _d_sel_T_2[4]; // @[OneHot.scala:65:27] wire d_sel_5 = _d_sel_T_2[5]; // @[OneHot.scala:65:27] wire d_sel_6 = _d_sel_T_2[6]; // @[OneHot.scala:65:27] wire d_sel_7 = _d_sel_T_2[7]; // @[OneHot.scala:65:27] wire d_sel_8 = _d_sel_T_2[8]; // @[OneHot.scala:65:27] wire d_sel_9 = _d_sel_T_2[9]; // @[OneHot.scala:65:27] wire d_sel_10 = _d_sel_T_2[10]; // @[OneHot.scala:65:27] wire d_sel_11 = _d_sel_T_2[11]; // @[OneHot.scala:65:27] wire d_sel_12 = _d_sel_T_2[12]; // @[OneHot.scala:65:27] wire d_sel_13 = _d_sel_T_2[13]; // @[OneHot.scala:65:27] wire d_sel_14 = _d_sel_T_2[14]; // @[OneHot.scala:65:27] wire d_sel_15 = _d_sel_T_2[15]; // @[OneHot.scala:65:27] wire d_sel_16 = _d_sel_T_2[16]; // @[OneHot.scala:65:27] wire d_sel_17 = _d_sel_T_2[17]; // @[OneHot.scala:65:27] wire d_sel_18 = _d_sel_T_2[18]; // @[OneHot.scala:65:27] wire d_sel_19 = _d_sel_T_2[19]; // @[OneHot.scala:65:27] wire d_sel_20 = _d_sel_T_2[20]; // @[OneHot.scala:65:27] wire d_sel_21 = _d_sel_T_2[21]; // @[OneHot.scala:65:27] wire d_sel_22 = _d_sel_T_2[22]; // @[OneHot.scala:65:27] wire d_sel_23 = _d_sel_T_2[23]; // @[OneHot.scala:65:27] wire d_sel_24 = _d_sel_T_2[24]; // @[OneHot.scala:65:27] wire d_sel_25 = _d_sel_T_2[25]; // @[OneHot.scala:65:27] wire d_sel_26 = _d_sel_T_2[26]; // @[OneHot.scala:65:27] wire d_sel_27 = _d_sel_T_2[27]; // @[OneHot.scala:65:27] wire d_sel_28 = _d_sel_T_2[28]; // @[OneHot.scala:65:27] wire d_sel_29 = _d_sel_T_2[29]; // @[OneHot.scala:65:27] wire d_sel_30 = _d_sel_T_2[30]; // @[OneHot.scala:65:27] wire d_sel_31 = _d_sel_T_2[31]; // @[OneHot.scala:65:27] wire d_sel_32 = _d_sel_T_2[32]; // @[OneHot.scala:65:27] wire d_sel_33 = _d_sel_T_2[33]; // @[OneHot.scala:65:27] wire d_sel_34 = _d_sel_T_2[34]; // @[OneHot.scala:65:27] wire d_sel_35 = _d_sel_T_2[35]; // @[OneHot.scala:65:27] wire d_sel_36 = _d_sel_T_2[36]; // @[OneHot.scala:65:27] wire d_sel_37 = _d_sel_T_2[37]; // @[OneHot.scala:65:27] wire d_sel_38 = _d_sel_T_2[38]; // @[OneHot.scala:65:27] wire d_sel_39 = _d_sel_T_2[39]; // @[OneHot.scala:65:27] wire d_last = ~r_wins | nodeOut_r_bits_last; // @[ToAXI4.scala:225:53, :262:23] reg count; // @[ToAXI4.scala:272:28] wire _idStall_0_T_2 = count; // @[ToAXI4.scala:272:28, :286:44] reg write; // @[ToAXI4.scala:273:24] wire idle = ~count; // @[ToAXI4.scala:272:28, :274:26] wire _GEN_2 = out_arw_ready & out_arw_valid; // @[Decoupled.scala:51:35] wire _inc_T; // @[Decoupled.scala:51:35] assign _inc_T = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_1; // @[Decoupled.scala:51:35] assign _inc_T_1 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_2; // @[Decoupled.scala:51:35] assign _inc_T_2 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_3; // @[Decoupled.scala:51:35] assign _inc_T_3 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_4; // @[Decoupled.scala:51:35] assign _inc_T_4 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_5; // @[Decoupled.scala:51:35] assign _inc_T_5 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_6; // @[Decoupled.scala:51:35] assign _inc_T_6 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_7; // @[Decoupled.scala:51:35] assign _inc_T_7 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_8; // @[Decoupled.scala:51:35] assign _inc_T_8 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_9; // @[Decoupled.scala:51:35] assign _inc_T_9 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_10; // @[Decoupled.scala:51:35] assign _inc_T_10 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_11; // @[Decoupled.scala:51:35] assign _inc_T_11 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_12; // @[Decoupled.scala:51:35] assign _inc_T_12 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_13; // @[Decoupled.scala:51:35] assign _inc_T_13 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_14; // @[Decoupled.scala:51:35] assign _inc_T_14 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_15; // @[Decoupled.scala:51:35] assign _inc_T_15 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_16; // @[Decoupled.scala:51:35] assign _inc_T_16 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_17; // @[Decoupled.scala:51:35] assign _inc_T_17 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_18; // @[Decoupled.scala:51:35] assign _inc_T_18 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_19; // @[Decoupled.scala:51:35] assign _inc_T_19 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_20; // @[Decoupled.scala:51:35] assign _inc_T_20 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_21; // @[Decoupled.scala:51:35] assign _inc_T_21 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_22; // @[Decoupled.scala:51:35] assign _inc_T_22 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_23; // @[Decoupled.scala:51:35] assign _inc_T_23 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_24; // @[Decoupled.scala:51:35] assign _inc_T_24 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_25; // @[Decoupled.scala:51:35] assign _inc_T_25 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_26; // @[Decoupled.scala:51:35] assign _inc_T_26 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_27; // @[Decoupled.scala:51:35] assign _inc_T_27 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_28; // @[Decoupled.scala:51:35] assign _inc_T_28 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_29; // @[Decoupled.scala:51:35] assign _inc_T_29 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_30; // @[Decoupled.scala:51:35] assign _inc_T_30 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_31; // @[Decoupled.scala:51:35] assign _inc_T_31 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_32; // @[Decoupled.scala:51:35] assign _inc_T_32 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_33; // @[Decoupled.scala:51:35] assign _inc_T_33 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_34; // @[Decoupled.scala:51:35] assign _inc_T_34 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_35; // @[Decoupled.scala:51:35] assign _inc_T_35 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_36; // @[Decoupled.scala:51:35] assign _inc_T_36 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_37; // @[Decoupled.scala:51:35] assign _inc_T_37 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_38; // @[Decoupled.scala:51:35] assign _inc_T_38 = _GEN_2; // @[Decoupled.scala:51:35] wire _inc_T_39; // @[Decoupled.scala:51:35] assign _inc_T_39 = _GEN_2; // @[Decoupled.scala:51:35] wire inc = a_sel_0 & _inc_T; // @[Decoupled.scala:51:35] wire _dec_T = d_sel_0 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire _GEN_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire _dec_T_1; // @[Decoupled.scala:51:35] assign _dec_T_1 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_3; // @[Decoupled.scala:51:35] assign _dec_T_3 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_5; // @[Decoupled.scala:51:35] assign _dec_T_5 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_7; // @[Decoupled.scala:51:35] assign _dec_T_7 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_9; // @[Decoupled.scala:51:35] assign _dec_T_9 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_11; // @[Decoupled.scala:51:35] assign _dec_T_11 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_13; // @[Decoupled.scala:51:35] assign _dec_T_13 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_15; // @[Decoupled.scala:51:35] assign _dec_T_15 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_17; // @[Decoupled.scala:51:35] assign _dec_T_17 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_19; // @[Decoupled.scala:51:35] assign _dec_T_19 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_21; // @[Decoupled.scala:51:35] assign _dec_T_21 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_23; // @[Decoupled.scala:51:35] assign _dec_T_23 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_25; // @[Decoupled.scala:51:35] assign _dec_T_25 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_27; // @[Decoupled.scala:51:35] assign _dec_T_27 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_29; // @[Decoupled.scala:51:35] assign _dec_T_29 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_31; // @[Decoupled.scala:51:35] assign _dec_T_31 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_33; // @[Decoupled.scala:51:35] assign _dec_T_33 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_35; // @[Decoupled.scala:51:35] assign _dec_T_35 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_37; // @[Decoupled.scala:51:35] assign _dec_T_37 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_39; // @[Decoupled.scala:51:35] assign _dec_T_39 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_41; // @[Decoupled.scala:51:35] assign _dec_T_41 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_43; // @[Decoupled.scala:51:35] assign _dec_T_43 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_45; // @[Decoupled.scala:51:35] assign _dec_T_45 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_47; // @[Decoupled.scala:51:35] assign _dec_T_47 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_49; // @[Decoupled.scala:51:35] assign _dec_T_49 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_51; // @[Decoupled.scala:51:35] assign _dec_T_51 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_53; // @[Decoupled.scala:51:35] assign _dec_T_53 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_55; // @[Decoupled.scala:51:35] assign _dec_T_55 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_57; // @[Decoupled.scala:51:35] assign _dec_T_57 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_59; // @[Decoupled.scala:51:35] assign _dec_T_59 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_61; // @[Decoupled.scala:51:35] assign _dec_T_61 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_63; // @[Decoupled.scala:51:35] assign _dec_T_63 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_65; // @[Decoupled.scala:51:35] assign _dec_T_65 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_67; // @[Decoupled.scala:51:35] assign _dec_T_67 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_69; // @[Decoupled.scala:51:35] assign _dec_T_69 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_71; // @[Decoupled.scala:51:35] assign _dec_T_71 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_73; // @[Decoupled.scala:51:35] assign _dec_T_73 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_75; // @[Decoupled.scala:51:35] assign _dec_T_75 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_77; // @[Decoupled.scala:51:35] assign _dec_T_77 = _GEN_3; // @[Decoupled.scala:51:35] wire _dec_T_79; // @[Decoupled.scala:51:35] assign _dec_T_79 = _GEN_3; // @[Decoupled.scala:51:35] wire dec = _dec_T & _dec_T_1; // @[Decoupled.scala:51:35] wire [1:0] _count_T = {1'h0, count} + {1'h0, inc}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_1 = _count_T[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_2 = {1'h0, _count_T_1} - {1'h0, dec}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_3 = _count_T_2[0]; // @[ToAXI4.scala:278:37] wire _idStall_0_T = ~idle; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_0_T_3 = _idStall_0_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_0 = _idStall_0_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_1; // @[ToAXI4.scala:272:28] wire _idStall_1_T_2 = count_1; // @[ToAXI4.scala:272:28, :286:44] reg write_1; // @[ToAXI4.scala:273:24] wire idle_1 = ~count_1; // @[ToAXI4.scala:272:28, :274:26] wire inc_1 = a_sel_1 & _inc_T_1; // @[Decoupled.scala:51:35] wire _dec_T_2 = d_sel_1 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_1 = _dec_T_2 & _dec_T_3; // @[Decoupled.scala:51:35] wire [1:0] _count_T_4 = {1'h0, count_1} + {1'h0, inc_1}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_5 = _count_T_4[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_6 = {1'h0, _count_T_5} - {1'h0, dec_1}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_7 = _count_T_6[0]; // @[ToAXI4.scala:278:37] wire _idStall_1_T = ~idle_1; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_1_T_3 = _idStall_1_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_1 = _idStall_1_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_2; // @[ToAXI4.scala:272:28] wire _idStall_2_T_2 = count_2; // @[ToAXI4.scala:272:28, :286:44] reg write_2; // @[ToAXI4.scala:273:24] wire idle_2 = ~count_2; // @[ToAXI4.scala:272:28, :274:26] wire inc_2 = a_sel_2 & _inc_T_2; // @[Decoupled.scala:51:35] wire _dec_T_4 = d_sel_2 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_2 = _dec_T_4 & _dec_T_5; // @[Decoupled.scala:51:35] wire [1:0] _count_T_8 = {1'h0, count_2} + {1'h0, inc_2}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_9 = _count_T_8[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_10 = {1'h0, _count_T_9} - {1'h0, dec_2}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_11 = _count_T_10[0]; // @[ToAXI4.scala:278:37] wire _idStall_2_T = ~idle_2; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_2_T_3 = _idStall_2_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_2 = _idStall_2_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_3; // @[ToAXI4.scala:272:28] wire _idStall_3_T_2 = count_3; // @[ToAXI4.scala:272:28, :286:44] reg write_3; // @[ToAXI4.scala:273:24] wire idle_3 = ~count_3; // @[ToAXI4.scala:272:28, :274:26] wire inc_3 = a_sel_3 & _inc_T_3; // @[Decoupled.scala:51:35] wire _dec_T_6 = d_sel_3 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_3 = _dec_T_6 & _dec_T_7; // @[Decoupled.scala:51:35] wire [1:0] _count_T_12 = {1'h0, count_3} + {1'h0, inc_3}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_13 = _count_T_12[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_14 = {1'h0, _count_T_13} - {1'h0, dec_3}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_15 = _count_T_14[0]; // @[ToAXI4.scala:278:37] wire _idStall_3_T = ~idle_3; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_3_T_3 = _idStall_3_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_3 = _idStall_3_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_4; // @[ToAXI4.scala:272:28] wire _idStall_4_T_2 = count_4; // @[ToAXI4.scala:272:28, :286:44] reg write_4; // @[ToAXI4.scala:273:24] wire idle_4 = ~count_4; // @[ToAXI4.scala:272:28, :274:26] wire inc_4 = a_sel_4 & _inc_T_4; // @[Decoupled.scala:51:35] wire _dec_T_8 = d_sel_4 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_4 = _dec_T_8 & _dec_T_9; // @[Decoupled.scala:51:35] wire [1:0] _count_T_16 = {1'h0, count_4} + {1'h0, inc_4}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_17 = _count_T_16[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_18 = {1'h0, _count_T_17} - {1'h0, dec_4}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_19 = _count_T_18[0]; // @[ToAXI4.scala:278:37] wire _idStall_4_T = ~idle_4; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_4_T_3 = _idStall_4_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_4 = _idStall_4_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_5; // @[ToAXI4.scala:272:28] wire _idStall_5_T_2 = count_5; // @[ToAXI4.scala:272:28, :286:44] reg write_5; // @[ToAXI4.scala:273:24] wire idle_5 = ~count_5; // @[ToAXI4.scala:272:28, :274:26] wire inc_5 = a_sel_5 & _inc_T_5; // @[Decoupled.scala:51:35] wire _dec_T_10 = d_sel_5 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_5 = _dec_T_10 & _dec_T_11; // @[Decoupled.scala:51:35] wire [1:0] _count_T_20 = {1'h0, count_5} + {1'h0, inc_5}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_21 = _count_T_20[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_22 = {1'h0, _count_T_21} - {1'h0, dec_5}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_23 = _count_T_22[0]; // @[ToAXI4.scala:278:37] wire _idStall_5_T = ~idle_5; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_5_T_3 = _idStall_5_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_5 = _idStall_5_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_6; // @[ToAXI4.scala:272:28] wire _idStall_6_T_2 = count_6; // @[ToAXI4.scala:272:28, :286:44] reg write_6; // @[ToAXI4.scala:273:24] wire idle_6 = ~count_6; // @[ToAXI4.scala:272:28, :274:26] wire inc_6 = a_sel_6 & _inc_T_6; // @[Decoupled.scala:51:35] wire _dec_T_12 = d_sel_6 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_6 = _dec_T_12 & _dec_T_13; // @[Decoupled.scala:51:35] wire [1:0] _count_T_24 = {1'h0, count_6} + {1'h0, inc_6}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_25 = _count_T_24[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_26 = {1'h0, _count_T_25} - {1'h0, dec_6}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_27 = _count_T_26[0]; // @[ToAXI4.scala:278:37] wire _idStall_6_T = ~idle_6; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_6_T_3 = _idStall_6_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_6 = _idStall_6_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_7; // @[ToAXI4.scala:272:28] wire _idStall_7_T_2 = count_7; // @[ToAXI4.scala:272:28, :286:44] reg write_7; // @[ToAXI4.scala:273:24] wire idle_7 = ~count_7; // @[ToAXI4.scala:272:28, :274:26] wire inc_7 = a_sel_7 & _inc_T_7; // @[Decoupled.scala:51:35] wire _dec_T_14 = d_sel_7 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_7 = _dec_T_14 & _dec_T_15; // @[Decoupled.scala:51:35] wire [1:0] _count_T_28 = {1'h0, count_7} + {1'h0, inc_7}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_29 = _count_T_28[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_30 = {1'h0, _count_T_29} - {1'h0, dec_7}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_31 = _count_T_30[0]; // @[ToAXI4.scala:278:37] wire _idStall_7_T = ~idle_7; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_7_T_3 = _idStall_7_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_7 = _idStall_7_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_8; // @[ToAXI4.scala:272:28] wire _idStall_8_T_2 = count_8; // @[ToAXI4.scala:272:28, :286:44] reg write_8; // @[ToAXI4.scala:273:24] wire idle_8 = ~count_8; // @[ToAXI4.scala:272:28, :274:26] wire inc_8 = a_sel_8 & _inc_T_8; // @[Decoupled.scala:51:35] wire _dec_T_16 = d_sel_8 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_8 = _dec_T_16 & _dec_T_17; // @[Decoupled.scala:51:35] wire [1:0] _count_T_32 = {1'h0, count_8} + {1'h0, inc_8}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_33 = _count_T_32[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_34 = {1'h0, _count_T_33} - {1'h0, dec_8}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_35 = _count_T_34[0]; // @[ToAXI4.scala:278:37] wire _idStall_8_T = ~idle_8; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_8_T_3 = _idStall_8_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_8 = _idStall_8_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_9; // @[ToAXI4.scala:272:28] wire _idStall_9_T_2 = count_9; // @[ToAXI4.scala:272:28, :286:44] reg write_9; // @[ToAXI4.scala:273:24] wire idle_9 = ~count_9; // @[ToAXI4.scala:272:28, :274:26] wire inc_9 = a_sel_9 & _inc_T_9; // @[Decoupled.scala:51:35] wire _dec_T_18 = d_sel_9 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_9 = _dec_T_18 & _dec_T_19; // @[Decoupled.scala:51:35] wire [1:0] _count_T_36 = {1'h0, count_9} + {1'h0, inc_9}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_37 = _count_T_36[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_38 = {1'h0, _count_T_37} - {1'h0, dec_9}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_39 = _count_T_38[0]; // @[ToAXI4.scala:278:37] wire _idStall_9_T = ~idle_9; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_9_T_3 = _idStall_9_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_9 = _idStall_9_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_10; // @[ToAXI4.scala:272:28] wire _idStall_10_T_2 = count_10; // @[ToAXI4.scala:272:28, :286:44] reg write_10; // @[ToAXI4.scala:273:24] wire idle_10 = ~count_10; // @[ToAXI4.scala:272:28, :274:26] wire inc_10 = a_sel_10 & _inc_T_10; // @[Decoupled.scala:51:35] wire _dec_T_20 = d_sel_10 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_10 = _dec_T_20 & _dec_T_21; // @[Decoupled.scala:51:35] wire [1:0] _count_T_40 = {1'h0, count_10} + {1'h0, inc_10}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_41 = _count_T_40[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_42 = {1'h0, _count_T_41} - {1'h0, dec_10}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_43 = _count_T_42[0]; // @[ToAXI4.scala:278:37] wire _idStall_10_T = ~idle_10; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_10_T_3 = _idStall_10_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_10 = _idStall_10_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_11; // @[ToAXI4.scala:272:28] wire _idStall_11_T_2 = count_11; // @[ToAXI4.scala:272:28, :286:44] reg write_11; // @[ToAXI4.scala:273:24] wire idle_11 = ~count_11; // @[ToAXI4.scala:272:28, :274:26] wire inc_11 = a_sel_11 & _inc_T_11; // @[Decoupled.scala:51:35] wire _dec_T_22 = d_sel_11 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_11 = _dec_T_22 & _dec_T_23; // @[Decoupled.scala:51:35] wire [1:0] _count_T_44 = {1'h0, count_11} + {1'h0, inc_11}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_45 = _count_T_44[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_46 = {1'h0, _count_T_45} - {1'h0, dec_11}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_47 = _count_T_46[0]; // @[ToAXI4.scala:278:37] wire _idStall_11_T = ~idle_11; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_11_T_3 = _idStall_11_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_11 = _idStall_11_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_12; // @[ToAXI4.scala:272:28] wire _idStall_12_T_2 = count_12; // @[ToAXI4.scala:272:28, :286:44] reg write_12; // @[ToAXI4.scala:273:24] wire idle_12 = ~count_12; // @[ToAXI4.scala:272:28, :274:26] wire inc_12 = a_sel_12 & _inc_T_12; // @[Decoupled.scala:51:35] wire _dec_T_24 = d_sel_12 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_12 = _dec_T_24 & _dec_T_25; // @[Decoupled.scala:51:35] wire [1:0] _count_T_48 = {1'h0, count_12} + {1'h0, inc_12}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_49 = _count_T_48[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_50 = {1'h0, _count_T_49} - {1'h0, dec_12}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_51 = _count_T_50[0]; // @[ToAXI4.scala:278:37] wire _idStall_12_T = ~idle_12; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_12_T_3 = _idStall_12_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_12 = _idStall_12_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_13; // @[ToAXI4.scala:272:28] wire _idStall_13_T_2 = count_13; // @[ToAXI4.scala:272:28, :286:44] reg write_13; // @[ToAXI4.scala:273:24] wire idle_13 = ~count_13; // @[ToAXI4.scala:272:28, :274:26] wire inc_13 = a_sel_13 & _inc_T_13; // @[Decoupled.scala:51:35] wire _dec_T_26 = d_sel_13 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_13 = _dec_T_26 & _dec_T_27; // @[Decoupled.scala:51:35] wire [1:0] _count_T_52 = {1'h0, count_13} + {1'h0, inc_13}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_53 = _count_T_52[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_54 = {1'h0, _count_T_53} - {1'h0, dec_13}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_55 = _count_T_54[0]; // @[ToAXI4.scala:278:37] wire _idStall_13_T = ~idle_13; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_13_T_3 = _idStall_13_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_13 = _idStall_13_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_14; // @[ToAXI4.scala:272:28] wire _idStall_14_T_2 = count_14; // @[ToAXI4.scala:272:28, :286:44] reg write_14; // @[ToAXI4.scala:273:24] wire idle_14 = ~count_14; // @[ToAXI4.scala:272:28, :274:26] wire inc_14 = a_sel_14 & _inc_T_14; // @[Decoupled.scala:51:35] wire _dec_T_28 = d_sel_14 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_14 = _dec_T_28 & _dec_T_29; // @[Decoupled.scala:51:35] wire [1:0] _count_T_56 = {1'h0, count_14} + {1'h0, inc_14}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_57 = _count_T_56[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_58 = {1'h0, _count_T_57} - {1'h0, dec_14}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_59 = _count_T_58[0]; // @[ToAXI4.scala:278:37] wire _idStall_14_T = ~idle_14; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_14_T_3 = _idStall_14_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_14 = _idStall_14_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_15; // @[ToAXI4.scala:272:28] wire _idStall_15_T_2 = count_15; // @[ToAXI4.scala:272:28, :286:44] reg write_15; // @[ToAXI4.scala:273:24] wire idle_15 = ~count_15; // @[ToAXI4.scala:272:28, :274:26] wire inc_15 = a_sel_15 & _inc_T_15; // @[Decoupled.scala:51:35] wire _dec_T_30 = d_sel_15 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_15 = _dec_T_30 & _dec_T_31; // @[Decoupled.scala:51:35] wire [1:0] _count_T_60 = {1'h0, count_15} + {1'h0, inc_15}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_61 = _count_T_60[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_62 = {1'h0, _count_T_61} - {1'h0, dec_15}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_63 = _count_T_62[0]; // @[ToAXI4.scala:278:37] wire _idStall_15_T = ~idle_15; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_15_T_3 = _idStall_15_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_15 = _idStall_15_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_16; // @[ToAXI4.scala:272:28] wire _idStall_16_T_2 = count_16; // @[ToAXI4.scala:272:28, :286:44] reg write_16; // @[ToAXI4.scala:273:24] wire idle_16 = ~count_16; // @[ToAXI4.scala:272:28, :274:26] wire inc_16 = a_sel_16 & _inc_T_16; // @[Decoupled.scala:51:35] wire _dec_T_32 = d_sel_16 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_16 = _dec_T_32 & _dec_T_33; // @[Decoupled.scala:51:35] wire [1:0] _count_T_64 = {1'h0, count_16} + {1'h0, inc_16}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_65 = _count_T_64[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_66 = {1'h0, _count_T_65} - {1'h0, dec_16}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_67 = _count_T_66[0]; // @[ToAXI4.scala:278:37] wire _idStall_16_T = ~idle_16; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_16_T_3 = _idStall_16_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_16 = _idStall_16_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_17; // @[ToAXI4.scala:272:28] wire _idStall_17_T_2 = count_17; // @[ToAXI4.scala:272:28, :286:44] reg write_17; // @[ToAXI4.scala:273:24] wire idle_17 = ~count_17; // @[ToAXI4.scala:272:28, :274:26] wire inc_17 = a_sel_17 & _inc_T_17; // @[Decoupled.scala:51:35] wire _dec_T_34 = d_sel_17 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_17 = _dec_T_34 & _dec_T_35; // @[Decoupled.scala:51:35] wire [1:0] _count_T_68 = {1'h0, count_17} + {1'h0, inc_17}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_69 = _count_T_68[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_70 = {1'h0, _count_T_69} - {1'h0, dec_17}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_71 = _count_T_70[0]; // @[ToAXI4.scala:278:37] wire _idStall_17_T = ~idle_17; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_17_T_3 = _idStall_17_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_17 = _idStall_17_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_18; // @[ToAXI4.scala:272:28] wire _idStall_18_T_2 = count_18; // @[ToAXI4.scala:272:28, :286:44] reg write_18; // @[ToAXI4.scala:273:24] wire idle_18 = ~count_18; // @[ToAXI4.scala:272:28, :274:26] wire inc_18 = a_sel_18 & _inc_T_18; // @[Decoupled.scala:51:35] wire _dec_T_36 = d_sel_18 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_18 = _dec_T_36 & _dec_T_37; // @[Decoupled.scala:51:35] wire [1:0] _count_T_72 = {1'h0, count_18} + {1'h0, inc_18}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_73 = _count_T_72[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_74 = {1'h0, _count_T_73} - {1'h0, dec_18}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_75 = _count_T_74[0]; // @[ToAXI4.scala:278:37] wire _idStall_18_T = ~idle_18; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_18_T_3 = _idStall_18_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_18 = _idStall_18_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_19; // @[ToAXI4.scala:272:28] wire _idStall_19_T_2 = count_19; // @[ToAXI4.scala:272:28, :286:44] reg write_19; // @[ToAXI4.scala:273:24] wire idle_19 = ~count_19; // @[ToAXI4.scala:272:28, :274:26] wire inc_19 = a_sel_19 & _inc_T_19; // @[Decoupled.scala:51:35] wire _dec_T_38 = d_sel_19 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_19 = _dec_T_38 & _dec_T_39; // @[Decoupled.scala:51:35] wire [1:0] _count_T_76 = {1'h0, count_19} + {1'h0, inc_19}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_77 = _count_T_76[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_78 = {1'h0, _count_T_77} - {1'h0, dec_19}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_79 = _count_T_78[0]; // @[ToAXI4.scala:278:37] wire _idStall_19_T = ~idle_19; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_19_T_3 = _idStall_19_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_19 = _idStall_19_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_20; // @[ToAXI4.scala:272:28] wire _idStall_20_T_2 = count_20; // @[ToAXI4.scala:272:28, :286:44] reg write_20; // @[ToAXI4.scala:273:24] wire idle_20 = ~count_20; // @[ToAXI4.scala:272:28, :274:26] wire inc_20 = a_sel_20 & _inc_T_20; // @[Decoupled.scala:51:35] wire _dec_T_40 = d_sel_20 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_20 = _dec_T_40 & _dec_T_41; // @[Decoupled.scala:51:35] wire [1:0] _count_T_80 = {1'h0, count_20} + {1'h0, inc_20}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_81 = _count_T_80[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_82 = {1'h0, _count_T_81} - {1'h0, dec_20}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_83 = _count_T_82[0]; // @[ToAXI4.scala:278:37] wire _idStall_20_T = ~idle_20; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_20_T_3 = _idStall_20_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_20 = _idStall_20_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_21; // @[ToAXI4.scala:272:28] wire _idStall_21_T_2 = count_21; // @[ToAXI4.scala:272:28, :286:44] reg write_21; // @[ToAXI4.scala:273:24] wire idle_21 = ~count_21; // @[ToAXI4.scala:272:28, :274:26] wire inc_21 = a_sel_21 & _inc_T_21; // @[Decoupled.scala:51:35] wire _dec_T_42 = d_sel_21 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_21 = _dec_T_42 & _dec_T_43; // @[Decoupled.scala:51:35] wire [1:0] _count_T_84 = {1'h0, count_21} + {1'h0, inc_21}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_85 = _count_T_84[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_86 = {1'h0, _count_T_85} - {1'h0, dec_21}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_87 = _count_T_86[0]; // @[ToAXI4.scala:278:37] wire _idStall_21_T = ~idle_21; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_21_T_3 = _idStall_21_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_21 = _idStall_21_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_22; // @[ToAXI4.scala:272:28] wire _idStall_22_T_2 = count_22; // @[ToAXI4.scala:272:28, :286:44] reg write_22; // @[ToAXI4.scala:273:24] wire idle_22 = ~count_22; // @[ToAXI4.scala:272:28, :274:26] wire inc_22 = a_sel_22 & _inc_T_22; // @[Decoupled.scala:51:35] wire _dec_T_44 = d_sel_22 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_22 = _dec_T_44 & _dec_T_45; // @[Decoupled.scala:51:35] wire [1:0] _count_T_88 = {1'h0, count_22} + {1'h0, inc_22}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_89 = _count_T_88[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_90 = {1'h0, _count_T_89} - {1'h0, dec_22}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_91 = _count_T_90[0]; // @[ToAXI4.scala:278:37] wire _idStall_22_T = ~idle_22; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_22_T_3 = _idStall_22_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_22 = _idStall_22_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_23; // @[ToAXI4.scala:272:28] wire _idStall_23_T_2 = count_23; // @[ToAXI4.scala:272:28, :286:44] reg write_23; // @[ToAXI4.scala:273:24] wire idle_23 = ~count_23; // @[ToAXI4.scala:272:28, :274:26] wire inc_23 = a_sel_23 & _inc_T_23; // @[Decoupled.scala:51:35] wire _dec_T_46 = d_sel_23 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_23 = _dec_T_46 & _dec_T_47; // @[Decoupled.scala:51:35] wire [1:0] _count_T_92 = {1'h0, count_23} + {1'h0, inc_23}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_93 = _count_T_92[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_94 = {1'h0, _count_T_93} - {1'h0, dec_23}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_95 = _count_T_94[0]; // @[ToAXI4.scala:278:37] wire _idStall_23_T = ~idle_23; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_23_T_3 = _idStall_23_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_23 = _idStall_23_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_24; // @[ToAXI4.scala:272:28] wire _idStall_24_T_2 = count_24; // @[ToAXI4.scala:272:28, :286:44] reg write_24; // @[ToAXI4.scala:273:24] wire idle_24 = ~count_24; // @[ToAXI4.scala:272:28, :274:26] wire inc_24 = a_sel_24 & _inc_T_24; // @[Decoupled.scala:51:35] wire _dec_T_48 = d_sel_24 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_24 = _dec_T_48 & _dec_T_49; // @[Decoupled.scala:51:35] wire [1:0] _count_T_96 = {1'h0, count_24} + {1'h0, inc_24}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_97 = _count_T_96[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_98 = {1'h0, _count_T_97} - {1'h0, dec_24}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_99 = _count_T_98[0]; // @[ToAXI4.scala:278:37] wire _idStall_24_T = ~idle_24; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_24_T_3 = _idStall_24_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_24 = _idStall_24_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_25; // @[ToAXI4.scala:272:28] wire _idStall_25_T_2 = count_25; // @[ToAXI4.scala:272:28, :286:44] reg write_25; // @[ToAXI4.scala:273:24] wire idle_25 = ~count_25; // @[ToAXI4.scala:272:28, :274:26] wire inc_25 = a_sel_25 & _inc_T_25; // @[Decoupled.scala:51:35] wire _dec_T_50 = d_sel_25 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_25 = _dec_T_50 & _dec_T_51; // @[Decoupled.scala:51:35] wire [1:0] _count_T_100 = {1'h0, count_25} + {1'h0, inc_25}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_101 = _count_T_100[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_102 = {1'h0, _count_T_101} - {1'h0, dec_25}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_103 = _count_T_102[0]; // @[ToAXI4.scala:278:37] wire _idStall_25_T = ~idle_25; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_25_T_3 = _idStall_25_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_25 = _idStall_25_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_26; // @[ToAXI4.scala:272:28] wire _idStall_26_T_2 = count_26; // @[ToAXI4.scala:272:28, :286:44] reg write_26; // @[ToAXI4.scala:273:24] wire idle_26 = ~count_26; // @[ToAXI4.scala:272:28, :274:26] wire inc_26 = a_sel_26 & _inc_T_26; // @[Decoupled.scala:51:35] wire _dec_T_52 = d_sel_26 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_26 = _dec_T_52 & _dec_T_53; // @[Decoupled.scala:51:35] wire [1:0] _count_T_104 = {1'h0, count_26} + {1'h0, inc_26}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_105 = _count_T_104[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_106 = {1'h0, _count_T_105} - {1'h0, dec_26}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_107 = _count_T_106[0]; // @[ToAXI4.scala:278:37] wire _idStall_26_T = ~idle_26; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_26_T_3 = _idStall_26_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_26 = _idStall_26_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_27; // @[ToAXI4.scala:272:28] wire _idStall_27_T_2 = count_27; // @[ToAXI4.scala:272:28, :286:44] reg write_27; // @[ToAXI4.scala:273:24] wire idle_27 = ~count_27; // @[ToAXI4.scala:272:28, :274:26] wire inc_27 = a_sel_27 & _inc_T_27; // @[Decoupled.scala:51:35] wire _dec_T_54 = d_sel_27 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_27 = _dec_T_54 & _dec_T_55; // @[Decoupled.scala:51:35] wire [1:0] _count_T_108 = {1'h0, count_27} + {1'h0, inc_27}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_109 = _count_T_108[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_110 = {1'h0, _count_T_109} - {1'h0, dec_27}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_111 = _count_T_110[0]; // @[ToAXI4.scala:278:37] wire _idStall_27_T = ~idle_27; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_27_T_3 = _idStall_27_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_27 = _idStall_27_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_28; // @[ToAXI4.scala:272:28] wire _idStall_28_T_2 = count_28; // @[ToAXI4.scala:272:28, :286:44] reg write_28; // @[ToAXI4.scala:273:24] wire idle_28 = ~count_28; // @[ToAXI4.scala:272:28, :274:26] wire inc_28 = a_sel_28 & _inc_T_28; // @[Decoupled.scala:51:35] wire _dec_T_56 = d_sel_28 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_28 = _dec_T_56 & _dec_T_57; // @[Decoupled.scala:51:35] wire [1:0] _count_T_112 = {1'h0, count_28} + {1'h0, inc_28}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_113 = _count_T_112[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_114 = {1'h0, _count_T_113} - {1'h0, dec_28}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_115 = _count_T_114[0]; // @[ToAXI4.scala:278:37] wire _idStall_28_T = ~idle_28; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_28_T_3 = _idStall_28_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_28 = _idStall_28_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_29; // @[ToAXI4.scala:272:28] wire _idStall_29_T_2 = count_29; // @[ToAXI4.scala:272:28, :286:44] reg write_29; // @[ToAXI4.scala:273:24] wire idle_29 = ~count_29; // @[ToAXI4.scala:272:28, :274:26] wire inc_29 = a_sel_29 & _inc_T_29; // @[Decoupled.scala:51:35] wire _dec_T_58 = d_sel_29 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_29 = _dec_T_58 & _dec_T_59; // @[Decoupled.scala:51:35] wire [1:0] _count_T_116 = {1'h0, count_29} + {1'h0, inc_29}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_117 = _count_T_116[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_118 = {1'h0, _count_T_117} - {1'h0, dec_29}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_119 = _count_T_118[0]; // @[ToAXI4.scala:278:37] wire _idStall_29_T = ~idle_29; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_29_T_3 = _idStall_29_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_29 = _idStall_29_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_30; // @[ToAXI4.scala:272:28] wire _idStall_30_T_2 = count_30; // @[ToAXI4.scala:272:28, :286:44] reg write_30; // @[ToAXI4.scala:273:24] wire idle_30 = ~count_30; // @[ToAXI4.scala:272:28, :274:26] wire inc_30 = a_sel_30 & _inc_T_30; // @[Decoupled.scala:51:35] wire _dec_T_60 = d_sel_30 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_30 = _dec_T_60 & _dec_T_61; // @[Decoupled.scala:51:35] wire [1:0] _count_T_120 = {1'h0, count_30} + {1'h0, inc_30}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_121 = _count_T_120[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_122 = {1'h0, _count_T_121} - {1'h0, dec_30}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_123 = _count_T_122[0]; // @[ToAXI4.scala:278:37] wire _idStall_30_T = ~idle_30; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_30_T_3 = _idStall_30_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_30 = _idStall_30_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_31; // @[ToAXI4.scala:272:28] wire _idStall_31_T_2 = count_31; // @[ToAXI4.scala:272:28, :286:44] reg write_31; // @[ToAXI4.scala:273:24] wire idle_31 = ~count_31; // @[ToAXI4.scala:272:28, :274:26] wire inc_31 = a_sel_31 & _inc_T_31; // @[Decoupled.scala:51:35] wire _dec_T_62 = d_sel_31 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_31 = _dec_T_62 & _dec_T_63; // @[Decoupled.scala:51:35] wire [1:0] _count_T_124 = {1'h0, count_31} + {1'h0, inc_31}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_125 = _count_T_124[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_126 = {1'h0, _count_T_125} - {1'h0, dec_31}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_127 = _count_T_126[0]; // @[ToAXI4.scala:278:37] wire _idStall_31_T = ~idle_31; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_31_T_3 = _idStall_31_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_31 = _idStall_31_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_32; // @[ToAXI4.scala:272:28] wire _idStall_32_T_2 = count_32; // @[ToAXI4.scala:272:28, :286:44] reg write_32; // @[ToAXI4.scala:273:24] wire idle_32 = ~count_32; // @[ToAXI4.scala:272:28, :274:26] wire inc_32 = a_sel_32 & _inc_T_32; // @[Decoupled.scala:51:35] wire _dec_T_64 = d_sel_32 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_32 = _dec_T_64 & _dec_T_65; // @[Decoupled.scala:51:35] wire [1:0] _count_T_128 = {1'h0, count_32} + {1'h0, inc_32}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_129 = _count_T_128[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_130 = {1'h0, _count_T_129} - {1'h0, dec_32}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_131 = _count_T_130[0]; // @[ToAXI4.scala:278:37] wire _idStall_32_T = ~idle_32; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_32_T_3 = _idStall_32_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_32 = _idStall_32_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_33; // @[ToAXI4.scala:272:28] wire _idStall_33_T_2 = count_33; // @[ToAXI4.scala:272:28, :286:44] reg write_33; // @[ToAXI4.scala:273:24] wire idle_33 = ~count_33; // @[ToAXI4.scala:272:28, :274:26] wire inc_33 = a_sel_33 & _inc_T_33; // @[Decoupled.scala:51:35] wire _dec_T_66 = d_sel_33 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_33 = _dec_T_66 & _dec_T_67; // @[Decoupled.scala:51:35] wire [1:0] _count_T_132 = {1'h0, count_33} + {1'h0, inc_33}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_133 = _count_T_132[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_134 = {1'h0, _count_T_133} - {1'h0, dec_33}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_135 = _count_T_134[0]; // @[ToAXI4.scala:278:37] wire _idStall_33_T = ~idle_33; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_33_T_3 = _idStall_33_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_33 = _idStall_33_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_34; // @[ToAXI4.scala:272:28] wire _idStall_34_T_2 = count_34; // @[ToAXI4.scala:272:28, :286:44] reg write_34; // @[ToAXI4.scala:273:24] wire idle_34 = ~count_34; // @[ToAXI4.scala:272:28, :274:26] wire inc_34 = a_sel_34 & _inc_T_34; // @[Decoupled.scala:51:35] wire _dec_T_68 = d_sel_34 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_34 = _dec_T_68 & _dec_T_69; // @[Decoupled.scala:51:35] wire [1:0] _count_T_136 = {1'h0, count_34} + {1'h0, inc_34}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_137 = _count_T_136[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_138 = {1'h0, _count_T_137} - {1'h0, dec_34}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_139 = _count_T_138[0]; // @[ToAXI4.scala:278:37] wire _idStall_34_T = ~idle_34; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_34_T_3 = _idStall_34_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_34 = _idStall_34_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_35; // @[ToAXI4.scala:272:28] wire _idStall_35_T_2 = count_35; // @[ToAXI4.scala:272:28, :286:44] reg write_35; // @[ToAXI4.scala:273:24] wire idle_35 = ~count_35; // @[ToAXI4.scala:272:28, :274:26] wire inc_35 = a_sel_35 & _inc_T_35; // @[Decoupled.scala:51:35] wire _dec_T_70 = d_sel_35 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_35 = _dec_T_70 & _dec_T_71; // @[Decoupled.scala:51:35] wire [1:0] _count_T_140 = {1'h0, count_35} + {1'h0, inc_35}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_141 = _count_T_140[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_142 = {1'h0, _count_T_141} - {1'h0, dec_35}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_143 = _count_T_142[0]; // @[ToAXI4.scala:278:37] wire _idStall_35_T = ~idle_35; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_35_T_3 = _idStall_35_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_35 = _idStall_35_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_36; // @[ToAXI4.scala:272:28] wire _idStall_36_T_2 = count_36; // @[ToAXI4.scala:272:28, :286:44] reg write_36; // @[ToAXI4.scala:273:24] wire idle_36 = ~count_36; // @[ToAXI4.scala:272:28, :274:26] wire inc_36 = a_sel_36 & _inc_T_36; // @[Decoupled.scala:51:35] wire _dec_T_72 = d_sel_36 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_36 = _dec_T_72 & _dec_T_73; // @[Decoupled.scala:51:35] wire [1:0] _count_T_144 = {1'h0, count_36} + {1'h0, inc_36}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_145 = _count_T_144[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_146 = {1'h0, _count_T_145} - {1'h0, dec_36}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_147 = _count_T_146[0]; // @[ToAXI4.scala:278:37] wire _idStall_36_T = ~idle_36; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_36_T_3 = _idStall_36_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_36 = _idStall_36_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_37; // @[ToAXI4.scala:272:28] wire _idStall_37_T_2 = count_37; // @[ToAXI4.scala:272:28, :286:44] reg write_37; // @[ToAXI4.scala:273:24] wire idle_37 = ~count_37; // @[ToAXI4.scala:272:28, :274:26] wire inc_37 = a_sel_37 & _inc_T_37; // @[Decoupled.scala:51:35] wire _dec_T_74 = d_sel_37 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_37 = _dec_T_74 & _dec_T_75; // @[Decoupled.scala:51:35] wire [1:0] _count_T_148 = {1'h0, count_37} + {1'h0, inc_37}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_149 = _count_T_148[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_150 = {1'h0, _count_T_149} - {1'h0, dec_37}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_151 = _count_T_150[0]; // @[ToAXI4.scala:278:37] wire _idStall_37_T = ~idle_37; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_37_T_3 = _idStall_37_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_37 = _idStall_37_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_38; // @[ToAXI4.scala:272:28] wire _idStall_38_T_2 = count_38; // @[ToAXI4.scala:272:28, :286:44] reg write_38; // @[ToAXI4.scala:273:24] wire idle_38 = ~count_38; // @[ToAXI4.scala:272:28, :274:26] wire inc_38 = a_sel_38 & _inc_T_38; // @[Decoupled.scala:51:35] wire _dec_T_76 = d_sel_38 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_38 = _dec_T_76 & _dec_T_77; // @[Decoupled.scala:51:35] wire [1:0] _count_T_152 = {1'h0, count_38} + {1'h0, inc_38}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_153 = _count_T_152[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_154 = {1'h0, _count_T_153} - {1'h0, dec_38}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_155 = _count_T_154[0]; // @[ToAXI4.scala:278:37] wire _idStall_38_T = ~idle_38; // @[ToAXI4.scala:274:26, :286:15] assign _idStall_38_T_3 = _idStall_38_T_2; // @[ToAXI4.scala:286:{34,44}] assign idStall_38 = _idStall_38_T_3; // @[ToAXI4.scala:115:32, :286:34] reg count_39; // @[ToAXI4.scala:272:28] wire _idStall_39_T_2 = count_39; // @[ToAXI4.scala:272:28, :286:44] reg write_39; // @[ToAXI4.scala:273:24] wire idle_39 = ~count_39; // @[ToAXI4.scala:272:28, :274:26] wire inc_39 = a_sel_39 & _inc_T_39; // @[Decoupled.scala:51:35] wire _dec_T_78 = d_sel_39 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22] wire dec_39 = _dec_T_78 & _dec_T_79; // @[Decoupled.scala:51:35] wire [1:0] _count_T_156 = {1'h0, count_39} + {1'h0, inc_39}; // @[ToAXI4.scala:272:28, :276:22, :278:24] wire _count_T_157 = _count_T_156[0]; // @[ToAXI4.scala:278:24] wire [1:0] _count_T_158 = {1'h0, _count_T_157} - {1'h0, dec_39}; // @[ToAXI4.scala:277:32, :278:{24,37}] wire _count_T_159 = _count_T_158[0]; // @[ToAXI4.scala:278:37]

Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulAddRecFNToRaw_postMul_e8_s24_6( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29] wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 | _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_184( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_194 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_110( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131073:0] _c_sizes_set_T_1 = 131074'h0; // @[Monitor.scala:768:52] wire [16:0] _c_opcodes_set_T = 17'h0; // @[Monitor.scala:767:79] wire [16:0] _c_sizes_set_T = 17'h0; // @[Monitor.scala:768:77] wire [131074:0] _c_opcodes_set_T_1 = 131075'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [16383:0] _c_set_wo_ready_T = 16384'h1; // @[OneHot.scala:58:35] wire [16383:0] _c_set_T = 16384'h1; // @[OneHot.scala:58:35] wire [32831:0] c_opcodes_set = 32832'h0; // @[Monitor.scala:740:34] wire [32831:0] c_sizes_set = 32832'h0; // @[Monitor.scala:741:34] wire [8207:0] c_set = 8208'h0; // @[Monitor.scala:738:34] wire [8207:0] c_set_wo_ready = 8208'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [13:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [13:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [13:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [13:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [13:0] source_1; // @[Monitor.scala:541:22] reg [8207:0] inflight; // @[Monitor.scala:614:27] reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [8207:0] a_set; // @[Monitor.scala:626:34] wire [8207:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [32831:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [32831:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [16:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [16:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [16:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [16:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [16:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [16:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [16:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [16:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [16:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [32831:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [32831:0] _a_opcode_lookup_T_6 = {32828'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [32831:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [32831:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [32831:0] _a_size_lookup_T_6 = {32828'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [32831:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[32831:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [16383:0] _GEN_2 = 16384'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [16383:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [16:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [16:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [16:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [131074:0] _a_opcodes_set_T_1 = {131071'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [131073:0] _a_sizes_set_T_1 = {131071'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8207:0] d_clr; // @[Monitor.scala:664:34] wire [8207:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [32831:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [32831:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [16383:0] _GEN_5 = 16384'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_5 = 131087'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [131086:0] _d_sizes_clr_T_5 = 131087'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8207:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8207:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8207:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [32831:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [32831:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [32831:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [32831:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [32831:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [32831:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8207:0] inflight_1; // @[Monitor.scala:726:35] wire [8207:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [32831:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [32831:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [32831:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [32831:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [32831:0] _c_opcode_lookup_T_6 = {32828'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [32831:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [32831:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [32831:0] _c_size_lookup_T_6 = {32828'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [32831:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[32831:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [8207:0] d_clr_1; // @[Monitor.scala:774:34] wire [8207:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [32831:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [32831:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_11 = 131087'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [131086:0] _d_sizes_clr_T_11 = 131087'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 14'h0; // @[Monitor.scala:36:7, :795:113] wire [8207:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8207:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [32831:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [32831:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [32831:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [32831:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_10( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_sizes_set = 32'h0; // @[Monitor.scala:741:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_set = 4'h0; // @[Monitor.scala:738:34] wire [3:0] c_set_wo_ready = 4'h0; // @[Monitor.scala:739:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [35:0] _c_sizes_set_T_1 = 36'h0; // @[Monitor.scala:768:52] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_T = 5'h0; // @[Monitor.scala:767:79] wire [4:0] _c_sizes_set_T = 5'h0; // @[Monitor.scala:768:77] wire [34:0] _c_opcodes_set_T_1 = 35'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_set_wo_ready_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_set_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] c_opcodes_set = 16'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [3:0] inflight; // @[Monitor.scala:614:27] reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [31:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] a_set; // @[Monitor.scala:626:34] wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [31:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_3 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_4 = 4'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [3:0] d_clr; // @[Monitor.scala:664:34] wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_6 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_7 = 4'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [3:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [15:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [31:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [3:0] inflight_1; // @[Monitor.scala:726:35] wire [3:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] d_clr_1; // @[Monitor.scala:774:34] wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7, :795:113] wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_259( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w4_d3_i0_21( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_209 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_210 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_211 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_212 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module Router_20( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_3_to_5_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_3_to_5_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_3_to_5_io_out_valid; // @[Router.scala:125:13] wire _output_unit_2_to_8_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_2_to_8_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_5_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_1_to_5_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _ingress_unit_2_from_5_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_2_from_5_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_5_io_in_ready; // @[Router.scala:116:13] wire _input_unit_1_from_8_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_1_from_8_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_5_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_8_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_5_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_56( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_76 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }

module IssueSlot_45( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } }

module NoCMonitor_121( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h1; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to the following Chisel files. File PMA.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters} class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val paddr = Input(UInt()) val resp = Output(new Bundle { val cacheable = Bool() val r = Bool() val w = Bool() val pp = Bool() val al = Bool() val aa = Bool() val x = Bool() val eff = Bool() }) }) // PMA // check exist a slave can consume this address. val legal_address = manager.findSafe(io.paddr).reduce(_||_) // check utility to help check SoC property. def fastCheck(member: TLManagerParameters => Boolean) = legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B) io.resp.cacheable := fastCheck(_.supportsAcquireB) io.resp.r := fastCheck(_.supportsGet) io.resp.w := fastCheck(_.supportsPutFull) io.resp.pp := fastCheck(_.supportsPutPartial) io.resp.al := fastCheck(_.supportsLogical) io.resp.aa := fastCheck(_.supportsArithmetic) io.resp.x := fastCheck(_.executable) io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }

module PMAChecker_2( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_65 = 1'h0; // @[Mux.scala:30:73] wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_37; // @[PMA.scala:39:19] wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_55; // @[PMA.scala:39:19] wire _io_resp_pp_T_55; // @[PMA.scala:39:19] wire _io_resp_al_T_55; // @[PMA.scala:39:19] wire _io_resp_aa_T_55; // @[PMA.scala:39:19] wire _io_resp_x_T_79; // @[PMA.scala:39:19] wire _io_resp_eff_T_67; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_41; // @[Parameters.scala:137:31] assign _io_resp_eff_T_41 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_47; // @[Parameters.scala:137:31] assign _io_resp_w_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_47; // @[Parameters.scala:137:31] assign _io_resp_pp_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_47; // @[Parameters.scala:137:31] assign _io_resp_al_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_47; // @[Parameters.scala:137:31] assign _io_resp_aa_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_46; // @[Parameters.scala:137:31] assign _io_resp_eff_T_46 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h20000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h21000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_30 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h22000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_35 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h23000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h24000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_50 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_60; // @[Parameters.scala:137:31] assign _legal_address_T_60 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_61 = {1'h0, _legal_address_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_62 = _legal_address_T_61 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_63 = _legal_address_T_62; // @[Parameters.scala:137:46] wire _legal_address_T_64 = _legal_address_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_12 = _legal_address_T_64; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_65; // @[Parameters.scala:137:31] assign _legal_address_T_65 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_23; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_23 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_51; // @[Parameters.scala:137:31] assign _io_resp_eff_T_51 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_66 = {1'h0, _legal_address_T_65}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_67 = _legal_address_T_66 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_68 = _legal_address_T_67; // @[Parameters.scala:137:46] wire _legal_address_T_69 = _legal_address_T_68 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_13 = _legal_address_T_69; // @[Parameters.scala:612:40] wire [39:0] _GEN_8 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_70; // @[Parameters.scala:137:31] assign _legal_address_T_70 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_15; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_15 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_59; // @[Parameters.scala:137:31] assign _io_resp_x_T_59 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_71 = {1'h0, _legal_address_T_70}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_72 = _legal_address_T_71 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_73 = _legal_address_T_72; // @[Parameters.scala:137:46] wire _legal_address_T_74 = _legal_address_T_73 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_14 = _legal_address_T_74; // @[Parameters.scala:612:40] wire [39:0] _GEN_9 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_75; // @[Parameters.scala:137:31] assign _legal_address_T_75 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_64; // @[Parameters.scala:137:31] assign _io_resp_x_T_64 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_30; // @[Parameters.scala:137:31] assign _io_resp_eff_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_76 = {1'h0, _legal_address_T_75}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_77 = _legal_address_T_76 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_78 = _legal_address_T_77; // @[Parameters.scala:137:46] wire _legal_address_T_79 = _legal_address_T_78 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_15 = _legal_address_T_79; // @[Parameters.scala:612:40] wire [39:0] _GEN_10 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_80; // @[Parameters.scala:137:31] assign _legal_address_T_80 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_28; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_28 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_35; // @[Parameters.scala:137:31] assign _io_resp_w_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_35; // @[Parameters.scala:137:31] assign _io_resp_pp_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_35; // @[Parameters.scala:137:31] assign _io_resp_al_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_35; // @[Parameters.scala:137:31] assign _io_resp_aa_T_35 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_56; // @[Parameters.scala:137:31] assign _io_resp_eff_T_56 = _GEN_10; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_81 = {1'h0, _legal_address_T_80}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_82 = _legal_address_T_81 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_83 = _legal_address_T_82; // @[Parameters.scala:137:46] wire _legal_address_T_84 = _legal_address_T_83 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_16 = _legal_address_T_84; // @[Parameters.scala:612:40] wire _legal_address_T_85 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_86 = _legal_address_T_85 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_87 = _legal_address_T_86 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_88 = _legal_address_T_87 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_89 = _legal_address_T_88 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_90 = _legal_address_T_89 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_91 = _legal_address_T_90 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_92 = _legal_address_T_91 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_93 = _legal_address_T_92 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_94 = _legal_address_T_93 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire _legal_address_T_95 = _legal_address_T_94 | _legal_address_WIRE_11; // @[Parameters.scala:612:40] wire _legal_address_T_96 = _legal_address_T_95 | _legal_address_WIRE_12; // @[Parameters.scala:612:40] wire _legal_address_T_97 = _legal_address_T_96 | _legal_address_WIRE_13; // @[Parameters.scala:612:40] wire _legal_address_T_98 = _legal_address_T_97 | _legal_address_WIRE_14; // @[Parameters.scala:612:40] wire _legal_address_T_99 = _legal_address_T_98 | _legal_address_WIRE_15; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_99 | _legal_address_WIRE_16; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C020000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C031000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C030000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_16 = {1'h0, _io_resp_cacheable_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_17 = _io_resp_cacheable_T_16 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_18 = _io_resp_cacheable_T_17; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_20 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_22 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_19; // @[Parameters.scala:629:89] wire [40:0] _io_resp_cacheable_T_24 = {1'h0, _io_resp_cacheable_T_23}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24 & 41'h8C030000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_26 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_29 = {1'h0, _io_resp_cacheable_T_28}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_31 = _io_resp_cacheable_T_30; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_32 = _io_resp_cacheable_T_31 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_33 = _io_resp_cacheable_T_27 | _io_resp_cacheable_T_32; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_35 = _io_resp_cacheable_T_33; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_36 = _io_resp_cacheable_T_35; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_36; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_37 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_37; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_36 = {1'h0, _io_resp_w_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_37 = _io_resp_w_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_38 = _io_resp_w_T_37; // @[Parameters.scala:137:46] wire _io_resp_w_T_39 = _io_resp_w_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_40 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_41 = _io_resp_w_T_40 | _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_42 = _io_resp_w_T_41 | _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_43 = _io_resp_w_T_42 | _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_44 = _io_resp_w_T_43 | _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_45 = _io_resp_w_T_44 | _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_45 | _io_resp_w_T_39; // @[Parameters.scala:629:89] wire _io_resp_w_T_52 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_w_T_48 = {1'h0, _io_resp_w_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_49 = _io_resp_w_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_50 = _io_resp_w_T_49; // @[Parameters.scala:137:46] wire _io_resp_w_T_51 = _io_resp_w_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_54 = _io_resp_w_T_52; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_54; // @[Mux.scala:30:73] assign _io_resp_w_T_55 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_36 = {1'h0, _io_resp_pp_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_37 = _io_resp_pp_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_38 = _io_resp_pp_T_37; // @[Parameters.scala:137:46] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_40 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_41 = _io_resp_pp_T_40 | _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_42 = _io_resp_pp_T_41 | _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_43 = _io_resp_pp_T_42 | _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_44 = _io_resp_pp_T_43 | _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 | _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_45 | _io_resp_pp_T_39; // @[Parameters.scala:629:89] wire _io_resp_pp_T_52 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_pp_T_48 = {1'h0, _io_resp_pp_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_49 = _io_resp_pp_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_50 = _io_resp_pp_T_49; // @[Parameters.scala:137:46] wire _io_resp_pp_T_51 = _io_resp_pp_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_54 = _io_resp_pp_T_52; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_54; // @[Mux.scala:30:73] assign _io_resp_pp_T_55 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_36 = {1'h0, _io_resp_al_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_37 = _io_resp_al_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_38 = _io_resp_al_T_37; // @[Parameters.scala:137:46] wire _io_resp_al_T_39 = _io_resp_al_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_40 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_41 = _io_resp_al_T_40 | _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_42 = _io_resp_al_T_41 | _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_43 = _io_resp_al_T_42 | _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_44 = _io_resp_al_T_43 | _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_45 = _io_resp_al_T_44 | _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_45 | _io_resp_al_T_39; // @[Parameters.scala:629:89] wire _io_resp_al_T_52 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_al_T_48 = {1'h0, _io_resp_al_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_49 = _io_resp_al_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_50 = _io_resp_al_T_49; // @[Parameters.scala:137:46] wire _io_resp_al_T_51 = _io_resp_al_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_54 = _io_resp_al_T_52; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_54; // @[Mux.scala:30:73] assign _io_resp_al_T_55 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_36 = {1'h0, _io_resp_aa_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_37 = _io_resp_aa_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_38 = _io_resp_aa_T_37; // @[Parameters.scala:137:46] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_40 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_41 = _io_resp_aa_T_40 | _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_42 = _io_resp_aa_T_41 | _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_43 = _io_resp_aa_T_42 | _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_44 = _io_resp_aa_T_43 | _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 | _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_45 | _io_resp_aa_T_39; // @[Parameters.scala:629:89] wire _io_resp_aa_T_52 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire [40:0] _io_resp_aa_T_48 = {1'h0, _io_resp_aa_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_49 = _io_resp_aa_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_50 = _io_resp_aa_T_49; // @[Parameters.scala:137:46] wire _io_resp_aa_T_51 = _io_resp_aa_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_54 = _io_resp_aa_T_52; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_54; // @[Mux.scala:30:73] assign _io_resp_aa_T_55 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_55; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_76 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'hFFFFC000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'hFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_60 = {1'h0, _io_resp_x_T_59}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_61 = _io_resp_x_T_60 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_62 = _io_resp_x_T_61; // @[Parameters.scala:137:46] wire _io_resp_x_T_63 = _io_resp_x_T_62 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_65 = {1'h0, _io_resp_x_T_64}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_66 = _io_resp_x_T_65 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_67 = _io_resp_x_T_66; // @[Parameters.scala:137:46] wire _io_resp_x_T_68 = _io_resp_x_T_67 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_69 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_70 = _io_resp_x_T_69 | _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_71 = _io_resp_x_T_70 | _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_72 = _io_resp_x_T_71 | _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_73 = _io_resp_x_T_72 | _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_74 = _io_resp_x_T_73 | _io_resp_x_T_63; // @[Parameters.scala:629:89] wire _io_resp_x_T_75 = _io_resp_x_T_74 | _io_resp_x_T_68; // @[Parameters.scala:629:89] wire _io_resp_x_T_78 = _io_resp_x_T_76; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_78; // @[Mux.scala:30:73] assign _io_resp_x_T_79 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_79; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'hFFFFA000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'hFFFF8000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'hFFFEB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_31 = {1'h0, _io_resp_eff_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_32 = _io_resp_eff_T_31 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_33 = _io_resp_eff_T_32; // @[Parameters.scala:137:46] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_35 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_36 = _io_resp_eff_T_35 | _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_37 = _io_resp_eff_T_36 | _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_38 = _io_resp_eff_T_37 | _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 | _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_40 = _io_resp_eff_T_39 | _io_resp_eff_T_34; // @[Parameters.scala:629:89] wire _io_resp_eff_T_64 = _io_resp_eff_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_eff_T_42 = {1'h0, _io_resp_eff_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_44 = _io_resp_eff_T_43; // @[Parameters.scala:137:46] wire _io_resp_eff_T_45 = _io_resp_eff_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_47 = {1'h0, _io_resp_eff_T_46}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_49 = _io_resp_eff_T_48; // @[Parameters.scala:137:46] wire _io_resp_eff_T_50 = _io_resp_eff_T_49 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_52 = {1'h0, _io_resp_eff_T_51}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_54 = _io_resp_eff_T_53; // @[Parameters.scala:137:46] wire _io_resp_eff_T_55 = _io_resp_eff_T_54 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_57 = {1'h0, _io_resp_eff_T_56}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_58 = _io_resp_eff_T_57 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_59 = _io_resp_eff_T_58; // @[Parameters.scala:137:46] wire _io_resp_eff_T_60 = _io_resp_eff_T_59 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_61 = _io_resp_eff_T_45 | _io_resp_eff_T_50; // @[Parameters.scala:629:89] wire _io_resp_eff_T_62 = _io_resp_eff_T_61 | _io_resp_eff_T_55; // @[Parameters.scala:629:89] wire _io_resp_eff_T_63 = _io_resp_eff_T_62 | _io_resp_eff_T_60; // @[Parameters.scala:629:89] wire _io_resp_eff_T_66 = _io_resp_eff_T_64; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_66; // @[Mux.scala:30:73] assign _io_resp_eff_T_67 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_67; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_117( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_132 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RegisterFile.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import freechips.rocketchip.util._ import saturn.common._ class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { val io = IO(new ArbiterIO(new VectorReadReq, n)) val arb = Module(new RRArbiter(new VectorReadReq, n)) io <> arb.io val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) //assert(PopCount(oldest_oh) <= 1.U) when (oldest_oh.orR) { io.chosen := VecInit(oldest_oh).asUInt io.out.valid := true.B io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) for (i <- 0 until n) { io.in(i).ready := oldest_oh(i) && io.out.ready } } } class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Vec(n, Flipped(new VectorReadIO)) val out = Vec(banks, new VectorReadIO) }) val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } for (i <- 0 until banks) { io.out(i).req <> arbs(i).io.out } val bankOffset = log2Ceil(banks) for (i <- 0 until n) { val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) for (j <- 0 until banks) { arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest } io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) } } class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val read = Vec(reads, Flipped(new VectorReadIO)) val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) val write = Input(Valid(new VectorWrite(dLen))) val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) }) val ll_write_valid = RegInit(false.B) val ll_write_bits = Reg(new VectorWrite(dLen)) val vrf = Mem(rows, Vec(dLen, Bool())) val v0_mask = Mem(maskRows, Vec(dLen, Bool())) for (read <- io.read) { read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) read.resp := DontCare when (read.req.valid) { read.resp := vrf.read(read.req.bits.eg).asUInt } } for (mask_read <- io.mask_read) { mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) mask_read.resp := DontCare when (mask_read.req.valid) { mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt } } val write = WireInit(io.write) io.ll_write.ready := false.B if (vParams.vrfHiccupBuffer) { when (!io.write.valid) { // drain hiccup buffer write.valid := ll_write_valid || io.ll_write.valid write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) ll_write_valid := false.B when (io.ll_write.valid && ll_write_valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } .elsewhen (!ll_write_valid) { // fill hiccup buffer when (io.ll_write.valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } } else { when (!io.write.valid) { io.ll_write.ready := true.B write.valid := io.ll_write.valid write.bits := io.ll_write.bits } } when (write.valid) { vrf.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) when (write.bits.eg < maskRows.U) { v0_mask.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) } } } class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val nBanks = vParams.vrfBanking // Support 1, 2, and 4 banks for the VRF require(nBanks == 1 || nBanks == 2 || nBanks == 4) val io = IO(new Bundle { val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) }) val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } reads.zipWithIndex.foreach { case (rc, i) => val xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.read(i) <> xbar.io.out(j) } xbar.io.in <> io.read(i) } maskReads.zipWithIndex.foreach { case (rc, i) => val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.mask_read(i) <> mask_xbar.io.out(j) } mask_xbar.io.in <> io.mask_read(i) } io.ll_writes.foreach(_.ready := false.B) vrf.zipWithIndex.foreach { case (rf, i) => val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) val bank_write_valid = bank_match.orR rf.io.write.valid := bank_write_valid rf.io.write.bits.data := bank_write_data rf.io.write.bits.mask := bank_write_mask rf.io.write.bits.eg := bank_write_eg >> vrfBankBits when (bank_write_valid) { PopCount(bank_match) === 1.U } val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) rf.io.ll_write <> ll_arb.io.out io.ll_writes.zipWithIndex.foreach { case (w, j) => ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits ll_arb.io.in(j).bits.data := w.bits.data ll_arb.io.in(j).bits.mask := w.bits.mask when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { w.ready := true.B } } } }

module RegisterFile( // @[RegisterFile.scala:120:7] input clock, // @[RegisterFile.scala:120:7] input reset, // @[RegisterFile.scala:120:7] output io_read_2_0_req_ready, // @[RegisterFile.scala:126:14] input io_read_2_0_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_2_0_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_2_0_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_2_0_resp, // @[RegisterFile.scala:126:14] output io_read_2_1_req_ready, // @[RegisterFile.scala:126:14] input io_read_2_1_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_2_1_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_2_1_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_2_1_resp, // @[RegisterFile.scala:126:14] output io_read_2_2_req_ready, // @[RegisterFile.scala:126:14] input io_read_2_2_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_2_2_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_2_2_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_2_2_resp, // @[RegisterFile.scala:126:14] output io_read_1_0_req_ready, // @[RegisterFile.scala:126:14] input io_read_1_0_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_1_0_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_1_0_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_1_0_resp, // @[RegisterFile.scala:126:14] output io_read_1_1_req_ready, // @[RegisterFile.scala:126:14] input io_read_1_1_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_1_1_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_1_1_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_1_1_resp, // @[RegisterFile.scala:126:14] output io_read_0_0_req_ready, // @[RegisterFile.scala:126:14] input io_read_0_0_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_0_0_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_0_0_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_0_0_resp, // @[RegisterFile.scala:126:14] output io_read_0_1_req_ready, // @[RegisterFile.scala:126:14] input io_read_0_1_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_0_1_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_0_1_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_0_1_resp, // @[RegisterFile.scala:126:14] output io_read_0_2_req_ready, // @[RegisterFile.scala:126:14] input io_read_0_2_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_0_2_req_bits_eg, // @[RegisterFile.scala:126:14] input io_read_0_2_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_read_0_2_resp, // @[RegisterFile.scala:126:14] output io_read_0_3_req_ready, // @[RegisterFile.scala:126:14] input io_read_0_3_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_read_0_3_req_bits_eg, // @[RegisterFile.scala:126:14] output [127:0] io_read_0_3_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_0_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_0_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_0_req_bits_eg, // @[RegisterFile.scala:126:14] input io_mask_read_0_0_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_0_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_1_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_1_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_1_req_bits_eg, // @[RegisterFile.scala:126:14] input io_mask_read_0_1_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_1_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_2_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_2_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_2_req_bits_eg, // @[RegisterFile.scala:126:14] input io_mask_read_0_2_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_2_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_3_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_3_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_3_req_bits_eg, // @[RegisterFile.scala:126:14] input io_mask_read_0_3_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_3_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_4_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_4_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_4_req_bits_eg, // @[RegisterFile.scala:126:14] input io_mask_read_0_4_req_bits_oldest, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_4_resp, // @[RegisterFile.scala:126:14] output io_mask_read_0_5_req_ready, // @[RegisterFile.scala:126:14] input io_mask_read_0_5_req_valid, // @[RegisterFile.scala:126:14] input [5:0] io_mask_read_0_5_req_bits_eg, // @[RegisterFile.scala:126:14] output [127:0] io_mask_read_0_5_resp, // @[RegisterFile.scala:126:14] input io_pipe_writes_0_valid, // @[RegisterFile.scala:126:14] input [5:0] io_pipe_writes_0_bits_eg, // @[RegisterFile.scala:126:14] input [127:0] io_pipe_writes_0_bits_data, // @[RegisterFile.scala:126:14] input [127:0] io_pipe_writes_0_bits_mask, // @[RegisterFile.scala:126:14] input io_pipe_writes_1_valid, // @[RegisterFile.scala:126:14] input [5:0] io_pipe_writes_1_bits_eg, // @[RegisterFile.scala:126:14] input [127:0] io_pipe_writes_1_bits_data, // @[RegisterFile.scala:126:14] input [127:0] io_pipe_writes_1_bits_mask, // @[RegisterFile.scala:126:14] output io_ll_writes_0_ready, // @[RegisterFile.scala:126:14] input io_ll_writes_0_valid, // @[RegisterFile.scala:126:14] input [5:0] io_ll_writes_0_bits_eg, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_0_bits_data, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_0_bits_mask, // @[RegisterFile.scala:126:14] input io_ll_writes_1_valid, // @[RegisterFile.scala:126:14] input [5:0] io_ll_writes_1_bits_eg, // @[RegisterFile.scala:126:14] output io_ll_writes_2_ready, // @[RegisterFile.scala:126:14] input io_ll_writes_2_valid, // @[RegisterFile.scala:126:14] input [5:0] io_ll_writes_2_bits_eg, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_2_bits_data, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_2_bits_mask, // @[RegisterFile.scala:126:14] output io_ll_writes_3_ready, // @[RegisterFile.scala:126:14] input io_ll_writes_3_valid, // @[RegisterFile.scala:126:14] input [5:0] io_ll_writes_3_bits_eg, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_3_bits_data, // @[RegisterFile.scala:126:14] input [127:0] io_ll_writes_3_bits_mask // @[RegisterFile.scala:126:14] ); wire _ll_arb_3_io_in_0_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_3_io_in_2_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_3_io_in_3_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_3_io_out_valid; // @[RegisterFile.scala:167:24] wire [5:0] _ll_arb_3_io_out_bits_eg; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_3_io_out_bits_data; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_3_io_out_bits_mask; // @[RegisterFile.scala:167:24] wire _ll_arb_2_io_in_0_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_2_io_in_2_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_2_io_in_3_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_2_io_out_valid; // @[RegisterFile.scala:167:24] wire [5:0] _ll_arb_2_io_out_bits_eg; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_2_io_out_bits_data; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_2_io_out_bits_mask; // @[RegisterFile.scala:167:24] wire _ll_arb_1_io_in_0_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_1_io_in_2_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_1_io_in_3_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_1_io_out_valid; // @[RegisterFile.scala:167:24] wire [5:0] _ll_arb_1_io_out_bits_eg; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_1_io_out_bits_data; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_1_io_out_bits_mask; // @[RegisterFile.scala:167:24] wire _ll_arb_io_in_0_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_io_in_2_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_io_in_3_ready; // @[RegisterFile.scala:167:24] wire _ll_arb_io_out_valid; // @[RegisterFile.scala:167:24] wire [5:0] _ll_arb_io_out_bits_eg; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_io_out_bits_data; // @[RegisterFile.scala:167:24] wire [127:0] _ll_arb_io_out_bits_mask; // @[RegisterFile.scala:167:24] wire [5:0] _mask_xbar_io_out_0_req_bits_eg; // @[RegisterFile.scala:145:27] wire [5:0] _mask_xbar_io_out_1_req_bits_eg; // @[RegisterFile.scala:145:27] wire [5:0] _mask_xbar_io_out_2_req_bits_eg; // @[RegisterFile.scala:145:27] wire [5:0] _mask_xbar_io_out_3_req_bits_eg; // @[RegisterFile.scala:145:27] wire _xbar_2_io_out_0_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_2_io_out_0_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_2_io_out_1_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_2_io_out_1_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_2_io_out_2_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_2_io_out_2_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_2_io_out_3_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_2_io_out_3_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_1_io_out_0_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_1_io_out_0_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_1_io_out_1_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_1_io_out_1_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_1_io_out_2_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_1_io_out_2_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_1_io_out_3_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_1_io_out_3_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_io_out_0_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_io_out_0_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_io_out_1_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_io_out_1_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_io_out_2_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_io_out_2_req_bits_eg; // @[RegisterFile.scala:137:22] wire _xbar_io_out_3_req_valid; // @[RegisterFile.scala:137:22] wire [5:0] _xbar_io_out_3_req_bits_eg; // @[RegisterFile.scala:137:22] wire _vrf_3_io_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_3_io_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_3_io_read_1_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_3_io_read_1_resp; // @[RegisterFile.scala:134:38] wire _vrf_3_io_read_2_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_3_io_read_2_resp; // @[RegisterFile.scala:134:38] wire _vrf_3_io_mask_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_3_io_mask_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_3_io_ll_write_ready; // @[RegisterFile.scala:134:38] wire _vrf_2_io_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_2_io_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_2_io_read_1_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_2_io_read_1_resp; // @[RegisterFile.scala:134:38] wire _vrf_2_io_read_2_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_2_io_read_2_resp; // @[RegisterFile.scala:134:38] wire _vrf_2_io_mask_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_2_io_mask_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_2_io_ll_write_ready; // @[RegisterFile.scala:134:38] wire _vrf_1_io_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_1_io_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_1_io_read_1_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_1_io_read_1_resp; // @[RegisterFile.scala:134:38] wire _vrf_1_io_read_2_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_1_io_read_2_resp; // @[RegisterFile.scala:134:38] wire _vrf_1_io_mask_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_1_io_mask_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_1_io_ll_write_ready; // @[RegisterFile.scala:134:38] wire _vrf_0_io_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_0_io_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_0_io_read_1_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_0_io_read_1_resp; // @[RegisterFile.scala:134:38] wire _vrf_0_io_read_2_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_0_io_read_2_resp; // @[RegisterFile.scala:134:38] wire _vrf_0_io_mask_read_0_req_ready; // @[RegisterFile.scala:134:38] wire [127:0] _vrf_0_io_mask_read_0_resp; // @[RegisterFile.scala:134:38] wire _vrf_0_io_ll_write_ready; // @[RegisterFile.scala:134:38] wire bank_match_0 = io_pipe_writes_0_bits_eg[1:0] == 2'h0 & io_pipe_writes_0_valid; // @[Bundles.scala:112:49] wire bank_match_1 = io_pipe_writes_1_bits_eg[1:0] == 2'h0 & io_pipe_writes_1_valid; // @[Bundles.scala:112:49] wire [5:0] ll_arb_io_in_0_bits_eg = {2'h0, io_ll_writes_0_bits_eg[5:2]}; // @[RegisterFile.scala:155:63, :172:{33,46}] wire [5:0] ll_arb_io_in_1_bits_eg = {2'h0, io_ll_writes_1_bits_eg[5:2]}; // @[RegisterFile.scala:155:63, :172:{33,46}] wire [5:0] ll_arb_io_in_2_bits_eg = {2'h0, io_ll_writes_2_bits_eg[5:2]}; // @[RegisterFile.scala:155:63, :172:{33,46}] wire [5:0] ll_arb_io_in_3_bits_eg = {2'h0, io_ll_writes_3_bits_eg[5:2]}; // @[RegisterFile.scala:155:63, :172:{33,46}] wire bank_match_0_1 = io_pipe_writes_0_bits_eg[1:0] == 2'h1 & io_pipe_writes_0_valid; // @[Bundles.scala:112:49] wire bank_match_1_1 = io_pipe_writes_1_bits_eg[1:0] == 2'h1 & io_pipe_writes_1_valid; // @[Bundles.scala:112:49] wire bank_match_0_2 = io_pipe_writes_0_bits_eg[1:0] == 2'h2 & io_pipe_writes_0_valid; // @[Bundles.scala:112:49] wire bank_match_1_2 = io_pipe_writes_1_bits_eg[1:0] == 2'h2 & io_pipe_writes_1_valid; // @[Bundles.scala:112:49] wire bank_match_0_3 = (&(io_pipe_writes_0_bits_eg[1:0])) & io_pipe_writes_0_valid; // @[Bundles.scala:112:49] wire bank_match_1_3 = (&(io_pipe_writes_1_bits_eg[1:0])) & io_pipe_writes_1_valid; // @[Bundles.scala:112:49] RegisterFileBank vrf_0 ( // @[RegisterFile.scala:134:38] .clock (clock), .reset (reset), .io_read_0_req_ready (_vrf_0_io_read_0_req_ready), .io_read_0_req_valid (_xbar_io_out_0_req_valid), // @[RegisterFile.scala:137:22] .io_read_0_req_bits_eg (_xbar_io_out_0_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_0_resp (_vrf_0_io_read_0_resp), .io_read_1_req_ready (_vrf_0_io_read_1_req_ready), .io_read_1_req_valid (_xbar_1_io_out_0_req_valid), // @[RegisterFile.scala:137:22] .io_read_1_req_bits_eg (_xbar_1_io_out_0_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_1_resp (_vrf_0_io_read_1_resp), .io_read_2_req_ready (_vrf_0_io_read_2_req_ready), .io_read_2_req_valid (_xbar_2_io_out_0_req_valid), // @[RegisterFile.scala:137:22] .io_read_2_req_bits_eg (_xbar_2_io_out_0_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_2_resp (_vrf_0_io_read_2_resp), .io_mask_read_0_req_ready (_vrf_0_io_mask_read_0_req_ready), .io_mask_read_0_req_bits_eg (_mask_xbar_io_out_0_req_bits_eg), // @[RegisterFile.scala:145:27] .io_mask_read_0_resp (_vrf_0_io_mask_read_0_resp), .io_write_valid (bank_match_0 | bank_match_1), // @[RegisterFile.scala:155:72] .io_write_bits_eg ({2'h0, (bank_match_0 ? io_pipe_writes_0_bits_eg[5:2] : 4'h0) | (bank_match_1 ? io_pipe_writes_1_bits_eg[5:2] : 4'h0)}), // @[Mux.scala:30:73] .io_write_bits_data ((bank_match_0 ? io_pipe_writes_0_bits_data : 128'h0) | (bank_match_1 ? io_pipe_writes_1_bits_data : 128'h0)), // @[Mux.scala:30:73] .io_write_bits_mask ((bank_match_0 ? io_pipe_writes_0_bits_mask : 128'h0) | (bank_match_1 ? io_pipe_writes_1_bits_mask : 128'h0)), // @[Mux.scala:30:73] .io_ll_write_ready (_vrf_0_io_ll_write_ready), .io_ll_write_valid (_ll_arb_io_out_valid), // @[RegisterFile.scala:167:24] .io_ll_write_bits_eg (_ll_arb_io_out_bits_eg), // @[RegisterFile.scala:167:24] .io_ll_write_bits_data (_ll_arb_io_out_bits_data), // @[RegisterFile.scala:167:24] .io_ll_write_bits_mask (_ll_arb_io_out_bits_mask) // @[RegisterFile.scala:167:24] ); // @[RegisterFile.scala:134:38] RegisterFileBank vrf_1 ( // @[RegisterFile.scala:134:38] .clock (clock), .reset (reset), .io_read_0_req_ready (_vrf_1_io_read_0_req_ready), .io_read_0_req_valid (_xbar_io_out_1_req_valid), // @[RegisterFile.scala:137:22] .io_read_0_req_bits_eg (_xbar_io_out_1_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_0_resp (_vrf_1_io_read_0_resp), .io_read_1_req_ready (_vrf_1_io_read_1_req_ready), .io_read_1_req_valid (_xbar_1_io_out_1_req_valid), // @[RegisterFile.scala:137:22] .io_read_1_req_bits_eg (_xbar_1_io_out_1_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_1_resp (_vrf_1_io_read_1_resp), .io_read_2_req_ready (_vrf_1_io_read_2_req_ready), .io_read_2_req_valid (_xbar_2_io_out_1_req_valid), // @[RegisterFile.scala:137:22] .io_read_2_req_bits_eg (_xbar_2_io_out_1_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_2_resp (_vrf_1_io_read_2_resp), .io_mask_read_0_req_ready (_vrf_1_io_mask_read_0_req_ready), .io_mask_read_0_req_bits_eg (_mask_xbar_io_out_1_req_bits_eg), // @[RegisterFile.scala:145:27] .io_mask_read_0_resp (_vrf_1_io_mask_read_0_resp), .io_write_valid (bank_match_0_1 | bank_match_1_1), // @[RegisterFile.scala:155:72] .io_write_bits_eg ({2'h0, (bank_match_0_1 ? io_pipe_writes_0_bits_eg[5:2] : 4'h0) | (bank_match_1_1 ? io_pipe_writes_1_bits_eg[5:2] : 4'h0)}), // @[Mux.scala:30:73] .io_write_bits_data ((bank_match_0_1 ? io_pipe_writes_0_bits_data : 128'h0) | (bank_match_1_1 ? io_pipe_writes_1_bits_data : 128'h0)), // @[Mux.scala:30:73] .io_write_bits_mask ((bank_match_0_1 ? io_pipe_writes_0_bits_mask : 128'h0) | (bank_match_1_1 ? io_pipe_writes_1_bits_mask : 128'h0)), // @[Mux.scala:30:73] .io_ll_write_ready (_vrf_1_io_ll_write_ready), .io_ll_write_valid (_ll_arb_1_io_out_valid), // @[RegisterFile.scala:167:24] .io_ll_write_bits_eg (_ll_arb_1_io_out_bits_eg), // @[RegisterFile.scala:167:24] .io_ll_write_bits_data (_ll_arb_1_io_out_bits_data), // @[RegisterFile.scala:167:24] .io_ll_write_bits_mask (_ll_arb_1_io_out_bits_mask) // @[RegisterFile.scala:167:24] ); // @[RegisterFile.scala:134:38] RegisterFileBank vrf_2 ( // @[RegisterFile.scala:134:38] .clock (clock), .reset (reset), .io_read_0_req_ready (_vrf_2_io_read_0_req_ready), .io_read_0_req_valid (_xbar_io_out_2_req_valid), // @[RegisterFile.scala:137:22] .io_read_0_req_bits_eg (_xbar_io_out_2_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_0_resp (_vrf_2_io_read_0_resp), .io_read_1_req_ready (_vrf_2_io_read_1_req_ready), .io_read_1_req_valid (_xbar_1_io_out_2_req_valid), // @[RegisterFile.scala:137:22] .io_read_1_req_bits_eg (_xbar_1_io_out_2_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_1_resp (_vrf_2_io_read_1_resp), .io_read_2_req_ready (_vrf_2_io_read_2_req_ready), .io_read_2_req_valid (_xbar_2_io_out_2_req_valid), // @[RegisterFile.scala:137:22] .io_read_2_req_bits_eg (_xbar_2_io_out_2_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_2_resp (_vrf_2_io_read_2_resp), .io_mask_read_0_req_ready (_vrf_2_io_mask_read_0_req_ready), .io_mask_read_0_req_bits_eg (_mask_xbar_io_out_2_req_bits_eg), // @[RegisterFile.scala:145:27] .io_mask_read_0_resp (_vrf_2_io_mask_read_0_resp), .io_write_valid (bank_match_0_2 | bank_match_1_2), // @[RegisterFile.scala:155:72] .io_write_bits_eg ({2'h0, (bank_match_0_2 ? io_pipe_writes_0_bits_eg[5:2] : 4'h0) | (bank_match_1_2 ? io_pipe_writes_1_bits_eg[5:2] : 4'h0)}), // @[Mux.scala:30:73] .io_write_bits_data ((bank_match_0_2 ? io_pipe_writes_0_bits_data : 128'h0) | (bank_match_1_2 ? io_pipe_writes_1_bits_data : 128'h0)), // @[Mux.scala:30:73] .io_write_bits_mask ((bank_match_0_2 ? io_pipe_writes_0_bits_mask : 128'h0) | (bank_match_1_2 ? io_pipe_writes_1_bits_mask : 128'h0)), // @[Mux.scala:30:73] .io_ll_write_ready (_vrf_2_io_ll_write_ready), .io_ll_write_valid (_ll_arb_2_io_out_valid), // @[RegisterFile.scala:167:24] .io_ll_write_bits_eg (_ll_arb_2_io_out_bits_eg), // @[RegisterFile.scala:167:24] .io_ll_write_bits_data (_ll_arb_2_io_out_bits_data), // @[RegisterFile.scala:167:24] .io_ll_write_bits_mask (_ll_arb_2_io_out_bits_mask) // @[RegisterFile.scala:167:24] ); // @[RegisterFile.scala:134:38] RegisterFileBank vrf_3 ( // @[RegisterFile.scala:134:38] .clock (clock), .reset (reset), .io_read_0_req_ready (_vrf_3_io_read_0_req_ready), .io_read_0_req_valid (_xbar_io_out_3_req_valid), // @[RegisterFile.scala:137:22] .io_read_0_req_bits_eg (_xbar_io_out_3_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_0_resp (_vrf_3_io_read_0_resp), .io_read_1_req_ready (_vrf_3_io_read_1_req_ready), .io_read_1_req_valid (_xbar_1_io_out_3_req_valid), // @[RegisterFile.scala:137:22] .io_read_1_req_bits_eg (_xbar_1_io_out_3_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_1_resp (_vrf_3_io_read_1_resp), .io_read_2_req_ready (_vrf_3_io_read_2_req_ready), .io_read_2_req_valid (_xbar_2_io_out_3_req_valid), // @[RegisterFile.scala:137:22] .io_read_2_req_bits_eg (_xbar_2_io_out_3_req_bits_eg), // @[RegisterFile.scala:137:22] .io_read_2_resp (_vrf_3_io_read_2_resp), .io_mask_read_0_req_ready (_vrf_3_io_mask_read_0_req_ready), .io_mask_read_0_req_bits_eg (_mask_xbar_io_out_3_req_bits_eg), // @[RegisterFile.scala:145:27] .io_mask_read_0_resp (_vrf_3_io_mask_read_0_resp), .io_write_valid (bank_match_0_3 | bank_match_1_3), // @[RegisterFile.scala:155:72] .io_write_bits_eg ({2'h0, (bank_match_0_3 ? io_pipe_writes_0_bits_eg[5:2] : 4'h0) | (bank_match_1_3 ? io_pipe_writes_1_bits_eg[5:2] : 4'h0)}), // @[Mux.scala:30:73] .io_write_bits_data ((bank_match_0_3 ? io_pipe_writes_0_bits_data : 128'h0) | (bank_match_1_3 ? io_pipe_writes_1_bits_data : 128'h0)), // @[Mux.scala:30:73] .io_write_bits_mask ((bank_match_0_3 ? io_pipe_writes_0_bits_mask : 128'h0) | (bank_match_1_3 ? io_pipe_writes_1_bits_mask : 128'h0)), // @[Mux.scala:30:73] .io_ll_write_ready (_vrf_3_io_ll_write_ready), .io_ll_write_valid (_ll_arb_3_io_out_valid), // @[RegisterFile.scala:167:24] .io_ll_write_bits_eg (_ll_arb_3_io_out_bits_eg), // @[RegisterFile.scala:167:24] .io_ll_write_bits_data (_ll_arb_3_io_out_bits_data), // @[RegisterFile.scala:167:24] .io_ll_write_bits_mask (_ll_arb_3_io_out_bits_mask) // @[RegisterFile.scala:167:24] ); // @[RegisterFile.scala:134:38] RegisterReadXbar xbar ( // @[RegisterFile.scala:137:22] .clock (clock), .io_in_0_req_ready (io_read_0_0_req_ready), .io_in_0_req_valid (io_read_0_0_req_valid), .io_in_0_req_bits_eg (io_read_0_0_req_bits_eg), .io_in_0_req_bits_oldest (io_read_0_0_req_bits_oldest), .io_in_0_resp (io_read_0_0_resp), .io_in_1_req_ready (io_read_0_1_req_ready), .io_in_1_req_valid (io_read_0_1_req_valid), .io_in_1_req_bits_eg (io_read_0_1_req_bits_eg), .io_in_1_req_bits_oldest (io_read_0_1_req_bits_oldest), .io_in_1_resp (io_read_0_1_resp), .io_in_2_req_ready (io_read_0_2_req_ready), .io_in_2_req_valid (io_read_0_2_req_valid), .io_in_2_req_bits_eg (io_read_0_2_req_bits_eg), .io_in_2_req_bits_oldest (io_read_0_2_req_bits_oldest), .io_in_2_resp (io_read_0_2_resp), .io_in_3_req_ready (io_read_0_3_req_ready), .io_in_3_req_valid (io_read_0_3_req_valid), .io_in_3_req_bits_eg (io_read_0_3_req_bits_eg), .io_in_3_resp (io_read_0_3_resp), .io_out_0_req_ready (_vrf_0_io_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_0_req_valid (_xbar_io_out_0_req_valid), .io_out_0_req_bits_eg (_xbar_io_out_0_req_bits_eg), .io_out_0_resp (_vrf_0_io_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_1_req_ready (_vrf_1_io_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_1_req_valid (_xbar_io_out_1_req_valid), .io_out_1_req_bits_eg (_xbar_io_out_1_req_bits_eg), .io_out_1_resp (_vrf_1_io_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_2_req_ready (_vrf_2_io_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_2_req_valid (_xbar_io_out_2_req_valid), .io_out_2_req_bits_eg (_xbar_io_out_2_req_bits_eg), .io_out_2_resp (_vrf_2_io_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_3_req_ready (_vrf_3_io_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_3_req_valid (_xbar_io_out_3_req_valid), .io_out_3_req_bits_eg (_xbar_io_out_3_req_bits_eg), .io_out_3_resp (_vrf_3_io_read_0_resp) // @[RegisterFile.scala:134:38] ); // @[RegisterFile.scala:137:22] RegisterReadXbar_1 xbar_1 ( // @[RegisterFile.scala:137:22] .clock (clock), .io_in_0_req_ready (io_read_1_0_req_ready), .io_in_0_req_valid (io_read_1_0_req_valid), .io_in_0_req_bits_eg (io_read_1_0_req_bits_eg), .io_in_0_req_bits_oldest (io_read_1_0_req_bits_oldest), .io_in_0_resp (io_read_1_0_resp), .io_in_1_req_ready (io_read_1_1_req_ready), .io_in_1_req_valid (io_read_1_1_req_valid), .io_in_1_req_bits_eg (io_read_1_1_req_bits_eg), .io_in_1_req_bits_oldest (io_read_1_1_req_bits_oldest), .io_in_1_resp (io_read_1_1_resp), .io_out_0_req_ready (_vrf_0_io_read_1_req_ready), // @[RegisterFile.scala:134:38] .io_out_0_req_valid (_xbar_1_io_out_0_req_valid), .io_out_0_req_bits_eg (_xbar_1_io_out_0_req_bits_eg), .io_out_0_resp (_vrf_0_io_read_1_resp), // @[RegisterFile.scala:134:38] .io_out_1_req_ready (_vrf_1_io_read_1_req_ready), // @[RegisterFile.scala:134:38] .io_out_1_req_valid (_xbar_1_io_out_1_req_valid), .io_out_1_req_bits_eg (_xbar_1_io_out_1_req_bits_eg), .io_out_1_resp (_vrf_1_io_read_1_resp), // @[RegisterFile.scala:134:38] .io_out_2_req_ready (_vrf_2_io_read_1_req_ready), // @[RegisterFile.scala:134:38] .io_out_2_req_valid (_xbar_1_io_out_2_req_valid), .io_out_2_req_bits_eg (_xbar_1_io_out_2_req_bits_eg), .io_out_2_resp (_vrf_2_io_read_1_resp), // @[RegisterFile.scala:134:38] .io_out_3_req_ready (_vrf_3_io_read_1_req_ready), // @[RegisterFile.scala:134:38] .io_out_3_req_valid (_xbar_1_io_out_3_req_valid), .io_out_3_req_bits_eg (_xbar_1_io_out_3_req_bits_eg), .io_out_3_resp (_vrf_3_io_read_1_resp) // @[RegisterFile.scala:134:38] ); // @[RegisterFile.scala:137:22] RegisterReadXbar_2 xbar_2 ( // @[RegisterFile.scala:137:22] .clock (clock), .io_in_0_req_ready (io_read_2_0_req_ready), .io_in_0_req_valid (io_read_2_0_req_valid), .io_in_0_req_bits_eg (io_read_2_0_req_bits_eg), .io_in_0_req_bits_oldest (io_read_2_0_req_bits_oldest), .io_in_0_resp (io_read_2_0_resp), .io_in_1_req_ready (io_read_2_1_req_ready), .io_in_1_req_valid (io_read_2_1_req_valid), .io_in_1_req_bits_eg (io_read_2_1_req_bits_eg), .io_in_1_req_bits_oldest (io_read_2_1_req_bits_oldest), .io_in_1_resp (io_read_2_1_resp), .io_in_2_req_ready (io_read_2_2_req_ready), .io_in_2_req_valid (io_read_2_2_req_valid), .io_in_2_req_bits_eg (io_read_2_2_req_bits_eg), .io_in_2_req_bits_oldest (io_read_2_2_req_bits_oldest), .io_in_2_resp (io_read_2_2_resp), .io_out_0_req_ready (_vrf_0_io_read_2_req_ready), // @[RegisterFile.scala:134:38] .io_out_0_req_valid (_xbar_2_io_out_0_req_valid), .io_out_0_req_bits_eg (_xbar_2_io_out_0_req_bits_eg), .io_out_0_resp (_vrf_0_io_read_2_resp), // @[RegisterFile.scala:134:38] .io_out_1_req_ready (_vrf_1_io_read_2_req_ready), // @[RegisterFile.scala:134:38] .io_out_1_req_valid (_xbar_2_io_out_1_req_valid), .io_out_1_req_bits_eg (_xbar_2_io_out_1_req_bits_eg), .io_out_1_resp (_vrf_1_io_read_2_resp), // @[RegisterFile.scala:134:38] .io_out_2_req_ready (_vrf_2_io_read_2_req_ready), // @[RegisterFile.scala:134:38] .io_out_2_req_valid (_xbar_2_io_out_2_req_valid), .io_out_2_req_bits_eg (_xbar_2_io_out_2_req_bits_eg), .io_out_2_resp (_vrf_2_io_read_2_resp), // @[RegisterFile.scala:134:38] .io_out_3_req_ready (_vrf_3_io_read_2_req_ready), // @[RegisterFile.scala:134:38] .io_out_3_req_valid (_xbar_2_io_out_3_req_valid), .io_out_3_req_bits_eg (_xbar_2_io_out_3_req_bits_eg), .io_out_3_resp (_vrf_3_io_read_2_resp) // @[RegisterFile.scala:134:38] ); // @[RegisterFile.scala:137:22] RegisterReadXbar_3 mask_xbar ( // @[RegisterFile.scala:145:27] .clock (clock), .io_in_0_req_ready (io_mask_read_0_0_req_ready), .io_in_0_req_valid (io_mask_read_0_0_req_valid), .io_in_0_req_bits_eg (io_mask_read_0_0_req_bits_eg), .io_in_0_req_bits_oldest (io_mask_read_0_0_req_bits_oldest), .io_in_0_resp (io_mask_read_0_0_resp), .io_in_1_req_ready (io_mask_read_0_1_req_ready), .io_in_1_req_valid (io_mask_read_0_1_req_valid), .io_in_1_req_bits_eg (io_mask_read_0_1_req_bits_eg), .io_in_1_req_bits_oldest (io_mask_read_0_1_req_bits_oldest), .io_in_1_resp (io_mask_read_0_1_resp), .io_in_2_req_ready (io_mask_read_0_2_req_ready), .io_in_2_req_valid (io_mask_read_0_2_req_valid), .io_in_2_req_bits_eg (io_mask_read_0_2_req_bits_eg), .io_in_2_req_bits_oldest (io_mask_read_0_2_req_bits_oldest), .io_in_2_resp (io_mask_read_0_2_resp), .io_in_3_req_ready (io_mask_read_0_3_req_ready), .io_in_3_req_valid (io_mask_read_0_3_req_valid), .io_in_3_req_bits_eg (io_mask_read_0_3_req_bits_eg), .io_in_3_req_bits_oldest (io_mask_read_0_3_req_bits_oldest), .io_in_3_resp (io_mask_read_0_3_resp), .io_in_4_req_ready (io_mask_read_0_4_req_ready), .io_in_4_req_valid (io_mask_read_0_4_req_valid), .io_in_4_req_bits_eg (io_mask_read_0_4_req_bits_eg), .io_in_4_req_bits_oldest (io_mask_read_0_4_req_bits_oldest), .io_in_4_resp (io_mask_read_0_4_resp), .io_in_5_req_ready (io_mask_read_0_5_req_ready), .io_in_5_req_valid (io_mask_read_0_5_req_valid), .io_in_5_req_bits_eg (io_mask_read_0_5_req_bits_eg), .io_in_5_resp (io_mask_read_0_5_resp), .io_out_0_req_ready (_vrf_0_io_mask_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_0_req_bits_eg (_mask_xbar_io_out_0_req_bits_eg), .io_out_0_resp (_vrf_0_io_mask_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_1_req_ready (_vrf_1_io_mask_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_1_req_bits_eg (_mask_xbar_io_out_1_req_bits_eg), .io_out_1_resp (_vrf_1_io_mask_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_2_req_ready (_vrf_2_io_mask_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_2_req_bits_eg (_mask_xbar_io_out_2_req_bits_eg), .io_out_2_resp (_vrf_2_io_mask_read_0_resp), // @[RegisterFile.scala:134:38] .io_out_3_req_ready (_vrf_3_io_mask_read_0_req_ready), // @[RegisterFile.scala:134:38] .io_out_3_req_bits_eg (_mask_xbar_io_out_3_req_bits_eg), .io_out_3_resp (_vrf_3_io_mask_read_0_resp) // @[RegisterFile.scala:134:38] ); // @[RegisterFile.scala:145:27] Arbiter4_VectorWrite ll_arb ( // @[RegisterFile.scala:167:24] .io_in_0_ready (_ll_arb_io_in_0_ready), .io_in_0_valid (io_ll_writes_0_valid & ~(|(io_ll_writes_0_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_0_bits_eg (ll_arb_io_in_0_bits_eg), // @[RegisterFile.scala:172:33] .io_in_0_bits_data (io_ll_writes_0_bits_data), .io_in_0_bits_mask (io_ll_writes_0_bits_mask), .io_in_1_valid (io_ll_writes_1_valid & io_ll_writes_1_bits_eg[1:0] == 2'h0), // @[Bundles.scala:112:49] .io_in_1_bits_eg (ll_arb_io_in_1_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_ready (_ll_arb_io_in_2_ready), .io_in_2_valid (io_ll_writes_2_valid & ~(|(io_ll_writes_2_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_2_bits_eg (ll_arb_io_in_2_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_bits_data (io_ll_writes_2_bits_data), .io_in_2_bits_mask (io_ll_writes_2_bits_mask), .io_in_3_ready (_ll_arb_io_in_3_ready), .io_in_3_valid (io_ll_writes_3_valid & ~(|(io_ll_writes_3_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_3_bits_eg (ll_arb_io_in_3_bits_eg), // @[RegisterFile.scala:172:33] .io_in_3_bits_data (io_ll_writes_3_bits_data), .io_in_3_bits_mask (io_ll_writes_3_bits_mask), .io_out_ready (_vrf_0_io_ll_write_ready), // @[RegisterFile.scala:134:38] .io_out_valid (_ll_arb_io_out_valid), .io_out_bits_eg (_ll_arb_io_out_bits_eg), .io_out_bits_data (_ll_arb_io_out_bits_data), .io_out_bits_mask (_ll_arb_io_out_bits_mask) ); // @[RegisterFile.scala:167:24] Arbiter4_VectorWrite ll_arb_1 ( // @[RegisterFile.scala:167:24] .io_in_0_ready (_ll_arb_1_io_in_0_ready), .io_in_0_valid (io_ll_writes_0_valid & io_ll_writes_0_bits_eg[1:0] == 2'h1), // @[Bundles.scala:112:49] .io_in_0_bits_eg (ll_arb_io_in_0_bits_eg), // @[RegisterFile.scala:172:33] .io_in_0_bits_data (io_ll_writes_0_bits_data), .io_in_0_bits_mask (io_ll_writes_0_bits_mask), .io_in_1_valid (io_ll_writes_1_valid & io_ll_writes_1_bits_eg[1:0] == 2'h1), // @[Bundles.scala:112:49] .io_in_1_bits_eg (ll_arb_io_in_1_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_ready (_ll_arb_1_io_in_2_ready), .io_in_2_valid (io_ll_writes_2_valid & io_ll_writes_2_bits_eg[1:0] == 2'h1), // @[Bundles.scala:112:49] .io_in_2_bits_eg (ll_arb_io_in_2_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_bits_data (io_ll_writes_2_bits_data), .io_in_2_bits_mask (io_ll_writes_2_bits_mask), .io_in_3_ready (_ll_arb_1_io_in_3_ready), .io_in_3_valid (io_ll_writes_3_valid & io_ll_writes_3_bits_eg[1:0] == 2'h1), // @[Bundles.scala:112:49] .io_in_3_bits_eg (ll_arb_io_in_3_bits_eg), // @[RegisterFile.scala:172:33] .io_in_3_bits_data (io_ll_writes_3_bits_data), .io_in_3_bits_mask (io_ll_writes_3_bits_mask), .io_out_ready (_vrf_1_io_ll_write_ready), // @[RegisterFile.scala:134:38] .io_out_valid (_ll_arb_1_io_out_valid), .io_out_bits_eg (_ll_arb_1_io_out_bits_eg), .io_out_bits_data (_ll_arb_1_io_out_bits_data), .io_out_bits_mask (_ll_arb_1_io_out_bits_mask) ); // @[RegisterFile.scala:167:24] Arbiter4_VectorWrite ll_arb_2 ( // @[RegisterFile.scala:167:24] .io_in_0_ready (_ll_arb_2_io_in_0_ready), .io_in_0_valid (io_ll_writes_0_valid & io_ll_writes_0_bits_eg[1:0] == 2'h2), // @[Bundles.scala:112:49] .io_in_0_bits_eg (ll_arb_io_in_0_bits_eg), // @[RegisterFile.scala:172:33] .io_in_0_bits_data (io_ll_writes_0_bits_data), .io_in_0_bits_mask (io_ll_writes_0_bits_mask), .io_in_1_valid (io_ll_writes_1_valid & io_ll_writes_1_bits_eg[1:0] == 2'h2), // @[Bundles.scala:112:49] .io_in_1_bits_eg (ll_arb_io_in_1_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_ready (_ll_arb_2_io_in_2_ready), .io_in_2_valid (io_ll_writes_2_valid & io_ll_writes_2_bits_eg[1:0] == 2'h2), // @[Bundles.scala:112:49] .io_in_2_bits_eg (ll_arb_io_in_2_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_bits_data (io_ll_writes_2_bits_data), .io_in_2_bits_mask (io_ll_writes_2_bits_mask), .io_in_3_ready (_ll_arb_2_io_in_3_ready), .io_in_3_valid (io_ll_writes_3_valid & io_ll_writes_3_bits_eg[1:0] == 2'h2), // @[Bundles.scala:112:49] .io_in_3_bits_eg (ll_arb_io_in_3_bits_eg), // @[RegisterFile.scala:172:33] .io_in_3_bits_data (io_ll_writes_3_bits_data), .io_in_3_bits_mask (io_ll_writes_3_bits_mask), .io_out_ready (_vrf_2_io_ll_write_ready), // @[RegisterFile.scala:134:38] .io_out_valid (_ll_arb_2_io_out_valid), .io_out_bits_eg (_ll_arb_2_io_out_bits_eg), .io_out_bits_data (_ll_arb_2_io_out_bits_data), .io_out_bits_mask (_ll_arb_2_io_out_bits_mask) ); // @[RegisterFile.scala:167:24] Arbiter4_VectorWrite ll_arb_3 ( // @[RegisterFile.scala:167:24] .io_in_0_ready (_ll_arb_3_io_in_0_ready), .io_in_0_valid (io_ll_writes_0_valid & (&(io_ll_writes_0_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_0_bits_eg (ll_arb_io_in_0_bits_eg), // @[RegisterFile.scala:172:33] .io_in_0_bits_data (io_ll_writes_0_bits_data), .io_in_0_bits_mask (io_ll_writes_0_bits_mask), .io_in_1_valid (io_ll_writes_1_valid & (&(io_ll_writes_1_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_1_bits_eg (ll_arb_io_in_1_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_ready (_ll_arb_3_io_in_2_ready), .io_in_2_valid (io_ll_writes_2_valid & (&(io_ll_writes_2_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_2_bits_eg (ll_arb_io_in_2_bits_eg), // @[RegisterFile.scala:172:33] .io_in_2_bits_data (io_ll_writes_2_bits_data), .io_in_2_bits_mask (io_ll_writes_2_bits_mask), .io_in_3_ready (_ll_arb_3_io_in_3_ready), .io_in_3_valid (io_ll_writes_3_valid & (&(io_ll_writes_3_bits_eg[1:0]))), // @[Bundles.scala:112:49] .io_in_3_bits_eg (ll_arb_io_in_3_bits_eg), // @[RegisterFile.scala:172:33] .io_in_3_bits_data (io_ll_writes_3_bits_data), .io_in_3_bits_mask (io_ll_writes_3_bits_mask), .io_out_ready (_vrf_3_io_ll_write_ready), // @[RegisterFile.scala:134:38] .io_out_valid (_ll_arb_3_io_out_valid), .io_out_bits_eg (_ll_arb_3_io_out_bits_eg), .io_out_bits_data (_ll_arb_3_io_out_bits_data), .io_out_bits_mask (_ll_arb_3_io_out_bits_mask) ); // @[RegisterFile.scala:167:24] assign io_ll_writes_0_ready = _ll_arb_3_io_in_0_ready & (&(io_ll_writes_0_bits_eg[1:0])) | _ll_arb_2_io_in_0_ready & io_ll_writes_0_bits_eg[1:0] == 2'h2 | _ll_arb_1_io_in_0_ready & io_ll_writes_0_bits_eg[1:0] == 2'h1 | _ll_arb_io_in_0_ready & ~(|(io_ll_writes_0_bits_eg[1:0])); // @[Bundles.scala:112:49] assign io_ll_writes_2_ready = _ll_arb_3_io_in_2_ready & (&(io_ll_writes_2_bits_eg[1:0])) | _ll_arb_2_io_in_2_ready & io_ll_writes_2_bits_eg[1:0] == 2'h2 | _ll_arb_1_io_in_2_ready & io_ll_writes_2_bits_eg[1:0] == 2'h1 | _ll_arb_io_in_2_ready & ~(|(io_ll_writes_2_bits_eg[1:0])); // @[Bundles.scala:112:49] assign io_ll_writes_3_ready = _ll_arb_3_io_in_3_ready & (&(io_ll_writes_3_bits_eg[1:0])) | _ll_arb_2_io_in_3_ready & io_ll_writes_3_bits_eg[1:0] == 2'h2 | _ll_arb_1_io_in_3_ready & io_ll_writes_3_bits_eg[1:0] == 2'h1 | _ll_arb_io_in_3_ready & ~(|(io_ll_writes_3_bits_eg[1:0])); // @[Bundles.scala:112:49] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module MacUnit_33( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File WidthWidget.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ object WidthWidget { def split[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth require(inBits > outBits && inBits % outBits == 0) val ratio = inBits / outBits val count = RegInit(0.U(log2Ceil(ratio).W)) val first = count === 0.U val last = count === (ratio - 1).U val stored = Reg(UInt((inBits - outBits).W)) out.valid := in.valid out.bits := in.bits out.bits.head := in.bits.head && first out.bits.tail := in.bits.tail && last out.bits.payload := Mux(first, in.bits.payload, stored) in.ready := last && out.ready when (out.fire) { count := Mux(last, 0.U, count + 1.U) stored := Mux(first, in.bits.payload, stored) >> outBits } } def merge[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth require(outBits > inBits && outBits % inBits == 0) val ratio = outBits / inBits val count = RegInit(0.U(log2Ceil(ratio).W)) val first = count === 0.U val last = count === (ratio - 1).U val flit = Reg(out.bits.cloneType) val payload = Reg(Vec(ratio-1, UInt(inBits.W))) out.valid := in.valid && last out.bits := flit out.bits.tail := last && in.bits.tail out.bits.payload := Cat(in.bits.payload, payload.asUInt) in.ready := !last || out.ready when (in.fire) { count := Mux(last, 0.U, count + 1.U) payload(count) := in.bits.payload when (first) { flit := in.bits } } } def apply[T <: BaseFlit](in: IrrevocableIO[T], out: IrrevocableIO[T]) = { val inBits = in.bits.payload.getWidth val outBits = out.bits.payload.getWidth if (inBits == outBits) { out <> in } else if (inBits < outBits) { merge(in, out) } else { split(in, out) } } } class IngressWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new IngressChannelAdapterNode( slaveFn = { s => s.copy(payloadBits=srcBits) } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => WidthWidget(in.flit, out.flit) } } } object IngressWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = IngressChannelEphemeralNode() node } else { val ingress_width_widget = LazyModule(new IngressWidthWidget(srcBits)) ingress_width_widget.node } } } class EgressWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new EgressChannelAdapterNode( slaveFn = { s => s.copy(payloadBits=srcBits) } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => WidthWidget(in.flit, out.flit) } } } object EgressWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = EgressChannelEphemeralNode() node } else { val egress_width_widget = LazyModule(new EgressWidthWidget(srcBits)) egress_width_widget.node } } } class ChannelWidthWidget(srcBits: Int)(implicit p: Parameters) extends LazyModule { val node = new ChannelAdapterNode( slaveFn = { s => val destBits = s.payloadBits if (srcBits > destBits) { val ratio = srcBits / destBits val virtualChannelParams = s.virtualChannelParams.map { vP => require(vP.bufferSize >= ratio) vP.copy(bufferSize = vP.bufferSize / ratio) } s.copy(payloadBits=srcBits, virtualChannelParams=virtualChannelParams) } else { val ratio = destBits / srcBits val virtualChannelParams = s.virtualChannelParams.map { vP => vP.copy(bufferSize = vP.bufferSize * ratio) } s.copy(payloadBits=srcBits, virtualChannelParams=virtualChannelParams) } } ) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val destBits = out.cParam.payloadBits in.vc_free := out.vc_free if (srcBits == destBits) { in.credit_return := out.credit_return out.flit <> in.flit } else if (srcBits > destBits) { require(srcBits % destBits == 0, s"$srcBits, $destBits") (in.flit zip out.flit) foreach { case (iF, oF) => val in_q = Module(new Queue(new Flit(in.cParam.payloadBits), in.cParam.virtualChannelParams.map(_.bufferSize).sum, pipe=true, flow=true)) in_q.io.enq.valid := iF.valid in_q.io.enq.bits := iF.bits assert(!(in_q.io.enq.valid && !in_q.io.enq.ready)) val in_flit = Wire(Irrevocable(new Flit(in.cParam.payloadBits))) in_flit.valid := in_q.io.deq.valid in_flit.bits := in_q.io.deq.bits in_q.io.deq.ready := in_flit.ready val out_flit = Wire(Irrevocable(new Flit(out.cParam.payloadBits))) oF.valid := out_flit.valid oF.bits := out_flit.bits out_flit.ready := true.B WidthWidget(in_flit, out_flit) } val ratio = srcBits / destBits val counts = RegInit(VecInit(Seq.fill(in.nVirtualChannels) { 0.U(log2Ceil(ratio).W) })) val in_credit_return = Wire(Vec(in.nVirtualChannels, Bool())) in.credit_return := in_credit_return.asUInt for (i <- 0 until in.nVirtualChannels) { in_credit_return(i) := false.B when (out.credit_return(i)) { val last = counts(i) === (ratio-1).U counts(i) := Mux(last, 0.U, counts(i) + 1.U) when (last) { in_credit_return(i) := true.B } } } } else { require(destBits % srcBits == 0) val in_flits = Wire(Vec(in.nVirtualChannels, Irrevocable(new Flit(in.cParam.payloadBits)))) val out_flits = Wire(Vec(in.nVirtualChannels, Irrevocable(new Flit(out.cParam.payloadBits)))) for (i <- 0 until in.nVirtualChannels) { val sel = in.flit.map(f => f.valid && f.bits.virt_channel_id === i.U) in_flits(i).valid := sel.orR in_flits(i).bits := Mux1H(sel, in.flit.map(_.bits)) out_flits(i).ready := sel.orR WidthWidget(in_flits(i), out_flits(i)) } for (i <- 0 until in.flit.size) { val sel = UIntToOH(in.flit(i).bits.virt_channel_id) out.flit(i).valid := Mux1H(sel, out_flits.map(_.valid)) out.flit(i).bits := Mux1H(sel, out_flits.map(_.bits)) } val ratio = destBits / srcBits val credits = RegInit(VecInit((0 until in.nVirtualChannels).map { i => 0.U(log2Ceil(ratio*in.cParam.virtualChannelParams(i).bufferSize).W) })) val in_credit_return = Wire(Vec(in.nVirtualChannels, Bool())) in.credit_return := in_credit_return.asUInt for (i <- 0 until in.nVirtualChannels) { when (out.credit_return(i)) { in_credit_return(i) := true.B credits(i) := credits(i) + (ratio - 1).U } .otherwise { val empty = credits(i) === 0.U in_credit_return(i) := !empty credits(i) := Mux(empty, 0.U, credits(i) - 1.U) } } } } } } object ChannelWidthWidget { def apply(destBits: Int, srcBits: Int)(implicit p: Parameters) = { if (destBits == srcBits) { val node = ChannelEphemeralNode() node } else { val channel_width_widget = LazyModule(new ChannelWidthWidget(srcBits)) channel_width_widget.node } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn || noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }

module TLSplitACDxBENoC_be_router_12ClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_egress_width_widget_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [147:0] auto_egress_width_widget_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_width_widget_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [147:0] auto_ingress_width_widget_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_width_widget_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _egress_width_widget_auto_in_flit_ready; // @[WidthWidget.scala:111:43] wire _ingress_width_widget_auto_out_flit_valid; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_head; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_tail; // @[WidthWidget.scala:88:44] wire [36:0] _ingress_width_widget_auto_out_flit_bits_payload; // @[WidthWidget.scala:88:44] wire [4:0] _ingress_width_widget_auto_out_flit_bits_egress_id; // @[WidthWidget.scala:88:44] wire _routers_auto_egress_nodes_out_flit_valid; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_head; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_tail; // @[NoC.scala:67:22] wire [36:0] _routers_auto_egress_nodes_out_flit_bits_payload; // @[NoC.scala:67:22] wire _routers_auto_ingress_nodes_in_flit_ready; // @[NoC.scala:67:22] Router_28 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_egress_nodes_out_flit_ready (_egress_width_widget_auto_in_flit_ready), // @[WidthWidget.scala:111:43] .auto_egress_nodes_out_flit_valid (_routers_auto_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), .auto_ingress_nodes_in_flit_valid (_ingress_width_widget_auto_out_flit_valid), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id), // @[WidthWidget.scala:88:44] .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] IngressWidthWidget ingress_width_widget ( // @[WidthWidget.scala:88:44] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (auto_ingress_width_widget_in_flit_ready), .auto_in_flit_valid (auto_ingress_width_widget_in_flit_valid), .auto_in_flit_bits_head (auto_ingress_width_widget_in_flit_bits_head), .auto_in_flit_bits_payload (auto_ingress_width_widget_in_flit_bits_payload), .auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_flit_bits_egress_id), .auto_out_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), // @[NoC.scala:67:22] .auto_out_flit_valid (_ingress_width_widget_auto_out_flit_valid), .auto_out_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), .auto_out_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), .auto_out_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), .auto_out_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id) ); // @[WidthWidget.scala:88:44] EgressWidthWidget_1 egress_width_widget ( // @[WidthWidget.scala:111:43] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (_egress_width_widget_auto_in_flit_ready), .auto_in_flit_valid (_routers_auto_egress_nodes_out_flit_valid), // @[NoC.scala:67:22] .auto_in_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), // @[NoC.scala:67:22] .auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), // @[NoC.scala:67:22] .auto_in_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), // @[NoC.scala:67:22] .auto_out_flit_ready (auto_egress_width_widget_out_flit_ready), .auto_out_flit_valid (auto_egress_width_widget_out_flit_valid), .auto_out_flit_bits_head (auto_egress_width_widget_out_flit_bits_head), .auto_out_flit_bits_tail (auto_egress_width_widget_out_flit_bits_tail), .auto_out_flit_bits_payload (auto_egress_width_widget_out_flit_bits_payload) ); // @[WidthWidget.scala:111:43] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [511:0] c_sizes_set = 512'h0; // @[Monitor.scala:741:34] wire [255:0] c_opcodes_set = 256'h0; // @[Monitor.scala:740:34] wire [63:0] c_set = 64'h0; // @[Monitor.scala:738:34] wire [63:0] c_set_wo_ready = 64'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [5:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [5:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1267 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1267; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1267; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1340 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1340; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1340; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1340; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [63:0] inflight; // @[Monitor.scala:614:27] reg [255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [511:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [63:0] a_set; // @[Monitor.scala:626:34] wire [63:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [511:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [255:0] _a_opcode_lookup_T_6 = {252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [511:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [511:0] _a_size_lookup_T_6 = {504'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [511:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[511:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = {58'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [63:0] _GEN_4 = 64'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 64'h0; // @[OneHot.scala:58:35] wire _T_1193 = _T_1267 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1193 ? _a_set_T : 64'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1193 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1193 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1193 ? _a_opcodes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1193 ? _a_sizes_set_T_1[511:0] : 512'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [63:0] d_clr; // @[Monitor.scala:664:34] wire [63:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [511:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1239 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_6 = {58'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [63:0] _GEN_7 = 64'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1239 & ~d_release_ack ? _d_clr_wo_ready_T : 64'h0; // @[OneHot.scala:58:35] wire _T_1208 = _T_1340 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1208 ? _d_clr_T : 64'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1208 ? _d_opcodes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1208 ? _d_sizes_clr_T_5[511:0] : 512'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [63:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [63:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [63:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [511:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [511:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [511:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [63:0] inflight_1; // @[Monitor.scala:726:35] wire [63:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [511:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [511:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [255:0] _c_opcode_lookup_T_6 = {252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [511:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [511:0] _c_size_lookup_T_6 = {504'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [511:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[511:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [63:0] d_clr_1; // @[Monitor.scala:774:34] wire [63:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [511:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1311 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1311 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 64'h0; // @[OneHot.scala:58:35] wire _T_1293 = _T_1340 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1293 ? _d_clr_T_1 : 64'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1293 ? _d_opcodes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1293 ? _d_sizes_clr_T_11[511:0] : 512'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [63:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [63:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [511:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [511:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_43(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }

module PriorityQueueStage_74( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File FunctionalUnit.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns.{VectorInstruction} abstract class FunctionalUnitIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val iss = new Bundle { val valid = Input(Bool()) val op = Input(new ExecuteMicroOp) val ready = Output(Bool()) } val scalar_write = Decoupled(new ScalarWrite) val set_vxsat = Output(Bool()) val set_fflags = Output(Valid(UInt(5.W))) } class PipelinedFunctionalUnitIO(depth: Int)(implicit p: Parameters) extends FunctionalUnitIO { val write = Valid(new VectorWrite(dLen)) val pipe = Input(Vec(depth, Valid(new ExecuteMicroOp))) val pipe0_stall = Output(Bool()) } class IterativeFunctionalUnitIO(implicit p: Parameters) extends FunctionalUnitIO { val write = Decoupled(new VectorWrite(dLen)) val hazard = Output(Valid(new PipeHazard(10))) val acc = Output(Bool()) val tail = Output(Bool()) val busy = Output(Bool()) } trait FunctionalUnitFactory { def insns: Seq[VectorInstruction] def generate(implicit p: Parameters): FunctionalUnit } abstract class FunctionalUnit(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io: FunctionalUnitIO } abstract class PipelinedFunctionalUnit(val depth: Int)(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new PipelinedFunctionalUnitIO(depth)) require (depth > 0) def narrow2_expand(bits: Seq[UInt], eew: UInt, upper: Bool, sext: Bool): Vec[UInt] = { val narrow_eew = (0 until 3).map { eew => Wire(Vec(dLenB >> (eew + 1), UInt((16 << eew).W))) } for (eew <- 0 until 3) { val in_vec = bits.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq for (i <- 0 until dLenB >> (eew + 1)) { val lo = Mux(upper, in_vec(i + (dLenB >> (eew + 1))), in_vec(i)) val hi = Fill(16 << eew, lo((8 << eew)-1) && sext) narrow_eew(eew)(i) := Cat(hi, lo) } } VecInit(narrow_eew.map(_.asUInt))(eew).asTypeOf(Vec(dLenB, UInt(8.W))) } } abstract class IterativeFunctionalUnit(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new IterativeFunctionalUnitIO) val valid = RegInit(false.B) val op = Reg(new ExecuteMicroOp) val last = Wire(Bool()) io.busy := valid io.hazard.bits.latency := DontCare when (io.iss.valid && io.iss.ready) { valid := true.B op := io.iss.op } .elsewhen (last) { valid := false.B } } File BitwisePipe.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns._ case object BitwisePipeFactory extends FunctionalUnitFactory { def insns = Seq( AND.VV, AND.VX, AND.VI, OR.VV, OR.VX, OR.VI, XOR.VV, XOR.VX, XOR.VI, MANDNOT.VV, MAND.VV, MOR.VV, MXOR.VV, MORNOT.VV, MNAND.VV, MNOR.VV, MXNOR.VV, REDAND.VV, REDOR.VV, REDXOR.VV, // Zvbb ANDN.VV, ANDN.VX ) def generate(implicit p: Parameters) = new BitwisePipe()(p) } class BitwisePipe(implicit p: Parameters) extends PipelinedFunctionalUnit(1)(p) { val supported_insns = BitwisePipeFactory.insns val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, Seq(BWAnd, BWOr, BWXor, BWInvOut, BWInv1)) io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched val in1 = Mux(ctrl.bool(BWInv1), ~io.pipe(0).bits.rvs1_data, io.pipe(0).bits.rvs1_data) val in2 = io.pipe(0).bits.rvs2_data val op = Mux1H(Seq( (ctrl.bool(BWAnd), (in1 & in2)), (ctrl.bool(BWOr) , (in1 | in2)), (ctrl.bool(BWXor), (in1 ^ in2)) )) val out = Mux(ctrl.bool(BWInvOut), ~op, op) io.pipe0_stall := false.B io.write.valid := io.pipe(0).valid io.write.bits.eg := io.pipe(0).bits.wvd_eg io.write.bits.mask := Mux(io.pipe(0).bits.isOpm && !io.pipe(0).bits.acc, io.pipe(0).bits.full_tail_mask, FillInterleaved(8, io.pipe(0).bits.wmask)) io.write.bits.data := out io.set_vxsat := false.B io.set_fflags.valid := false.B io.set_fflags.bits := DontCare io.scalar_write.valid := false.B io.scalar_write.bits := DontCare }

module BitwisePipe( // @[BitwisePipe.scala:23:7] input [2:0] io_iss_op_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_iss_op_funct6, // @[FunctionalUnit.scala:49:14] output io_iss_ready, // @[FunctionalUnit.scala:49:14] output io_write_valid, // @[FunctionalUnit.scala:49:14] output [4:0] io_write_bits_eg, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_data, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_mask, // @[FunctionalUnit.scala:49:14] input io_pipe_0_valid, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs1_data, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs2_data, // @[FunctionalUnit.scala:49:14] input [7:0] io_pipe_0_bits_wmask, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_full_tail_mask, // @[FunctionalUnit.scala:49:14] input [4:0] io_pipe_0_bits_wvd_eg, // @[FunctionalUnit.scala:49:14] input [2:0] io_pipe_0_bits_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_pipe_0_bits_funct6, // @[FunctionalUnit.scala:49:14] input io_pipe_0_bits_acc // @[FunctionalUnit.scala:49:14] ); wire [3:0] _GEN = ~(io_pipe_0_bits_funct6[3:0]); // @[pla.scala:78:21] wire [2:0] _decode_andMatrixOutputs_T = {_GEN[0], _GEN[1], _GEN[2]}; // @[pla.scala:78:21, :91:29, :98:53] wire [2:0] _decode_andMatrixOutputs_T_7 = {_GEN[0], _GEN[1], io_pipe_0_bits_funct6[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [2:0] _GEN_0 = ~io_iss_op_funct3; // @[pla.scala:78:21] wire [4:0] _GEN_1 = ~(io_iss_op_funct6[5:1]); // @[pla.scala:78:21] wire [63:0] in1 = {64{|{&_decode_andMatrixOutputs_T, &{_GEN[3], ~(io_pipe_0_bits_funct3[1])}, &_decode_andMatrixOutputs_T_7}}} ^ io_pipe_0_bits_rvs1_data; // @[pla.scala:78:21, :91:29, :98:{53,70}, :114:{19,36}] assign io_iss_ready = |{&{io_iss_op_funct6[0], _GEN_1[0], _GEN_1[1], _GEN_1[3], _GEN_1[4], _GEN_0[0], _GEN_0[1]}, &{io_iss_op_funct6[0], _GEN_1[0], _GEN_1[1], _GEN_1[2], _GEN_1[3], _GEN_1[4], _GEN_0[0], _GEN_0[2]}, &{io_iss_op_funct6[1], _GEN_1[1], io_iss_op_funct6[3], _GEN_1[3], _GEN_1[4], _GEN_0[0], _GEN_0[1]}, &{io_iss_op_funct6[1], _GEN_1[1], _GEN_1[2], _GEN_1[3], _GEN_1[4], _GEN_0[0], io_iss_op_funct3[1], _GEN_0[2]}, &{io_iss_op_funct6[3], io_iss_op_funct6[4], _GEN_1[4], _GEN_0[0], io_iss_op_funct3[1], _GEN_0[2]}, &{io_iss_op_funct6[0], _GEN_1[1], io_iss_op_funct6[3], _GEN_1[3], _GEN_1[4], io_iss_op_funct3[0], io_iss_op_funct3[1], _GEN_0[2]}, &{io_iss_op_funct6[1], _GEN_1[1], io_iss_op_funct6[3], _GEN_1[3], _GEN_1[4], io_iss_op_funct3[0], io_iss_op_funct3[1], _GEN_0[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_write_valid = io_pipe_0_valid; // @[BitwisePipe.scala:23:7] assign io_write_bits_eg = io_pipe_0_bits_wvd_eg; // @[BitwisePipe.scala:23:7] assign io_write_bits_data = {64{|{&{io_pipe_0_bits_funct6[0], io_pipe_0_bits_funct6[2]}, &{io_pipe_0_bits_funct6[1], io_pipe_0_bits_funct6[2]}}}} ^ (((|{&_decode_andMatrixOutputs_T, &{io_pipe_0_bits_funct6[0], _GEN[1]}}) ? in1 & io_pipe_0_bits_rvs2_data : 64'h0) | ((|{&{_GEN[0], io_pipe_0_bits_funct6[1]}, &_decode_andMatrixOutputs_T_7}) ? in1 | io_pipe_0_bits_rvs2_data : 64'h0) | ((&{io_pipe_0_bits_funct6[0], io_pipe_0_bits_funct6[1]}) ? in1 ^ io_pipe_0_bits_rvs2_data : 64'h0)); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_write_bits_mask = (io_pipe_0_bits_funct3 == 3'h2 | io_pipe_0_bits_funct3 == 3'h6) & ~io_pipe_0_bits_acc ? io_pipe_0_bits_full_tail_mask : {{8{io_pipe_0_bits_wmask[7]}}, {8{io_pipe_0_bits_wmask[6]}}, {8{io_pipe_0_bits_wmask[5]}}, {8{io_pipe_0_bits_wmask[4]}}, {8{io_pipe_0_bits_wmask[3]}}, {8{io_pipe_0_bits_wmask[2]}}, {8{io_pipe_0_bits_wmask[1]}}, {8{io_pipe_0_bits_wmask[0]}}}; // @[BitwisePipe.scala:23:7, :42:{28,51,54}, :44:20] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_15( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h0; // @[Edges.scala:92:37] wire _a_first_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:92:37] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire a_first_beats1_opdata = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire a_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] a_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h2; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_opcode = 3'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] io_in_a_bits_mask = 8'hF; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:657:53] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:657:61] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [4:0] _a_sizes_set_interm_T_1 = 5'h5; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'h4; // @[Monitor.scala:658:51] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [11:0] is_aligned_mask = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFFC; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC; // @[package.scala:243:71] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [28:0] _is_aligned_T = {27'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_0_1 = _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_0_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire mask_sub_1_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_1 = _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_3_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1081 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1081; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1081; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [28:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1004 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1004; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1004; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1081 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = {3'h0, a_set}; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'h5 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1053 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1053 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1125 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1125 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready || !io.in.bits.head || at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready || !io.in.bits.head || at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) && (vcalloc_q.io.enq.ready || !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }

module IngressUnit_23( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h13; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 4'hA : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'h9 : 4'h0); // @[Mux.scala:30:73] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_T_10[3], _route_buffer_io_enq_bits_flow_egress_node_T_10[2:0] | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 3'h6 : 3'h0)}; // @[Mux.scala:30:73] wire [1:0] _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_4, 1'h0}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'hC; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'hC; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr | (mask >> 1), ~(~addr | mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0) msbsLess || (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound || straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r || ignore) cur.cfg.w := aligned && (pmp.cfg.w || ignore) cur.cfg.x := aligned && (pmp.cfg.x || ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x }

module PMPChecker_s4_1( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire [10:0] _res_hit_lsbMask_T = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_3 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_3 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_16 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_2 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_6 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_29 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_4 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_9 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_42 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_6 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_12 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_55 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_8 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_15 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_68 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_10 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_18 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_81 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_12 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_lsbMask_T_21 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_hit_T_94 = 11'hF0; // @[package.scala:243:71] wire [10:0] _res_aligned_lsbMask_T_14 = 11'hF0; // @[package.scala:243:71] wire [27:0] _res_hit_msbsLess_T_89 = 28'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [27:0] _res_hit_msbsEqual_T_103 = 28'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_124 = 28'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [3:0] _res_hit_lsbMask_T_1 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_4 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_1 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_4 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_17 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_3 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_7 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_30 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_5 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_10 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_43 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_7 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_13 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_56 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_9 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_16 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_69 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_11 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_19 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_82 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_13 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_22 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_T_95 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbsLess_T_104 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_lsbMask_T_15 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_straddlesLowerBound_T_131 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_aligned_straddlesLowerBound_T_134 = 4'h0; // @[package.scala:243:76] wire [3:0] _res_hit_lsbMask_T_2 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_5 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_1 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_14 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_5 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_18 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_15 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_1 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_31 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_8 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_31 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_29 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_2 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_48 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_11 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_44 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_43 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_3 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_65 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_14 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_57 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_57 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_4 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_82 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_17 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_70 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_71 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_5 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_99 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_20 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_83 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_85 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_6 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_116 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbMask_T_23 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_T_96 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_hit_lsbsLess_T_99 = 4'hF; // @[package.scala:243:46] wire [3:0] res_aligned_lsbMask_7 = 4'hF; // @[package.scala:243:46] wire [3:0] _res_aligned_straddlesUpperBound_T_133 = 4'hF; // @[package.scala:243:46] wire [2:0] io_size = 3'h4; // @[PMP.scala:143:7] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_lsbsLess = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_6 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_2 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_19 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_4 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_32 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_6 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_45 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_8 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_58 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_10 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_71 = 1'h0; // @[PMP.scala:83:30] wire res_hit_lsbsLess_12 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_84 = 1'h0; // @[PMP.scala:83:30] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, 4'hF}; // @[package.scala:243:46] wire [27:0] _res_hit_msbMatch_T = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_6 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_10 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_12 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_18 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_20 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_24 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_30 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_30 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_36 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_42 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_40 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_48 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_54 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_50 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_60 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_66 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_60 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_72 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_78 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [27:0] _res_hit_msbMatch_T_70 = io_addr_0[31:4]; // @[PMP.scala:69:29, :143:7] wire [27:0] _res_hit_msbsLess_T_84 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_hit_msbsLess_T_90 = io_addr_0[31:4]; // @[PMP.scala:69:29, :80:25, :143:7] wire [27:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:4]; // @[PMP.scala:69:29, :81:27, :143:7] wire [27:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:4]; // @[PMP.scala:69:29, :123:35, :143:7] wire [27:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:4]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [3:0] _res_hit_lsbMatch_T = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_7 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_10 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_14 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_21 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_20 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_28 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_35 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_30 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_42 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_49 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_40 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_56 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_63 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_50 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_70 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_77 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_60 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_84 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_91 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [3:0] _res_hit_lsbMatch_T_70 = io_addr_0[3:0]; // @[PMP.scala:70:28, :143:7] wire [3:0] _res_hit_lsbsLess_T_98 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_hit_lsbsLess_T_105 = io_addr_0[3:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [3:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[3:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [3:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[3:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_0 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_7 = res_hit_msbsLess; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_2 = _res_aligned_pow2Aligned_T_1; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 4'h0; // @[package.scala:243:76] wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_1 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_1; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_1; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_1; // @[PMP.scala:168:32, :178:63] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_3 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_3; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_4 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_5 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_20 = res_hit_msbsLess_2; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_5 = _res_aligned_pow2Aligned_T_4; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 4'h0; // @[package.scala:243:76] wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_6 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_6; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_6; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_6; // @[PMP.scala:168:32, :178:63] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_8 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_8; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_9 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_10 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_33 = res_hit_msbsLess_4; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_8 = _res_aligned_pow2Aligned_T_7; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 4'h0; // @[package.scala:243:76] wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_11 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_11; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_11; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_11; // @[PMP.scala:168:32, :178:63] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_13 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_13; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_14 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_15 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_46 = res_hit_msbsLess_6; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_11 = _res_aligned_pow2Aligned_T_10; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 4'h0; // @[package.scala:243:76] wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_16 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_16; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_16; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_16; // @[PMP.scala:168:32, :178:63] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_18 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_18; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_19 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_20 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_59 = res_hit_msbsLess_8; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_14 = _res_aligned_pow2Aligned_T_13; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 4'h0; // @[package.scala:243:76] wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_21 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_21; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_21; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_21; // @[PMP.scala:168:32, :178:63] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_23 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_23; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_24 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_25 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_72 = res_hit_msbsLess_10; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_17 = _res_aligned_pow2Aligned_T_16; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 4'h0; // @[package.scala:243:76] wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_26 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_26; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_26; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_26; // @[PMP.scala:168:32, :178:63] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_28 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_28; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_29 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_30 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire _res_hit_T_85 = res_hit_msbsLess_12; // @[PMP.scala:80:39, :83:16] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[3:0]; // @[PMP.scala:60:27, :82:64] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:4]; // @[PMP.scala:60:27, :123:67] wire [27:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[3:0]; // @[PMP.scala:60:27, :123:108] wire [3:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [3:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_20 = _res_aligned_pow2Aligned_T_19; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 4'h0; // @[package.scala:243:76] wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_31 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_31; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_31; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_31; // @[PMP.scala:168:32, :178:63] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_33 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_33; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_34 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [27:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:4]; // @[PMP.scala:68:26, :69:72, :143:7] wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, 4'hF}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:4]; // @[PMP.scala:60:27, :69:53] wire [27:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [27:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [27:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 28'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[3:0]; // @[PMP.scala:60:27, :70:55] wire [3:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[3:0]; // @[PMP.scala:68:26, :70:80] wire [3:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [3:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [3:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 4'h0; // @[package.scala:243:76] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [27:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:4]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [27:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:4]; // @[PMP.scala:60:27, :81:54] wire [27:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 28'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [3:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [3:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[3:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [27:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [3:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [27:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:4]; // @[PMP.scala:60:27, :124:62] wire [27:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 28'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [3:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[3:0]; // @[PMP.scala:60:27, :124:98] wire [3:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131; // @[PMP.scala:124:{98,115}] wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [3:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[3:0]; // @[PMP.scala:126:39, :143:7] wire [3:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire [3:0] _res_aligned_pow2Aligned_T_23 = _res_aligned_pow2Aligned_T_22; // @[PMP.scala:126:{32,34}] wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 4'h0; // @[package.scala:243:76] wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_35 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_35; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_35; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_35; // @[PMP.scala:168:32, :178:63] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_37 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_37; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_38 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_48( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File predictor.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} // A branch prediction for a single instruction class BranchPrediction(implicit p: Parameters) extends BoomBundle()(p) { // If this is a branch, do we take it? val taken = Bool() // Is this a branch? val is_br = Bool() // Is this a JAL? val is_jal = Bool() // What is the target of his branch/jump? Do we know the target? val predicted_pc = Valid(UInt(vaddrBitsExtended.W)) } // A branch prediction for a entire fetch-width worth of instructions // This is typically merged from individual predictions from the banked // predictor class BranchPredictionBundle(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val pc = UInt(vaddrBitsExtended.W) val preds = Vec(fetchWidth, new BranchPrediction) val meta = Output(Vec(nBanks, UInt(bpdMaxMetaLength.W))) val lhist = Output(Vec(nBanks, UInt(localHistoryLength.W))) } // A branch update for a fetch-width worth of instructions class BranchPredictionUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { // Indicates that this update is due to a speculated misprediction // Local predictors typically update themselves with speculative info // Global predictors only care about non-speculative updates val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(fetchWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) // Mask of instructions which are branches. // If these are not cfi_idx, then they were predicted not taken val br_mask = UInt(fetchWidth.W) // Which CFI was taken/mispredicted (if any) val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W)) // Was the cfi taken? val cfi_taken = Bool() // Was the cfi mispredicted from the original prediction? val cfi_mispredicted = Bool() // Was the cfi a br? val cfi_is_br = Bool() // Was the cfi a jal/jalr? val cfi_is_jal = Bool() // Was the cfi a jalr val cfi_is_jalr = Bool() //val cfi_is_ret = Bool() val ghist = new GlobalHistory val lhist = Vec(nBanks, UInt(localHistoryLength.W)) // What did this CFI jump to? val target = UInt(vaddrBitsExtended.W) val meta = Vec(nBanks, UInt(bpdMaxMetaLength.W)) } // A branch update to a single bank class BranchPredictionBankUpdate(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val is_mispredict_update = Bool() val is_repair_update = Bool() val btb_mispredicts = UInt(bankWidth.W) def is_btb_mispredict_update = btb_mispredicts =/= 0.U def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update) val pc = UInt(vaddrBitsExtended.W) val br_mask = UInt(bankWidth.W) val cfi_idx = Valid(UInt(log2Ceil(bankWidth).W)) val cfi_taken = Bool() val cfi_mispredicted = Bool() val cfi_is_br = Bool() val cfi_is_jal = Bool() val cfi_is_jalr = Bool() val ghist = UInt(globalHistoryLength.W) val lhist = UInt(localHistoryLength.W) val target = UInt(vaddrBitsExtended.W) val meta = UInt(bpdMaxMetaLength.W) } class BranchPredictionRequest(implicit p: Parameters) extends BoomBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val ghist = new GlobalHistory } class BranchPredictionBankResponse(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val f1 = Vec(bankWidth, new BranchPrediction) val f2 = Vec(bankWidth, new BranchPrediction) val f3 = Vec(bankWidth, new BranchPrediction) } abstract class BranchPredictorBank(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val metaSz = 0 def nInputs = 1 val mems: Seq[Tuple3[String, Int, Int]] val io = IO(new Bundle { val f0_valid = Input(Bool()) val f0_pc = Input(UInt(vaddrBitsExtended.W)) val f0_mask = Input(UInt(bankWidth.W)) // Local history not available until end of f1 val f1_ghist = Input(UInt(globalHistoryLength.W)) val f1_lhist = Input(UInt(localHistoryLength.W)) val resp_in = Input(Vec(nInputs, new BranchPredictionBankResponse)) val resp = Output(new BranchPredictionBankResponse) // Store the meta as a UInt, use width inference to figure out the shape val f3_meta = Output(UInt(bpdMaxMetaLength.W)) val f3_fire = Input(Bool()) val update = Input(Valid(new BranchPredictionBankUpdate)) }) io.resp := io.resp_in(0) io.f3_meta := 0.U val s0_idx = fetchIdx(io.f0_pc) val s1_idx = RegNext(s0_idx) val s2_idx = RegNext(s1_idx) val s3_idx = RegNext(s2_idx) val s0_valid = io.f0_valid val s1_valid = RegNext(s0_valid) val s2_valid = RegNext(s1_valid) val s3_valid = RegNext(s2_valid) val s0_mask = io.f0_mask val s1_mask = RegNext(s0_mask) val s2_mask = RegNext(s1_mask) val s3_mask = RegNext(s2_mask) val s0_pc = io.f0_pc val s1_pc = RegNext(s0_pc) val s0_update = io.update val s0_update_idx = fetchIdx(io.update.bits.pc) val s0_update_valid = io.update.valid val s1_update = RegNext(s0_update) val s1_update_idx = RegNext(s0_update_idx) val s1_update_valid = RegNext(s0_update_valid) } class BranchPredictor(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val io = IO(new Bundle { // Requests and responses val f0_req = Input(Valid(new BranchPredictionRequest)) val resp = Output(new Bundle { val f1 = new BranchPredictionBundle val f2 = new BranchPredictionBundle val f3 = new BranchPredictionBundle }) val f3_fire = Input(Bool()) // Update val update = Input(Valid(new BranchPredictionUpdate)) }) var total_memsize = 0 val bpdStr = new StringBuilder bpdStr.append(BoomCoreStringPrefix("==Branch Predictor Memory Sizes==\n")) val banked_predictors = (0 until nBanks) map ( b => { val m = Module(if (useBPD) new ComposedBranchPredictorBank else new NullBranchPredictorBank) for ((n, d, w) <- m.mems) { bpdStr.append(BoomCoreStringPrefix(f"bank$b $n: $d x $w = ${d * w / 8}")) total_memsize = total_memsize + d * w / 8 } m }) bpdStr.append(BoomCoreStringPrefix(f"Total bpd size: ${total_memsize / 1024} KB\n")) override def toString: String = bpdStr.toString val banked_lhist_providers = Seq.fill(nBanks) { Module(if (localHistoryNSets > 0) new LocalBranchPredictorBank else new NullLocalBranchPredictorBank) } if (nBanks == 1) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) } else { require(nBanks == 2) banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(1).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse) banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist banked_predictors(1).io.f1_lhist := banked_lhist_providers(1).io.f1_lhist when (bank(io.f0_req.bits.pc) === 0.U) { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := ~(0.U(bankWidth.W)) } .otherwise { banked_lhist_providers(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_lhist_providers(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_lhist_providers(1).io.f0_valid := io.f0_req.valid banked_lhist_providers(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc) banked_predictors(0).io.f0_pc := nextBank(io.f0_req.bits.pc) banked_predictors(0).io.f0_mask := ~(0.U(bankWidth.W)) banked_predictors(1).io.f0_valid := io.f0_req.valid banked_predictors(1).io.f0_pc := bankAlign(io.f0_req.bits.pc) banked_predictors(1).io.f0_mask := fetchMask(io.f0_req.bits.pc) } when (RegNext(bank(io.f0_req.bits.pc) === 0.U)) { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) } .otherwise { banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1)) banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0)) } } for (i <- 0 until nBanks) { banked_lhist_providers(i).io.f3_taken_br := banked_predictors(i).io.resp.f3.map ( p => p.is_br && p.predicted_pc.valid && p.taken ).reduce(_||_) } if (nBanks == 1) { io.resp.f1.preds := banked_predictors(0).io.resp.f1 io.resp.f2.preds := banked_predictors(0).io.resp.f2 io.resp.f3.preds := banked_predictors(0).io.resp.f3 io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist banked_predictors(0).io.f3_fire := io.f3_fire banked_lhist_providers(0).io.f3_fire := io.f3_fire } else { require(nBanks == 2) val b0_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(0).io.f0_valid))) val b1_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(1).io.f0_valid))) banked_predictors(0).io.f3_fire := b0_fire banked_predictors(1).io.f3_fire := b1_fire banked_lhist_providers(0).io.f3_fire := b0_fire banked_lhist_providers(1).io.f3_fire := b1_fire // The branch prediction metadata is stored un-shuffled io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta io.resp.f3.meta(1) := banked_predictors(1).io.f3_meta io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist io.resp.f3.lhist(1) := banked_lhist_providers(1).io.f3_lhist when (bank(io.resp.f1.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(0).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(1).io.resp.f1(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f1.preds(i) := banked_predictors(1).io.resp.f1(i) io.resp.f1.preds(i+bankWidth) := banked_predictors(0).io.resp.f1(i) } } when (bank(io.resp.f2.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(0).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(1).io.resp.f2(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f2.preds(i) := banked_predictors(1).io.resp.f2(i) io.resp.f2.preds(i+bankWidth) := banked_predictors(0).io.resp.f2(i) } } when (bank(io.resp.f3.pc) === 0.U) { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(0).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(1).io.resp.f3(i) } } .otherwise { for (i <- 0 until bankWidth) { io.resp.f3.preds(i) := banked_predictors(1).io.resp.f3(i) io.resp.f3.preds(i+bankWidth) := banked_predictors(0).io.resp.f3(i) } } } io.resp.f1.pc := RegNext(io.f0_req.bits.pc) io.resp.f2.pc := RegNext(io.resp.f1.pc) io.resp.f3.pc := RegNext(io.resp.f2.pc) // We don't care about meta from the f1 and f2 resps // Use the meta from the latest resp io.resp.f1.meta := DontCare io.resp.f2.meta := DontCare io.resp.f1.lhist := DontCare io.resp.f2.lhist := DontCare for (i <- 0 until nBanks) { banked_predictors(i).io.update.bits.is_mispredict_update := io.update.bits.is_mispredict_update banked_predictors(i).io.update.bits.is_repair_update := io.update.bits.is_repair_update banked_predictors(i).io.update.bits.meta := io.update.bits.meta(i) banked_predictors(i).io.update.bits.lhist := io.update.bits.lhist(i) banked_predictors(i).io.update.bits.cfi_idx.bits := io.update.bits.cfi_idx.bits banked_predictors(i).io.update.bits.cfi_taken := io.update.bits.cfi_taken banked_predictors(i).io.update.bits.cfi_mispredicted := io.update.bits.cfi_mispredicted banked_predictors(i).io.update.bits.cfi_is_br := io.update.bits.cfi_is_br banked_predictors(i).io.update.bits.cfi_is_jal := io.update.bits.cfi_is_jal banked_predictors(i).io.update.bits.cfi_is_jalr := io.update.bits.cfi_is_jalr banked_predictors(i).io.update.bits.target := io.update.bits.target banked_lhist_providers(i).io.update.mispredict := io.update.bits.is_mispredict_update banked_lhist_providers(i).io.update.repair := io.update.bits.is_repair_update banked_lhist_providers(i).io.update.lhist := io.update.bits.lhist(i) } if (nBanks == 1) { banked_predictors(0).io.update.valid := io.update.valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) } else { require(nBanks == 2) // Split the single update bundle for the fetchpacket into two updates // 1 for each bank. when (bank(io.update.bits.pc) === 0.U) { val b1_update_valid = io.update.valid && (!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(1).io.update.valid := b1_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(1).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.valid := io.update.valid banked_predictors(1).io.update.valid := b1_update_valid banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(1).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(1) } .otherwise { val b0_update_valid = io.update.valid && !mayNotBeDualBanked(io.update.bits.pc) && (!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U) banked_lhist_providers(1).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U banked_lhist_providers(0).io.update.valid := b0_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U banked_lhist_providers(1).io.update.pc := bankAlign(io.update.bits.pc) banked_lhist_providers(0).io.update.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.valid := io.update.valid banked_predictors(0).io.update.valid := b0_update_valid banked_predictors(1).io.update.bits.pc := bankAlign(io.update.bits.pc) banked_predictors(0).io.update.bits.pc := nextBank(io.update.bits.pc) banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(0) banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(1) } } when (io.update.valid) { when (io.update.bits.cfi_is_br && io.update.bits.cfi_idx.valid) { assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits)) } } } class NullBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val mems = Nil } File btb.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomBTBParams( nSets: Int = 128, nWays: Int = 2, offsetSz: Int = 13, extendedNSets: Int = 128 ) class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { override val nSets = params.nSets override val nWays = params.nWays val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1 val offsetSz = params.offsetSz val extendedNSets = params.extendedNSets require(isPow2(nSets)) require(isPow2(extendedNSets) || extendedNSets == 0) require(extendedNSets <= nSets) require(extendedNSets >= 1) class BTBEntry extends Bundle { val offset = SInt(offsetSz.W) val extended = Bool() } val btbEntrySz = offsetSz + 1 class BTBMeta extends Bundle { val is_br = Bool() val tag = UInt(tagSz.W) } val btbMetaSz = tagSz + 1 class BTBPredictMeta extends Bundle { val write_way = UInt(log2Ceil(nWays).W) } val s1_meta = Wire(new BTBPredictMeta) val f3_meta = RegNext(RegNext(s1_meta)) io.f3_meta := f3_meta.asUInt override val metaSz = s1_meta.asUInt.getWidth val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) } val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) } val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W)) val mems = (((0 until nWays) map ({w:Int => Seq( (f"btb_meta_way$w", nSets, bankWidth * btbMetaSz), (f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended))) val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) }) val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) }) val s1_req_rebtb = ebtb.read(s0_idx, s0_valid) val s1_req_tag = s1_idx >> log2Ceil(nSets) val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W)))) val s1_is_br = Wire(Vec(bankWidth, Bool())) val s1_is_jal = Wire(Vec(bankWidth, Bool())) val s1_hit_ohs = VecInit((0 until bankWidth) map { i => VecInit((0 until nWays) map { w => s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0) }) }) val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) } val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) } for (w <- 0 until bankWidth) { val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w) val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w) s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w) s1_resp(w).bits := Mux( entry_btb.extended, s1_req_rebtb, (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt) s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br io.resp.f2(w) := io.resp_in(0).f2(w) io.resp.f3(w) := io.resp_in(0).f3(w) when (RegNext(s1_hits(w))) { io.resp.f2(w).predicted_pc := RegNext(s1_resp(w)) io.resp.f2(w).is_br := RegNext(s1_is_br(w)) io.resp.f2(w).is_jal := RegNext(s1_is_jal(w)) when (RegNext(s1_is_jal(w))) { io.resp.f2(w).taken := true.B } } when (RegNext(RegNext(s1_hits(w)))) { io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc) io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br) io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal) when (RegNext(RegNext(s1_is_jal(w)))) { io.resp.f3(w).taken := true.B } } } val alloc_way = if (nWays > 1) { val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0)) val l = log2Ceil(nWays) val nChunks = (r_metas.getWidth + l - 1) / l val chunks = (0 until nChunks) map { i => r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l) } chunks.reduce(_^_) } else { 0.U } s1_meta.write_way := Mux(s1_hits.reduce(_||_), PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)), alloc_way) val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta) val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt val new_offset_value = (s1_update.bits.target.asSInt - (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt) val offset_is_extended = (new_offset_value > max_offset_value || new_offset_value < min_offset_value) val s1_update_wbtb_data = Wire(new BTBEntry) s1_update_wbtb_data.extended := offset_is_extended s1_update_wbtb_data.offset := new_offset_value val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) & Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update)) val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) & (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) | (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts) ) ) val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta)) for (w <- 0 until bankWidth) { s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets)) s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w) } for (w <- 0 until nWays) { when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) { btb(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }), VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wbtb_mask).asBools ) meta(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }), VecInit(s1_update_wmeta_data.map(_.asUInt))), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmeta_mask).asBools ) } } when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) { ebtb.write(s1_update_idx, s1_update.bits.target) } }

module BTBBranchPredictorBank( // @[btb.scala:23:7] input clock, // @[btb.scala:23:7] input reset, // @[btb.scala:23:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [29:0] meta_1_MPORT_3_data_3; // @[btb.scala:183:12] wire [29:0] meta_1_MPORT_3_data_2; // @[btb.scala:183:12] wire [29:0] meta_1_MPORT_3_data_1; // @[btb.scala:183:12] wire [29:0] meta_1_MPORT_3_data_0; // @[btb.scala:183:12] wire [13:0] btb_1_MPORT_2_data_3; // @[btb.scala:172:12] wire [13:0] btb_1_MPORT_2_data_2; // @[btb.scala:172:12] wire [13:0] btb_1_MPORT_2_data_1; // @[btb.scala:172:12] wire [13:0] btb_1_MPORT_2_data_0; // @[btb.scala:172:12] wire [29:0] meta_0_MPORT_1_data_3; // @[btb.scala:183:12] wire [29:0] meta_0_MPORT_1_data_2; // @[btb.scala:183:12] wire [29:0] meta_0_MPORT_1_data_1; // @[btb.scala:183:12] wire [29:0] meta_0_MPORT_1_data_0; // @[btb.scala:183:12] wire [13:0] btb_0_MPORT_data_3; // @[btb.scala:172:12] wire [13:0] btb_0_MPORT_data_2; // @[btb.scala:172:12] wire [13:0] btb_0_MPORT_data_1; // @[btb.scala:172:12] wire [13:0] btb_0_MPORT_data_0; // @[btb.scala:172:12] wire _s1_update_meta_WIRE; // @[btb.scala:138:55] wire _s1_req_rmeta_WIRE_17_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_17_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_15_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_15_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_13_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_13_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_11_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_11_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_7_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_7_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_5_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_5_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_3_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_3_tag; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_1_is_br; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_WIRE_1_tag; // @[btb.scala:74:93] wire [12:0] _s1_req_rbtb_WIRE_17_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_17_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_15_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_15_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_13_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_13_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_11_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_11_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_7_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_7_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_5_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_5_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_3_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_3_extended; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_1_offset; // @[btb.scala:73:93] wire _s1_req_rbtb_WIRE_1_extended; // @[btb.scala:73:93] wire [39:0] _ebtb_R0_data; // @[btb.scala:67:29] wire [55:0] _btb_1_R0_data; // @[btb.scala:66:47] wire [55:0] _btb_0_R0_data; // @[btb.scala:66:47] wire [119:0] _meta_1_R0_data; // @[btb.scala:65:47] wire [119:0] _meta_0_R0_data; // @[btb.scala:65:47] wire io_f0_valid_0 = io_f0_valid; // @[btb.scala:23:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[btb.scala:23:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[btb.scala:23:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[btb.scala:23:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[btb.scala:23:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[btb.scala:23:7] wire io_f3_fire_0 = io_f3_fire; // @[btb.scala:23:7] wire io_update_valid_0 = io_update_valid; // @[btb.scala:23:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[btb.scala:23:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[btb.scala:23:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[btb.scala:23:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[btb.scala:23:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[btb.scala:23:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[btb.scala:23:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[btb.scala:23:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[btb.scala:23:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[btb.scala:23:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[btb.scala:23:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[btb.scala:23:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[btb.scala:23:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[btb.scala:23:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[btb.scala:23:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[btb.scala:23:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[btb.scala:23:7] wire [11:0] _max_offset_value_T = 12'hFFF; // @[btb.scala:140:35] wire [12:0] _max_offset_value_T_1 = 13'hFFF; // @[btb.scala:140:{29,59}] wire [12:0] max_offset_value = 13'hFFF; // @[btb.scala:140:59] wire [12:0] _min_offset_value_T = 13'h1000; // @[btb.scala:141:{29,59}] wire [12:0] min_offset_value = 13'h1000; // @[btb.scala:141:59] wire io_f1_lhist = 1'h0; // @[btb.scala:23:7] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[btb.scala:23:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[btb.scala:23:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[btb.scala:23:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[btb.scala:23:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[btb.scala:23:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[btb.scala:23:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_0_taken_0; // @[btb.scala:23:7] wire io_resp_f2_0_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_0_is_jal_0; // @[btb.scala:23:7] wire io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_1_taken_0; // @[btb.scala:23:7] wire io_resp_f2_1_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_1_is_jal_0; // @[btb.scala:23:7] wire io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_2_taken_0; // @[btb.scala:23:7] wire io_resp_f2_2_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_2_is_jal_0; // @[btb.scala:23:7] wire io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f2_3_taken_0; // @[btb.scala:23:7] wire io_resp_f2_3_is_br_0; // @[btb.scala:23:7] wire io_resp_f2_3_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_0_taken_0; // @[btb.scala:23:7] wire io_resp_f3_0_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_0_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_1_taken_0; // @[btb.scala:23:7] wire io_resp_f3_1_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_1_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_2_taken_0; // @[btb.scala:23:7] wire io_resp_f3_2_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_2_is_jal_0; // @[btb.scala:23:7] wire io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7] wire io_resp_f3_3_taken_0; // @[btb.scala:23:7] wire io_resp_f3_3_is_br_0; // @[btb.scala:23:7] wire io_resp_f3_3_is_jal_0; // @[btb.scala:23:7] wire [119:0] io_f3_meta_0; // @[btb.scala:23:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35] wire [35:0] _s1_req_rbtb_WIRE = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rbtb_WIRE_10 = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rmeta_WIRE = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rmeta_WIRE_10 = s0_idx; // @[frontend.scala:162:35] wire [35:0] _s1_req_rebtb_WIRE = s0_idx; // @[frontend.scala:162:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_0_bits_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_1_bits_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_2_bits_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_resp_3_bits_T = s1_pc; // @[predictor.scala:178:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] wire [39:0] _new_offset_value_T = s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [35:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire _s1_meta_write_way_T_13; // @[btb.scala:133:27] wire s1_meta_write_way; // @[btb.scala:52:21] reg f3_meta_REG_write_way; // @[btb.scala:53:32] reg f3_meta_write_way; // @[btb.scala:53:24] assign io_f3_meta_0 = {119'h0, f3_meta_write_way}; // @[btb.scala:23:7, :53:24, :56:14] reg doing_reset; // @[btb.scala:60:28] reg [6:0] reset_idx; // @[btb.scala:61:28] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[btb.scala:60:28, :61:28, :62:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[btb.scala:62:26] wire [29:0] _s1_req_rmeta_WIRE_2 = _meta_0_R0_data[29:0]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_4 = _meta_0_R0_data[59:30]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_6 = _meta_0_R0_data[89:60]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_8 = _meta_0_R0_data[119:90]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_12 = _meta_1_R0_data[29:0]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_14 = _meta_1_R0_data[59:30]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_16 = _meta_1_R0_data[89:60]; // @[btb.scala:65:47, :74:93] wire [29:0] _s1_req_rmeta_WIRE_18 = _meta_1_R0_data[119:90]; // @[btb.scala:65:47, :74:93] wire [13:0] _s1_req_rbtb_WIRE_2 = _btb_0_R0_data[13:0]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_4 = _btb_0_R0_data[27:14]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_6 = _btb_0_R0_data[41:28]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_8 = _btb_0_R0_data[55:42]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_12 = _btb_1_R0_data[13:0]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_14 = _btb_1_R0_data[27:14]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_16 = _btb_1_R0_data[41:28]; // @[btb.scala:66:47, :73:93] wire [13:0] _s1_req_rbtb_WIRE_18 = _btb_1_R0_data[55:42]; // @[btb.scala:66:47, :73:93] wire [6:0] _s1_req_rbtb_T = _s1_req_rbtb_WIRE[6:0]; // @[btb.scala:73:59] wire [12:0] _s1_req_rbtb_T_3; // @[btb.scala:73:93] wire _s1_req_rbtb_T_1; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_0_offset = _s1_req_rbtb_WIRE_1_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_0_extended = _s1_req_rbtb_WIRE_1_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_1 = _s1_req_rbtb_WIRE_2[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_1_extended = _s1_req_rbtb_T_1; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_2 = _s1_req_rbtb_WIRE_2[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_3 = _s1_req_rbtb_T_2; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_1_offset = _s1_req_rbtb_T_3; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_6; // @[btb.scala:73:93] wire _s1_req_rbtb_T_4; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_1_offset = _s1_req_rbtb_WIRE_3_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_1_extended = _s1_req_rbtb_WIRE_3_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_4 = _s1_req_rbtb_WIRE_4[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_3_extended = _s1_req_rbtb_T_4; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_5 = _s1_req_rbtb_WIRE_4[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_6 = _s1_req_rbtb_T_5; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_3_offset = _s1_req_rbtb_T_6; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_9; // @[btb.scala:73:93] wire _s1_req_rbtb_T_7; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_2_offset = _s1_req_rbtb_WIRE_5_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_2_extended = _s1_req_rbtb_WIRE_5_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_7 = _s1_req_rbtb_WIRE_6[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_5_extended = _s1_req_rbtb_T_7; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_8 = _s1_req_rbtb_WIRE_6[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_9 = _s1_req_rbtb_T_8; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_5_offset = _s1_req_rbtb_T_9; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_12; // @[btb.scala:73:93] wire _s1_req_rbtb_T_10; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_9_3_offset = _s1_req_rbtb_WIRE_7_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_9_3_extended = _s1_req_rbtb_WIRE_7_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_10 = _s1_req_rbtb_WIRE_8[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_7_extended = _s1_req_rbtb_T_10; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_11 = _s1_req_rbtb_WIRE_8[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_12 = _s1_req_rbtb_T_11; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_7_offset = _s1_req_rbtb_T_12; // @[btb.scala:73:93] wire [12:0] s1_req_rbtb_0_0_offset = _s1_req_rbtb_WIRE_9_0_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_0_extended = _s1_req_rbtb_WIRE_9_0_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_0_1_offset = _s1_req_rbtb_WIRE_9_1_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_1_extended = _s1_req_rbtb_WIRE_9_1_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_0_2_offset = _s1_req_rbtb_WIRE_9_2_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_2_extended = _s1_req_rbtb_WIRE_9_2_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_0_3_offset = _s1_req_rbtb_WIRE_9_3_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_0_3_extended = _s1_req_rbtb_WIRE_9_3_extended; // @[btb.scala:73:{29,52}] wire [6:0] _s1_req_rbtb_T_13 = _s1_req_rbtb_WIRE_10[6:0]; // @[btb.scala:73:59] wire [12:0] _s1_req_rbtb_T_16; // @[btb.scala:73:93] wire _s1_req_rbtb_T_14; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_0_offset = _s1_req_rbtb_WIRE_11_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_0_extended = _s1_req_rbtb_WIRE_11_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_14 = _s1_req_rbtb_WIRE_12[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_11_extended = _s1_req_rbtb_T_14; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_15 = _s1_req_rbtb_WIRE_12[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_16 = _s1_req_rbtb_T_15; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_11_offset = _s1_req_rbtb_T_16; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_19; // @[btb.scala:73:93] wire _s1_req_rbtb_T_17; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_1_offset = _s1_req_rbtb_WIRE_13_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_1_extended = _s1_req_rbtb_WIRE_13_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_17 = _s1_req_rbtb_WIRE_14[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_13_extended = _s1_req_rbtb_T_17; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_18 = _s1_req_rbtb_WIRE_14[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_19 = _s1_req_rbtb_T_18; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_13_offset = _s1_req_rbtb_T_19; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_22; // @[btb.scala:73:93] wire _s1_req_rbtb_T_20; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_2_offset = _s1_req_rbtb_WIRE_15_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_2_extended = _s1_req_rbtb_WIRE_15_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_20 = _s1_req_rbtb_WIRE_16[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_15_extended = _s1_req_rbtb_T_20; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_21 = _s1_req_rbtb_WIRE_16[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_22 = _s1_req_rbtb_T_21; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_15_offset = _s1_req_rbtb_T_22; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_25; // @[btb.scala:73:93] wire _s1_req_rbtb_T_23; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_WIRE_19_3_offset = _s1_req_rbtb_WIRE_17_offset; // @[btb.scala:73:{52,93}] wire _s1_req_rbtb_WIRE_19_3_extended = _s1_req_rbtb_WIRE_17_extended; // @[btb.scala:73:{52,93}] assign _s1_req_rbtb_T_23 = _s1_req_rbtb_WIRE_18[0]; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_17_extended = _s1_req_rbtb_T_23; // @[btb.scala:73:93] wire [12:0] _s1_req_rbtb_T_24 = _s1_req_rbtb_WIRE_18[13:1]; // @[btb.scala:73:93] assign _s1_req_rbtb_T_25 = _s1_req_rbtb_T_24; // @[btb.scala:73:93] assign _s1_req_rbtb_WIRE_17_offset = _s1_req_rbtb_T_25; // @[btb.scala:73:93] wire [12:0] s1_req_rbtb_1_0_offset = _s1_req_rbtb_WIRE_19_0_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_0_extended = _s1_req_rbtb_WIRE_19_0_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_1_1_offset = _s1_req_rbtb_WIRE_19_1_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_1_extended = _s1_req_rbtb_WIRE_19_1_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_1_2_offset = _s1_req_rbtb_WIRE_19_2_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_2_extended = _s1_req_rbtb_WIRE_19_2_extended; // @[btb.scala:73:{29,52}] wire [12:0] s1_req_rbtb_1_3_offset = _s1_req_rbtb_WIRE_19_3_offset; // @[btb.scala:73:{29,52}] wire s1_req_rbtb_1_3_extended = _s1_req_rbtb_WIRE_19_3_extended; // @[btb.scala:73:{29,52}] wire [6:0] _s1_req_rmeta_T = _s1_req_rmeta_WIRE[6:0]; // @[btb.scala:74:60] wire _s1_req_rmeta_T_2; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_1; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_0_is_br = _s1_req_rmeta_WIRE_1_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_0_tag = _s1_req_rmeta_WIRE_1_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_1 = _s1_req_rmeta_WIRE_2[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_1_tag = _s1_req_rmeta_T_1; // @[btb.scala:74:93] assign _s1_req_rmeta_T_2 = _s1_req_rmeta_WIRE_2[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_1_is_br = _s1_req_rmeta_T_2; // @[btb.scala:74:93] wire _s1_req_rmeta_T_4; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_3; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_1_is_br = _s1_req_rmeta_WIRE_3_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_1_tag = _s1_req_rmeta_WIRE_3_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_3 = _s1_req_rmeta_WIRE_4[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_3_tag = _s1_req_rmeta_T_3; // @[btb.scala:74:93] assign _s1_req_rmeta_T_4 = _s1_req_rmeta_WIRE_4[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_3_is_br = _s1_req_rmeta_T_4; // @[btb.scala:74:93] wire _s1_req_rmeta_T_6; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_5; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_2_is_br = _s1_req_rmeta_WIRE_5_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_2_tag = _s1_req_rmeta_WIRE_5_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_5 = _s1_req_rmeta_WIRE_6[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_5_tag = _s1_req_rmeta_T_5; // @[btb.scala:74:93] assign _s1_req_rmeta_T_6 = _s1_req_rmeta_WIRE_6[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_5_is_br = _s1_req_rmeta_T_6; // @[btb.scala:74:93] wire _s1_req_rmeta_T_8; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_7; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_9_3_is_br = _s1_req_rmeta_WIRE_7_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_9_3_tag = _s1_req_rmeta_WIRE_7_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_7 = _s1_req_rmeta_WIRE_8[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_7_tag = _s1_req_rmeta_T_7; // @[btb.scala:74:93] assign _s1_req_rmeta_T_8 = _s1_req_rmeta_WIRE_8[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_7_is_br = _s1_req_rmeta_T_8; // @[btb.scala:74:93] wire s1_req_rmeta_0_0_is_br = _s1_req_rmeta_WIRE_9_0_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_0_tag = _s1_req_rmeta_WIRE_9_0_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_0_1_is_br = _s1_req_rmeta_WIRE_9_1_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_1_tag = _s1_req_rmeta_WIRE_9_1_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_0_2_is_br = _s1_req_rmeta_WIRE_9_2_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_2_tag = _s1_req_rmeta_WIRE_9_2_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_0_3_is_br = _s1_req_rmeta_WIRE_9_3_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_0_3_tag = _s1_req_rmeta_WIRE_9_3_tag; // @[btb.scala:74:{29,53}] wire [6:0] _s1_req_rmeta_T_9 = _s1_req_rmeta_WIRE_10[6:0]; // @[btb.scala:74:60] wire _s1_req_rmeta_T_11; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_10; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_0_is_br = _s1_req_rmeta_WIRE_11_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_0_tag = _s1_req_rmeta_WIRE_11_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_10 = _s1_req_rmeta_WIRE_12[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_11_tag = _s1_req_rmeta_T_10; // @[btb.scala:74:93] assign _s1_req_rmeta_T_11 = _s1_req_rmeta_WIRE_12[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_11_is_br = _s1_req_rmeta_T_11; // @[btb.scala:74:93] wire _s1_req_rmeta_T_13; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_12; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_1_is_br = _s1_req_rmeta_WIRE_13_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_1_tag = _s1_req_rmeta_WIRE_13_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_12 = _s1_req_rmeta_WIRE_14[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_13_tag = _s1_req_rmeta_T_12; // @[btb.scala:74:93] assign _s1_req_rmeta_T_13 = _s1_req_rmeta_WIRE_14[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_13_is_br = _s1_req_rmeta_T_13; // @[btb.scala:74:93] wire _s1_req_rmeta_T_15; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_14; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_2_is_br = _s1_req_rmeta_WIRE_15_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_2_tag = _s1_req_rmeta_WIRE_15_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_14 = _s1_req_rmeta_WIRE_16[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_15_tag = _s1_req_rmeta_T_14; // @[btb.scala:74:93] assign _s1_req_rmeta_T_15 = _s1_req_rmeta_WIRE_16[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_15_is_br = _s1_req_rmeta_T_15; // @[btb.scala:74:93] wire _s1_req_rmeta_T_17; // @[btb.scala:74:93] wire [28:0] _s1_req_rmeta_T_16; // @[btb.scala:74:93] wire _s1_req_rmeta_WIRE_19_3_is_br = _s1_req_rmeta_WIRE_17_is_br; // @[btb.scala:74:{53,93}] wire [28:0] _s1_req_rmeta_WIRE_19_3_tag = _s1_req_rmeta_WIRE_17_tag; // @[btb.scala:74:{53,93}] assign _s1_req_rmeta_T_16 = _s1_req_rmeta_WIRE_18[28:0]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_17_tag = _s1_req_rmeta_T_16; // @[btb.scala:74:93] assign _s1_req_rmeta_T_17 = _s1_req_rmeta_WIRE_18[29]; // @[btb.scala:74:93] assign _s1_req_rmeta_WIRE_17_is_br = _s1_req_rmeta_T_17; // @[btb.scala:74:93] wire s1_req_rmeta_1_0_is_br = _s1_req_rmeta_WIRE_19_0_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_0_tag = _s1_req_rmeta_WIRE_19_0_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_1_1_is_br = _s1_req_rmeta_WIRE_19_1_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_1_tag = _s1_req_rmeta_WIRE_19_1_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_1_2_is_br = _s1_req_rmeta_WIRE_19_2_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_2_tag = _s1_req_rmeta_WIRE_19_2_tag; // @[btb.scala:74:{29,53}] wire s1_req_rmeta_1_3_is_br = _s1_req_rmeta_WIRE_19_3_is_br; // @[btb.scala:74:{29,53}] wire [28:0] s1_req_rmeta_1_3_tag = _s1_req_rmeta_WIRE_19_3_tag; // @[btb.scala:74:{29,53}] wire [28:0] _alloc_way_r_metas_WIRE_0 = s1_req_rmeta_0_0_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1 = s1_req_rmeta_0_1_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_2 = s1_req_rmeta_0_2_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_3 = s1_req_rmeta_0_3_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_0 = s1_req_rmeta_1_0_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_1 = s1_req_rmeta_1_1_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_2 = s1_req_rmeta_1_2_tag; // @[btb.scala:74:29, :123:62] wire [28:0] _alloc_way_r_metas_WIRE_1_3 = s1_req_rmeta_1_3_tag; // @[btb.scala:74:29, :123:62] wire [6:0] _s1_req_rebtb_T = _s1_req_rebtb_WIRE[6:0]; // @[btb.scala:75:31] wire [28:0] s1_req_tag = s1_idx[35:7]; // @[predictor.scala:163:29] wire [28:0] _s1_hit_ohs_T = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_2 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_4 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_6 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_8 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_10 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_12 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _s1_hit_ohs_T_14 = s1_req_tag; // @[btb.scala:76:29, :84:44] wire [28:0] _alloc_way_r_metas_T_3 = s1_req_tag; // @[btb.scala:76:29, :123:98] wire _s1_resp_0_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_0_bits_T_8; // @[btb.scala:94:28] wire _s1_resp_1_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_1_bits_T_8; // @[btb.scala:94:28] wire _s1_resp_2_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_2_bits_T_8; // @[btb.scala:94:28] wire _s1_resp_3_valid_T_2; // @[btb.scala:93:50] wire [39:0] _s1_resp_3_bits_T_8; // @[btb.scala:94:28] wire s1_resp_0_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_0_bits; // @[btb.scala:78:23] wire s1_resp_1_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_1_bits; // @[btb.scala:78:23] wire s1_resp_2_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_2_bits; // @[btb.scala:78:23] wire s1_resp_3_valid; // @[btb.scala:78:23] wire [39:0] s1_resp_3_bits; // @[btb.scala:78:23] wire _s1_is_br_0_T_2; // @[btb.scala:98:54] wire _s1_is_br_1_T_2; // @[btb.scala:98:54] wire _s1_is_br_2_T_2; // @[btb.scala:98:54] wire _s1_is_br_3_T_2; // @[btb.scala:98:54] wire s1_is_br_0; // @[btb.scala:79:23] wire s1_is_br_1; // @[btb.scala:79:23] wire s1_is_br_2; // @[btb.scala:79:23] wire s1_is_br_3; // @[btb.scala:79:23] wire _s1_is_jal_0_T_3; // @[btb.scala:99:54] wire _s1_is_jal_1_T_3; // @[btb.scala:99:54] wire _s1_is_jal_2_T_3; // @[btb.scala:99:54] wire _s1_is_jal_3_T_3; // @[btb.scala:99:54] wire s1_is_jal_0; // @[btb.scala:80:23] wire s1_is_jal_1; // @[btb.scala:80:23] wire s1_is_jal_2; // @[btb.scala:80:23] wire s1_is_jal_3; // @[btb.scala:80:23] wire _s1_hit_ohs_T_1 = s1_req_rmeta_0_0_tag == _s1_hit_ohs_T; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_0 = _s1_hit_ohs_T_1; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_3 = s1_req_rmeta_1_0_tag == _s1_hit_ohs_T_2; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_1 = _s1_hit_ohs_T_3; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_0_0 = _s1_hit_ohs_WIRE_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_0_1 = _s1_hit_ohs_WIRE_1; // @[btb.scala:82:27, :83:12] wire _s1_hit_ohs_T_5 = s1_req_rmeta_0_1_tag == _s1_hit_ohs_T_4; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_1_0 = _s1_hit_ohs_T_5; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_7 = s1_req_rmeta_1_1_tag == _s1_hit_ohs_T_6; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_1_1 = _s1_hit_ohs_T_7; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_1_0 = _s1_hit_ohs_WIRE_1_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_1_1 = _s1_hit_ohs_WIRE_1_1; // @[btb.scala:82:27, :83:12] wire _s1_hit_ohs_T_9 = s1_req_rmeta_0_2_tag == _s1_hit_ohs_T_8; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_2_0 = _s1_hit_ohs_T_9; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_11 = s1_req_rmeta_1_2_tag == _s1_hit_ohs_T_10; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_2_1 = _s1_hit_ohs_T_11; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_2_0 = _s1_hit_ohs_WIRE_2_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_2_1 = _s1_hit_ohs_WIRE_2_1; // @[btb.scala:82:27, :83:12] wire _s1_hit_ohs_T_13 = s1_req_rmeta_0_3_tag == _s1_hit_ohs_T_12; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_3_0 = _s1_hit_ohs_T_13; // @[btb.scala:83:12, :84:30] wire _s1_hit_ohs_T_15 = s1_req_rmeta_1_3_tag == _s1_hit_ohs_T_14; // @[btb.scala:74:29, :84:{30,44}] wire _s1_hit_ohs_WIRE_3_1 = _s1_hit_ohs_T_15; // @[btb.scala:83:12, :84:30] wire s1_hit_ohs_3_0 = _s1_hit_ohs_WIRE_3_0; // @[btb.scala:82:27, :83:12] wire s1_hit_ohs_3_1 = _s1_hit_ohs_WIRE_3_1; // @[btb.scala:82:27, :83:12] wire s1_hits_0 = s1_hit_ohs_0_0 | s1_hit_ohs_0_1; // @[btb.scala:82:27, :87:55] wire s1_hits_1 = s1_hit_ohs_1_0 | s1_hit_ohs_1_1; // @[btb.scala:82:27, :87:55] wire s1_hits_2 = s1_hit_ohs_2_0 | s1_hit_ohs_2_1; // @[btb.scala:82:27, :87:55] wire s1_hits_3 = s1_hit_ohs_3_0 | s1_hit_ohs_3_1; // @[btb.scala:82:27, :87:55] wire s1_hit_ways_0 = ~s1_hit_ohs_0_0; // @[Mux.scala:50:70] wire s1_hit_ways_1 = ~s1_hit_ohs_1_0; // @[Mux.scala:50:70] wire s1_hit_ways_2 = ~s1_hit_ohs_2_0; // @[Mux.scala:50:70] wire s1_hit_ways_3 = ~s1_hit_ohs_3_0; // @[Mux.scala:50:70] wire _s1_resp_0_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_0_valid_T_1 = _s1_resp_0_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_0_valid_T_2 = _s1_resp_0_valid_T_1 & s1_hits_0; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_0_valid = _s1_resp_0_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_0_bits_T_1 = {_s1_resp_0_bits_T[39], _s1_resp_0_bits_T}; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_0_bits_T_2 = _s1_resp_0_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_0_bits_T_3 = _s1_resp_0_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN = s1_hit_ways_0 ? s1_req_rbtb_1_0_offset : s1_req_rbtb_0_0_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_0_bits_T_4 = {_s1_resp_0_bits_T_3[39], _s1_resp_0_bits_T_3} + {{28{_GEN[12]}}, _GEN}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_0_bits_T_5 = _s1_resp_0_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_0_bits_T_6 = _s1_resp_0_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_0_bits_T_7 = _s1_resp_0_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_0_bits_T_8 = (s1_hit_ways_0 ? s1_req_rbtb_1_0_extended : s1_req_rbtb_0_0_extended) ? _ebtb_R0_data : _s1_resp_0_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_0_bits = _s1_resp_0_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_0_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_0_T_1 = _s1_is_br_0_T & s1_resp_0_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_0 = s1_hit_ways_0 ? s1_req_rmeta_1_0_is_br : s1_req_rmeta_0_0_is_br; // @[Mux.scala:50:70] assign _s1_is_br_0_T_2 = _s1_is_br_0_T_1 & _GEN_0; // @[btb.scala:98:{34,54}] assign s1_is_br_0 = _s1_is_br_0_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_0_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_0_T_1 = _s1_is_jal_0_T & s1_resp_0_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_0_T_2 = ~_GEN_0; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_0_T_3 = _s1_is_jal_0_T_1 & _s1_is_jal_0_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_0 = _s1_is_jal_0_T_3; // @[btb.scala:80:23, :99:54] reg REG; // @[btb.scala:104:18] reg io_resp_f2_0_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_0_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_0_predicted_pc_valid_0 = REG ? io_resp_f2_0_predicted_pc_REG_valid : io_resp_in_0_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_0_predicted_pc_bits_0 = REG ? io_resp_f2_0_predicted_pc_REG_bits : io_resp_in_0_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_0_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_0_is_br_0 = REG ? io_resp_f2_0_is_br_REG : io_resp_in_0_f2_0_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_0_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_0_is_jal_0 = REG ? io_resp_f2_0_is_jal_REG : io_resp_in_0_f2_0_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_1; // @[btb.scala:108:20] assign io_resp_f2_0_taken_0 = REG & REG_1 | io_resp_in_0_f2_0_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_2; // @[btb.scala:112:26] reg REG_3; // @[btb.scala:112:18] reg io_resp_f3_0_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_0_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_0_predicted_pc_valid_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_valid : io_resp_in_0_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_0_predicted_pc_bits_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_bits : io_resp_in_0_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_0_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_0_is_br_0 = REG_3 ? io_resp_f3_0_is_br_REG : io_resp_in_0_f3_0_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_0_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_0_is_jal_0 = REG_3 ? io_resp_f3_0_is_jal_REG : io_resp_in_0_f3_0_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_4; // @[btb.scala:116:28] reg REG_5; // @[btb.scala:116:20] assign io_resp_f3_0_taken_0 = REG_3 & REG_5 | io_resp_in_0_f3_0_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire _s1_resp_1_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_1_valid_T_1 = _s1_resp_1_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_1_valid_T_2 = _s1_resp_1_valid_T_1 & s1_hits_1; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_1_valid = _s1_resp_1_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_1_bits_T_1 = {_s1_resp_1_bits_T[39], _s1_resp_1_bits_T} + 41'h2; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_1_bits_T_2 = _s1_resp_1_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_1_bits_T_3 = _s1_resp_1_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN_1 = s1_hit_ways_1 ? s1_req_rbtb_1_1_offset : s1_req_rbtb_0_1_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_1_bits_T_4 = {_s1_resp_1_bits_T_3[39], _s1_resp_1_bits_T_3} + {{28{_GEN_1[12]}}, _GEN_1}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_1_bits_T_5 = _s1_resp_1_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_1_bits_T_6 = _s1_resp_1_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_1_bits_T_7 = _s1_resp_1_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_1_bits_T_8 = (s1_hit_ways_1 ? s1_req_rbtb_1_1_extended : s1_req_rbtb_0_1_extended) ? _ebtb_R0_data : _s1_resp_1_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_1_bits = _s1_resp_1_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_1_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_1_T_1 = _s1_is_br_1_T & s1_resp_1_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_2 = s1_hit_ways_1 ? s1_req_rmeta_1_1_is_br : s1_req_rmeta_0_1_is_br; // @[Mux.scala:50:70] assign _s1_is_br_1_T_2 = _s1_is_br_1_T_1 & _GEN_2; // @[btb.scala:98:{34,54}] assign s1_is_br_1 = _s1_is_br_1_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_1_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_1_T_1 = _s1_is_jal_1_T & s1_resp_1_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_1_T_2 = ~_GEN_2; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_1_T_3 = _s1_is_jal_1_T_1 & _s1_is_jal_1_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_1 = _s1_is_jal_1_T_3; // @[btb.scala:80:23, :99:54] reg REG_6; // @[btb.scala:104:18] reg io_resp_f2_1_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_1_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_1_predicted_pc_valid_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_valid : io_resp_in_0_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_1_predicted_pc_bits_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_bits : io_resp_in_0_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_1_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_1_is_br_0 = REG_6 ? io_resp_f2_1_is_br_REG : io_resp_in_0_f2_1_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_1_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_1_is_jal_0 = REG_6 ? io_resp_f2_1_is_jal_REG : io_resp_in_0_f2_1_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_7; // @[btb.scala:108:20] assign io_resp_f2_1_taken_0 = REG_6 & REG_7 | io_resp_in_0_f2_1_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_8; // @[btb.scala:112:26] reg REG_9; // @[btb.scala:112:18] reg io_resp_f3_1_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_1_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_1_predicted_pc_valid_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_valid : io_resp_in_0_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_1_predicted_pc_bits_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_bits : io_resp_in_0_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_1_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_1_is_br_0 = REG_9 ? io_resp_f3_1_is_br_REG : io_resp_in_0_f3_1_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_1_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_1_is_jal_0 = REG_9 ? io_resp_f3_1_is_jal_REG : io_resp_in_0_f3_1_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_10; // @[btb.scala:116:28] reg REG_11; // @[btb.scala:116:20] assign io_resp_f3_1_taken_0 = REG_9 & REG_11 | io_resp_in_0_f3_1_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire _s1_resp_2_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_2_valid_T_1 = _s1_resp_2_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_2_valid_T_2 = _s1_resp_2_valid_T_1 & s1_hits_2; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_2_valid = _s1_resp_2_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_2_bits_T_1 = {_s1_resp_2_bits_T[39], _s1_resp_2_bits_T} + 41'h4; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_2_bits_T_2 = _s1_resp_2_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_2_bits_T_3 = _s1_resp_2_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN_3 = s1_hit_ways_2 ? s1_req_rbtb_1_2_offset : s1_req_rbtb_0_2_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_2_bits_T_4 = {_s1_resp_2_bits_T_3[39], _s1_resp_2_bits_T_3} + {{28{_GEN_3[12]}}, _GEN_3}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_2_bits_T_5 = _s1_resp_2_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_2_bits_T_6 = _s1_resp_2_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_2_bits_T_7 = _s1_resp_2_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_2_bits_T_8 = (s1_hit_ways_2 ? s1_req_rbtb_1_2_extended : s1_req_rbtb_0_2_extended) ? _ebtb_R0_data : _s1_resp_2_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_2_bits = _s1_resp_2_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_2_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_2_T_1 = _s1_is_br_2_T & s1_resp_2_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_4 = s1_hit_ways_2 ? s1_req_rmeta_1_2_is_br : s1_req_rmeta_0_2_is_br; // @[Mux.scala:50:70] assign _s1_is_br_2_T_2 = _s1_is_br_2_T_1 & _GEN_4; // @[btb.scala:98:{34,54}] assign s1_is_br_2 = _s1_is_br_2_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_2_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_2_T_1 = _s1_is_jal_2_T & s1_resp_2_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_2_T_2 = ~_GEN_4; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_2_T_3 = _s1_is_jal_2_T_1 & _s1_is_jal_2_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_2 = _s1_is_jal_2_T_3; // @[btb.scala:80:23, :99:54] reg REG_12; // @[btb.scala:104:18] reg io_resp_f2_2_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_2_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_2_predicted_pc_valid_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_valid : io_resp_in_0_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_2_predicted_pc_bits_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_bits : io_resp_in_0_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_2_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_2_is_br_0 = REG_12 ? io_resp_f2_2_is_br_REG : io_resp_in_0_f2_2_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_2_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_2_is_jal_0 = REG_12 ? io_resp_f2_2_is_jal_REG : io_resp_in_0_f2_2_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_13; // @[btb.scala:108:20] assign io_resp_f2_2_taken_0 = REG_12 & REG_13 | io_resp_in_0_f2_2_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_14; // @[btb.scala:112:26] reg REG_15; // @[btb.scala:112:18] reg io_resp_f3_2_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_2_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_2_predicted_pc_valid_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_valid : io_resp_in_0_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_2_predicted_pc_bits_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_bits : io_resp_in_0_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_2_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_2_is_br_0 = REG_15 ? io_resp_f3_2_is_br_REG : io_resp_in_0_f3_2_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_2_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_2_is_jal_0 = REG_15 ? io_resp_f3_2_is_jal_REG : io_resp_in_0_f3_2_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_16; // @[btb.scala:116:28] reg REG_17; // @[btb.scala:116:20] assign io_resp_f3_2_taken_0 = REG_15 & REG_17 | io_resp_in_0_f3_2_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire _s1_resp_3_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25] wire _s1_resp_3_valid_T_1 = _s1_resp_3_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_3_valid_T_2 = _s1_resp_3_valid_T_1 & s1_hits_3; // @[btb.scala:87:55, :93:{38,50}] assign s1_resp_3_valid = _s1_resp_3_valid_T_2; // @[btb.scala:78:23, :93:50] wire [40:0] _s1_resp_3_bits_T_1 = {_s1_resp_3_bits_T[39], _s1_resp_3_bits_T} + 41'h6; // @[btb.scala:97:{14,21}] wire [39:0] _s1_resp_3_bits_T_2 = _s1_resp_3_bits_T_1[39:0]; // @[btb.scala:97:21] wire [39:0] _s1_resp_3_bits_T_3 = _s1_resp_3_bits_T_2; // @[btb.scala:97:21] wire [12:0] _GEN_5 = s1_hit_ways_3 ? s1_req_rbtb_1_3_offset : s1_req_rbtb_0_3_offset; // @[Mux.scala:50:70] wire [40:0] _s1_resp_3_bits_T_4 = {_s1_resp_3_bits_T_3[39], _s1_resp_3_bits_T_3} + {{28{_GEN_5[12]}}, _GEN_5}; // @[btb.scala:97:{21,34}] wire [39:0] _s1_resp_3_bits_T_5 = _s1_resp_3_bits_T_4[39:0]; // @[btb.scala:97:34] wire [39:0] _s1_resp_3_bits_T_6 = _s1_resp_3_bits_T_5; // @[btb.scala:97:34] wire [39:0] _s1_resp_3_bits_T_7 = _s1_resp_3_bits_T_6; // @[btb.scala:97:{34,54}] assign _s1_resp_3_bits_T_8 = (s1_hit_ways_3 ? s1_req_rbtb_1_3_extended : s1_req_rbtb_0_3_extended) ? _ebtb_R0_data : _s1_resp_3_bits_T_7; // @[Mux.scala:50:70] assign s1_resp_3_bits = _s1_resp_3_bits_T_8; // @[btb.scala:78:23, :94:28] wire _s1_is_br_3_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21] wire _s1_is_br_3_T_1 = _s1_is_br_3_T & s1_resp_3_valid; // @[btb.scala:78:23, :98:{21,34}] wire _GEN_6 = s1_hit_ways_3 ? s1_req_rmeta_1_3_is_br : s1_req_rmeta_0_3_is_br; // @[Mux.scala:50:70] assign _s1_is_br_3_T_2 = _s1_is_br_3_T_1 & _GEN_6; // @[btb.scala:98:{34,54}] assign s1_is_br_3 = _s1_is_br_3_T_2; // @[btb.scala:79:23, :98:54] wire _s1_is_jal_3_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21] wire _s1_is_jal_3_T_1 = _s1_is_jal_3_T & s1_resp_3_valid; // @[btb.scala:78:23, :99:{21,34}] wire _s1_is_jal_3_T_2 = ~_GEN_6; // @[btb.scala:98:54, :99:57] assign _s1_is_jal_3_T_3 = _s1_is_jal_3_T_1 & _s1_is_jal_3_T_2; // @[btb.scala:99:{34,54,57}] assign s1_is_jal_3 = _s1_is_jal_3_T_3; // @[btb.scala:80:23, :99:54] reg REG_18; // @[btb.scala:104:18] reg io_resp_f2_3_predicted_pc_REG_valid; // @[btb.scala:105:44] reg [39:0] io_resp_f2_3_predicted_pc_REG_bits; // @[btb.scala:105:44] assign io_resp_f2_3_predicted_pc_valid_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_valid : io_resp_in_0_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] assign io_resp_f2_3_predicted_pc_bits_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_bits : io_resp_in_0_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}] reg io_resp_f2_3_is_br_REG; // @[btb.scala:106:44] assign io_resp_f2_3_is_br_0 = REG_18 ? io_resp_f2_3_is_br_REG : io_resp_in_0_f2_3_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}] reg io_resp_f2_3_is_jal_REG; // @[btb.scala:107:44] assign io_resp_f2_3_is_jal_0 = REG_18 ? io_resp_f2_3_is_jal_REG : io_resp_in_0_f2_3_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}] reg REG_19; // @[btb.scala:108:20] assign io_resp_f2_3_taken_0 = REG_18 & REG_19 | io_resp_in_0_f2_3_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34] reg REG_20; // @[btb.scala:112:26] reg REG_21; // @[btb.scala:112:18] reg io_resp_f3_3_predicted_pc_REG_valid; // @[btb.scala:113:44] reg [39:0] io_resp_f3_3_predicted_pc_REG_bits; // @[btb.scala:113:44] assign io_resp_f3_3_predicted_pc_valid_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_valid : io_resp_in_0_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] assign io_resp_f3_3_predicted_pc_bits_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_bits : io_resp_in_0_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}] reg io_resp_f3_3_is_br_REG; // @[btb.scala:114:44] assign io_resp_f3_3_is_br_0 = REG_21 ? io_resp_f3_3_is_br_REG : io_resp_in_0_f3_3_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}] reg io_resp_f3_3_is_jal_REG; // @[btb.scala:115:44] assign io_resp_f3_3_is_jal_0 = REG_21 ? io_resp_f3_3_is_jal_REG : io_resp_in_0_f3_3_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}] reg REG_22; // @[btb.scala:116:28] reg REG_23; // @[btb.scala:116:20] assign io_resp_f3_3_taken_0 = REG_21 & REG_23 | io_resp_in_0_f3_3_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34] wire [28:0] _alloc_way_r_metas_WIRE_2_0_0 = _alloc_way_r_metas_WIRE_0; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_1 = _alloc_way_r_metas_WIRE_1; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_2 = _alloc_way_r_metas_WIRE_2; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_3 = _alloc_way_r_metas_WIRE_3; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_0 = _alloc_way_r_metas_WIRE_1_0; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_1 = _alloc_way_r_metas_WIRE_1_1; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_2 = _alloc_way_r_metas_WIRE_1_2; // @[btb.scala:123:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_3 = _alloc_way_r_metas_WIRE_1_3; // @[btb.scala:123:{30,62}] wire [57:0] alloc_way_r_metas_lo = {_alloc_way_r_metas_WIRE_2_0_1, _alloc_way_r_metas_WIRE_2_0_0}; // @[btb.scala:123:{30,80}] wire [57:0] alloc_way_r_metas_hi = {_alloc_way_r_metas_WIRE_2_0_3, _alloc_way_r_metas_WIRE_2_0_2}; // @[btb.scala:123:{30,80}] wire [115:0] _alloc_way_r_metas_T = {alloc_way_r_metas_hi, alloc_way_r_metas_lo}; // @[btb.scala:123:80] wire [57:0] alloc_way_r_metas_lo_1 = {_alloc_way_r_metas_WIRE_2_1_1, _alloc_way_r_metas_WIRE_2_1_0}; // @[btb.scala:123:{30,80}] wire [57:0] alloc_way_r_metas_hi_1 = {_alloc_way_r_metas_WIRE_2_1_3, _alloc_way_r_metas_WIRE_2_1_2}; // @[btb.scala:123:{30,80}] wire [115:0] _alloc_way_r_metas_T_1 = {alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1}; // @[btb.scala:123:80] wire [231:0] _alloc_way_r_metas_T_2 = {_alloc_way_r_metas_T_1, _alloc_way_r_metas_T}; // @[btb.scala:123:80] wire [260:0] alloc_way_r_metas = {_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3}; // @[btb.scala:123:{22,80,98}] wire alloc_way_chunks_0 = alloc_way_r_metas[0]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_1 = alloc_way_r_metas[1]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_2 = alloc_way_r_metas[2]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_3 = alloc_way_r_metas[3]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_4 = alloc_way_r_metas[4]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_5 = alloc_way_r_metas[5]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_6 = alloc_way_r_metas[6]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_7 = alloc_way_r_metas[7]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_8 = alloc_way_r_metas[8]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_9 = alloc_way_r_metas[9]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_10 = alloc_way_r_metas[10]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_11 = alloc_way_r_metas[11]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_12 = alloc_way_r_metas[12]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_13 = alloc_way_r_metas[13]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_14 = alloc_way_r_metas[14]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_15 = alloc_way_r_metas[15]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_16 = alloc_way_r_metas[16]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_17 = alloc_way_r_metas[17]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_18 = alloc_way_r_metas[18]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_19 = alloc_way_r_metas[19]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_20 = alloc_way_r_metas[20]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_21 = alloc_way_r_metas[21]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_22 = alloc_way_r_metas[22]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_23 = alloc_way_r_metas[23]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_24 = alloc_way_r_metas[24]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_25 = alloc_way_r_metas[25]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_26 = alloc_way_r_metas[26]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_27 = alloc_way_r_metas[27]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_28 = alloc_way_r_metas[28]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_29 = alloc_way_r_metas[29]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_30 = alloc_way_r_metas[30]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_31 = alloc_way_r_metas[31]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_32 = alloc_way_r_metas[32]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_33 = alloc_way_r_metas[33]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_34 = alloc_way_r_metas[34]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_35 = alloc_way_r_metas[35]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_36 = alloc_way_r_metas[36]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_37 = alloc_way_r_metas[37]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_38 = alloc_way_r_metas[38]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_39 = alloc_way_r_metas[39]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_40 = alloc_way_r_metas[40]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_41 = alloc_way_r_metas[41]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_42 = alloc_way_r_metas[42]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_43 = alloc_way_r_metas[43]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_44 = alloc_way_r_metas[44]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_45 = alloc_way_r_metas[45]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_46 = alloc_way_r_metas[46]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_47 = alloc_way_r_metas[47]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_48 = alloc_way_r_metas[48]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_49 = alloc_way_r_metas[49]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_50 = alloc_way_r_metas[50]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_51 = alloc_way_r_metas[51]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_52 = alloc_way_r_metas[52]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_53 = alloc_way_r_metas[53]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_54 = alloc_way_r_metas[54]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_55 = alloc_way_r_metas[55]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_56 = alloc_way_r_metas[56]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_57 = alloc_way_r_metas[57]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_58 = alloc_way_r_metas[58]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_59 = alloc_way_r_metas[59]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_60 = alloc_way_r_metas[60]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_61 = alloc_way_r_metas[61]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_62 = alloc_way_r_metas[62]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_63 = alloc_way_r_metas[63]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_64 = alloc_way_r_metas[64]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_65 = alloc_way_r_metas[65]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_66 = alloc_way_r_metas[66]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_67 = alloc_way_r_metas[67]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_68 = alloc_way_r_metas[68]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_69 = alloc_way_r_metas[69]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_70 = alloc_way_r_metas[70]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_71 = alloc_way_r_metas[71]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_72 = alloc_way_r_metas[72]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_73 = alloc_way_r_metas[73]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_74 = alloc_way_r_metas[74]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_75 = alloc_way_r_metas[75]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_76 = alloc_way_r_metas[76]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_77 = alloc_way_r_metas[77]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_78 = alloc_way_r_metas[78]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_79 = alloc_way_r_metas[79]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_80 = alloc_way_r_metas[80]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_81 = alloc_way_r_metas[81]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_82 = alloc_way_r_metas[82]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_83 = alloc_way_r_metas[83]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_84 = alloc_way_r_metas[84]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_85 = alloc_way_r_metas[85]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_86 = alloc_way_r_metas[86]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_87 = alloc_way_r_metas[87]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_88 = alloc_way_r_metas[88]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_89 = alloc_way_r_metas[89]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_90 = alloc_way_r_metas[90]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_91 = alloc_way_r_metas[91]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_92 = alloc_way_r_metas[92]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_93 = alloc_way_r_metas[93]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_94 = alloc_way_r_metas[94]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_95 = alloc_way_r_metas[95]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_96 = alloc_way_r_metas[96]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_97 = alloc_way_r_metas[97]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_98 = alloc_way_r_metas[98]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_99 = alloc_way_r_metas[99]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_100 = alloc_way_r_metas[100]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_101 = alloc_way_r_metas[101]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_102 = alloc_way_r_metas[102]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_103 = alloc_way_r_metas[103]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_104 = alloc_way_r_metas[104]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_105 = alloc_way_r_metas[105]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_106 = alloc_way_r_metas[106]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_107 = alloc_way_r_metas[107]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_108 = alloc_way_r_metas[108]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_109 = alloc_way_r_metas[109]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_110 = alloc_way_r_metas[110]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_111 = alloc_way_r_metas[111]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_112 = alloc_way_r_metas[112]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_113 = alloc_way_r_metas[113]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_114 = alloc_way_r_metas[114]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_115 = alloc_way_r_metas[115]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_116 = alloc_way_r_metas[116]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_117 = alloc_way_r_metas[117]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_118 = alloc_way_r_metas[118]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_119 = alloc_way_r_metas[119]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_120 = alloc_way_r_metas[120]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_121 = alloc_way_r_metas[121]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_122 = alloc_way_r_metas[122]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_123 = alloc_way_r_metas[123]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_124 = alloc_way_r_metas[124]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_125 = alloc_way_r_metas[125]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_126 = alloc_way_r_metas[126]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_127 = alloc_way_r_metas[127]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_128 = alloc_way_r_metas[128]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_129 = alloc_way_r_metas[129]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_130 = alloc_way_r_metas[130]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_131 = alloc_way_r_metas[131]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_132 = alloc_way_r_metas[132]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_133 = alloc_way_r_metas[133]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_134 = alloc_way_r_metas[134]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_135 = alloc_way_r_metas[135]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_136 = alloc_way_r_metas[136]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_137 = alloc_way_r_metas[137]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_138 = alloc_way_r_metas[138]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_139 = alloc_way_r_metas[139]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_140 = alloc_way_r_metas[140]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_141 = alloc_way_r_metas[141]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_142 = alloc_way_r_metas[142]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_143 = alloc_way_r_metas[143]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_144 = alloc_way_r_metas[144]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_145 = alloc_way_r_metas[145]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_146 = alloc_way_r_metas[146]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_147 = alloc_way_r_metas[147]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_148 = alloc_way_r_metas[148]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_149 = alloc_way_r_metas[149]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_150 = alloc_way_r_metas[150]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_151 = alloc_way_r_metas[151]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_152 = alloc_way_r_metas[152]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_153 = alloc_way_r_metas[153]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_154 = alloc_way_r_metas[154]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_155 = alloc_way_r_metas[155]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_156 = alloc_way_r_metas[156]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_157 = alloc_way_r_metas[157]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_158 = alloc_way_r_metas[158]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_159 = alloc_way_r_metas[159]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_160 = alloc_way_r_metas[160]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_161 = alloc_way_r_metas[161]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_162 = alloc_way_r_metas[162]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_163 = alloc_way_r_metas[163]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_164 = alloc_way_r_metas[164]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_165 = alloc_way_r_metas[165]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_166 = alloc_way_r_metas[166]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_167 = alloc_way_r_metas[167]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_168 = alloc_way_r_metas[168]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_169 = alloc_way_r_metas[169]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_170 = alloc_way_r_metas[170]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_171 = alloc_way_r_metas[171]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_172 = alloc_way_r_metas[172]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_173 = alloc_way_r_metas[173]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_174 = alloc_way_r_metas[174]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_175 = alloc_way_r_metas[175]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_176 = alloc_way_r_metas[176]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_177 = alloc_way_r_metas[177]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_178 = alloc_way_r_metas[178]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_179 = alloc_way_r_metas[179]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_180 = alloc_way_r_metas[180]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_181 = alloc_way_r_metas[181]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_182 = alloc_way_r_metas[182]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_183 = alloc_way_r_metas[183]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_184 = alloc_way_r_metas[184]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_185 = alloc_way_r_metas[185]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_186 = alloc_way_r_metas[186]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_187 = alloc_way_r_metas[187]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_188 = alloc_way_r_metas[188]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_189 = alloc_way_r_metas[189]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_190 = alloc_way_r_metas[190]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_191 = alloc_way_r_metas[191]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_192 = alloc_way_r_metas[192]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_193 = alloc_way_r_metas[193]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_194 = alloc_way_r_metas[194]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_195 = alloc_way_r_metas[195]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_196 = alloc_way_r_metas[196]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_197 = alloc_way_r_metas[197]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_198 = alloc_way_r_metas[198]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_199 = alloc_way_r_metas[199]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_200 = alloc_way_r_metas[200]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_201 = alloc_way_r_metas[201]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_202 = alloc_way_r_metas[202]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_203 = alloc_way_r_metas[203]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_204 = alloc_way_r_metas[204]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_205 = alloc_way_r_metas[205]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_206 = alloc_way_r_metas[206]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_207 = alloc_way_r_metas[207]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_208 = alloc_way_r_metas[208]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_209 = alloc_way_r_metas[209]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_210 = alloc_way_r_metas[210]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_211 = alloc_way_r_metas[211]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_212 = alloc_way_r_metas[212]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_213 = alloc_way_r_metas[213]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_214 = alloc_way_r_metas[214]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_215 = alloc_way_r_metas[215]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_216 = alloc_way_r_metas[216]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_217 = alloc_way_r_metas[217]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_218 = alloc_way_r_metas[218]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_219 = alloc_way_r_metas[219]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_220 = alloc_way_r_metas[220]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_221 = alloc_way_r_metas[221]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_222 = alloc_way_r_metas[222]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_223 = alloc_way_r_metas[223]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_224 = alloc_way_r_metas[224]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_225 = alloc_way_r_metas[225]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_226 = alloc_way_r_metas[226]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_227 = alloc_way_r_metas[227]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_228 = alloc_way_r_metas[228]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_229 = alloc_way_r_metas[229]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_230 = alloc_way_r_metas[230]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_231 = alloc_way_r_metas[231]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_232 = alloc_way_r_metas[232]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_233 = alloc_way_r_metas[233]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_234 = alloc_way_r_metas[234]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_235 = alloc_way_r_metas[235]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_236 = alloc_way_r_metas[236]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_237 = alloc_way_r_metas[237]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_238 = alloc_way_r_metas[238]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_239 = alloc_way_r_metas[239]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_240 = alloc_way_r_metas[240]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_241 = alloc_way_r_metas[241]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_242 = alloc_way_r_metas[242]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_243 = alloc_way_r_metas[243]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_244 = alloc_way_r_metas[244]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_245 = alloc_way_r_metas[245]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_246 = alloc_way_r_metas[246]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_247 = alloc_way_r_metas[247]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_248 = alloc_way_r_metas[248]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_249 = alloc_way_r_metas[249]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_250 = alloc_way_r_metas[250]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_251 = alloc_way_r_metas[251]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_252 = alloc_way_r_metas[252]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_253 = alloc_way_r_metas[253]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_254 = alloc_way_r_metas[254]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_255 = alloc_way_r_metas[255]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_256 = alloc_way_r_metas[256]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_257 = alloc_way_r_metas[257]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_258 = alloc_way_r_metas[258]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_259 = alloc_way_r_metas[259]; // @[btb.scala:123:22, :127:14] wire alloc_way_chunks_260 = alloc_way_r_metas[260]; // @[btb.scala:123:22, :127:14] wire _alloc_way_T = alloc_way_chunks_0 ^ alloc_way_chunks_1; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_1 = _alloc_way_T ^ alloc_way_chunks_2; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_2 = _alloc_way_T_1 ^ alloc_way_chunks_3; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_3 = _alloc_way_T_2 ^ alloc_way_chunks_4; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_4 = _alloc_way_T_3 ^ alloc_way_chunks_5; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_5 = _alloc_way_T_4 ^ alloc_way_chunks_6; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_6 = _alloc_way_T_5 ^ alloc_way_chunks_7; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_7 = _alloc_way_T_6 ^ alloc_way_chunks_8; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_8 = _alloc_way_T_7 ^ alloc_way_chunks_9; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_9 = _alloc_way_T_8 ^ alloc_way_chunks_10; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_10 = _alloc_way_T_9 ^ alloc_way_chunks_11; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_11 = _alloc_way_T_10 ^ alloc_way_chunks_12; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_12 = _alloc_way_T_11 ^ alloc_way_chunks_13; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_13 = _alloc_way_T_12 ^ alloc_way_chunks_14; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_14 = _alloc_way_T_13 ^ alloc_way_chunks_15; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_15 = _alloc_way_T_14 ^ alloc_way_chunks_16; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_16 = _alloc_way_T_15 ^ alloc_way_chunks_17; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_17 = _alloc_way_T_16 ^ alloc_way_chunks_18; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_18 = _alloc_way_T_17 ^ alloc_way_chunks_19; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_19 = _alloc_way_T_18 ^ alloc_way_chunks_20; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_20 = _alloc_way_T_19 ^ alloc_way_chunks_21; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_21 = _alloc_way_T_20 ^ alloc_way_chunks_22; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_22 = _alloc_way_T_21 ^ alloc_way_chunks_23; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_23 = _alloc_way_T_22 ^ alloc_way_chunks_24; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_24 = _alloc_way_T_23 ^ alloc_way_chunks_25; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_25 = _alloc_way_T_24 ^ alloc_way_chunks_26; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_26 = _alloc_way_T_25 ^ alloc_way_chunks_27; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_27 = _alloc_way_T_26 ^ alloc_way_chunks_28; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_28 = _alloc_way_T_27 ^ alloc_way_chunks_29; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_29 = _alloc_way_T_28 ^ alloc_way_chunks_30; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_30 = _alloc_way_T_29 ^ alloc_way_chunks_31; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_31 = _alloc_way_T_30 ^ alloc_way_chunks_32; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_32 = _alloc_way_T_31 ^ alloc_way_chunks_33; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_33 = _alloc_way_T_32 ^ alloc_way_chunks_34; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_34 = _alloc_way_T_33 ^ alloc_way_chunks_35; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_35 = _alloc_way_T_34 ^ alloc_way_chunks_36; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_36 = _alloc_way_T_35 ^ alloc_way_chunks_37; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_37 = _alloc_way_T_36 ^ alloc_way_chunks_38; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_38 = _alloc_way_T_37 ^ alloc_way_chunks_39; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_39 = _alloc_way_T_38 ^ alloc_way_chunks_40; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_40 = _alloc_way_T_39 ^ alloc_way_chunks_41; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_41 = _alloc_way_T_40 ^ alloc_way_chunks_42; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_42 = _alloc_way_T_41 ^ alloc_way_chunks_43; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_43 = _alloc_way_T_42 ^ alloc_way_chunks_44; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_44 = _alloc_way_T_43 ^ alloc_way_chunks_45; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_45 = _alloc_way_T_44 ^ alloc_way_chunks_46; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_46 = _alloc_way_T_45 ^ alloc_way_chunks_47; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_47 = _alloc_way_T_46 ^ alloc_way_chunks_48; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_48 = _alloc_way_T_47 ^ alloc_way_chunks_49; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_49 = _alloc_way_T_48 ^ alloc_way_chunks_50; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_50 = _alloc_way_T_49 ^ alloc_way_chunks_51; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_51 = _alloc_way_T_50 ^ alloc_way_chunks_52; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_52 = _alloc_way_T_51 ^ alloc_way_chunks_53; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_53 = _alloc_way_T_52 ^ alloc_way_chunks_54; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_54 = _alloc_way_T_53 ^ alloc_way_chunks_55; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_55 = _alloc_way_T_54 ^ alloc_way_chunks_56; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_56 = _alloc_way_T_55 ^ alloc_way_chunks_57; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_57 = _alloc_way_T_56 ^ alloc_way_chunks_58; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_58 = _alloc_way_T_57 ^ alloc_way_chunks_59; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_59 = _alloc_way_T_58 ^ alloc_way_chunks_60; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_60 = _alloc_way_T_59 ^ alloc_way_chunks_61; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_61 = _alloc_way_T_60 ^ alloc_way_chunks_62; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_62 = _alloc_way_T_61 ^ alloc_way_chunks_63; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_63 = _alloc_way_T_62 ^ alloc_way_chunks_64; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_64 = _alloc_way_T_63 ^ alloc_way_chunks_65; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_65 = _alloc_way_T_64 ^ alloc_way_chunks_66; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_66 = _alloc_way_T_65 ^ alloc_way_chunks_67; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_67 = _alloc_way_T_66 ^ alloc_way_chunks_68; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_68 = _alloc_way_T_67 ^ alloc_way_chunks_69; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_69 = _alloc_way_T_68 ^ alloc_way_chunks_70; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_70 = _alloc_way_T_69 ^ alloc_way_chunks_71; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_71 = _alloc_way_T_70 ^ alloc_way_chunks_72; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_72 = _alloc_way_T_71 ^ alloc_way_chunks_73; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_73 = _alloc_way_T_72 ^ alloc_way_chunks_74; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_74 = _alloc_way_T_73 ^ alloc_way_chunks_75; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_75 = _alloc_way_T_74 ^ alloc_way_chunks_76; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_76 = _alloc_way_T_75 ^ alloc_way_chunks_77; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_77 = _alloc_way_T_76 ^ alloc_way_chunks_78; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_78 = _alloc_way_T_77 ^ alloc_way_chunks_79; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_79 = _alloc_way_T_78 ^ alloc_way_chunks_80; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_80 = _alloc_way_T_79 ^ alloc_way_chunks_81; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_81 = _alloc_way_T_80 ^ alloc_way_chunks_82; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_82 = _alloc_way_T_81 ^ alloc_way_chunks_83; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_83 = _alloc_way_T_82 ^ alloc_way_chunks_84; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_84 = _alloc_way_T_83 ^ alloc_way_chunks_85; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_85 = _alloc_way_T_84 ^ alloc_way_chunks_86; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_86 = _alloc_way_T_85 ^ alloc_way_chunks_87; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_87 = _alloc_way_T_86 ^ alloc_way_chunks_88; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_88 = _alloc_way_T_87 ^ alloc_way_chunks_89; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_89 = _alloc_way_T_88 ^ alloc_way_chunks_90; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_90 = _alloc_way_T_89 ^ alloc_way_chunks_91; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_91 = _alloc_way_T_90 ^ alloc_way_chunks_92; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_92 = _alloc_way_T_91 ^ alloc_way_chunks_93; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_93 = _alloc_way_T_92 ^ alloc_way_chunks_94; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_94 = _alloc_way_T_93 ^ alloc_way_chunks_95; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_95 = _alloc_way_T_94 ^ alloc_way_chunks_96; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_96 = _alloc_way_T_95 ^ alloc_way_chunks_97; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_97 = _alloc_way_T_96 ^ alloc_way_chunks_98; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_98 = _alloc_way_T_97 ^ alloc_way_chunks_99; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_99 = _alloc_way_T_98 ^ alloc_way_chunks_100; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_100 = _alloc_way_T_99 ^ alloc_way_chunks_101; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_101 = _alloc_way_T_100 ^ alloc_way_chunks_102; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_102 = _alloc_way_T_101 ^ alloc_way_chunks_103; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_103 = _alloc_way_T_102 ^ alloc_way_chunks_104; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_104 = _alloc_way_T_103 ^ alloc_way_chunks_105; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_105 = _alloc_way_T_104 ^ alloc_way_chunks_106; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_106 = _alloc_way_T_105 ^ alloc_way_chunks_107; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_107 = _alloc_way_T_106 ^ alloc_way_chunks_108; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_108 = _alloc_way_T_107 ^ alloc_way_chunks_109; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_109 = _alloc_way_T_108 ^ alloc_way_chunks_110; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_110 = _alloc_way_T_109 ^ alloc_way_chunks_111; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_111 = _alloc_way_T_110 ^ alloc_way_chunks_112; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_112 = _alloc_way_T_111 ^ alloc_way_chunks_113; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_113 = _alloc_way_T_112 ^ alloc_way_chunks_114; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_114 = _alloc_way_T_113 ^ alloc_way_chunks_115; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_115 = _alloc_way_T_114 ^ alloc_way_chunks_116; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_116 = _alloc_way_T_115 ^ alloc_way_chunks_117; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_117 = _alloc_way_T_116 ^ alloc_way_chunks_118; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_118 = _alloc_way_T_117 ^ alloc_way_chunks_119; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_119 = _alloc_way_T_118 ^ alloc_way_chunks_120; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_120 = _alloc_way_T_119 ^ alloc_way_chunks_121; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_121 = _alloc_way_T_120 ^ alloc_way_chunks_122; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_122 = _alloc_way_T_121 ^ alloc_way_chunks_123; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_123 = _alloc_way_T_122 ^ alloc_way_chunks_124; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_124 = _alloc_way_T_123 ^ alloc_way_chunks_125; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_125 = _alloc_way_T_124 ^ alloc_way_chunks_126; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_126 = _alloc_way_T_125 ^ alloc_way_chunks_127; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_127 = _alloc_way_T_126 ^ alloc_way_chunks_128; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_128 = _alloc_way_T_127 ^ alloc_way_chunks_129; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_129 = _alloc_way_T_128 ^ alloc_way_chunks_130; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_130 = _alloc_way_T_129 ^ alloc_way_chunks_131; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_131 = _alloc_way_T_130 ^ alloc_way_chunks_132; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_132 = _alloc_way_T_131 ^ alloc_way_chunks_133; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_133 = _alloc_way_T_132 ^ alloc_way_chunks_134; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_134 = _alloc_way_T_133 ^ alloc_way_chunks_135; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_135 = _alloc_way_T_134 ^ alloc_way_chunks_136; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_136 = _alloc_way_T_135 ^ alloc_way_chunks_137; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_137 = _alloc_way_T_136 ^ alloc_way_chunks_138; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_138 = _alloc_way_T_137 ^ alloc_way_chunks_139; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_139 = _alloc_way_T_138 ^ alloc_way_chunks_140; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_140 = _alloc_way_T_139 ^ alloc_way_chunks_141; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_141 = _alloc_way_T_140 ^ alloc_way_chunks_142; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_142 = _alloc_way_T_141 ^ alloc_way_chunks_143; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_143 = _alloc_way_T_142 ^ alloc_way_chunks_144; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_144 = _alloc_way_T_143 ^ alloc_way_chunks_145; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_145 = _alloc_way_T_144 ^ alloc_way_chunks_146; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_146 = _alloc_way_T_145 ^ alloc_way_chunks_147; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_147 = _alloc_way_T_146 ^ alloc_way_chunks_148; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_148 = _alloc_way_T_147 ^ alloc_way_chunks_149; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_149 = _alloc_way_T_148 ^ alloc_way_chunks_150; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_150 = _alloc_way_T_149 ^ alloc_way_chunks_151; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_151 = _alloc_way_T_150 ^ alloc_way_chunks_152; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_152 = _alloc_way_T_151 ^ alloc_way_chunks_153; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_153 = _alloc_way_T_152 ^ alloc_way_chunks_154; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_154 = _alloc_way_T_153 ^ alloc_way_chunks_155; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_155 = _alloc_way_T_154 ^ alloc_way_chunks_156; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_156 = _alloc_way_T_155 ^ alloc_way_chunks_157; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_157 = _alloc_way_T_156 ^ alloc_way_chunks_158; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_158 = _alloc_way_T_157 ^ alloc_way_chunks_159; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_159 = _alloc_way_T_158 ^ alloc_way_chunks_160; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_160 = _alloc_way_T_159 ^ alloc_way_chunks_161; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_161 = _alloc_way_T_160 ^ alloc_way_chunks_162; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_162 = _alloc_way_T_161 ^ alloc_way_chunks_163; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_163 = _alloc_way_T_162 ^ alloc_way_chunks_164; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_164 = _alloc_way_T_163 ^ alloc_way_chunks_165; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_165 = _alloc_way_T_164 ^ alloc_way_chunks_166; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_166 = _alloc_way_T_165 ^ alloc_way_chunks_167; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_167 = _alloc_way_T_166 ^ alloc_way_chunks_168; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_168 = _alloc_way_T_167 ^ alloc_way_chunks_169; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_169 = _alloc_way_T_168 ^ alloc_way_chunks_170; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_170 = _alloc_way_T_169 ^ alloc_way_chunks_171; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_171 = _alloc_way_T_170 ^ alloc_way_chunks_172; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_172 = _alloc_way_T_171 ^ alloc_way_chunks_173; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_173 = _alloc_way_T_172 ^ alloc_way_chunks_174; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_174 = _alloc_way_T_173 ^ alloc_way_chunks_175; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_175 = _alloc_way_T_174 ^ alloc_way_chunks_176; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_176 = _alloc_way_T_175 ^ alloc_way_chunks_177; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_177 = _alloc_way_T_176 ^ alloc_way_chunks_178; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_178 = _alloc_way_T_177 ^ alloc_way_chunks_179; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_179 = _alloc_way_T_178 ^ alloc_way_chunks_180; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_180 = _alloc_way_T_179 ^ alloc_way_chunks_181; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_181 = _alloc_way_T_180 ^ alloc_way_chunks_182; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_182 = _alloc_way_T_181 ^ alloc_way_chunks_183; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_183 = _alloc_way_T_182 ^ alloc_way_chunks_184; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_184 = _alloc_way_T_183 ^ alloc_way_chunks_185; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_185 = _alloc_way_T_184 ^ alloc_way_chunks_186; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_186 = _alloc_way_T_185 ^ alloc_way_chunks_187; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_187 = _alloc_way_T_186 ^ alloc_way_chunks_188; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_188 = _alloc_way_T_187 ^ alloc_way_chunks_189; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_189 = _alloc_way_T_188 ^ alloc_way_chunks_190; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_190 = _alloc_way_T_189 ^ alloc_way_chunks_191; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_191 = _alloc_way_T_190 ^ alloc_way_chunks_192; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_192 = _alloc_way_T_191 ^ alloc_way_chunks_193; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_193 = _alloc_way_T_192 ^ alloc_way_chunks_194; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_194 = _alloc_way_T_193 ^ alloc_way_chunks_195; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_195 = _alloc_way_T_194 ^ alloc_way_chunks_196; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_196 = _alloc_way_T_195 ^ alloc_way_chunks_197; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_197 = _alloc_way_T_196 ^ alloc_way_chunks_198; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_198 = _alloc_way_T_197 ^ alloc_way_chunks_199; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_199 = _alloc_way_T_198 ^ alloc_way_chunks_200; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_200 = _alloc_way_T_199 ^ alloc_way_chunks_201; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_201 = _alloc_way_T_200 ^ alloc_way_chunks_202; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_202 = _alloc_way_T_201 ^ alloc_way_chunks_203; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_203 = _alloc_way_T_202 ^ alloc_way_chunks_204; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_204 = _alloc_way_T_203 ^ alloc_way_chunks_205; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_205 = _alloc_way_T_204 ^ alloc_way_chunks_206; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_206 = _alloc_way_T_205 ^ alloc_way_chunks_207; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_207 = _alloc_way_T_206 ^ alloc_way_chunks_208; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_208 = _alloc_way_T_207 ^ alloc_way_chunks_209; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_209 = _alloc_way_T_208 ^ alloc_way_chunks_210; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_210 = _alloc_way_T_209 ^ alloc_way_chunks_211; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_211 = _alloc_way_T_210 ^ alloc_way_chunks_212; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_212 = _alloc_way_T_211 ^ alloc_way_chunks_213; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_213 = _alloc_way_T_212 ^ alloc_way_chunks_214; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_214 = _alloc_way_T_213 ^ alloc_way_chunks_215; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_215 = _alloc_way_T_214 ^ alloc_way_chunks_216; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_216 = _alloc_way_T_215 ^ alloc_way_chunks_217; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_217 = _alloc_way_T_216 ^ alloc_way_chunks_218; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_218 = _alloc_way_T_217 ^ alloc_way_chunks_219; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_219 = _alloc_way_T_218 ^ alloc_way_chunks_220; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_220 = _alloc_way_T_219 ^ alloc_way_chunks_221; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_221 = _alloc_way_T_220 ^ alloc_way_chunks_222; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_222 = _alloc_way_T_221 ^ alloc_way_chunks_223; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_223 = _alloc_way_T_222 ^ alloc_way_chunks_224; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_224 = _alloc_way_T_223 ^ alloc_way_chunks_225; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_225 = _alloc_way_T_224 ^ alloc_way_chunks_226; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_226 = _alloc_way_T_225 ^ alloc_way_chunks_227; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_227 = _alloc_way_T_226 ^ alloc_way_chunks_228; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_228 = _alloc_way_T_227 ^ alloc_way_chunks_229; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_229 = _alloc_way_T_228 ^ alloc_way_chunks_230; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_230 = _alloc_way_T_229 ^ alloc_way_chunks_231; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_231 = _alloc_way_T_230 ^ alloc_way_chunks_232; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_232 = _alloc_way_T_231 ^ alloc_way_chunks_233; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_233 = _alloc_way_T_232 ^ alloc_way_chunks_234; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_234 = _alloc_way_T_233 ^ alloc_way_chunks_235; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_235 = _alloc_way_T_234 ^ alloc_way_chunks_236; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_236 = _alloc_way_T_235 ^ alloc_way_chunks_237; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_237 = _alloc_way_T_236 ^ alloc_way_chunks_238; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_238 = _alloc_way_T_237 ^ alloc_way_chunks_239; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_239 = _alloc_way_T_238 ^ alloc_way_chunks_240; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_240 = _alloc_way_T_239 ^ alloc_way_chunks_241; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_241 = _alloc_way_T_240 ^ alloc_way_chunks_242; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_242 = _alloc_way_T_241 ^ alloc_way_chunks_243; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_243 = _alloc_way_T_242 ^ alloc_way_chunks_244; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_244 = _alloc_way_T_243 ^ alloc_way_chunks_245; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_245 = _alloc_way_T_244 ^ alloc_way_chunks_246; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_246 = _alloc_way_T_245 ^ alloc_way_chunks_247; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_247 = _alloc_way_T_246 ^ alloc_way_chunks_248; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_248 = _alloc_way_T_247 ^ alloc_way_chunks_249; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_249 = _alloc_way_T_248 ^ alloc_way_chunks_250; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_250 = _alloc_way_T_249 ^ alloc_way_chunks_251; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_251 = _alloc_way_T_250 ^ alloc_way_chunks_252; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_252 = _alloc_way_T_251 ^ alloc_way_chunks_253; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_253 = _alloc_way_T_252 ^ alloc_way_chunks_254; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_254 = _alloc_way_T_253 ^ alloc_way_chunks_255; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_255 = _alloc_way_T_254 ^ alloc_way_chunks_256; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_256 = _alloc_way_T_255 ^ alloc_way_chunks_257; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_257 = _alloc_way_T_256 ^ alloc_way_chunks_258; // @[btb.scala:127:14, :129:20] wire _alloc_way_T_258 = _alloc_way_T_257 ^ alloc_way_chunks_259; // @[btb.scala:127:14, :129:20] wire alloc_way = _alloc_way_T_258 ^ alloc_way_chunks_260; // @[btb.scala:127:14, :129:20] wire _s1_meta_write_way_T = s1_hits_0 | s1_hits_1; // @[btb.scala:87:55, :133:44] wire _s1_meta_write_way_T_1 = _s1_meta_write_way_T | s1_hits_2; // @[btb.scala:87:55, :133:44] wire _s1_meta_write_way_T_2 = _s1_meta_write_way_T_1 | s1_hits_3; // @[btb.scala:87:55, :133:44] wire [1:0] _s1_meta_write_way_T_3 = {s1_hit_ohs_0_1, s1_hit_ohs_0_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_4 = {s1_hit_ohs_1_1, s1_hit_ohs_1_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_5 = {s1_hit_ohs_2_1, s1_hit_ohs_2_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_6 = {s1_hit_ohs_3_1, s1_hit_ohs_3_0}; // @[btb.scala:82:27, :134:38] wire [1:0] _s1_meta_write_way_T_7 = _s1_meta_write_way_T_3 | _s1_meta_write_way_T_4; // @[btb.scala:134:{38,54}] wire [1:0] _s1_meta_write_way_T_8 = _s1_meta_write_way_T_7 | _s1_meta_write_way_T_5; // @[btb.scala:134:{38,54}] wire [1:0] _s1_meta_write_way_T_9 = _s1_meta_write_way_T_8 | _s1_meta_write_way_T_6; // @[btb.scala:134:{38,54}] wire _s1_meta_write_way_T_10 = _s1_meta_write_way_T_9[0]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_11 = _s1_meta_write_way_T_9[1]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_12 = ~_s1_meta_write_way_T_10; // @[OneHot.scala:48:45] assign _s1_meta_write_way_T_13 = _s1_meta_write_way_T_2 ? _s1_meta_write_way_T_12 : alloc_way; // @[Mux.scala:50:70] assign s1_meta_write_way = _s1_meta_write_way_T_13; // @[btb.scala:52:21, :133:27] wire _s1_update_meta_T; // @[btb.scala:138:55] wire s1_update_meta_write_way; // @[btb.scala:138:55] assign _s1_update_meta_T = _s1_update_meta_WIRE; // @[btb.scala:138:55] assign _s1_update_meta_WIRE = s1_update_bits_meta[0]; // @[predictor.scala:184:30] assign s1_update_meta_write_way = _s1_update_meta_T; // @[btb.scala:138:55] wire [2:0] _new_offset_value_T_1 = {s1_update_bits_cfi_idx_bits, 1'h0}; // @[predictor.scala:184:30] wire [40:0] _new_offset_value_T_2 = {1'h0, s1_update_bits_pc} + {38'h0, _new_offset_value_T_1}; // @[predictor.scala:184:30] wire [39:0] _new_offset_value_T_3 = _new_offset_value_T_2[39:0]; // @[btb.scala:143:24] wire [39:0] _new_offset_value_T_4 = _new_offset_value_T_3; // @[btb.scala:143:{24,62}] wire [40:0] _new_offset_value_T_5 = {_new_offset_value_T[39], _new_offset_value_T} - {_new_offset_value_T_4[39], _new_offset_value_T_4}; // @[btb.scala:142:{49,56}, :143:62] wire [39:0] _new_offset_value_T_6 = _new_offset_value_T_5[39:0]; // @[btb.scala:142:56] wire [39:0] new_offset_value = _new_offset_value_T_6; // @[btb.scala:142:56] wire _offset_is_extended_T = $signed(new_offset_value) > 40'shFFF; // @[btb.scala:142:56, :144:46] wire _offset_is_extended_T_1 = $signed(new_offset_value) < -40'sh1000; // @[btb.scala:142:56, :145:46] wire offset_is_extended = _offset_is_extended_T | _offset_is_extended_T_1; // @[btb.scala:144:{46,65}, :145:46] wire s1_update_wbtb_data_extended = offset_is_extended; // @[btb.scala:144:65, :148:34] wire [12:0] s1_update_wbtb_data_offset; // @[btb.scala:148:34] assign s1_update_wbtb_data_offset = new_offset_value[12:0]; // @[btb.scala:142:56, :148:34, :150:32] wire [3:0] _s1_update_wbtb_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35] wire _s1_update_wbtb_mask_T_1 = s1_update_bits_cfi_idx_valid & s1_update_valid; // @[predictor.scala:184:30] wire _s1_update_wbtb_mask_T_2 = _s1_update_wbtb_mask_T_1 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30] wire _GEN_7 = s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update; // @[predictor.scala:96:49, :184:30] wire _s1_update_wbtb_mask_T_3; // @[predictor.scala:96:49] assign _s1_update_wbtb_mask_T_3 = _GEN_7; // @[predictor.scala:96:49] wire _s1_update_wmeta_mask_T_1; // @[predictor.scala:96:49] assign _s1_update_wmeta_mask_T_1 = _GEN_7; // @[predictor.scala:96:49] wire _s1_update_wbtb_mask_T_4 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30] wire _s1_update_wbtb_mask_T_5 = _s1_update_wbtb_mask_T_3 | _s1_update_wbtb_mask_T_4; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wbtb_mask_T_6 = ~_s1_update_wbtb_mask_T_5; // @[predictor.scala:96:{26,69}] wire _s1_update_wbtb_mask_T_7 = _s1_update_wbtb_mask_T_2 & _s1_update_wbtb_mask_T_6; // @[predictor.scala:96:26] wire [3:0] _s1_update_wbtb_mask_T_8 = {4{_s1_update_wbtb_mask_T_7}}; // @[btb.scala:152:{9,97}] wire [3:0] s1_update_wbtb_mask = _s1_update_wbtb_mask_T & _s1_update_wbtb_mask_T_8; // @[OneHot.scala:58:35] wire [3:0] _s1_update_wmeta_mask_T = s1_update_wbtb_mask | s1_update_bits_br_mask; // @[predictor.scala:184:30] wire _s1_update_wmeta_mask_T_2 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30] wire _s1_update_wmeta_mask_T_3 = _s1_update_wmeta_mask_T_1 | _s1_update_wmeta_mask_T_2; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wmeta_mask_T_4 = ~_s1_update_wmeta_mask_T_3; // @[predictor.scala:96:{26,69}] wire _s1_update_wmeta_mask_T_5 = s1_update_valid & _s1_update_wmeta_mask_T_4; // @[predictor.scala:96:26, :184:30] wire [3:0] _s1_update_wmeta_mask_T_6 = {4{_s1_update_wmeta_mask_T_5}}; // @[btb.scala:155:{10,38}] wire [3:0] _s1_update_wmeta_mask_T_7 = {4{s1_update_valid}}; // @[predictor.scala:184:30] wire [3:0] _s1_update_wmeta_mask_T_8 = _s1_update_wmeta_mask_T_7 & s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] wire [3:0] _s1_update_wmeta_mask_T_9 = _s1_update_wmeta_mask_T_6 | _s1_update_wmeta_mask_T_8; // @[btb.scala:155:{10,74}, :156:40] wire [3:0] s1_update_wmeta_mask = _s1_update_wmeta_mask_T & _s1_update_wmeta_mask_T_9; // @[btb.scala:154:{52,78}, :155:74] wire _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:162:43] wire _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:162:43] wire _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:162:43] wire _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:163:62] wire [28:0] _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:162:43] wire s1_update_wmeta_data_0_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_0_tag; // @[btb.scala:159:34] wire s1_update_wmeta_data_1_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_1_tag; // @[btb.scala:159:34] wire s1_update_wmeta_data_2_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_2_tag; // @[btb.scala:159:34] wire s1_update_wmeta_data_3_is_br; // @[btb.scala:159:34] wire [28:0] s1_update_wmeta_data_3_tag; // @[btb.scala:159:34] wire _s1_update_wmeta_data_0_tag_T = s1_update_bits_btb_mispredicts[0]; // @[predictor.scala:184:30] wire [28:0] _s1_update_wmeta_data_0_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_1_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_2_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_3_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_0_tag_T_2 = _s1_update_wmeta_data_0_tag_T ? 29'h0 : _s1_update_wmeta_data_0_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_0_tag = _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_0_is_br_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_0_is_br = _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:159:34, :163:62] wire _s1_update_wmeta_data_1_tag_T = s1_update_bits_btb_mispredicts[1]; // @[predictor.scala:184:30] assign _s1_update_wmeta_data_1_tag_T_2 = _s1_update_wmeta_data_1_tag_T ? 29'h0 : _s1_update_wmeta_data_1_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_1_tag = _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_1_is_br_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_1_is_br = _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:159:34, :163:62] wire _s1_update_wmeta_data_2_tag_T = s1_update_bits_btb_mispredicts[2]; // @[predictor.scala:184:30] assign _s1_update_wmeta_data_2_tag_T_2 = _s1_update_wmeta_data_2_tag_T ? 29'h0 : _s1_update_wmeta_data_2_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_2_tag = _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_2_is_br_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_2_is_br = _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:159:34, :163:62] wire _s1_update_wmeta_data_3_tag_T = s1_update_bits_btb_mispredicts[3]; // @[predictor.scala:184:30] assign _s1_update_wmeta_data_3_tag_T_2 = _s1_update_wmeta_data_3_tag_T ? 29'h0 : _s1_update_wmeta_data_3_tag_T_1; // @[btb.scala:162:{43,74,98}] assign s1_update_wmeta_data_3_tag = _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:159:34, :162:43] assign _s1_update_wmeta_data_3_is_br_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] assign s1_update_wmeta_data_3_is_br = _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:159:34, :163:62] wire btb_0_MPORT_en = doing_reset | ~s1_update_meta_write_way; // @[btb.scala:60:28, :138:55, :167:{23,51}] wire [6:0] _T_34 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:185:30] assign btb_0_MPORT_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_0_MPORT_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_0_MPORT_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_0_MPORT_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign meta_0_MPORT_1_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_0_MPORT_1_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_0_MPORT_1_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_0_MPORT_1_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] wire btb_1_MPORT_2_en = doing_reset | s1_update_meta_write_way; // @[btb.scala:60:28, :138:55, :167:23] wire [6:0] _T_69 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:185:30] assign btb_1_MPORT_2_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_1_MPORT_2_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_1_MPORT_2_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign btb_1_MPORT_2_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61] assign meta_1_MPORT_3_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_1_MPORT_3_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_1_MPORT_3_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] assign meta_1_MPORT_3_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46] always @(posedge clock) begin // @[btb.scala:23:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] f3_meta_REG_write_way <= s1_meta_write_way; // @[btb.scala:52:21, :53:32] f3_meta_write_way <= f3_meta_REG_write_way; // @[btb.scala:53:{24,32}] REG <= s1_hits_0; // @[btb.scala:87:55, :104:18] io_resp_f2_0_predicted_pc_REG_valid <= s1_resp_0_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_0_predicted_pc_REG_bits <= s1_resp_0_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_0_is_br_REG <= s1_is_br_0; // @[btb.scala:79:23, :106:44] io_resp_f2_0_is_jal_REG <= s1_is_jal_0; // @[btb.scala:80:23, :107:44] REG_1 <= s1_is_jal_0; // @[btb.scala:80:23, :108:20] REG_2 <= s1_hits_0; // @[btb.scala:87:55, :112:26] REG_3 <= REG_2; // @[btb.scala:112:{18,26}] io_resp_f3_0_predicted_pc_REG_valid <= io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_0_predicted_pc_REG_bits <= io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_0_is_br_REG <= io_resp_f2_0_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_0_is_jal_REG <= io_resp_f2_0_is_jal_0; // @[btb.scala:23:7, :115:44] REG_4 <= s1_is_jal_0; // @[btb.scala:80:23, :116:28] REG_5 <= REG_4; // @[btb.scala:116:{20,28}] REG_6 <= s1_hits_1; // @[btb.scala:87:55, :104:18] io_resp_f2_1_predicted_pc_REG_valid <= s1_resp_1_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_1_predicted_pc_REG_bits <= s1_resp_1_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_1_is_br_REG <= s1_is_br_1; // @[btb.scala:79:23, :106:44] io_resp_f2_1_is_jal_REG <= s1_is_jal_1; // @[btb.scala:80:23, :107:44] REG_7 <= s1_is_jal_1; // @[btb.scala:80:23, :108:20] REG_8 <= s1_hits_1; // @[btb.scala:87:55, :112:26] REG_9 <= REG_8; // @[btb.scala:112:{18,26}] io_resp_f3_1_predicted_pc_REG_valid <= io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_1_predicted_pc_REG_bits <= io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_1_is_br_REG <= io_resp_f2_1_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_1_is_jal_REG <= io_resp_f2_1_is_jal_0; // @[btb.scala:23:7, :115:44] REG_10 <= s1_is_jal_1; // @[btb.scala:80:23, :116:28] REG_11 <= REG_10; // @[btb.scala:116:{20,28}] REG_12 <= s1_hits_2; // @[btb.scala:87:55, :104:18] io_resp_f2_2_predicted_pc_REG_valid <= s1_resp_2_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_2_predicted_pc_REG_bits <= s1_resp_2_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_2_is_br_REG <= s1_is_br_2; // @[btb.scala:79:23, :106:44] io_resp_f2_2_is_jal_REG <= s1_is_jal_2; // @[btb.scala:80:23, :107:44] REG_13 <= s1_is_jal_2; // @[btb.scala:80:23, :108:20] REG_14 <= s1_hits_2; // @[btb.scala:87:55, :112:26] REG_15 <= REG_14; // @[btb.scala:112:{18,26}] io_resp_f3_2_predicted_pc_REG_valid <= io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_2_predicted_pc_REG_bits <= io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_2_is_br_REG <= io_resp_f2_2_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_2_is_jal_REG <= io_resp_f2_2_is_jal_0; // @[btb.scala:23:7, :115:44] REG_16 <= s1_is_jal_2; // @[btb.scala:80:23, :116:28] REG_17 <= REG_16; // @[btb.scala:116:{20,28}] REG_18 <= s1_hits_3; // @[btb.scala:87:55, :104:18] io_resp_f2_3_predicted_pc_REG_valid <= s1_resp_3_valid; // @[btb.scala:78:23, :105:44] io_resp_f2_3_predicted_pc_REG_bits <= s1_resp_3_bits; // @[btb.scala:78:23, :105:44] io_resp_f2_3_is_br_REG <= s1_is_br_3; // @[btb.scala:79:23, :106:44] io_resp_f2_3_is_jal_REG <= s1_is_jal_3; // @[btb.scala:80:23, :107:44] REG_19 <= s1_is_jal_3; // @[btb.scala:80:23, :108:20] REG_20 <= s1_hits_3; // @[btb.scala:87:55, :112:26] REG_21 <= REG_20; // @[btb.scala:112:{18,26}] io_resp_f3_3_predicted_pc_REG_valid <= io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44] io_resp_f3_3_predicted_pc_REG_bits <= io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44] io_resp_f3_3_is_br_REG <= io_resp_f2_3_is_br_0; // @[btb.scala:23:7, :114:44] io_resp_f3_3_is_jal_REG <= io_resp_f2_3_is_jal_0; // @[btb.scala:23:7, :115:44] REG_22 <= s1_is_jal_3; // @[btb.scala:80:23, :116:28] REG_23 <= REG_22; // @[btb.scala:116:{20,28}] if (reset) begin // @[btb.scala:23:7] doing_reset <= 1'h1; // @[btb.scala:60:28] reset_idx <= 7'h0; // @[btb.scala:61:28] end else begin // @[btb.scala:23:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[btb.scala:60:28, :61:28, :63:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[btb.scala:61:28, :62:26] end always @(posedge) meta_0 meta_0 ( // @[btb.scala:65:47] .R0_addr (_s1_req_rmeta_T), // @[btb.scala:74:60] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_meta_0_R0_data), .W0_addr (_T_34), // @[btb.scala:169:12] .W0_en (btb_0_MPORT_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({meta_0_MPORT_1_data_3, meta_0_MPORT_1_data_2, meta_0_MPORT_1_data_1, meta_0_MPORT_1_data_0}), // @[btb.scala:65:47, :183:12] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:60:28, :154:78, :186:12] ); // @[btb.scala:65:47] meta_1 meta_1 ( // @[btb.scala:65:47] .R0_addr (_s1_req_rmeta_T_9), // @[btb.scala:74:60] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_meta_1_R0_data), .W0_addr (_T_69), // @[btb.scala:169:12] .W0_en (btb_1_MPORT_2_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({meta_1_MPORT_3_data_3, meta_1_MPORT_3_data_2, meta_1_MPORT_3_data_1, meta_1_MPORT_3_data_0}), // @[btb.scala:65:47, :183:12] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:60:28, :154:78, :186:12] ); // @[btb.scala:65:47] btb_0 btb_0 ( // @[btb.scala:66:47] .R0_addr (_s1_req_rbtb_T), // @[btb.scala:73:59] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_btb_0_R0_data), .W0_addr (_T_34), // @[btb.scala:169:12] .W0_en (btb_0_MPORT_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({btb_0_MPORT_data_3, btb_0_MPORT_data_2, btb_0_MPORT_data_1, btb_0_MPORT_data_0}), // @[btb.scala:66:47, :172:12] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:60:28, :151:58, :175:12] ); // @[btb.scala:66:47] btb_1 btb_1 ( // @[btb.scala:66:47] .R0_addr (_s1_req_rbtb_T_13), // @[btb.scala:73:59] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_btb_1_R0_data), .W0_addr (_T_69), // @[btb.scala:169:12] .W0_en (btb_1_MPORT_2_en), // @[btb.scala:167:23] .W0_clk (clock), .W0_data ({btb_1_MPORT_2_data_3, btb_1_MPORT_2_data_2, btb_1_MPORT_2_data_1, btb_1_MPORT_2_data_0}), // @[btb.scala:66:47, :172:12] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:60:28, :151:58, :175:12] ); // @[btb.scala:66:47] ebtb ebtb ( // @[btb.scala:67:29] .R0_addr (_s1_req_rebtb_T), // @[btb.scala:75:31] .R0_en (io_f0_valid_0), // @[btb.scala:23:7] .R0_clk (clock), .R0_data (_ebtb_R0_data), .W0_addr (s1_update_idx[6:0]), // @[predictor.scala:185:30] .W0_en ((|s1_update_wbtb_mask) & offset_is_extended), // @[btb.scala:144:65, :151:58, :194:{29,37}] .W0_clk (clock), .W0_data (s1_update_bits_target) // @[predictor.scala:184:30] ); // @[btb.scala:67:29] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[btb.scala:23:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[btb.scala:23:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[btb.scala:23:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[btb.scala:23:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[btb.scala:23:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[btb.scala:23:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[btb.scala:23:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[btb.scala:23:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[btb.scala:23:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[btb.scala:23:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[btb.scala:23:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[btb.scala:23:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[btb.scala:23:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[btb.scala:23:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[btb.scala:23:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[btb.scala:23:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[btb.scala:23:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[btb.scala:23:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7] assign io_f3_meta = io_f3_meta_0; // @[btb.scala:23:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module ClockCrossingReg_w32_3( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [31:0] io_d, // @[SynchronizerReg.scala:195:14] output [31:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [31:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [31:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [31:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }

module EgressUnit_16( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_22 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_46( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_181( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_196 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty || floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) || helper(unswizzled, prevT) val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL*/fmv.*.x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) | x, maxType) } // implement NaN unboxing and un-recoding for FS*/fmv.x.* def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out | (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma || cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid || io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm || io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx || mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 | memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) || divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) | Mux(divSqrt_wen, divSqrt_flags, 0.U) | Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight) io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B || io.keep_clock_enabled || // chicken bit io.valid || // ID stage req_valid || // EX stage mem_reg_valid || mem_cp_valid || // MEM stage wb_reg_valid || wb_cp_valid || // WB stage wen.orR || divSqrt_inFlight || // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }

module FPUFMAPipe_l3_f16( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input io_in_bits_vec, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [64:0] res_data; // @[FPU.scala:728:17] wire [16:0] _fma_io_out; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [15:0] one = 16'h8000; // @[FPU.scala:710:19] wire [16:0] _zero_T_1 = 17'h10000; // @[FPU.scala:711:57] wire io_out_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg in_vec; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = {48'h0, _zero_T[16], 16'h0}; // @[FPU.scala:711:{32,50}] assign io_out_out_bits_data = res_data; // @[Valid.scala:135:21] wire [4:0] res_exc; // @[FPU.scala:728:17] assign io_out_out_bits_exc = res_exc; // @[Valid.scala:135:21] assign res_data = {48'h0, _fma_io_out}; // @[FPU.scala:711:50, :719:19, :728:17, :729:12] assign io_out_valid = io_out_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_vec <= io_in_bits_vec_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h8000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 | io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end always @(posedge) MulAddRecFNPipe_l2_e5_s11 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1[16:0]), // @[FPU.scala:708:15, :724:12] .io_b (in_in2[16:0]), // @[FPU.scala:708:15, :725:12] .io_c (in_in3[16:0]), // @[FPU.scala:708:15, :726:12] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (io_out_out_valid) ); // @[FPU.scala:719:19] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundRawFNToRecFN_e11_s53_12( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:299:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_12 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_detectTininess (io_detectTininess_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty || floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) || helper(unswizzled, prevT) val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL*/fmv.*.x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) | x, maxType) } // implement NaN unboxing and un-recoding for FS*/fmv.x.* def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out | (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma || cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid || io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm || io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx || mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 | memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) || divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) | Mux(divSqrt_wen, divSqrt_flags, 0.U) | Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight) io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B || io.keep_clock_enabled || // chicken bit io.valid || // ID stage req_valid || // EX stage mem_reg_valid || mem_cp_valid || // MEM stage wb_reg_valid || wb_cp_valid || // WB stage wen.orR || divSqrt_inFlight || // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }

module FPUFMAPipe_l4_f16( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output io_out_valid, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [16:0] _fma_io_out; // @[FPU.scala:719:19] wire _fma_io_validout; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [15:0] one = 16'h8000; // @[FPU.scala:710:19] wire [16:0] _zero_T_1 = 17'h10000; // @[FPU.scala:711:57] wire io_in_bits_vec = 1'h0; // @[FPU.scala:697:7] wire io_out_pipe_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid_0; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = {48'h0, _zero_T[16], 16'h0}; // @[FPU.scala:711:{32,50}] wire [64:0] res_data; // @[FPU.scala:728:17] wire [4:0] res_exc; // @[FPU.scala:728:17] assign res_data = {48'h0, _fma_io_out}; // @[FPU.scala:711:50, :719:19, :728:17, :729:12] reg io_out_pipe_v; // @[Valid.scala:141:24] assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26] assign io_out_valid_0 = io_out_pipe_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h8000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 | io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end if (_fma_io_validout) begin // @[FPU.scala:719:19] io_out_pipe_b_data <= res_data; // @[Valid.scala:142:26] io_out_pipe_b_exc <= res_exc; // @[Valid.scala:142:26] end if (reset) // @[FPU.scala:697:7] io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] else // @[FPU.scala:697:7] io_out_pipe_v <= _fma_io_validout; // @[Valid.scala:141:24] always @(posedge) MulAddRecFNPipe_l2_e5_s11 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1[16:0]), // @[FPU.scala:708:15, :724:12] .io_b (in_in2[16:0]), // @[FPU.scala:708:15, :725:12] .io_c (in_in3[16:0]), // @[FPU.scala:708:15, :726:12] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (_fma_io_validout) ); // @[FPU.scala:719:19] assign io_out_valid = io_out_valid_0; // @[FPU.scala:697:7] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module TLBuffer_a32d64s4k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_13 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s4k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s4k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_466( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_210 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_120( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_61( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_78 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1)) }) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf || io.b.isInf val notNaN_isZeroOut = io.a.isZero || io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN || io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulFullRawFN_50( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module MacUnit_148( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }

module cc_banks_3_4( // @[DescribedSRAM.scala:17:26] input [14:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); cc_banks_0_ext cc_banks_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_101( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_12( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_25 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }

module IntSyncCrossingSource_n1x1_5( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_5 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module Router_14( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_2_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_7; // @[Router.scala:136:32] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_2_to_20_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_0_io_channel_status_7_occupied; // @[Router.scala:122:13] wire [2:0] _input_unit_2_from_20_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_20_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_20_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_20_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_17_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_0_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_0_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_0_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_0_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_0_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_0_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_0_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_0_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_0_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_0_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_17_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_20_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to the following Chisel files. File NextLine.scala: package barf import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem.{CacheBlockBytes} case class SingleNextLinePrefetcherParams( ahead: Int = 4, waitForHit: Boolean = false, handleVA: Boolean = false ) extends CanInstantiatePrefetcher { def desc() = "Single Next-Line Prefetcher" def instantiate()(implicit p: Parameters) = Module(new SingleNextLinePrefetcher(this)(p)) } class SingleNextLinePrefetcher(params: SingleNextLinePrefetcherParams)(implicit p: Parameters) extends AbstractPrefetcher()(p) { // Assume 4KB pages val lowerBits = 12 - log2Ceil(p(CacheBlockBytes)) val s_idle :: s_wait :: s_active :: s_done :: Nil = Enum(4) val state = RegInit(s_idle) val write = Reg(Bool()) val block_upper = Reg(UInt()) val block_lower = Reg(UInt(lowerBits.W)) val prefetch = Reg(UInt(lowerBits.W)) val wrap = RegInit(false.B) val wrap_block_upper = block_upper + 1.U val delta = Mux(wrap, Cat(1.U(1.W), prefetch) - block_lower, prefetch - block_lower) val addr_hit = if (params.handleVA) { (io.snoop.bits.block >= Cat(block_upper, block_lower)) && (io.snoop.bits.block <= Cat(Mux(wrap, wrap_block_upper, block_upper), prefetch)) } else { (block_upper === io.snoop.bits.block >> lowerBits) && (io.snoop.bits.block(lowerBits-1,0) >= block_lower) && (io.snoop.bits.block(lowerBits-1,0) <= prefetch) } io.hit := state =/= s_idle && addr_hit val snoop_next_block = (io.snoop.bits.block(lowerBits-1,0) + 1.U)(lowerBits-1,0) when ((state === s_idle || (state === s_wait && !io.hit)) && io.snoop.valid) { when (~io.snoop.bits.block(lowerBits-1,0) =/= 0.U || params.handleVA.B) { state := (if (params.waitForHit) s_wait else s_active) } block_upper := io.snoop.bits.block >> lowerBits block_lower := io.snoop.bits.block prefetch := snoop_next_block when (params.handleVA.B && !io.hit) { wrap := snoop_next_block === 0.U } write := io.snoop.bits.write } io.request.valid := state === s_active io.request.bits.write := write io.request.bits.address := Cat(Mux(wrap, wrap_block_upper, block_upper), prefetch) << log2Up(io.request.bits.blockBytes) when (io.request.fire) { prefetch := prefetch + 1.U when (prefetch === ~(0.U(lowerBits.W))) { if (params.handleVA) { state := Mux(delta >= params.ahead.U, s_wait, s_active) prefetch := 0.U wrap := true.B } else { state := s_done prefetch := prefetch } } .elsewhen (delta >= params.ahead.U) { state := s_wait } .otherwise { state := s_active } } when (state === s_done && block_lower === prefetch) { state := s_idle } when (io.hit && io.snoop.valid) { when (state =/= s_done && io.snoop.bits.block =/= Cat(block_upper, block_lower)) { state := s_active } write := io.snoop.bits.write block_lower := io.snoop.bits.block block_upper := io.snoop.bits.block >> lowerBits when (io.snoop.bits.block(lowerBits-1,0) === prefetch) { prefetch := prefetch + 1.U } when (wrap && ((io.snoop.bits.block >> lowerBits) =/= block_upper)) { wrap := false.B } } } case class MultiNextLinePrefetcherParams( singles: Seq[SingleNextLinePrefetcherParams] = Seq.fill(4) { SingleNextLinePrefetcherParams() }, handleVA: Boolean = false ) extends CanInstantiatePrefetcher { def desc() = "Multi Next-Line Prefetcher" def instantiate()(implicit p: Parameters) = Module(new MultiNextLinePrefetcher(this)(p)) } class MultiNextLinePrefetcher(params: MultiNextLinePrefetcherParams)(implicit p: Parameters) extends AbstractPrefetcher()(p) { val singles = params.singles.map(_.copy(waitForHit=true, handleVA=params.handleVA).instantiate()) val any_hit = singles.map(_.io.hit).reduce(_||_) singles.foreach(_.io.snoop.valid := false.B) singles.foreach(_.io.snoop.bits := io.snoop.bits) val replacer = ReplacementPolicy.fromString("lru", singles.size) when (io.snoop.valid) { for (s <- 0 until singles.size) { when (singles(s).io.hit || (!any_hit && replacer.way === s.U)) { singles(s).io.snoop.valid := true.B replacer.miss } when (singles(s).io.hit) { replacer.access(s.U) } } } val arb = Module(new RRArbiter(new Prefetch, singles.size)) arb.io.in <> singles.map(_.io.request) io.request <> arb.io.out } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AMPM.scala: /* --------------------------------------------------------------------- Access Map Pattern Matching Adapted from "Access map pattern matching for data cache prefetch" Yasuo Ishii, Mary Inaba, and Kei Hiraki. 2009. Access map pattern matching for data cache prefetch. In Proceedings of the 23rd international conference on Supercomputing (ICS '09). Association for Computing Machinery, New York, NY, USA, 499–500. https://doi.org/10.1145/1542275.1542349 --------------------------------------------------------------------- */ package barf import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem.{CacheBlockBytes} case class SingleAMPMPrefetcherParams( entries: Int = 64, //Number of entries per access map N: Int = 16, //Number of cache lines per zone ) extends CanInstantiatePrefetcher { def desc() = "Single AMPM Prefetcher" def instantiate()(implicit p: Parameters) = Module(new AMPMPrefetcher(this)(p)) } class AMPMPrefetcher(params: SingleAMPMPrefetcherParams)(implicit p: Parameters) extends AbstractPrefetcher()(p) { val entries_bits = log2Ceil(params.entries) val line_bits = log2Ceil(params.N) val max_k = if (params.N % 2 == 0) { params.N / 2 } else { (params.N - 1) / 2} //----------------- memory access map table ----------------- val snoop_tag = io.snoop.bits.block >> (line_bits) val snoop_offset = io.snoop.bits.block(line_bits - 1, 0) val memory_access_map_table = Reg(Valid(new MemoryAccessMapBank(entries = params.entries, N = params.N))) val tag_candidate = Wire(UInt(params.N.W)) val prefetch_input = Wire(UInt(params.N.W)) val entry_existence_vec = Wire(Vec(params.entries, Bool())) val entry_existence = Wire(Bool()) val initial_state_vec = Wire(Vec(params.N, Bool())) val head = RegInit(0.U((entries_bits).W)) val already_accessed = Wire(Bool()) //Set initial state for new maps for (i <- 0 until params.N) { initial_state_vec(i) := snoop_offset === i.U } //Check table for map tag_candidate := 0.U val map_bank = memory_access_map_table for (j <- 0 until params.entries) { val map = map_bank.bits.maps(j) //found entry -> send to prefetch generator when (io.snoop.valid && map.valid && (map.bits.tag === snoop_tag)) { tag_candidate := map.bits.states.asUInt map.bits.states(snoop_offset) := true.B //set map entry to "accessed" entry_existence_vec(j) := true.B } .otherwise { entry_existence_vec(j) := false.B } } entry_existence := entry_existence_vec.reduce(_ || _) //if entry not in table, add new entry when (!entry_existence && io.snoop.valid) { memory_access_map_table.bits.maps(head).bits.states := initial_state_vec memory_access_map_table.bits.maps(head).bits.tag := snoop_tag memory_access_map_table.bits.maps(head).valid := true.B head := head + 1.U } prefetch_input := tag_candidate already_accessed := prefetch_input(snoop_offset) //pattern matching val forward_map = Wire(UInt((params.N).W)) val backward_map = Wire(UInt((params.N).W)) val logic_pos = Wire(Vec(max_k, UInt())) val logic_neg = Wire(Vec(max_k, UInt())) val and_back_pos = Wire(Vec(max_k, UInt())) val and_back_pos_uint = Wire(UInt(max_k.W)) val and_back_neg = Wire(Vec(max_k, UInt())) val and_back_neg_uint = Wire(UInt(max_k.W)) val delta_uint = Wire(UInt(max_k.W)) forward_map := Reverse(prefetch_input << (params.N.U - snoop_offset - 1.U)) backward_map := prefetch_input >> snoop_offset //should be unsigned for (k <- 0 until max_k) { logic_pos(k) := forward_map(k) & (forward_map(2*k) | forward_map((2*k)+1)) logic_neg(k) := backward_map(k) & (backward_map(2*k) | backward_map((2*k)+1)) } for (i <- 0 until max_k) { and_back_pos(i) := logic_pos(i) & !backward_map(i) and_back_neg(i) := logic_neg(i) & !forward_map(i) } and_back_pos_uint := and_back_pos.asUInt and_back_neg_uint := and_back_neg.asUInt //Prioritize positive delta delta_uint := Mux(and_back_pos_uint =/= 0.U, and_back_pos_uint, and_back_neg_uint) //Buffer prefetches using queue val pref_out = Reg(Output(Flipped(Decoupled(new prefetch_req)))) val queue_out = Reg(Input(Flipped(Decoupled(new prefetch_req)))) val prefetch_active = RegInit(false.B) val reset_deq = RegInit(true.B) val prefetch_queue = Module(new Queue(new prefetch_req, entries=8, flow=true)) prefetch_queue.io.enq <> pref_out prefetch_queue.io.deq <> queue_out //Add generated prefetch to queue when (delta_uint =/= 0.U && io.snoop.valid && !already_accessed) { when (and_back_pos_uint =/= 0.U) { //Positive delta was selected pref_out.bits.addr := io.snoop.bits.block_address + (PriorityEncoder(delta_uint) << log2Up(io.snoop.bits.blockBytes)) } .otherwise { //Negative delta was selected pref_out.bits.addr := io.snoop.bits.block_address - (PriorityEncoder(delta_uint) << log2Up(io.snoop.bits.blockBytes)) } pref_out.bits.write := io.snoop.bits.write pref_out.valid := true.B prefetch_active := true.B } .otherwise { pref_out.valid := false.B } io.request.bits.address := prefetch_queue.io.deq.bits.addr io.request.valid := prefetch_active io.request.bits.write := prefetch_queue.io.deq.bits.write //Dequeue when (io.request.fire) { prefetch_queue.io.deq.ready := true.B reset_deq := true.B prefetch_active := false.B } when (reset_deq) { //reset dequeue ready prefetch_queue.io.deq.ready := false.B reset_deq := false.B } } //N is num cache lines per zone class MemoryAccessMap(val N: Int) extends Bundle { // false -> init, true -> access val states = Vec(N, Bool()) val tag = UInt() // top bits of mem address } class MemoryAccessMapBank(val entries: Int, val N: Int) extends Bundle { val maps = Vec(entries, Valid(new MemoryAccessMap(N))) } class prefetch_req extends Bundle { val addr = UInt() val write = Bool() } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AbstractPrefetcher.scala: package barf import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem.{CacheBlockBytes} trait CanInstantiatePrefetcher { def desc: String def instantiate()(implicit p: Parameters): AbstractPrefetcher } class Snoop(implicit val p: Parameters) extends Bundle { val blockBytes = p(CacheBlockBytes) val write = Bool() val address = UInt() def block = address >> log2Up(blockBytes) def block_address = block << log2Up(blockBytes) } class Prefetch(implicit val p: Parameters) extends Bundle { val blockBytes = p(CacheBlockBytes) val write = Bool() val address = UInt() def block = address >> log2Up(blockBytes) def block_address = block << log2Up(blockBytes) } class PrefetcherIO(implicit p: Parameters) extends Bundle { val snoop = Input(Valid(new Snoop)) val request = Decoupled(new Prefetch) val hit = Output(Bool()) } abstract class AbstractPrefetcher(implicit p: Parameters) extends Module { val io = IO(new PrefetcherIO) io.request.valid := false.B io.request.bits := DontCare io.request.bits.address := 0.U(1.W) io.hit := false.B } case class NullPrefetcherParams() extends CanInstantiatePrefetcher { def desc() = "Null Prefetcher" def instantiate()(implicit p: Parameters) = Module(new NullPrefetcher()(p)) } class NullPrefetcher(implicit p: Parameters) extends AbstractPrefetcher()(p) File TLPrefetcher.scala: package barf import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ case class TLPrefetcherParams( prefetchIds: Int = 4, prefetcher: String => Option[CanInstantiatePrefetcher] = _ => None ) case object TLPrefetcherKey extends Field[TLPrefetcherParams](TLPrefetcherParams()) class TLPrefetcher(implicit p: Parameters) extends LazyModule { val params = p(TLPrefetcherKey) def mapInputIds(masters: Seq[TLMasterParameters]) = TLXbar.assignRanges(masters.map(_.sourceId.size + params.prefetchIds)) val node = TLAdapterNode( clientFn = { cp => cp.v1copy(clients = (mapInputIds(cp.clients) zip cp.clients).map { case (range, c) => c.v1copy( sourceId = range )}) }, managerFn = { mp => mp } ) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val nClients = edgeOut.master.clients.size val outIdMap = edgeOut.master.clients.map(_.sourceId) val inIdMap = edgeIn.master.clients.map(_.sourceId) val snoop = Wire(Valid(new Snoop)) val snoop_client = Wire(UInt(log2Ceil(nClients).W)) // Implement prefetchers per client. val prefetchers = edgeOut.master.clients.zipWithIndex.map { case (c,i) => val pParams = params.prefetcher(c.name).getOrElse(NullPrefetcherParams()) println(s"Prefetcher for ${c.name}: ${pParams.desc}") val prefetcher = pParams.instantiate() prefetcher.io.snoop.valid := snoop.valid && snoop_client === i.U prefetcher.io.snoop.bits := snoop.bits prefetcher } val out_arb = Module(new RRArbiter(new Prefetch, nClients)) out_arb.io.in <> prefetchers.map(_.io.request) val tracker = RegInit(0.U(params.prefetchIds.W)) val next_tracker = PriorityEncoder(~tracker) val tracker_free = !tracker(next_tracker) def inIdAdjuster(source: UInt) = Mux1H((inIdMap zip outIdMap).map { case (i,o) => i.contains(source) -> (o.start.U | (source - i.start.U)) }) def outIdAdjuster(source: UInt) = Mux1H((inIdMap zip outIdMap).map { case (i,o) => o.contains(source) -> (trim(source - o.start.U, i.size) + i.start.U) }) def outIdToPrefetchId(source: UInt) = Mux1H((inIdMap zip outIdMap).map { case (i,o) => o.contains(source) -> trim(source - (o.start + i.size).U, params.prefetchIds) }) def prefetchIdToOutId(source: UInt, client: UInt) = Mux1H((inIdMap zip outIdMap).zipWithIndex.map { case ((i,o),id) => (id.U === client) -> ((o.start + i.size).U +& source) }) def inIdToClientId(source: UInt) = Mux1H(inIdMap.zipWithIndex.map { case (i,id) => i.contains(source) -> id.U }) out <> in out.a.bits.source := inIdAdjuster(in.a.bits.source) in.b.bits.source := outIdAdjuster(out.b.bits.source) out.c.bits.source := inIdAdjuster(in.c.bits.source) val d_is_prefetch = out.d.bits.opcode === TLMessages.HintAck in.d.valid := out.d.valid && !d_is_prefetch when (d_is_prefetch) { out.d.ready := true.B } in.d.bits.source := outIdAdjuster(out.d.bits.source) tracker := (tracker ^ ((out.d.valid && d_is_prefetch) << outIdToPrefetchId(out.d.bits.source)) ^ ((out.a.fire && !in.a.valid) << next_tracker) ) snoop.valid := in.a.fire && edgeIn.manager.supportsAcquireBFast(in.a.bits.address, log2Ceil(p(CacheBlockBytes)).U) snoop.bits.address := in.a.bits.address val acq = in.a.bits.opcode.isOneOf(TLMessages.AcquireBlock, TLMessages.AcquirePerm) val toT = in.a.bits.param.isOneOf(TLPermissions.NtoT, TLPermissions.BtoT) val put = edgeIn.hasData(in.a.bits) snoop.bits.write := put || (acq && toT) snoop_client := inIdToClientId(in.a.bits.source) val legal_address = edgeOut.manager.findSafe(out_arb.io.out.bits.block_address).reduce(_||_) val (legal, hint) = edgeOut.Hint( prefetchIdToOutId(next_tracker, out_arb.io.chosen), out_arb.io.out.bits.block_address, log2Up(p(CacheBlockBytes)).U, Mux(out_arb.io.out.bits.write, TLHints.PREFETCH_WRITE, TLHints.PREFETCH_READ) ) out_arb.io.out.ready := false.B when (!in.a.valid) { out.a.valid := out_arb.io.out.valid && tracker_free && legal && legal_address out.a.bits := hint out_arb.io.out.ready := out.a.ready } when (!legal || !legal_address) { out_arb.io.out.ready := true.B } } } } object TLPrefetcher { def apply()(implicit p: Parameters) = { val prefetcher = LazyModule(new TLPrefetcher) prefetcher.node } } case class TilePrefetchingMasterPortParams(tileId: Int, base: HierarchicalElementPortParamsLike) extends HierarchicalElementPortParamsLike { val where = base.where def injectNode(context: Attachable)(implicit p: Parameters): TLNode = { TLPrefetcher() :*=* base.injectNode(context)(p) } }

module TLPrefetcher( // @[TLPrefetcher.scala:35:25] input clock, // @[TLPrefetcher.scala:35:25] input reset, // @[TLPrefetcher.scala:35:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire _out_arb_io_in_0_ready; // @[TLPrefetcher.scala:54:27] wire _out_arb_io_in_1_ready; // @[TLPrefetcher.scala:54:27] wire _out_arb_io_in_2_ready; // @[TLPrefetcher.scala:54:27] wire _out_arb_io_out_valid; // @[TLPrefetcher.scala:54:27] wire _out_arb_io_out_bits_write; // @[TLPrefetcher.scala:54:27] wire [31:0] _out_arb_io_out_bits_address; // @[TLPrefetcher.scala:54:27] wire [1:0] _out_arb_io_chosen; // @[TLPrefetcher.scala:54:27] wire _prefetchers_2_io_request_valid; // @[NextLine.scala:106:53] wire _prefetchers_2_io_request_bits_write; // @[NextLine.scala:106:53] wire [31:0] _prefetchers_2_io_request_bits_address; // @[NextLine.scala:106:53] wire _prefetchers_0_io_request_valid; // @[AMPM.scala:29:53] wire _prefetchers_0_io_request_bits_write; // @[AMPM.scala:29:53] wire [31:0] _prefetchers_0_io_request_bits_address; // @[AMPM.scala:29:53] wire auto_in_a_valid_0 = auto_in_a_valid; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[TLPrefetcher.scala:35:25] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[TLPrefetcher.scala:35:25] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[TLPrefetcher.scala:35:25] wire auto_in_b_ready_0 = auto_in_b_ready; // @[TLPrefetcher.scala:35:25] wire auto_in_c_valid_0 = auto_in_c_valid; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[TLPrefetcher.scala:35:25] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[TLPrefetcher.scala:35:25] wire auto_in_d_ready_0 = auto_in_d_ready; // @[TLPrefetcher.scala:35:25] wire auto_in_e_valid_0 = auto_in_e_valid; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[TLPrefetcher.scala:35:25] wire auto_out_a_ready_0 = auto_out_a_ready; // @[TLPrefetcher.scala:35:25] wire auto_out_b_valid_0 = auto_out_b_valid; // @[TLPrefetcher.scala:35:25] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[TLPrefetcher.scala:35:25] wire auto_out_c_ready_0 = auto_out_c_ready; // @[TLPrefetcher.scala:35:25] wire auto_out_d_valid_0 = auto_out_d_valid; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[TLPrefetcher.scala:35:25] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[TLPrefetcher.scala:35:25] wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[TLPrefetcher.scala:35:25] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[TLPrefetcher.scala:35:25] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[TLPrefetcher.scala:35:25] wire [2:0] _nodeIn_b_bits_source_T_19 = 3'h2; // @[Parameters.scala:46:9] wire [2:0] _nodeIn_d_bits_source_T_19 = 3'h2; // @[Parameters.scala:46:9] wire [5:0] _nodeIn_b_bits_source_T_6 = 6'h0; // @[TLPrefetcher.scala:65:44] wire [4:0] _nodeIn_b_bits_source_T_7 = 5'h0; // @[TLPrefetcher.scala:65:44] wire [5:0] _nodeIn_b_bits_source_T_17 = 6'h8; // @[TLPrefetcher.scala:65:44] wire [4:0] _nodeIn_b_bits_source_T_18 = 5'h8; // @[TLPrefetcher.scala:65:44] wire [5:0] _nodeIn_b_bits_source_T_27 = 6'h10; // @[TLPrefetcher.scala:65:44] wire [1:0] _nodeIn_b_bits_source_T_9 = 2'h0; // @[TLPrefetcher.scala:65:65] wire [1:0] _nodeIn_b_bits_source_T_32 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _nodeIn_b_bits_source_T_34 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _nodeIn_b_bits_source_T = 2'h2; // @[Parameters.scala:54:10] wire [1:0] _nodeIn_b_bits_source_T_11 = 2'h2; // @[Parameters.scala:54:10] wire [1:0] _nodeIn_b_bits_source_T_20 = 2'h2; // @[TLPrefetcher.scala:65:65] wire [1:0] _nodeIn_b_bits_source_T_21 = 2'h2; // @[Parameters.scala:54:10] wire [1:0] _nodeIn_d_bits_source_T_20 = 2'h2; // @[TLPrefetcher.scala:65:65] wire [1:0] a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _nodeIn_b_bits_source_T_29 = 4'h4; // @[TLPrefetcher.scala:62:52, :65:65] wire [3:0] _nodeIn_d_bits_source_T_29 = 4'h4; // @[TLPrefetcher.scala:62:52, :65:65] wire [3:0] _a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [2:0] _nodeIn_b_bits_source_T_30 = 3'h4; // @[TLPrefetcher.scala:65:65] wire [2:0] _nodeIn_d_bits_source_T_30 = 3'h4; // @[TLPrefetcher.scala:65:65] wire [2:0] _a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] hint_opcode = 3'h5; // @[Edges.scala:551:17] wire [2:0] a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [4:0] auto_out_b_bits_source = 5'h10; // @[TLPrefetcher.scala:35:25] wire [4:0] nodeOut_b_bits_source = 5'h10; // @[MixedNode.scala:542:17] wire [4:0] _nodeIn_b_bits_source_uncommonBits_T = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _nodeIn_b_bits_source_uncommonBits_T_1 = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _nodeIn_b_bits_source_uncommonBits_T_2 = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _nodeIn_b_bits_source_T_28 = 5'h10; // @[TLPrefetcher.scala:65:44] wire auto_in_e_ready = 1'h1; // @[TLPrefetcher.scala:35:25] wire auto_out_e_ready = 1'h1; // @[TLPrefetcher.scala:35:25] wire nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire nodeOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire _nodeOut_a_bits_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _nodeOut_a_bits_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_b_bits_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _nodeIn_b_bits_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_b_bits_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _nodeIn_b_bits_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_b_bits_source_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _nodeIn_b_bits_source_T_13 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_b_bits_source_T_15 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_b_bits_source_T_23 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_b_bits_source_T_25 = 1'h1; // @[Parameters.scala:57:20] wire _nodeOut_c_bits_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _nodeOut_c_bits_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_d_bits_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_d_bits_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_d_bits_source_T_13 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_d_bits_source_T_15 = 1'h1; // @[Parameters.scala:57:20] wire _nodeIn_d_bits_source_T_23 = 1'h1; // @[Parameters.scala:56:32] wire _nodeIn_d_bits_source_T_25 = 1'h1; // @[Parameters.scala:57:20] wire _tracker_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _tracker_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _tracker_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _tracker_T_14 = 1'h1; // @[Parameters.scala:57:20] wire _tracker_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _tracker_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _snoop_valid_T_20 = 1'h1; // @[Parameters.scala:91:44] wire _snoop_valid_T_21 = 1'h1; // @[Parameters.scala:684:29] wire _snoop_client_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _snoop_client_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_47 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_48 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_49 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_50 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire auto_in_b_bits_corrupt = 1'h0; // @[TLPrefetcher.scala:35:25] wire auto_out_b_bits_corrupt = 1'h0; // @[TLPrefetcher.scala:35:25] wire nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _nodeIn_b_bits_source_T_8 = 1'h0; // @[TLPrefetcher.scala:33:67] wire _nodeIn_b_bits_source_T_10 = 1'h0; // @[TLPrefetcher.scala:65:65] wire _nodeIn_b_bits_source_T_12 = 1'h0; // @[Parameters.scala:54:32] wire _nodeIn_b_bits_source_T_14 = 1'h0; // @[Parameters.scala:54:67] wire _nodeIn_b_bits_source_T_16 = 1'h0; // @[Parameters.scala:56:48] wire _nodeIn_b_bits_source_T_22 = 1'h0; // @[Parameters.scala:54:32] wire _nodeIn_b_bits_source_T_24 = 1'h0; // @[Parameters.scala:54:67] wire _nodeIn_b_bits_source_T_26 = 1'h0; // @[Parameters.scala:56:48] wire _nodeIn_b_bits_source_T_31 = 1'h0; // @[Mux.scala:30:73] wire _snoop_valid_T_1 = 1'h0; // @[Parameters.scala:684:29] wire _snoop_valid_T_19 = 1'h0; // @[Parameters.scala:684:54] wire _snoop_valid_T_34 = 1'h0; // @[Parameters.scala:686:26] wire _snoop_client_T_8 = 1'h0; // @[Mux.scala:30:73] wire _legal_T_10 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_46 = 1'h0; // @[Parameters.scala:684:54] wire hint_corrupt = 1'h0; // @[Edges.scala:551:17] wire a_mask_sub_sub_bit = 1'h0; // @[Misc.scala:210:26] wire a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire a_mask_sub_bit = 1'h0; // @[Misc.scala:210:26] wire _a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_mask_bit = 1'h0; // @[Misc.scala:210:26] wire [63:0] auto_in_b_bits_data = 64'h0; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_out_b_bits_data = 64'h0; // @[TLPrefetcher.scala:35:25] wire [63:0] nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] hint_data = 64'h0; // @[Edges.scala:551:17] wire [7:0] auto_in_b_bits_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] nodeIn_b_bits_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] hint_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] _a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire [2:0] auto_in_b_bits_source = 3'h0; // @[TLPrefetcher.scala:35:25] wire [2:0] nodeIn_b_bits_source = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_source_uncommonBits = 3'h0; // @[Parameters.scala:52:56] wire [2:0] nodeIn_b_bits_source_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] nodeIn_b_bits_source_uncommonBits_2 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _nodeIn_b_bits_source_T_33 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeIn_b_bits_source_T_35 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeIn_b_bits_source_WIRE = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_in_b_bits_size = 4'h6; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_out_b_bits_size = 4'h6; // @[TLPrefetcher.scala:35:25] wire [3:0] nodeIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] hint_size = 4'h6; // @[Edges.scala:551:17] wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[TLPrefetcher.scala:35:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] _a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire nodeIn_a_valid = auto_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire nodeIn_b_ready = auto_in_b_ready_0; // @[MixedNode.scala:551:17] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[MixedNode.scala:551:17] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[MixedNode.scala:551:17] wire nodeIn_d_ready = auto_in_d_ready_0; // @[MixedNode.scala:551:17] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[MixedNode.scala:542:17] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[MixedNode.scala:542:17] wire nodeOut_c_ready = auto_out_c_ready_0; // @[MixedNode.scala:542:17] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[TLPrefetcher.scala:35:25] wire [1:0] auto_in_b_bits_param_0; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_in_b_bits_address_0; // @[TLPrefetcher.scala:35:25] wire auto_in_b_valid_0; // @[TLPrefetcher.scala:35:25] wire auto_in_c_ready_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_d_bits_opcode_0; // @[TLPrefetcher.scala:35:25] wire [1:0] auto_in_d_bits_param_0; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_in_d_bits_size_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_d_bits_source_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_in_d_bits_sink_0; // @[TLPrefetcher.scala:35:25] wire auto_in_d_bits_denied_0; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_in_d_bits_data_0; // @[TLPrefetcher.scala:35:25] wire auto_in_d_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] wire auto_in_d_valid_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_a_bits_opcode_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_a_bits_param_0; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_out_a_bits_size_0; // @[TLPrefetcher.scala:35:25] wire [4:0] auto_out_a_bits_source_0; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_out_a_bits_address_0; // @[TLPrefetcher.scala:35:25] wire [7:0] auto_out_a_bits_mask_0; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_out_a_bits_data_0; // @[TLPrefetcher.scala:35:25] wire auto_out_a_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] wire auto_out_a_valid_0; // @[TLPrefetcher.scala:35:25] wire auto_out_b_ready_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_c_bits_opcode_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_c_bits_param_0; // @[TLPrefetcher.scala:35:25] wire [3:0] auto_out_c_bits_size_0; // @[TLPrefetcher.scala:35:25] wire [4:0] auto_out_c_bits_source_0; // @[TLPrefetcher.scala:35:25] wire [31:0] auto_out_c_bits_address_0; // @[TLPrefetcher.scala:35:25] wire [63:0] auto_out_c_bits_data_0; // @[TLPrefetcher.scala:35:25] wire auto_out_c_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] wire auto_out_c_valid_0; // @[TLPrefetcher.scala:35:25] wire auto_out_d_ready_0; // @[TLPrefetcher.scala:35:25] wire [2:0] auto_out_e_bits_sink_0; // @[TLPrefetcher.scala:35:25] wire auto_out_e_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] _nodeOut_a_bits_source_uncommonBits_T = nodeIn_a_bits_source; // @[Parameters.scala:52:29] wire [2:0] _snoop_client_uncommonBits_T = nodeIn_a_bits_source; // @[Parameters.scala:52:29] wire [31:0] snoop_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire [31:0] _snoop_valid_T_2 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[MixedNode.scala:551:17] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[MixedNode.scala:551:17] assign nodeOut_c_valid = nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_opcode = nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_param = nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_size = nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] _nodeOut_c_bits_source_uncommonBits_T = nodeIn_c_bits_source; // @[Parameters.scala:52:29] assign nodeOut_c_bits_address = nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_data = nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_corrupt = nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T_1; // @[TLPrefetcher.scala:82:33] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[MixedNode.scala:551:17] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] _nodeIn_d_bits_source_WIRE; // @[Mux.scala:30:73] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign nodeOut_e_valid = nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_e_bits_sink = nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[MixedNode.scala:542:17] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_param = nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_address = nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_c_ready = nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[MixedNode.scala:542:17] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[MixedNode.scala:542:17] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [4:0] _nodeOut_c_bits_source_WIRE; // @[Mux.scala:30:73] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[MixedNode.scala:542:17] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[MixedNode.scala:542:17] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[MixedNode.scala:542:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] _nodeIn_d_bits_source_uncommonBits_T = nodeOut_d_bits_source; // @[Parameters.scala:52:29] wire [4:0] _nodeIn_d_bits_source_uncommonBits_T_1 = nodeOut_d_bits_source; // @[Parameters.scala:52:29] wire [4:0] _nodeIn_d_bits_source_uncommonBits_T_2 = nodeOut_d_bits_source; // @[Parameters.scala:52:29] wire [4:0] _tracker_uncommonBits_T = nodeOut_d_bits_source; // @[Parameters.scala:52:29] wire [4:0] _tracker_uncommonBits_T_1 = nodeOut_d_bits_source; // @[Parameters.scala:52:29] wire [4:0] _tracker_uncommonBits_T_2 = nodeOut_d_bits_source; // @[Parameters.scala:52:29] assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire _snoop_valid_T_36; // @[TLPrefetcher.scala:90:32] wire _snoop_bits_write_T_1; // @[TLPrefetcher.scala:95:31] wire snoop_bits_write; // @[TLPrefetcher.scala:41:23] wire snoop_valid; // @[TLPrefetcher.scala:41:23] wire [1:0] _snoop_client_WIRE; // @[Mux.scala:30:73] wire [1:0] snoop_client; // @[TLPrefetcher.scala:42:30] wire _prefetcher_io_snoop_valid_T = snoop_client == 2'h0; // @[TLPrefetcher.scala:42:30, :49:66] wire _prefetcher_io_snoop_valid_T_1 = snoop_valid & _prefetcher_io_snoop_valid_T; // @[TLPrefetcher.scala:41:23, :49:{50,66}] wire _prefetcher_io_snoop_valid_T_2 = snoop_client == 2'h1; // @[TLPrefetcher.scala:42:30, :49:66] wire _prefetcher_io_snoop_valid_T_3 = snoop_valid & _prefetcher_io_snoop_valid_T_2; // @[TLPrefetcher.scala:41:23, :49:{50,66}] wire _prefetcher_io_snoop_valid_T_4 = snoop_client == 2'h2; // @[TLPrefetcher.scala:42:30, :49:66] wire _prefetcher_io_snoop_valid_T_5 = snoop_valid & _prefetcher_io_snoop_valid_T_4; // @[TLPrefetcher.scala:41:23, :49:{50,66}] reg [3:0] tracker; // @[TLPrefetcher.scala:57:28] wire [3:0] _next_tracker_T = ~tracker; // @[TLPrefetcher.scala:57:28, :58:42] wire _next_tracker_T_1 = _next_tracker_T[0]; // @[OneHot.scala:48:45] wire _next_tracker_T_2 = _next_tracker_T[1]; // @[OneHot.scala:48:45] wire _next_tracker_T_3 = _next_tracker_T[2]; // @[OneHot.scala:48:45] wire _next_tracker_T_4 = _next_tracker_T[3]; // @[OneHot.scala:48:45] wire [1:0] _next_tracker_T_5 = {1'h1, ~_next_tracker_T_3}; // @[OneHot.scala:48:45] wire [1:0] _next_tracker_T_6 = _next_tracker_T_2 ? 2'h1 : _next_tracker_T_5; // @[OneHot.scala:48:45] wire [1:0] next_tracker = _next_tracker_T_1 ? 2'h0 : _next_tracker_T_6; // @[OneHot.scala:48:45] wire [3:0] _GEN = {2'h0, next_tracker}; // @[Mux.scala:50:70] wire [3:0] _tracker_free_T = tracker >> _GEN; // @[TLPrefetcher.scala:57:28, :59:34] wire _tracker_free_T_1 = _tracker_free_T[0]; // @[TLPrefetcher.scala:59:34] wire tracker_free = ~_tracker_free_T_1; // @[TLPrefetcher.scala:59:{26,34}] wire nodeOut_a_bits_source_uncommonBits = _nodeOut_a_bits_source_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _nodeOut_a_bits_source_T = nodeIn_a_bits_source[2:1]; // @[Parameters.scala:54:10] wire [1:0] _snoop_client_T = nodeIn_a_bits_source[2:1]; // @[Parameters.scala:54:10] wire _nodeOut_a_bits_source_T_1 = _nodeOut_a_bits_source_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _nodeOut_a_bits_source_T_3 = _nodeOut_a_bits_source_T_1; // @[Parameters.scala:54:{32,67}] wire _nodeOut_a_bits_source_T_5 = _nodeOut_a_bits_source_T_3; // @[Parameters.scala:54:67, :56:48] wire [3:0] _nodeOut_a_bits_source_T_6 = {1'h0, nodeIn_a_bits_source}; // @[MixedNode.scala:551:17] wire [2:0] _nodeOut_a_bits_source_T_7 = _nodeOut_a_bits_source_T_6[2:0]; // @[TLPrefetcher.scala:62:52] wire [4:0] _nodeOut_a_bits_source_T_8 = {2'h2, _nodeOut_a_bits_source_T_7}; // @[TLPrefetcher.scala:62:{42,52}] wire _GEN_0 = nodeIn_a_bits_source == 3'h2; // @[Parameters.scala:46:9] wire _nodeOut_a_bits_source_T_9; // @[Parameters.scala:46:9] assign _nodeOut_a_bits_source_T_9 = _GEN_0; // @[Parameters.scala:46:9] wire _snoop_client_T_6; // @[Parameters.scala:46:9] assign _snoop_client_T_6 = _GEN_0; // @[Parameters.scala:46:9] wire [3:0] _nodeOut_a_bits_source_T_10 = _nodeOut_a_bits_source_T_6 - 4'h2; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_a_bits_source_T_11 = _nodeOut_a_bits_source_T_10[2:0]; // @[TLPrefetcher.scala:62:52] wire [3:0] _nodeOut_a_bits_source_T_12 = {1'h1, _nodeOut_a_bits_source_T_11}; // @[TLPrefetcher.scala:62:{42,52}] wire _GEN_1 = nodeIn_a_bits_source == 3'h4; // @[Parameters.scala:46:9] wire _nodeOut_a_bits_source_T_13; // @[Parameters.scala:46:9] assign _nodeOut_a_bits_source_T_13 = _GEN_1; // @[Parameters.scala:46:9] wire _snoop_client_T_7; // @[Parameters.scala:46:9] assign _snoop_client_T_7 = _GEN_1; // @[Parameters.scala:46:9] wire [3:0] _nodeOut_a_bits_source_T_14 = _nodeOut_a_bits_source_T_6 - 4'h4; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_a_bits_source_T_15 = _nodeOut_a_bits_source_T_14[2:0]; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_a_bits_source_T_16 = _nodeOut_a_bits_source_T_15; // @[TLPrefetcher.scala:62:{42,52}] wire [4:0] _nodeOut_a_bits_source_T_17 = _nodeOut_a_bits_source_T_5 ? _nodeOut_a_bits_source_T_8 : 5'h0; // @[Mux.scala:30:73] wire [3:0] _nodeOut_a_bits_source_T_18 = _nodeOut_a_bits_source_T_9 ? _nodeOut_a_bits_source_T_12 : 4'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_source_T_19 = _nodeOut_a_bits_source_T_13 ? _nodeOut_a_bits_source_T_16 : 3'h0; // @[Mux.scala:30:73] wire [4:0] _nodeOut_a_bits_source_T_20 = {_nodeOut_a_bits_source_T_17[4], _nodeOut_a_bits_source_T_17[3:0] | _nodeOut_a_bits_source_T_18}; // @[Mux.scala:30:73] wire [4:0] _nodeOut_a_bits_source_T_21 = {_nodeOut_a_bits_source_T_20[4:3], _nodeOut_a_bits_source_T_20[2:0] | _nodeOut_a_bits_source_T_19}; // @[Mux.scala:30:73] wire [4:0] _nodeOut_a_bits_source_WIRE = _nodeOut_a_bits_source_T_21; // @[Mux.scala:30:73] wire nodeOut_c_bits_source_uncommonBits = _nodeOut_c_bits_source_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _nodeOut_c_bits_source_T = nodeIn_c_bits_source[2:1]; // @[Parameters.scala:54:10] wire _nodeOut_c_bits_source_T_1 = _nodeOut_c_bits_source_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _nodeOut_c_bits_source_T_3 = _nodeOut_c_bits_source_T_1; // @[Parameters.scala:54:{32,67}] wire _nodeOut_c_bits_source_T_5 = _nodeOut_c_bits_source_T_3; // @[Parameters.scala:54:67, :56:48] wire [3:0] _nodeOut_c_bits_source_T_6 = {1'h0, nodeIn_c_bits_source}; // @[MixedNode.scala:551:17] wire [2:0] _nodeOut_c_bits_source_T_7 = _nodeOut_c_bits_source_T_6[2:0]; // @[TLPrefetcher.scala:62:52] wire [4:0] _nodeOut_c_bits_source_T_8 = {2'h2, _nodeOut_c_bits_source_T_7}; // @[TLPrefetcher.scala:62:{42,52}] wire _nodeOut_c_bits_source_T_9 = nodeIn_c_bits_source == 3'h2; // @[Parameters.scala:46:9] wire [3:0] _nodeOut_c_bits_source_T_10 = _nodeOut_c_bits_source_T_6 - 4'h2; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_c_bits_source_T_11 = _nodeOut_c_bits_source_T_10[2:0]; // @[TLPrefetcher.scala:62:52] wire [3:0] _nodeOut_c_bits_source_T_12 = {1'h1, _nodeOut_c_bits_source_T_11}; // @[TLPrefetcher.scala:62:{42,52}] wire _nodeOut_c_bits_source_T_13 = nodeIn_c_bits_source == 3'h4; // @[Parameters.scala:46:9] wire [3:0] _nodeOut_c_bits_source_T_14 = _nodeOut_c_bits_source_T_6 - 4'h4; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_c_bits_source_T_15 = _nodeOut_c_bits_source_T_14[2:0]; // @[TLPrefetcher.scala:62:52] wire [2:0] _nodeOut_c_bits_source_T_16 = _nodeOut_c_bits_source_T_15; // @[TLPrefetcher.scala:62:{42,52}] wire [4:0] _nodeOut_c_bits_source_T_17 = _nodeOut_c_bits_source_T_5 ? _nodeOut_c_bits_source_T_8 : 5'h0; // @[Mux.scala:30:73] wire [3:0] _nodeOut_c_bits_source_T_18 = _nodeOut_c_bits_source_T_9 ? _nodeOut_c_bits_source_T_12 : 4'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_source_T_19 = _nodeOut_c_bits_source_T_13 ? _nodeOut_c_bits_source_T_16 : 3'h0; // @[Mux.scala:30:73] wire [4:0] _nodeOut_c_bits_source_T_20 = {_nodeOut_c_bits_source_T_17[4], _nodeOut_c_bits_source_T_17[3:0] | _nodeOut_c_bits_source_T_18}; // @[Mux.scala:30:73] wire [4:0] _nodeOut_c_bits_source_T_21 = {_nodeOut_c_bits_source_T_20[4:3], _nodeOut_c_bits_source_T_20[2:0] | _nodeOut_c_bits_source_T_19}; // @[Mux.scala:30:73] assign _nodeOut_c_bits_source_WIRE = _nodeOut_c_bits_source_T_21; // @[Mux.scala:30:73] assign nodeOut_c_bits_source = _nodeOut_c_bits_source_WIRE; // @[Mux.scala:30:73] wire d_is_prefetch = nodeOut_d_bits_opcode == 3'h2; // @[Parameters.scala:46:9] wire _nodeIn_d_valid_T = ~d_is_prefetch; // @[TLPrefetcher.scala:81:45, :82:36] assign _nodeIn_d_valid_T_1 = nodeOut_d_valid & _nodeIn_d_valid_T; // @[MixedNode.scala:542:17] assign nodeIn_d_valid = _nodeIn_d_valid_T_1; // @[MixedNode.scala:551:17] assign nodeOut_d_ready = d_is_prefetch | nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire [2:0] nodeIn_d_bits_source_uncommonBits = _nodeIn_d_bits_source_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _nodeIn_d_bits_source_T = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire [1:0] _nodeIn_d_bits_source_T_11 = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire [1:0] _nodeIn_d_bits_source_T_21 = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire [1:0] _tracker_T_1 = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire [1:0] _tracker_T_10 = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire [1:0] _tracker_T_19 = nodeOut_d_bits_source[4:3]; // @[Parameters.scala:54:10] wire _nodeIn_d_bits_source_T_1 = _nodeIn_d_bits_source_T == 2'h2; // @[Parameters.scala:54:{10,32}] wire _nodeIn_d_bits_source_T_3 = _nodeIn_d_bits_source_T_1; // @[Parameters.scala:54:{32,67}] wire _nodeIn_d_bits_source_T_5 = _nodeIn_d_bits_source_T_3; // @[Parameters.scala:54:67, :56:48] wire [5:0] _nodeIn_d_bits_source_T_27 = {1'h0, nodeOut_d_bits_source}; // @[MixedNode.scala:542:17] wire [5:0] _nodeIn_d_bits_source_T_6 = _nodeIn_d_bits_source_T_27 - 6'h10; // @[TLPrefetcher.scala:65:44] wire [4:0] _nodeIn_d_bits_source_T_7 = _nodeIn_d_bits_source_T_6[4:0]; // @[TLPrefetcher.scala:65:44] wire _nodeIn_d_bits_source_T_8 = _nodeIn_d_bits_source_T_7[0]; // @[TLPrefetcher.scala:33:67, :65:44] wire [1:0] _nodeIn_d_bits_source_T_9 = {1'h0, _nodeIn_d_bits_source_T_8}; // @[TLPrefetcher.scala:33:67, :65:65] wire _nodeIn_d_bits_source_T_10 = _nodeIn_d_bits_source_T_9[0]; // @[TLPrefetcher.scala:65:65] wire [2:0] nodeIn_d_bits_source_uncommonBits_1 = _nodeIn_d_bits_source_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _nodeIn_d_bits_source_T_12 = _nodeIn_d_bits_source_T_11 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _nodeIn_d_bits_source_T_14 = _nodeIn_d_bits_source_T_12; // @[Parameters.scala:54:{32,67}] wire _nodeIn_d_bits_source_T_16 = _nodeIn_d_bits_source_T_14; // @[Parameters.scala:54:67, :56:48] wire [5:0] _nodeIn_d_bits_source_T_17 = _nodeIn_d_bits_source_T_27 - 6'h8; // @[TLPrefetcher.scala:65:44] wire [4:0] _nodeIn_d_bits_source_T_18 = _nodeIn_d_bits_source_T_17[4:0]; // @[TLPrefetcher.scala:65:44] wire [2:0] nodeIn_d_bits_source_uncommonBits_2 = _nodeIn_d_bits_source_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _nodeIn_d_bits_source_T_22 = _nodeIn_d_bits_source_T_21 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _nodeIn_d_bits_source_T_24 = _nodeIn_d_bits_source_T_22; // @[Parameters.scala:54:{32,67}] wire _nodeIn_d_bits_source_T_26 = _nodeIn_d_bits_source_T_24; // @[Parameters.scala:54:67, :56:48] wire [4:0] _nodeIn_d_bits_source_T_28 = _nodeIn_d_bits_source_T_27[4:0]; // @[TLPrefetcher.scala:65:44] wire _nodeIn_d_bits_source_T_31 = _nodeIn_d_bits_source_T_5 & _nodeIn_d_bits_source_T_10; // @[Mux.scala:30:73] wire [1:0] _nodeIn_d_bits_source_T_32 = {_nodeIn_d_bits_source_T_16, 1'h0}; // @[Mux.scala:30:73] wire [2:0] _nodeIn_d_bits_source_T_33 = {_nodeIn_d_bits_source_T_26, 2'h0}; // @[Mux.scala:30:73] wire [1:0] _nodeIn_d_bits_source_T_34 = {1'h0, _nodeIn_d_bits_source_T_31} | _nodeIn_d_bits_source_T_32; // @[Mux.scala:30:73] wire [2:0] _nodeIn_d_bits_source_T_35 = {1'h0, _nodeIn_d_bits_source_T_34} | _nodeIn_d_bits_source_T_33; // @[Mux.scala:30:73] assign _nodeIn_d_bits_source_WIRE = _nodeIn_d_bits_source_T_35; // @[Mux.scala:30:73] assign nodeIn_d_bits_source = _nodeIn_d_bits_source_WIRE; // @[Mux.scala:30:73] wire _tracker_T = nodeOut_d_valid & d_is_prefetch; // @[MixedNode.scala:542:17] wire [2:0] tracker_uncommonBits = _tracker_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _tracker_T_2 = _tracker_T_1 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _tracker_T_4 = _tracker_T_2; // @[Parameters.scala:54:{32,67}] wire _tracker_T_6 = _tracker_T_4; // @[Parameters.scala:54:67, :56:48] wire [5:0] _tracker_T_7 = _nodeIn_d_bits_source_T_27 - 6'h12; // @[TLPrefetcher.scala:65:44, :68:43] wire [4:0] _tracker_T_8 = _tracker_T_7[4:0]; // @[TLPrefetcher.scala:68:43] wire [1:0] _tracker_T_9 = _tracker_T_8[1:0]; // @[TLPrefetcher.scala:33:67, :68:43] wire [2:0] tracker_uncommonBits_1 = _tracker_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _tracker_T_11 = _tracker_T_10 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _tracker_T_13 = _tracker_T_11; // @[Parameters.scala:54:{32,67}] wire _tracker_T_15 = _tracker_T_13; // @[Parameters.scala:54:67, :56:48] wire [5:0] _tracker_T_16 = _nodeIn_d_bits_source_T_27 - 6'h9; // @[TLPrefetcher.scala:65:44, :68:43] wire [4:0] _tracker_T_17 = _tracker_T_16[4:0]; // @[TLPrefetcher.scala:68:43] wire [1:0] _tracker_T_18 = _tracker_T_17[1:0]; // @[TLPrefetcher.scala:33:67, :68:43] wire [2:0] tracker_uncommonBits_2 = _tracker_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _tracker_T_20 = _tracker_T_19 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _tracker_T_22 = _tracker_T_20; // @[Parameters.scala:54:{32,67}] wire _tracker_T_24 = _tracker_T_22; // @[Parameters.scala:54:67, :56:48] wire [5:0] _tracker_T_25 = _nodeIn_d_bits_source_T_27 - 6'h1; // @[TLPrefetcher.scala:65:44, :68:43] wire [4:0] _tracker_T_26 = _tracker_T_25[4:0]; // @[TLPrefetcher.scala:68:43] wire [1:0] _tracker_T_27 = _tracker_T_26[1:0]; // @[TLPrefetcher.scala:33:67, :68:43] wire [1:0] _tracker_T_28 = _tracker_T_6 ? _tracker_T_9 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _tracker_T_29 = _tracker_T_15 ? _tracker_T_18 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _tracker_T_30 = _tracker_T_24 ? _tracker_T_27 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _tracker_T_31 = _tracker_T_28 | _tracker_T_29; // @[Mux.scala:30:73] wire [1:0] _tracker_T_32 = _tracker_T_31 | _tracker_T_30; // @[Mux.scala:30:73] wire [1:0] _tracker_WIRE = _tracker_T_32; // @[Mux.scala:30:73] wire [3:0] _tracker_T_33 = {3'h0, _tracker_T} << _tracker_WIRE; // @[Mux.scala:30:73] wire [3:0] _tracker_T_34 = tracker ^ _tracker_T_33; // @[TLPrefetcher.scala:57:28, :87:{9,43}] wire _tracker_T_35 = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35] wire _tracker_T_36 = ~nodeIn_a_valid; // @[MixedNode.scala:551:17] wire _tracker_T_37 = _tracker_T_35 & _tracker_T_36; // @[Decoupled.scala:51:35] wire [3:0] _tracker_T_38 = {3'h0, _tracker_T_37} << _GEN; // @[TLPrefetcher.scala:59:34, :88:{24,40}] wire [3:0] _tracker_T_39 = _tracker_T_34 ^ _tracker_T_38; // @[TLPrefetcher.scala:87:9, :88:{9,40}] wire _snoop_valid_T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire [32:0] _snoop_valid_T_3 = {1'h0, _snoop_valid_T_2}; // @[Parameters.scala:137:{31,41}] wire [32:0] _snoop_valid_T_4 = _snoop_valid_T_3 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _snoop_valid_T_5 = _snoop_valid_T_4; // @[Parameters.scala:137:46] wire _snoop_valid_T_6 = _snoop_valid_T_5 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _snoop_valid_T_7 = {nodeIn_a_bits_address[31:17], nodeIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] _snoop_valid_T_8 = {1'h0, _snoop_valid_T_7}; // @[Parameters.scala:137:{31,41}] wire [32:0] _snoop_valid_T_9 = _snoop_valid_T_8 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _snoop_valid_T_10 = _snoop_valid_T_9; // @[Parameters.scala:137:46] wire _snoop_valid_T_11 = _snoop_valid_T_10 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _snoop_valid_T_12 = {nodeIn_a_bits_address[31:28], nodeIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] _snoop_valid_T_13 = {1'h0, _snoop_valid_T_12}; // @[Parameters.scala:137:{31,41}] wire [32:0] _snoop_valid_T_14 = _snoop_valid_T_13 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _snoop_valid_T_15 = _snoop_valid_T_14; // @[Parameters.scala:137:46] wire _snoop_valid_T_16 = _snoop_valid_T_15 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _snoop_valid_T_17 = _snoop_valid_T_6 | _snoop_valid_T_11; // @[Parameters.scala:685:42] wire _snoop_valid_T_18 = _snoop_valid_T_17 | _snoop_valid_T_16; // @[Parameters.scala:685:42] wire [31:0] _snoop_valid_T_22 = {nodeIn_a_bits_address[31:28], nodeIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] _snoop_valid_T_23 = {1'h0, _snoop_valid_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] _snoop_valid_T_24 = _snoop_valid_T_23 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _snoop_valid_T_25 = _snoop_valid_T_24; // @[Parameters.scala:137:46] wire _snoop_valid_T_26 = _snoop_valid_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _snoop_valid_T_27 = nodeIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _snoop_valid_T_28 = {1'h0, _snoop_valid_T_27}; // @[Parameters.scala:137:{31,41}] wire [32:0] _snoop_valid_T_29 = _snoop_valid_T_28 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _snoop_valid_T_30 = _snoop_valid_T_29; // @[Parameters.scala:137:46] wire _snoop_valid_T_31 = _snoop_valid_T_30 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _snoop_valid_T_32 = _snoop_valid_T_26 | _snoop_valid_T_31; // @[Parameters.scala:685:42] wire _snoop_valid_T_33 = _snoop_valid_T_32; // @[Parameters.scala:684:54, :685:42] wire _snoop_valid_T_35 = _snoop_valid_T_33; // @[Parameters.scala:684:54, :686:26] assign _snoop_valid_T_36 = _snoop_valid_T & _snoop_valid_T_35; // @[Decoupled.scala:51:35] assign snoop_valid = _snoop_valid_T_36; // @[TLPrefetcher.scala:41:23, :90:32] wire _acq_T = nodeIn_a_bits_opcode == 3'h6; // @[package.scala:16:47] wire _acq_T_1 = &nodeIn_a_bits_opcode; // @[package.scala:16:47] wire acq = _acq_T | _acq_T_1; // @[package.scala:16:47, :81:59] wire _toT_T = nodeIn_a_bits_param == 3'h1; // @[package.scala:16:47] wire _toT_T_1 = nodeIn_a_bits_param == 3'h2; // @[package.scala:16:47] wire toT = _toT_T | _toT_T_1; // @[package.scala:16:47, :81:59] wire _put_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire put = ~_put_opdata_T; // @[Edges.scala:92:{28,37}] wire _snoop_bits_write_T = acq & toT; // @[package.scala:81:59] assign _snoop_bits_write_T_1 = put | _snoop_bits_write_T; // @[Edges.scala:92:28] assign snoop_bits_write = _snoop_bits_write_T_1; // @[TLPrefetcher.scala:41:23, :95:31] wire snoop_client_uncommonBits = _snoop_client_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire _snoop_client_T_1 = _snoop_client_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _snoop_client_T_3 = _snoop_client_T_1; // @[Parameters.scala:54:{32,67}] wire _snoop_client_T_5 = _snoop_client_T_3; // @[Parameters.scala:54:67, :56:48] wire _snoop_client_T_9 = _snoop_client_T_6; // @[Mux.scala:30:73] wire _snoop_client_T_11 = _snoop_client_T_9; // @[Mux.scala:30:73] wire [1:0] _snoop_client_T_10 = {_snoop_client_T_7, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _snoop_client_T_12 = {1'h0, _snoop_client_T_11} | _snoop_client_T_10; // @[Mux.scala:30:73] assign _snoop_client_WIRE = _snoop_client_T_12; // @[Mux.scala:30:73] assign snoop_client = _snoop_client_WIRE; // @[Mux.scala:30:73] wire [25:0] _legal_address_T = _out_arb_io_out_bits_address[31:6]; // @[TLPrefetcher.scala:54:27] wire [31:0] _legal_address_T_1 = {_legal_address_T, 6'h0}; // @[AbstractPrefetcher.scala:30:23, :31:29] wire [31:0] _legal_address_T_2 = _legal_address_T_1; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_3 = {1'h0, _legal_address_T_2}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_4 = _legal_address_T_3 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_5 = _legal_address_T_4; // @[Parameters.scala:137:46] wire _legal_address_T_6 = _legal_address_T_5 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_6; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_7 = {_legal_address_T_1[31:13], _legal_address_T_1[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_8 = {1'h0, _legal_address_T_7}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_9 = _legal_address_T_8 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_10 = _legal_address_T_9; // @[Parameters.scala:137:46] wire _legal_address_T_11 = _legal_address_T_10 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_11; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_12 = {_legal_address_T_1[31:14], _legal_address_T_1[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_13 = {1'h0, _legal_address_T_12}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_14 = _legal_address_T_13 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_15 = _legal_address_T_14; // @[Parameters.scala:137:46] wire _legal_address_T_16 = _legal_address_T_15 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_16; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_17 = {_legal_address_T_1[31:17], _legal_address_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_18 = {1'h0, _legal_address_T_17}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_19 = _legal_address_T_18 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_20 = _legal_address_T_19; // @[Parameters.scala:137:46] wire _legal_address_T_21 = _legal_address_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_21; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_22 = {_legal_address_T_1[31:21], _legal_address_T_1[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_23 = {1'h0, _legal_address_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_24 = _legal_address_T_23 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_25 = _legal_address_T_24; // @[Parameters.scala:137:46] wire _legal_address_T_26 = _legal_address_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_26; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_27 = {_legal_address_T_1[31:21], _legal_address_T_1[20:0] ^ 21'h110000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_28 = {1'h0, _legal_address_T_27}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_29 = _legal_address_T_28 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_30 = _legal_address_T_29; // @[Parameters.scala:137:46] wire _legal_address_T_31 = _legal_address_T_30 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_31; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_32 = {_legal_address_T_1[31:26], _legal_address_T_1[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_33 = {1'h0, _legal_address_T_32}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_34 = _legal_address_T_33 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_35 = _legal_address_T_34; // @[Parameters.scala:137:46] wire _legal_address_T_36 = _legal_address_T_35 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_36; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_37 = {_legal_address_T_1[31:26], _legal_address_T_1[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_38 = {1'h0, _legal_address_T_37}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_39 = _legal_address_T_38 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_40 = _legal_address_T_39; // @[Parameters.scala:137:46] wire _legal_address_T_41 = _legal_address_T_40 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_41; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_42 = {_legal_address_T_1[31:28], _legal_address_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_43 = {1'h0, _legal_address_T_42}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_44 = _legal_address_T_43 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_45 = _legal_address_T_44; // @[Parameters.scala:137:46] wire _legal_address_T_46 = _legal_address_T_45 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_46; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_47 = {_legal_address_T_1[31:28], _legal_address_T_1[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_48 = {1'h0, _legal_address_T_47}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_49 = _legal_address_T_48 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_50 = _legal_address_T_49; // @[Parameters.scala:137:46] wire _legal_address_T_51 = _legal_address_T_50 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_51; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_52 = {_legal_address_T_1[31:29], _legal_address_T_1[28:0] ^ 29'h10020000}; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_53 = {1'h0, _legal_address_T_52}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_54 = _legal_address_T_53 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_55 = _legal_address_T_54; // @[Parameters.scala:137:46] wire _legal_address_T_56 = _legal_address_T_55 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_56; // @[Parameters.scala:612:40] wire [31:0] _legal_address_T_57 = _legal_address_T_1 ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _legal_address_T_58 = {1'h0, _legal_address_T_57}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_address_T_59 = _legal_address_T_58 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_address_T_60 = _legal_address_T_59; // @[Parameters.scala:137:46] wire _legal_address_T_61 = _legal_address_T_60 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_61; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_70 = _legal_address_T_69 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_71 = _legal_address_T_70 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_71 | _legal_address_WIRE_11; // @[Parameters.scala:612:40] wire [4:0] _GEN_2 = {3'h0, next_tracker}; // @[Mux.scala:50:70] wire [4:0] _GEN_3 = (_out_arb_io_chosen == 2'h0 ? _GEN_2 - 5'hE : 5'h0) | (_out_arb_io_chosen == 2'h1 ? _GEN_2 + 5'h9 : 5'h0); // @[Mux.scala:30:73] wire [31:0] _T_12 = {_legal_address_T, 6'h0}; // @[AbstractPrefetcher.scala:30:23, :31:29] wire [31:0] _legal_T_11; // @[Parameters.scala:137:31] assign _legal_T_11 = _T_12; // @[Parameters.scala:137:31] wire [31:0] hint_address; // @[Edges.scala:551:17] assign hint_address = _T_12; // @[Edges.scala:551:17] wire [31:0] _legal_T_4 = {_out_arb_io_out_bits_address[31:14], _out_arb_io_out_bits_address[13:6] ^ 8'hC0, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9E013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_63 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _legal_T_12 = {1'h0, _legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_13 = _legal_T_12 & 33'h9E012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_14 = _legal_T_13; // @[Parameters.scala:137:46] wire _legal_T_15 = _legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_out_arb_io_out_bits_address[31:17], _out_arb_io_out_bits_address[16:6] ^ 11'h400, 6'h0}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_16; // @[Parameters.scala:137:31] assign _legal_T_16 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_21; // @[Parameters.scala:137:31] assign _legal_T_21 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_17 = {1'h0, _legal_T_16}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_18 = _legal_T_17 & 33'h9C013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_19 = _legal_T_18; // @[Parameters.scala:137:46] wire _legal_T_20 = _legal_T_19 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_22 = {1'h0, _legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_23 = _legal_T_22 & 33'h9E010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_24 = _legal_T_23; // @[Parameters.scala:137:46] wire _legal_T_25 = _legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_26 = {_out_arb_io_out_bits_address[31:26], _out_arb_io_out_bits_address[25:6] ^ 20'h80000, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_27 = {1'h0, _legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_28 = _legal_T_27 & 33'h9E010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_29 = _legal_T_28; // @[Parameters.scala:137:46] wire _legal_T_30 = _legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_31 = {_out_arb_io_out_bits_address[31:28], _out_arb_io_out_bits_address[27:6] ^ 22'h300000, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_32 = {1'h0, _legal_T_31}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_33 = _legal_T_32 & 33'h9C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_34 = _legal_T_33; // @[Parameters.scala:137:46] wire _legal_T_35 = _legal_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_36 = {_out_arb_io_out_bits_address[31:29], _out_arb_io_out_bits_address[28:6] ^ 23'h400000, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_37 = {1'h0, _legal_T_36}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_38 = _legal_T_37 & 33'h9E013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_39 = _legal_T_38; // @[Parameters.scala:137:46] wire _legal_T_40 = _legal_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_41 = _legal_T_15 | _legal_T_20; // @[Parameters.scala:685:42] wire _legal_T_42 = _legal_T_41 | _legal_T_25; // @[Parameters.scala:685:42] wire _legal_T_43 = _legal_T_42 | _legal_T_30; // @[Parameters.scala:685:42] wire _legal_T_44 = _legal_T_43 | _legal_T_35; // @[Parameters.scala:685:42] wire _legal_T_45 = _legal_T_44 | _legal_T_40; // @[Parameters.scala:685:42] wire [31:0] _legal_T_51 = {_out_arb_io_out_bits_address[31:28], _out_arb_io_out_bits_address[27:6] ^ 22'h200000, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_52 = {1'h0, _legal_T_51}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_53 = _legal_T_52 & 33'h9E010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_54 = _legal_T_53; // @[Parameters.scala:137:46] wire _legal_T_55 = _legal_T_54 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_56 = {_legal_address_T ^ 26'h2000000, 6'h0}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_57 = {1'h0, _legal_T_56}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_58 = _legal_T_57 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_59 = _legal_T_58; // @[Parameters.scala:137:46] wire _legal_T_60 = _legal_T_59 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_61 = _legal_T_55 | _legal_T_60; // @[Parameters.scala:685:42] wire _legal_T_62 = _legal_T_61; // @[Parameters.scala:684:54, :685:42] wire _legal_T_64 = _legal_T_63; // @[Parameters.scala:686:26] wire legal = _legal_T_64 | _legal_T_62; // @[Parameters.scala:684:54, :686:26] wire [2:0] hint_param; // @[Edges.scala:551:17] wire [4:0] hint_source; // @[Edges.scala:551:17] assign hint_param = {2'h0, _out_arb_io_out_bits_write}; // @[Edges.scala:551:17, :553:15] assign hint_source = {_GEN_3[4:3], _GEN_3[2:0] | (_out_arb_io_chosen == 2'h2 ? {1'h0, next_tracker} + 3'h1 : 3'h0)}; // @[Mux.scala:30:73, :50:70] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T = a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _a_mask_sub_sub_acc_T_1 = a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_eq; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _nodeOut_a_valid_T = _out_arb_io_out_valid & tracker_free; // @[TLPrefetcher.scala:54:27, :59:26, :107:45] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & legal; // @[Parameters.scala:686:26] wire _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & legal_address; // @[TLPrefetcher.scala:98:95, :107:{61,70}] assign nodeOut_a_valid = nodeIn_a_valid ? nodeIn_a_valid : _nodeOut_a_valid_T_2; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_valid ? nodeIn_a_bits_opcode : 3'h5; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_valid ? nodeIn_a_bits_param : hint_param; // @[Edges.scala:551:17] assign nodeOut_a_bits_size = nodeIn_a_valid ? nodeIn_a_bits_size : 4'h6; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_valid ? _nodeOut_a_bits_source_WIRE : hint_source; // @[Mux.scala:30:73] assign nodeOut_a_bits_address = nodeIn_a_valid ? nodeIn_a_bits_address : hint_address; // @[Edges.scala:551:17] assign nodeOut_a_bits_mask = nodeIn_a_valid ? nodeIn_a_bits_mask : 8'hFF; // @[Misc.scala:222:10] assign nodeOut_a_bits_data = nodeIn_a_valid ? nodeIn_a_bits_data : 64'h0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_valid & nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] always @(posedge clock) begin // @[TLPrefetcher.scala:35:25] if (reset) // @[TLPrefetcher.scala:35:25] tracker <= 4'h0; // @[TLPrefetcher.scala:57:28] else // @[TLPrefetcher.scala:35:25] tracker <= _tracker_T_39; // @[TLPrefetcher.scala:57:28, :88:9] always @(posedge) TLMonitor_4 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AMPMPrefetcher prefetchers_0 ( // @[AMPM.scala:29:53] .clock (clock), .reset (reset), .io_snoop_valid (_prefetcher_io_snoop_valid_T_1), // @[TLPrefetcher.scala:49:50] .io_snoop_bits_write (snoop_bits_write), // @[TLPrefetcher.scala:41:23] .io_snoop_bits_address (snoop_bits_address), // @[TLPrefetcher.scala:41:23] .io_request_ready (_out_arb_io_in_0_ready), // @[TLPrefetcher.scala:54:27] .io_request_valid (_prefetchers_0_io_request_valid), .io_request_bits_write (_prefetchers_0_io_request_bits_write), .io_request_bits_address (_prefetchers_0_io_request_bits_address) ); // @[AMPM.scala:29:53] NullPrefetcher prefetchers_1 ( // @[AbstractPrefetcher.scala:51:53] .clock (clock), .reset (reset), .io_snoop_valid (_prefetcher_io_snoop_valid_T_3), // @[TLPrefetcher.scala:49:50] .io_snoop_bits_write (snoop_bits_write), // @[TLPrefetcher.scala:41:23] .io_snoop_bits_address (snoop_bits_address), // @[TLPrefetcher.scala:41:23] .io_request_ready (_out_arb_io_in_1_ready) // @[TLPrefetcher.scala:54:27] ); // @[AbstractPrefetcher.scala:51:53] MultiNextLinePrefetcher prefetchers_2 ( // @[NextLine.scala:106:53] .clock (clock), .reset (reset), .io_snoop_valid (_prefetcher_io_snoop_valid_T_5), // @[TLPrefetcher.scala:49:50] .io_snoop_bits_write (snoop_bits_write), // @[TLPrefetcher.scala:41:23] .io_snoop_bits_address (snoop_bits_address), // @[TLPrefetcher.scala:41:23] .io_request_ready (_out_arb_io_in_2_ready), // @[TLPrefetcher.scala:54:27] .io_request_valid (_prefetchers_2_io_request_valid), .io_request_bits_write (_prefetchers_2_io_request_bits_write), .io_request_bits_address (_prefetchers_2_io_request_bits_address) ); // @[NextLine.scala:106:53] RRArbiter_1 out_arb ( // @[TLPrefetcher.scala:54:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_io_in_0_ready), .io_in_0_valid (_prefetchers_0_io_request_valid), // @[AMPM.scala:29:53] .io_in_0_bits_write (_prefetchers_0_io_request_bits_write), // @[AMPM.scala:29:53] .io_in_0_bits_address (_prefetchers_0_io_request_bits_address), // @[AMPM.scala:29:53] .io_in_1_ready (_out_arb_io_in_1_ready), .io_in_2_ready (_out_arb_io_in_2_ready), .io_in_2_valid (_prefetchers_2_io_request_valid), // @[NextLine.scala:106:53] .io_in_2_bits_write (_prefetchers_2_io_request_bits_write), // @[NextLine.scala:106:53] .io_in_2_bits_address (_prefetchers_2_io_request_bits_address), // @[NextLine.scala:106:53] .io_out_ready (~legal | ~legal_address | ~nodeIn_a_valid & nodeOut_a_ready), // @[Parameters.scala:686:26] .io_out_valid (_out_arb_io_out_valid), .io_out_bits_write (_out_arb_io_out_bits_write), .io_out_bits_address (_out_arb_io_out_bits_address), .io_chosen (_out_arb_io_chosen) ); // @[TLPrefetcher.scala:54:27] assign auto_in_a_ready = auto_in_a_ready_0; // @[TLPrefetcher.scala:35:25] assign auto_in_b_valid = auto_in_b_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[TLPrefetcher.scala:35:25] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[TLPrefetcher.scala:35:25] assign auto_in_c_ready = auto_in_c_ready_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_valid = auto_in_d_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[TLPrefetcher.scala:35:25] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_valid = auto_out_a_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[TLPrefetcher.scala:35:25] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] assign auto_out_b_ready = auto_out_b_ready_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_valid = auto_out_c_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[TLPrefetcher.scala:35:25] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[TLPrefetcher.scala:35:25] assign auto_out_d_ready = auto_out_d_ready_0; // @[TLPrefetcher.scala:35:25] assign auto_out_e_valid = auto_out_e_valid_0; // @[TLPrefetcher.scala:35:25] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[TLPrefetcher.scala:35:25] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Plic.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.experimental._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.{Annotated, MuxT, property} import scala.math.min import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.SeqToAugmentedSeq class GatewayPLICIO extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) val complete = Input(Bool()) } class LevelGateway extends Module { val io = IO(new Bundle { val interrupt = Input(Bool()) val plic = new GatewayPLICIO }) val inFlight = RegInit(false.B) when (io.interrupt && io.plic.ready) { inFlight := true.B } when (io.plic.complete) { inFlight := false.B } io.plic.valid := io.interrupt && !inFlight } object PLICConsts { def maxDevices = 1023 def maxMaxHarts = 15872 def priorityBase = 0x0 def pendingBase = 0x1000 def enableBase = 0x2000 def hartBase = 0x200000 def claimOffset = 4 def priorityBytes = 4 def enableOffset(i: Int) = i * ((maxDevices+7)/8) def hartOffset(i: Int) = i * 0x1000 def enableBase(i: Int):Int = enableOffset(i) + enableBase def hartBase(i: Int):Int = hartOffset(i) + hartBase def size(maxHarts: Int): Int = { require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}") 1 << log2Ceil(hartBase(maxHarts)) } require(hartBase >= enableBase(maxMaxHarts)) } case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts) { require (maxPriorities >= 0) def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1) } case object PLICKey extends Field[Option[PLICParams]](None) case class PLICAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object PLICAttachKey extends Field(PLICAttachParams()) /** Platform-Level Interrupt Controller */ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // plic0 => max devices 1023 val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) { override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val extra = Map( "interrupt-controller" -> Nil, "riscv,ndev" -> Seq(ResourceInt(nDevices)), "riscv,max-priority" -> Seq(ResourceInt(nPriorities)), "#interrupt-cells" -> Seq(ResourceInt(1))) Description(name, mapping ++ extra) } } val node : TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes, undefZero = true, concurrency = 1) // limiting concurrency handles RAW hazards on claim registers val intnode: IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false, inputRequiresOutput = false) /* Negotiated sizes */ def nDevices: Int = intnode.edges.in.map(_.source.num).sum def minPriorities = min(params.maxPriorities, nDevices) def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1 def nHarts = intnode.edges.out.map(_.source.num).sum // Assign all the devices unique ranges lazy val sources = intnode.edges.in.map(_.source) lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten ResourceBinding { flatSources.foreach { s => s.resources.foreach { r => // +1 because interrupt 0 is reserved (s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) } } } } lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) val (io_devices, edgesIn) = intnode.in.unzip val (io_harts, _) = intnode.out.unzip // Compact the interrupt vector the same way val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten // This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence val harts = io_harts.flatten def getNInterrupts = interrupts.size println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):") flatSources.foreach { s => // +1 because 0 is reserved, +1-1 because the range is half-open println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}") } println("") require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}") require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}") require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}") require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}") // For now, use LevelGateways for all TL2 interrupts val gateways = interrupts.map { case i => val gateway = Module(new LevelGateway) gateway.io.interrupt := i gateway.io.plic } val prioBits = log2Ceil(nPriorities+1) val priority = if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W))) else WireDefault(VecInit.fill(nDevices max 1)(1.U)) val threshold = if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W))) else WireDefault(VecInit.fill(nHarts)(0.U)) val pending = RegInit(VecInit.fill(nDevices max 1){false.B}) /* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */ val firstEnable = nDevices min 7 val fullEnables = (nDevices - firstEnable) / 8 val tailEnable = nDevices - firstEnable - 8*fullEnables def enableRegs = (Reg(UInt(firstEnable.W)) +: Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++ (if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None) val enables = Seq.fill(nHarts) { enableRegs } val enableVec = VecInit(enables.map(x => Cat(x.reverse))) val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W)))) val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W))) val pendingUInt = Cat(pending.reverse) if(nDevices > 0) { for (hart <- 0 until nHarts) { val fanin = Module(new PLICFanIn(nDevices, prioBits)) fanin.io.prio := priority fanin.io.ip := enableVec(hart) & pendingUInt maxDevs(hart) := fanin.io.dev harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages) } } // Priority registers are 32-bit aligned so treat each as its own group. // Otherwise, the off-by-one nature of the priority registers gets confusing. require(PLICConsts.priorityBytes == 4, s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}") def priorityRegDesc(i: Int) = RegFieldDesc( name = s"priority_$i", desc = s"Acting priority of interrupt source $i", group = Some(s"priority_${i}"), groupDesc = Some(s"Acting priority of interrupt source ${i}"), reset = if (nPriorities > 0) None else Some(1)) def pendingRegDesc(i: Int) = RegFieldDesc( name = s"pending_$i", desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.", group = Some("pending"), groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."), volatile = true) def enableRegDesc(i: Int, j: Int, wide: Int) = { val low = if (j == 0) 1 else j*8 val high = low + wide - 1 RegFieldDesc( name = s"enables_${j}", desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.", group = Some(s"enables_${i}"), groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source.")) } def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, priorityRegDesc(i)) } else { RegField.r(prioBits, x, priorityRegDesc(i)) } val priorityRegFields = priority.zipWithIndex.map { case (p, i) => PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) -> Seq(priorityRegField(p, i+1)) } val pendingRegFields = Seq(PLICConsts.pendingBase -> (RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))})) val enableRegFields = enables.zipWithIndex.map { case (e, i) => PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) => RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) } // When a hart reads a claim/complete register, then the // device which is currently its highest priority is no longer pending. // This code exploits the fact that, practically, only one claim/complete // register can be read at a time. We check for this because if the address map // were to change, it may no longer be true. // Note: PLIC doesn't care which hart reads the register. val claimer = Wire(Vec(nHarts, Bool())) assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_) val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools) ((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) => g.ready := !p when (c || g.valid) { p := !c } } // When a hart writes a claim/complete register, then // the written device (as long as it is actually enabled for that // hart) is marked complete. // This code exploits the fact that, practically, only one claim/complete register // can be written at a time. We check for this because if the address map // were to change, it may no longer be true. // Note -- PLIC doesn't care which hart writes the register. val completer = Wire(Vec(nHarts, Bool())) assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot val completerDev = Wire(UInt(log2Up(nDevices + 1).W)) val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U) (gateways zip completedDevs.asBools.tail) foreach { case (g, c) => g.complete := c } def thresholdRegDesc(i: Int) = RegFieldDesc( name = s"threshold_$i", desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.", reset = if (nPriorities > 0) None else Some(1)) def thresholdRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, thresholdRegDesc(i)) } else { RegField.r(prioBits, x, thresholdRegDesc(i)) } val hartRegFields = Seq.tabulate(nHarts) { i => PLICConsts.hartBase(i) -> Seq( thresholdRegField(threshold(i), i), RegField(32-prioBits), RegField(32, RegReadFn { valid => claimer(i) := valid (true.B, maxDevs(i)) }, RegWriteFn { (valid, data) => assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), "completerDev should be consistent for all harts") completerDev := data.extract(log2Ceil(nDevices+1)-1, 0) completer(i) := valid && enableVec0(i)(completerDev) true.B }, Some(RegFieldDesc(s"claim_complete_$i", s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." + s"Writing the interrupt number back completes the interrupt.", reset = None, wrType = Some(RegFieldWrType.MODIFY), rdAction = Some(RegFieldRdAction.MODIFY), volatile = true)) ) ) } node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*) if (nDevices >= 2) { val claimed = claimer(0) && maxDevs(0) > 0.U val completed = completer(0) property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete") property.cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim") val ep = enables(0).asUInt & pending.asUInt val ep2 = RegNext(ep) val diff = ep & ~ep2 property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle") if (nPriorities > 0) ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)), "THRESHOLD", "interrupt pending but less than threshold") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc) } } class PLICFanIn(nDevices: Int, prioBits: Int) extends Module { val io = IO(new Bundle { val prio = Flipped(Vec(nDevices, UInt(prioBits.W))) val ip = Flipped(UInt(nDevices.W)) val dev = UInt(log2Ceil(nDevices+1).W) val max = UInt(prioBits.W) }) def findMax(x: Seq[UInt]): (UInt, UInt) = { if (x.length > 1) { val half = 1 << (log2Ceil(x.length) - 1) val left = findMax(x take half) val right = findMax(x drop half) MuxT(left._1 >= right._1, left, (right._1, half.U | right._2)) } else (x.head, 0.U) } val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) } val (maxPri, maxDev) = findMax(effectivePriority) io.max := maxPri // strips the always-constant high '1' bit io.dev := maxDev } /** Trait that will connect a PLIC to a subsystem */ trait CanHavePeripheryPLIC { this: BaseSubsystem => val (plicOpt, plicDomainOpt) = p(PLICKey).map { params => val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere) val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain") val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) } plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } } plicDomainWrapper { plic.intnode :=* ibus.toPLIC } (plic, plicDomainWrapper) }.unzip }

module TLPLIC( // @[Plic.scala:132:9] input clock, // @[Plic.scala:132:9] input reset, // @[Plic.scala:132:9] input auto_int_in_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_1, // @[LazyModuleImp.scala:107:25] input auto_int_in_2, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_0, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [22:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [22:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire [1:0] _fanin_1_io_dev; // @[Plic.scala:189:27] wire [1:0] _fanin_1_io_max; // @[Plic.scala:189:27] wire [1:0] _fanin_io_dev; // @[Plic.scala:189:27] wire [1:0] _fanin_io_max; // @[Plic.scala:189:27] wire _gateways_gateway_2_io_plic_valid; // @[Plic.scala:160:27] wire _gateways_gateway_1_io_plic_valid; // @[Plic.scala:160:27] wire _gateways_gateway_io_plic_valid; // @[Plic.scala:160:27] wire auto_int_in_0_0 = auto_int_in_0; // @[Plic.scala:132:9] wire auto_int_in_1_0 = auto_int_in_1; // @[Plic.scala:132:9] wire auto_int_in_2_0 = auto_int_in_2; // @[Plic.scala:132:9] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Plic.scala:132:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Plic.scala:132:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Plic.scala:132:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Plic.scala:132:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Plic.scala:132:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Plic.scala:132:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Plic.scala:132:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Plic.scala:132:9] wire _out_T_115 = reset; // @[Plic.scala:298:19] wire _out_T_151 = reset; // @[Plic.scala:298:19] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_denied = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_corrupt = 1'h0; // @[Plic.scala:132:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _pending_WIRE_0 = 1'h0; // @[Plic.scala:172:55] wire _pending_WIRE_1 = 1'h0; // @[Plic.scala:172:55] wire _pending_WIRE_2 = 1'h0; // @[Plic.scala:172:55] wire _out_T_21 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_22 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_63 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_2 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_171 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_172 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_24 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_72 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_80 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_92 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_96 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_100 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_130 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_25 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_73 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_81 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_93 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_97 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_101 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_131 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_24 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_72 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_80 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_92 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_96 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_100 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_130 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_25 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_73 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_81 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_93 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_97 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_101 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_131 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [31:0] _out_prepend_T_10 = 32'h0; // @[RegisterRouter.scala:87:24] wire [22:0] out_maskMatch = 23'h7BF9EE; // @[RegisterRouter.scala:87:24] wire intnodeIn_0 = auto_int_in_0_0; // @[Plic.scala:132:9] wire intnodeIn_1 = auto_int_in_1_0; // @[Plic.scala:132:9] wire intnodeIn_2 = auto_int_in_2_0; // @[Plic.scala:132:9] wire x1_intnodeOut_0; // @[MixedNode.scala:542:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Plic.scala:132:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Plic.scala:132:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Plic.scala:132:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Plic.scala:132:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Plic.scala:132:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Plic.scala:132:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Plic.scala:132:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Plic.scala:132:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_1_0_0; // @[Plic.scala:132:9] wire auto_int_out_0_0_0; // @[Plic.scala:132:9] wire auto_in_a_ready_0; // @[Plic.scala:132:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Plic.scala:132:9] wire [1:0] auto_in_d_bits_size_0; // @[Plic.scala:132:9] wire [11:0] auto_in_d_bits_source_0; // @[Plic.scala:132:9] wire [63:0] auto_in_d_bits_data_0; // @[Plic.scala:132:9] wire auto_in_d_valid_0; // @[Plic.scala:132:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Plic.scala:132:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Plic.scala:132:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Plic.scala:132:9] wire [11:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Plic.scala:132:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Plic.scala:132:9] wire _intnodeOut_0_T; // @[Plic.scala:193:60] assign auto_int_out_0_0_0 = intnodeOut_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_1; // @[Plic.scala:193:60] assign auto_int_out_1_0_0 = x1_intnodeOut_0; // @[Plic.scala:132:9] reg [1:0] priority_0; // @[Plic.scala:167:31] reg [1:0] priority_1; // @[Plic.scala:167:31] wire [1:0] _out_T_43 = priority_1; // @[RegisterRouter.scala:87:24] reg [1:0] priority_2; // @[Plic.scala:167:31] reg [1:0] threshold_0; // @[Plic.scala:170:31] wire [1:0] _out_T_137 = threshold_0; // @[RegisterRouter.scala:87:24] reg [1:0] threshold_1; // @[Plic.scala:170:31] wire [1:0] _out_T_101 = threshold_1; // @[RegisterRouter.scala:87:24] reg pending_0; // @[Plic.scala:172:26] reg pending_1; // @[Plic.scala:172:26] reg pending_2; // @[Plic.scala:172:26] reg [2:0] enables_0_0; // @[Plic.scala:178:26] wire [2:0] enableVec_0 = enables_0_0; // @[Plic.scala:178:26, :182:28] reg [2:0] enables_1_0; // @[Plic.scala:178:26] wire [2:0] enableVec_1 = enables_1_0; // @[Plic.scala:178:26, :182:28] wire [3:0] _enableVec0_T = {enableVec_0, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [3:0] enableVec0_0 = _enableVec0_T; // @[Plic.scala:183:{29,52}] wire [3:0] _enableVec0_T_1 = {enableVec_1, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [3:0] enableVec0_1 = _enableVec0_T_1; // @[Plic.scala:183:{29,52}] reg [1:0] maxDevs_0; // @[Plic.scala:185:22] reg [1:0] maxDevs_1; // @[Plic.scala:185:22] wire [1:0] _GEN = {pending_2, pending_1}; // @[Plic.scala:172:26, :186:26] wire [1:0] pendingUInt_hi; // @[Plic.scala:186:26] assign pendingUInt_hi = _GEN; // @[Plic.scala:186:26] wire [1:0] ep_hi; // @[Plic.scala:323:44] assign ep_hi = _GEN; // @[Plic.scala:186:26, :323:44] wire [2:0] pendingUInt = {pendingUInt_hi, pending_0}; // @[Plic.scala:172:26, :186:26] wire [2:0] _fanin_io_ip_T = enableVec_0 & pendingUInt; // @[Plic.scala:182:28, :186:26, :191:40] reg [1:0] intnodeOut_0_REG; // @[Plic.scala:193:45] assign _intnodeOut_0_T = intnodeOut_0_REG > threshold_0; // @[Plic.scala:170:31, :193:{45,60}] assign intnodeOut_0 = _intnodeOut_0_T; // @[Plic.scala:193:60] wire [2:0] _fanin_io_ip_T_1 = enableVec_1 & pendingUInt; // @[Plic.scala:182:28, :186:26, :191:40] reg [1:0] intnodeOut_0_REG_1; // @[Plic.scala:193:45] assign _intnodeOut_0_T_1 = intnodeOut_0_REG_1 > threshold_1; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_0 = _intnodeOut_0_T_1; // @[Plic.scala:193:60] wire out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_10; // @[RegisterRouter.scala:87:24] wire claimer_0; // @[Plic.scala:250:23] wire claimer_1; // @[Plic.scala:250:23] wire [1:0] _claiming_T = claimer_0 ? maxDevs_0 : 2'h0; // @[Plic.scala:185:22, :250:23, :252:49] wire [1:0] _claiming_T_1 = claimer_1 ? maxDevs_1 : 2'h0; // @[Plic.scala:185:22, :250:23, :252:49] wire [1:0] claiming = _claiming_T | _claiming_T_1; // @[Plic.scala:252:{49,92}] wire [1:0] claimedDevs_shiftAmount = claiming; // @[OneHot.scala:64:49] wire [3:0] _claimedDevs_T = 4'h1 << claimedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _claimedDevs_T_1 = _claimedDevs_T; // @[OneHot.scala:65:{12,27}] wire _claimedDevs_T_2 = _claimedDevs_T_1[0]; // @[OneHot.scala:65:27] wire claimedDevs_0 = _claimedDevs_T_2; // @[Plic.scala:253:{30,62}] wire _claimedDevs_T_3 = _claimedDevs_T_1[1]; // @[OneHot.scala:65:27] wire claimedDevs_1 = _claimedDevs_T_3; // @[Plic.scala:253:{30,62}] wire _claimedDevs_T_4 = _claimedDevs_T_1[2]; // @[OneHot.scala:65:27] wire claimedDevs_2 = _claimedDevs_T_4; // @[Plic.scala:253:{30,62}] wire _claimedDevs_T_5 = _claimedDevs_T_1[3]; // @[OneHot.scala:65:27] wire claimedDevs_3 = _claimedDevs_T_5; // @[Plic.scala:253:{30,62}] wire _gateway_io_plic_ready_T = ~pending_0; // @[Plic.scala:172:26, :256:18] wire _pending_0_T = ~claimedDevs_1; // @[Plic.scala:253:30, :257:34] wire _gateway_io_plic_ready_T_1 = ~pending_1; // @[Plic.scala:172:26, :256:18] wire _pending_1_T = ~claimedDevs_2; // @[Plic.scala:253:30, :257:34] wire _gateway_io_plic_ready_T_2 = ~pending_2; // @[Plic.scala:172:26, :256:18] wire _pending_2_T = ~claimedDevs_3; // @[Plic.scala:253:30, :257:34] wire _out_completer_0_T_2; // @[Plic.scala:301:35] wire _out_completer_1_T_2; // @[Plic.scala:301:35] wire completer_0; // @[Plic.scala:267:25] wire completer_1; // @[Plic.scala:267:25] wire [1:0] _out_completerDev_T_1; // @[package.scala:163:13] wire [1:0] completerDev; // @[Plic.scala:269:28] wire [1:0] completedDevs_shiftAmount = completerDev; // @[OneHot.scala:64:49] wire _completedDevs_T = completer_0 | completer_1; // @[Plic.scala:267:25, :270:48] wire [3:0] _completedDevs_T_1 = 4'h1 << completedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _completedDevs_T_2 = _completedDevs_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] completedDevs = _completedDevs_T ? _completedDevs_T_2 : 4'h0; // @[OneHot.scala:65:27] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [22:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [24:0] _in_bits_index_T = nodeIn_a_bits_address[27:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[22:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_q_io_deq_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_14; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [22:0] out_findex = out_front_bits_index & 23'h7BF9EE; // @[RegisterRouter.scala:87:24] wire [22:0] out_bindex = _out_back_front_q_io_deq_bits_index & 23'h7BF9EE; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_12; // @[RegisterRouter.scala:87:24] assign _out_T_12 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_13; // @[RegisterRouter.scala:87:24] assign _out_T_13 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_84; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_68; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_84; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_68; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_4 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_4 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_14 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_14 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_4 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_4 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_14 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_14 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_15 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_56 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_164 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_1 = out_frontMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_1 = out_frontMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_15 = out_frontMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_15 = out_frontMask[3:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_1 = out_backMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_1 = out_backMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_15 = out_backMask[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_15 = out_backMask[3:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_24 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_23 = _out_back_front_q_io_deq_bits_data[3:1]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_173 = _out_back_front_q_io_deq_bits_data[3:1]; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [3:0] out_prepend = {enables_1_0, 1'h0}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_32 = out_prepend; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_33 = _out_T_32; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_2 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_2 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_8 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_8 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_11 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_11 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_2 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_2 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_8 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_8 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_11 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_11 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_35 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_36 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_37 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_34 = _out_back_front_q_io_deq_bits_data[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_92 = _out_back_front_q_io_deq_bits_data[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_128 = _out_back_front_q_io_deq_bits_data[1:0]; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_44 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_3 = out_frontMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_3 = out_frontMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_16 = out_frontMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_16 = out_frontMask[33:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_3 = out_backMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_3 = out_backMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_16 = out_backMask[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_16 = out_backMask[33:32]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_46 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_47 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_48 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_45 = _out_back_front_q_io_deq_bits_data[33:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_184 = _out_back_front_q_io_deq_bits_data[33:32]; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_51 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_52 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1 = {30'h0, _out_T_44}; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_1 = {priority_2, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_54 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_55 = _out_T_54; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = _out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = _out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = _out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = _out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_57 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_58 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_59 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_60 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_61 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_62 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_5 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_5 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire _out_romask_T_5 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_5 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_68 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_69 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_70 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_71 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_2 = {pending_0, 1'h0}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_72 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_73 = _out_T_72; // @[RegisterRouter.scala:87:24] wire [1:0] _out_prepend_T_3 = _out_T_73; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_6 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_6 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire _out_romask_T_6 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_6 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_75 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = _out_back_front_q_io_deq_bits_data[2]; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_79 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_80 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [2:0] out_prepend_3 = {pending_1, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_81 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_82 = _out_T_81; // @[RegisterRouter.scala:87:24] wire [2:0] _out_prepend_T_4 = _out_T_82; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_7 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_7 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire _out_romask_T_7 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_7 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = _out_back_front_q_io_deq_bits_data[3]; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [3:0] out_prepend_4 = {pending_2, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_90 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [1:0] _out_prepend_T_5 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [29:0] _out_rimask_T_9 = out_frontMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_wimask_T_9 = out_frontMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_rimask_T_12 = out_frontMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_wimask_T_12 = out_frontMask[31:2]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [29:0] _out_romask_T_9 = out_backMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_womask_T_9 = out_backMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_romask_T_12 = out_backMask[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_womask_T_12 = out_backMask[31:2]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire [29:0] _out_T_103 = _out_back_front_q_io_deq_bits_data[31:2]; // @[RegisterRouter.scala:87:24] wire [29:0] _out_T_139 = _out_back_front_q_io_deq_bits_data[31:2]; // @[RegisterRouter.scala:87:24] wire _out_T_106 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [2:0] out_prepend_5 = {1'h0, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_110 = {29'h0, out_prepend_5}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_111 = _out_T_110; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_6 = _out_T_111; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_10 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_10 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_13 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_13 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_10 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_10 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_13 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_13 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] assign claimer_1 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire _out_T_119 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_112 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_148 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_113 = _out_T_112[1:0]; // @[package.scala:163:13] wire [1:0] _out_completerDev_T = _out_T_112[1:0]; // @[package.scala:163:13] wire _out_T_114 = completerDev == _out_T_113; // @[package.scala:163:13] wire _out_T_116 = ~_out_T_115; // @[Plic.scala:298:19] wire _out_T_117 = ~_out_T_114; // @[Plic.scala:298:{19,33}] wire [3:0] _GEN_2 = {2'h0, completerDev}; // @[Plic.scala:269:28, :301:51] wire [3:0] _out_completer_1_T = enableVec0_1 >> _GEN_2; // @[Plic.scala:183:29, :301:51] wire _out_completer_1_T_1 = _out_completer_1_T[0]; // @[Plic.scala:301:51] assign _out_completer_1_T_2 = out_f_woready_10 & _out_completer_1_T_1; // @[RegisterRouter.scala:87:24] assign completer_1 = _out_completer_1_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_122 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_123 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_124 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_125 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_6 = {maxDevs_1, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_126 = {30'h0, out_prepend_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_130 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_134 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_135 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_136 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24] wire [1:0] _out_prepend_T_7 = _out_T_138; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_141 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_145 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [2:0] out_prepend_7 = {1'h0, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_146 = {29'h0, out_prepend_7}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_8 = _out_T_147; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] assign claimer_0 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_156 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] wire _out_T_157 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_149 = _out_T_148[1:0]; // @[package.scala:163:13] assign _out_completerDev_T_1 = _out_T_148[1:0]; // @[package.scala:163:13] wire _out_T_150 = completerDev == _out_T_149; // @[package.scala:163:13] wire _out_T_152 = ~_out_T_151; // @[Plic.scala:298:19] wire _out_T_153 = ~_out_T_150; // @[Plic.scala:298:{19,33}]

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_145( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_401 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }

module TLXbar_mbus_i1_o2_a32d64s6k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [5:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [5:0] _addressC_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _addressC_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _requestBOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T = 6'h0; // @[Parameters.scala:52:29] wire [5:0] requestBOI_uncommonBits = 6'h0; // @[Parameters.scala:52:56] wire [5:0] _requestBOI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T_1 = 6'h0; // @[Parameters.scala:52:29] wire [5:0] requestBOI_uncommonBits_1 = 6'h0; // @[Parameters.scala:52:56] wire [5:0] _beatsBO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _beatsBO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _beatsBO_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _beatsCI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _portsBIO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _portsBIO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] portsBIO_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] _portsBIO_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _portsBIO_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] portsBIO_filtered_1_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] _portsCOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _portsCOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] portsCOI_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsCOI_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [27:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [5:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [5:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [5:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_5 = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [5:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [5:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [5:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address[27:0]; // @[Xbar.scala:216:19, :222:41] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [31:0] _requestAIO_T = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [5:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [5:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /** Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. */ class ClientMetadata extends Bundle { /** Actual state information stored in this bundle */ val state = UInt(ClientStates.width.W) /** Metadata equality */ def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /** Is the block's data present in this cache */ def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */ private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /** Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). */ private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd || param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /** Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). */ def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /** Does a secondary miss on the block require another Acquire message */ def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /** Metadata change on a returned Grant */ def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /** Determine what state to go to based on Probe param */ private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /** Translate cache control cmds into Probe param */ private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /** Factories for ClientMetadata, including on reset */ object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways * (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /** @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined || nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined || nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBits*rowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /** Bundle definitions for HellaCache interfaces */ trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /** Base classes for Diplomatic TL2 HellaCaches */ abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated */ case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /** Mix-ins for constructing tiles that have a HellaCache */ trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /** Metadata array used for all HellaCaches */ class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst || io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File ECC.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR abstract class Decoding { def uncorrected: UInt def corrected: UInt def correctable: Bool def uncorrectable: Bool // If true, correctable should be ignored def error = correctable || uncorrectable } abstract class Code { def canDetect: Boolean def canCorrect: Boolean def width(w0: Int): Int /** Takes the unencoded width and returns a list of indices indicating which * bits of the encoded value will be used for ecc */ def eccIndices(width: Int): Seq[Int] /** Encode x to a codeword suitable for decode. * If poison is true, the decoded value will report uncorrectable * error despite uncorrected == corrected == x. */ def encode(x: UInt, poison: Bool = false.B): UInt def decode(x: UInt): Decoding /** Copy the bits in x to the right bit positions in an encoded word, * so that x === decode(swizzle(x)).uncorrected; but don't generate * the other code bits, so decode(swizzle(x)).error might be true. * For codes for which this operation is not trivial, throw an * UnsupportedOperationException. */ def swizzle(x: UInt): UInt } class IdentityCode extends Code { def canDetect = false def canCorrect = false def width(w0: Int) = w0 def eccIndices(width: Int) = Seq.empty[Int] def encode(x: UInt, poison: Bool = false.B) = { require (poison.isLit && poison.litValue == 0, "IdentityCode can not be poisoned") x } def swizzle(x: UInt) = x def decode(y: UInt) = new Decoding { def uncorrected = y def corrected = y def correctable = false.B def uncorrectable = false.B } } class ParityCode extends Code { def canDetect = true def canCorrect = false def width(w0: Int) = w0+1 def eccIndices(w0: Int) = Seq(w0) def encode(x: UInt, poison: Bool = false.B) = Cat(x.xorR ^ poison, x) def swizzle(x: UInt) = Cat(false.B, x) def decode(y: UInt) = new Decoding { val uncorrected = y(y.getWidth-2,0) val corrected = uncorrected val correctable = false.B val uncorrectable = y.xorR } } class SECCode extends Code { def canDetect = true def canCorrect = true // SEC codes may or may not be poisonous depending on the length // If the code is perfect, every non-codeword is correctable def poisonous(n: Int) = !isPow2(n+1) def width(k: Int) = { val m = log2Floor(k) + 1 k + m + (if((1 << m) < m+k+1) 1 else 0) } def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def swizzle(x: UInt) = { val k = x.getWidth val n = width(k) Cat(0.U((n-k).W), x) } // An (n=16, k=11) Hamming code is naturally encoded as: // PPxPxxxPxxxxxxxP where P are parity bits and x are data // Indexes typically start at 1, because then the P are on powers of two // In systematic coding, you put all the data in the front: // xxxxxxxxxxxPPPPP // Indexes typically start at 0, because Computer Science // For sanity when reading SRAMs, you want systematic form. private def impl(n: Int, k: Int) = { require (n >= 3 && k >= 1 && !isPow2(n)) val hamm2sys = IndexedSeq.tabulate(n+1) { i => if (i == 0) { n /* undefined */ } else if (isPow2(i)) { k + log2Ceil(i) } else { i - 1 - log2Ceil(i) } } val sys2hamm = hamm2sys.zipWithIndex.sortBy(_._1).map(_._2).toIndexedSeq def syndrome(j: Int) = { val bit = 1 << j ("b" + Seq.tabulate(n) { i => if ((sys2hamm(i) & bit) != 0) "1" else "0" }.reverse.mkString).U } (hamm2sys, sys2hamm, syndrome _) } def encode(x: UInt, poison: Bool = false.B) = { val k = x.getWidth val n = width(k) val (_, _, syndrome) = impl(n, k) require ((poison.isLit && poison.litValue == 0) || poisonous(n), s"SEC code of length ${n} cannot be poisoned") /* By setting the entire syndrome on poison, the corrected bit falls off the end of the code */ val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j)(k-1, 0) & x).xorR ^ poison }.asUInt Cat(syndromeUInt, x) } def decode(y: UInt) = new Decoding { val n = y.getWidth val k = n - log2Ceil(n) val (_, sys2hamm, syndrome) = impl(n, k) val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j) & y).xorR }.asUInt val hammBadBitOH = UIntToOH(syndromeUInt, n+1) val sysBadBitOH = VecInit.tabulate(k) { i => hammBadBitOH(sys2hamm(i)) }.asUInt val uncorrected = y(k-1, 0) val corrected = uncorrected ^ sysBadBitOH val correctable = syndromeUInt.orR val uncorrectable = if (poisonous(n)) { syndromeUInt > n.U } else { false.B } } } class SECDEDCode extends Code { def canDetect = true def canCorrect = true private val sec = new SECCode private val par = new ParityCode def width(k: Int) = sec.width(k)+1 def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def encode(x: UInt, poison: Bool = false.B) = { // toggling two bits ensures the error is uncorrectable // to ensure corrected == uncorrected, we pick one redundant // bit from SEC (the highest); correcting it does not affect // corrected == uncorrected. the second toggled bit is the // parity bit, which also does not appear in the decoding val toggle_lo = Cat(poison.asUInt, poison.asUInt) val toggle_hi = toggle_lo << (sec.width(x.getWidth)-1) par.encode(sec.encode(x)) ^ toggle_hi } def swizzle(x: UInt) = par.swizzle(sec.swizzle(x)) def decode(x: UInt) = new Decoding { val secdec = sec.decode(x(x.getWidth-2,0)) val pardec = par.decode(x) val uncorrected = secdec.uncorrected val corrected = secdec.corrected val correctable = pardec.uncorrectable val uncorrectable = !pardec.uncorrectable && secdec.correctable } } object ErrGen { // generate a 1-bit error with approximate probability 2^-f def apply(width: Int, f: Int): UInt = { require(width > 0 && f >= 0 && log2Up(width) + f <= 16) UIntToOH(LFSR(16)(log2Up(width)+f-1,0))(width-1,0) } def apply(x: UInt, f: Int): UInt = x ^ apply(x.getWidth, f) } trait CanHaveErrors extends Bundle { val correctable: Option[ValidIO[UInt]] val uncorrectable: Option[ValidIO[UInt]] } case class ECCParams( bytes: Int = 1, code: Code = new IdentityCode, notifyErrors: Boolean = false, ) object Code { def fromString(s: Option[String]): Code = fromString(s.getOrElse("none")) def fromString(s: String): Code = s.toLowerCase match { case "none" => new IdentityCode case "identity" => new IdentityCode case "parity" => new ParityCode case "sec" => new SECCode case "secded" => new SECDEDCode case _ => throw new IllegalArgumentException("Unknown ECC type") } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class ECCTest(k: Int, timeout: Int = 500000) extends UnitTest(timeout) { val code = new SECDEDCode val n = code.width(k) // Brute force the decode space val test = RegInit(0.U((n+1).W)) val last = test(n) test := test + !last io.finished := RegNext(last, false.B) // Confirm the decoding matches the encoding val decoded = code.decode(test(n-1, 0)) val recoded = code.encode(decoded.corrected) val distance = PopCount(recoded ^ test) // Count the cases val correct = RegInit(0.U(n.W)) val correctable = RegInit(0.U(n.W)) val uncorrectable = RegInit(0.U(n.W)) when (!last) { when (decoded.uncorrectable) { assert (distance >= 2.U) // uncorrectable uncorrectable := uncorrectable + 1.U } .elsewhen (decoded.correctable) { assert (distance(0)) // correctable => odd bit errors correctable := correctable + 1.U } .otherwise { assert (distance === 0.U) // correct assert (decoded.uncorrected === decoded.corrected) correct := correct + 1.U } } // Expected number of each case val nCodes = BigInt(1) << n val nCorrect = BigInt(1) << k val nCorrectable = nCodes / 2 val nUncorrectable = nCodes - nCorrectable - nCorrect when (last) { assert (correct === nCorrect.U) assert (correctable === nCorrectable.U) assert (uncorrectable === nUncorrectable.U) } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /** =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} */ class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /** request address from CPU. */ val vaddr = UInt(vaddrBitsExtended.W) /** don't lookup TLB, bypass vaddr as paddr */ val passthrough = Bool() /** granularity */ val size = UInt(log2Ceil(lgMaxSize + 1).W) /** memory command. */ val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /** virtualization mode */ val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /** physical address */ val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /** page fault exception */ val pf = new TLBExceptions /** guest page fault exception */ val gf = new TLBExceptions /** access exception */ val ae = new TLBExceptions /** misaligned access exception */ val ma = new TLBExceptions /** if this address is cacheable */ val cacheable = Bool() /** if caches must allocate this address */ val must_alloc = Bool() /** if this address is prefetchable for caches*/ val prefetchable = Bool() /** size/cmd of request that generated this response*/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /** pte.u user */ val u = Bool() /** pte.g global */ val g = Bool() /** access exception. * D$ -> PTW -> TLB AE * Alignment failed. */ val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** supervisor write */ val sw = Bool() /** supervisor execute */ val sx = Bool() /** supervisor read */ val sr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor excute */ val hx = Bool() /** hypervisor read */ val hr = Bool() /** prot_w */ val pw = Bool() /** prot_x */ val px = Bool() /** prot_r */ val pr = Bool() /** PutPartial */ val ppp = Bool() /** AMO logical */ val pal = Bool() /** AMO arithmetic */ val paa = Bool() /** get/put effects */ val eff = Bool() /** cacheable */ val c = Bool() /** fragmented_superpage support */ val fragmented_superpage = Bool() } /** basic cell for TLB data */ class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 || !superpage) require(!superpageOnly || superpage) val level = UInt(log2Ceil(pgLevels).W) /** use vpn as tag */ val tag_vpn = UInt(vpnBits.W) /** tag in vitualization mode */ val tag_v = Bool() /** entry data */ val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /** valid bit */ val valid = Vec(nSectors, Bool()) /** returns all entry data in this entry */ def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /** returns the index of sector */ private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /** returns the entry data matched with this vpn*/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /** returns whether a sector hits */ def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /** returns whether tag matches vpn */ def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /** returns hit signal */ def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) * pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore || (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData */ def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels * pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits*(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) | data.ppn)(supervisorVPNBits - j*pgLevelBits - 1, supervisorVPNBits - (j + 1)*pgLevelBits)) } res } else { data.ppn } } /** does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data */ def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits * (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries */ case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /** =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * |vaddr | * |ppn/vpn | pgIndex | * | | | * | |nSets |nSector | |}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB*2+ITLB}}} * @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. */ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /** request from Core */ val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /** response to Core */ val resp = Output(new TLBResp(lgMaxSize)) /** SFence Input */ val sfence = Flipped(Valid(new SFenceReq)) /** IO to PTW */ val ptw = new TLBPTWIO /** suppress a TLB refill, one cycle after a miss */ val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /** index for sectored_Entry */ val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /** TLB Entry */ val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /** Superpage Entry */ val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /** Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. */ val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /** privilege mode */ val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /** VS-stage translation enable */ val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /** G-stage translation enable */ val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /** Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) */ val vm_enabled = (stage1_en || stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /** refill signal */ val do_refill = usingVM.B && io.ptw.resp.valid /** sfence invalidate refill */ val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) || io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction || !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en || r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s || sum, entries.map(_.u).asUInt, 0.U) | Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) | entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr | Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt | Mux(mxr, entries.map(_.sx).asUInt, 0.U))) | stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) | stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) | stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) | stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt | stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt | stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array | final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array | c_array val paa_array_if_cached = paa_array | (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array | (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels * pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U || signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM || (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write || io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad || usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) | Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array | ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array | ~pw_array, 0.U) | Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) | Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) | Mux(cmd_amo_logical, ~pal_array, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array, 0.U) | Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array | gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) | Fill(all_entries.size, !vstage1_en) hit_mask | ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) || (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) || (pf_st_array & hits).orR io.resp.pf.inst := bad_va || (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) || (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) || (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa || (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint).B io.resp.miss := do_refill || vsatp_mode_mismatch || tlb_miss || multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv || hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits || reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement */ def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r || w || x || c || a || l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /** PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss */ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /** PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info */ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /** ptw access exception */ val ae_ptw = Bool() /** final access exception */ val ae_final = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** hypervisor read */ val hr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor execute */ val hx = Bool() /** PTE to refill L1TLB * * source: L2TLB */ val pte = new PTE /** pte pglevel */ val level = UInt(log2Ceil(pgLevels).W) /** fragmented_superpage support */ val fragmented_superpage = Bool() /** homogeneous for both pma and pmp */ val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /** IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) */ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /** PTW performance statistics */ class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /** Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core */ class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /** enable clock generated by ptw */ val clock_enabled = Output(Bool()) } /** PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format */ class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** global mapping */ val g = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() /** valid bit */ val v = Bool() /** return true if find a pointer to next level page table */ def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /** return true if find a leaf PTE */ def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a /** user read */ def ur(dummy: Int = 0) = sr() && u /** user write*/ def uw(dummy: Int = 0) = sw() && u /** user execute */ def ux(dummy: Int = 0) = sx() && u /** supervisor read */ def sr(dummy: Int = 0) = leaf() && r /** supervisor write */ def sw(dummy: Int = 0) = leaf() && w && d /** supervisor execute */ def sx(dummy: Int = 0) = leaf() && x /** full permission: writable and executable in user mode */ def isFullPerm(dummy: Int = 0) = uw() && ux() } /** L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format */ class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() } /** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation */ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /** to n TLB */ val requestor = Flipped(Vec(n, new TLBPTWIO)) /** to HellaCache */ val mem = new HellaCacheIO /** to Core * * contains CSRs info and performance statistics */ val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /** Arbiter to arbite request from n TLB */ val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM || !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /** current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} */ val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /** tlb request */ val r_req = Reg(new PTWReq) /** current selected way in arbitor */ val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /** pte for 2-stage translation */ val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /** 2-stage translation both enable */ val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r || tmp.w || tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /** address send to mem for enquerry */ val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr */ val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i))) } /** PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation */ def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid | UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /** the valid vec for the selected set(including n ways) */ val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) | mask g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req || state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req || state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 || do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf || (pf && stage2) resp_hr := !stage2 || (!pf && !gf && pte.ur()) resp_hw := !stage2 || (!pf && !gf && pte.uw()) resp_hx := !stage2 || (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn */ private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /** use hgatp and vpn to construct a new ppn */ private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range */ private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File DCache.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.amba.AMBAProt import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing} import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions} import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck} import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits trait InlineInstance { self: chisel3.experimental.BaseModule => chisel3.experimental.annotate( new chisel3.experimental.ChiselAnnotation { def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } ) } class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) with CanHaveErrors { val correctable = (cacheParams.tagCode.canCorrect || cacheParams.dataCode.canCorrect).option(Valid(UInt(paddrBits.W))) val uncorrectable = (cacheParams.tagCode.canDetect || cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W))) val bus = Valid(UInt(paddrBits.W)) } class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val addr = UInt(untagBits.W) val write = Bool() val wdata = UInt((encBits * rowBytes / eccBytes).W) val wordMask = UInt((rowBytes / subWordBytes).W) val eccMask = UInt((wordBytes / eccBytes).W) val way_en = UInt(nWays.W) } class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Valid(new DCacheDataReq)) val resp = Output(Vec(nWays, UInt((req.bits.wdata.getWidth).W))) }) require(rowBits % subWordBits == 0, "rowBits must be a multiple of subWordBits") val eccMask = if (eccBits == subWordBits) Seq(true.B) else io.req.bits.eccMask.asBools val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i))) val wWords = io.req.bits.wdata.grouped(encBits * (subWordBits / eccBits)) val addr = io.req.bits.addr >> rowOffBits val data_arrays = Seq.tabulate(rowBits / subWordBits) { i => DescribedSRAM( name = s"${tileParams.baseName}_dcache_data_arrays_${i}", desc = "DCache Data Array", size = nSets * cacheBlockBytes / rowBytes, data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W)) ) } val rdata = for ((array , i) <- data_arrays.zipWithIndex) yield { val valid = io.req.valid && ((data_arrays.size == 1).B || io.req.bits.wordMask(i)) when (valid && io.req.bits.write) { val wMaskSlice = (0 until wMask.size).filter(j => i % (wordBits/subWordBits) == (j % (wordBytes/eccBytes)) / (subWordBytes/eccBytes)).map(wMask(_)) val wData = wWords(i).grouped(encBits) array.write(addr, VecInit((0 until nWays).flatMap(i => wData)), wMaskSlice) } val data = array.read(addr, valid && !io.req.bits.write) data.grouped(subWordBits / eccBits).map(_.asUInt).toSeq } (io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt } } class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val write = Bool() val addr = UInt(vaddrBitsExtended.W) val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W) } class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) { override lazy val module = new DCacheModule(this) } class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) { val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2))) val s1_resp = Output(new TLBResp(coreDataBytes.log2)) val s2_kill = Input(Bool()) } class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val tECC = cacheParams.tagCode val dECC = cacheParams.dataCode require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits") require(eccBytes == 1 || !dECC.isInstanceOf[IdentityCode]) require(cacheParams.silentDrop || cacheParams.acquireBeforeRelease, "!silentDrop requires acquireBeforeRelease") val usingRMW = eccBytes > 1 || usingAtomicsInCache val mmioOffset = outer.firstMMIO edge.manager.requireFifo(TLFIFOFixer.allVolatile) // TileLink pipelining MMIO requests val clock_en_reg = Reg(Bool()) io.cpu.clock_enabled := clock_en_reg val gated_clock = if (!cacheParams.clockGate) clock else ClockGate(clock, clock_en_reg, "dcache_clock_gate") class DCacheModuleImpl { // entering gated-clock domain val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages))) val pma_checker = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)) with InlineInstance) // tags val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays) /** Metadata Arbiter: * 0: Tag update on reset * 1: Tag update on ECC error * 2: Tag update on hit * 3: Tag update on refill * 4: Tag update on release * 5: Tag update on flush * 6: Tag update on probe * 7: Tag update on CPU request */ val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance) val tag_array = DescribedSRAM( name = s"${tileParams.baseName}_dcache_tag_array", desc = "DCache Tag Array", size = nSets, data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data)) ) // data val data = Module(new DCacheDataArray) /** Data Arbiter * 0: data from pending store buffer * 1: data from TL-D refill * 2: release to TL-A * 3: hit path to CPU */ val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance) dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default data.io.req.bits <> dataArb.io.out.bits data.io.req.valid := dataArb.io.out.valid dataArb.io.out.ready := true.B metaArb.io.out.ready := clock_en_reg val tl_out_a = Wire(chiselTypeOf(tl_out.a)) tl_out.a <> { val a_queue_depth = outer.crossing match { case RationalCrossing(_) => // TODO make this depend on the actual ratio? if (cacheParams.separateUncachedResp) (maxUncachedInFlight + 1) / 2 else 2 min maxUncachedInFlight-1 case SynchronousCrossing(BufferParams.none) => 1 // Need some buffering to guarantee livelock freedom case SynchronousCrossing(_) => 0 // Adequate buffering within the crossing case _: AsynchronousCrossing => 0 // Adequate buffering within the crossing case _: CreditedCrossing => 0 // Adequate buffering within the crossing } Queue(tl_out_a, a_queue_depth, flow = true) } val (tl_out_c, release_queue_empty) = if (cacheParams.acquireBeforeRelease) { val q = Module(new Queue(chiselTypeOf(tl_out.c.bits), cacheDataBeats, flow = true)) tl_out.c <> q.io.deq (q.io.enq, q.io.count === 0.U) } else { (tl_out.c, true.B) } val s1_valid = RegNext(io.cpu.req.fire, false.B) val s1_probe = RegNext(tl_out.b.fire, false.B) val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :( val s1_nack = WireDefault(false.B) val s1_valid_masked = s1_valid && !io.cpu.s1_kill val s1_valid_not_nacked = s1_valid && !s1_nack val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B) val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B) val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write val s0_req = WireInit(io.cpu.req.bits) s0_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0)) s0_req.idx.foreach(_ := Cat(metaArb.io.out.bits.idx, s0_req.addr(blockOffBits-1, 0))) when (!metaArb.io.in(7).ready) { s0_req.phys := true.B } val s1_req = RegEnable(s0_req, s0_clk_en) val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0)) val s0_tlb_req = WireInit(io.tlb_port.req.bits) when (!io.tlb_port.req.fire) { s0_tlb_req.passthrough := s0_req.phys s0_tlb_req.vaddr := s0_req.addr s0_tlb_req.size := s0_req.size s0_tlb_req.cmd := s0_req.cmd s0_tlb_req.prv := s0_req.dprv s0_tlb_req.v := s0_req.dv } val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en || io.tlb_port.req.valid) val s1_read = isRead(s1_req.cmd) val s1_write = isWrite(s1_req.cmd) val s1_readwrite = s1_read || s1_write val s1_sfence = s1_req.cmd === M_SFENCE || s1_req.cmd === M_HFENCEV || s1_req.cmd === M_HFENCEG val s1_flush_line = s1_req.cmd === M_FLUSH_ALL && s1_req.size(0) val s1_flush_valid = Reg(Bool()) val s1_waw_hazard = Wire(Bool()) val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: s_dummy :: s_voluntary_release :: Nil = Enum(10) val supports_flush = outer.flushOnFenceI || coreParams.haveCFlush val flushed = RegInit(true.B) val flushing = RegInit(false.B) val flushing_req = Reg(chiselTypeOf(s1_req)) val cached_grant_wait = RegInit(false.B) val resetting = RegInit(false.B) val flushCounter = RegInit((nSets * (nWays-1)).U(log2Ceil(nSets * nWays).W)) val release_ack_wait = RegInit(false.B) val release_ack_addr = Reg(UInt(paddrBits.W)) val release_state = RegInit(s_ready) val refill_way = Reg(UInt()) val any_pstore_valid = Wire(Bool()) val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty) val releaseWay = Wire(UInt()) io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack // I/O MSHRs val uncachedInFlight = RegInit(VecInit(Seq.fill(maxUncachedInFlight)(false.B))) val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq)) val uncachedResp = WireInit(new HellaCacheReq, DontCare) // hit initiation path val s0_read = isRead(io.cpu.req.bits.cmd) dataArb.io.in(3).valid := io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits) dataArb.io.in(3).bits := dataArb.io.in(1).bits dataArb.io.in(3).bits.write := false.B dataArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.idx.getOrElse(io.cpu.req.bits.addr) >> tagLSB, io.cpu.req.bits.addr(tagLSB-1, 0)) dataArb.io.in(3).bits.wordMask := { val mask = (subWordBytes.log2 until rowOffBits).foldLeft(1.U) { case (in, i) => val upper_mask = Mux((i >= wordBytes.log2).B || io.cpu.req.bits.size <= i.U, 0.U, ((BigInt(1) << (1 << (i - subWordBytes.log2)))-1).U) val upper = Mux(io.cpu.req.bits.addr(i), in, 0.U) | upper_mask val lower = Mux(io.cpu.req.bits.addr(i), 0.U, in) upper ## lower } Fill(subWordBytes / eccBytes, mask) } dataArb.io.in(3).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(3).bits.way_en := ~0.U(nWays.W) when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false.B } val s1_did_read = RegEnable(dataArb.io.in(3).ready && (io.cpu.req.valid && needsRead(io.cpu.req.bits)), s0_clk_en) val s1_read_mask = RegEnable(dataArb.io.in(3).bits.wordMask, s0_clk_en) metaArb.io.in(7).valid := io.cpu.req.valid metaArb.io.in(7).bits.write := false.B metaArb.io.in(7).bits.idx := dataArb.io.in(3).bits.addr(idxMSB, idxLSB) metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr metaArb.io.in(7).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(7).bits.data := metaArb.io.in(4).bits.data when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false.B } // address translation val s1_cmd_uses_tlb = s1_readwrite || s1_flush_line || s1_req.cmd === M_WOK io.ptw <> tlb.io.ptw tlb.io.kill := io.cpu.s2_kill || s2_tlb_req_valid && io.tlb_port.s2_kill tlb.io.req.valid := s1_tlb_req_valid || s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb tlb.io.req.bits := s1_tlb_req when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B } when (!s1_tlb_req_valid && s1_valid && s1_cmd_uses_tlb && tlb.io.resp.miss) { s1_nack := true.B } tlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence tlb.io.sfence.bits.rs1 := s1_req.size(0) tlb.io.sfence.bits.rs2 := s1_req.size(1) tlb.io.sfence.bits.asid := io.cpu.s1_data.data tlb.io.sfence.bits.addr := s1_req.addr tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG io.tlb_port.req.ready := clock_en_reg io.tlb_port.s1_resp := tlb.io.resp when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B } pma_checker.io <> DontCare pma_checker.io.req.bits.passthrough := true.B pma_checker.io.req.bits.vaddr := s1_req.addr pma_checker.io.req.bits.size := s1_req.size pma_checker.io.req.bits.cmd := s1_req.cmd pma_checker.io.req.bits.prv := s1_req.dprv pma_checker.io.req.bits.v := s1_req.dv val s1_paddr = Cat(Mux(s1_tlb_req_valid, s1_req.addr(paddrBits-1, pgIdxBits), tlb.io.resp.paddr >> pgIdxBits), s1_req.addr(pgIdxBits-1, 0)) val s1_victim_way = Wire(UInt()) val (s1_hit_way, s1_hit_state, s1_meta) = if (usingDataScratchpad) { val baseAddr = p(LookupByHartId)(_.dcache.flatMap(_.scratch.map(_.U)), io_hartid.get) | io_mmio_address_prefix.get val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + (nSets * cacheBlockBytes).U val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) val dummyMeta = L1Metadata(0.U, ClientMetadata.onReset) (inScratchpad, hitState, Seq(tECC.encode(dummyMeta.asUInt))) } else { val metaReq = metaArb.io.out val metaIdx = metaReq.bits.idx when (metaReq.valid && metaReq.bits.write) { val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.asBools tag_array.write(metaIdx, VecInit(Seq.fill(nWays)(metaReq.bits.data)), wmask) } val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata)) val s1_tag = s1_paddr >> tagLSB val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt val s1_meta_hit_state = ( s1_meta_uncorrected.map(r => Mux(r.tag === s1_tag && !s1_flush_valid, r.coh.asUInt, 0.U)) .reduce (_|_)).asTypeOf(chiselTypeOf(ClientMetadata.onReset)) (s1_meta_hit_way, s1_meta_hit_state, s1_meta) } val s1_data_way = WireDefault(if (nWays == 1) 1.U else Mux(inWriteback, releaseWay, s1_hit_way)) val tl_d_data_encoded = Wire(chiselTypeOf(encodeData(tl_out.d.bits.data, false.B))) val s1_all_data_ways = VecInit(data.io.resp ++ (!cacheParams.separateUncachedResp).option(tl_d_data_encoded)) val s1_mask_xwr = new StoreGen(s1_req.size, s1_req.addr, 0.U, wordBytes).mask val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, s1_mask_xwr) // for partial writes, s1_data.mask must be a subset of s1_mask_xwr assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR) val s2_valid = RegNext(s1_valid_masked && !s1_sfence, init=false.B) val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR val s2_probe = RegNext(s1_probe, init=false.B) val releaseInFlight = s1_probe || s2_probe || release_state =/= s_ready val s2_not_nacked_in_s1 = RegNext(!s1_nack) val s2_valid_not_nacked_in_s1 = s2_valid && s2_not_nacked_in_s1 val s2_valid_masked = s2_valid_no_xcpt && s2_not_nacked_in_s1 val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill val s2_req = Reg(chiselTypeOf(io.cpu.req.bits)) val s2_cmd_flush_all = s2_req.cmd === M_FLUSH_ALL && !s2_req.size(0) val s2_cmd_flush_line = s2_req.cmd === M_FLUSH_ALL && s2_req.size(0) val s2_tlb_xcpt = Reg(chiselTypeOf(tlb.io.resp)) val s2_pma = Reg(chiselTypeOf(tlb.io.resp)) val s2_uncached_resp_addr = Reg(chiselTypeOf(s2_req.addr)) // should be DCE'd in synthesis when (s1_valid_not_nacked || s1_flush_valid) { s2_req := s1_req s2_req.addr := s1_paddr s2_tlb_xcpt := tlb.io.resp s2_pma := Mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp) } val s2_vaddr = Cat(RegEnable(s1_vaddr, s1_valid_not_nacked || s1_flush_valid) >> tagLSB, s2_req.addr(tagLSB-1, 0)) val s2_read = isRead(s2_req.cmd) val s2_write = isWrite(s2_req.cmd) val s2_readwrite = s2_read || s2_write val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) val s1_meta_decoded = s1_meta.map(tECC.decode(_)) val s1_meta_clk_en = s1_valid_not_nacked || s1_flush_valid || s1_probe val s2_meta_correctable_errors = s1_meta_decoded.map(m => RegEnable(m.correctable, s1_meta_clk_en)).asUInt val s2_meta_uncorrectable_errors = s1_meta_decoded.map(m => RegEnable(m.uncorrectable, s1_meta_clk_en)).asUInt val s2_meta_error_uncorrectable = s2_meta_uncorrectable_errors.orR val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_meta_clk_en).asTypeOf(new L1Metadata)) val s2_meta_error = (s2_meta_uncorrectable_errors | s2_meta_correctable_errors).orR val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_data = { val wordsPerRow = rowBits / subWordBits val en = s1_valid || inWriteback || io.cpu.replay_next val word_en = Mux(inWriteback, Fill(wordsPerRow, 1.U), Mux(s1_did_read, s1_read_mask, 0.U)) val s1_way_words = s1_all_data_ways.map(_.grouped(dECC.width(eccBits) * (subWordBits / eccBits))) if (cacheParams.pipelineWayMux) { val s1_word_en = Mux(io.cpu.replay_next, 0.U, word_en) (for (i <- 0 until wordsPerRow) yield { val s2_way_en = RegEnable(Mux(s1_word_en(i), s1_data_way, 0.U), en) val s2_way_words = (0 until nWays).map(j => RegEnable(s1_way_words(j)(i), en && word_en(i))) (0 until nWays).map(j => Mux(s2_way_en(j), s2_way_words(j), 0.U)).reduce(_|_) }).asUInt } else { val s1_word_en = Mux(!io.cpu.replay_next, word_en, UIntToOH(uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)), wordsPerRow)) (for (i <- 0 until wordsPerRow) yield { RegEnable(Mux1H(Mux(s1_word_en(i), s1_data_way, 0.U), s1_way_words.map(_(i))), en) }).asUInt } } val s2_probe_way = RegEnable(s1_hit_way, s1_probe) val s2_probe_state = RegEnable(s1_hit_state, s1_probe) val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked) val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked || s1_flush_valid) val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked) val s2_store_merge = Wire(Bool()) val s2_hit_valid = s2_hit_state.isValid() val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val s2_data_error = s2_data_decoded.map(_.error).orR val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit val s2_no_alloc_hazard = if (!usingVM || pgIdxBits >= untagBits) false.B else { // make sure that any in-flight non-allocating accesses are ordered before // any allocating accesses. this can only happen if aliasing is possible. val any_no_alloc_in_flight = Reg(Bool()) when (!uncachedInFlight.asUInt.orR) { any_no_alloc_in_flight := false.B } when (s2_valid && s2_req.no_alloc) { any_no_alloc_in_flight := true.B } val s1_need_check = any_no_alloc_in_flight || s2_valid && s2_req.no_alloc val concerns = (uncachedInFlight zip uncachedReqs) :+ (s2_valid && s2_req.no_alloc, s2_req) val s1_uncached_hits = concerns.map { c => val concern_wmask = new StoreGen(c._2.size, c._2.addr, 0.U, wordBytes).mask val addr_match = (c._2.addr ^ s1_paddr)(pgIdxBits+pgLevelBits-1, wordBytes.log2) === 0.U val mask_match = (concern_wmask & s1_mask_xwr).orR || c._2.cmd === M_PWR || s1_req.cmd === M_PWR val cmd_match = isWrite(c._2.cmd) || isWrite(s1_req.cmd) c._1 && s1_need_check && cmd_match && addr_match && mask_match } val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked) s2_uncached_hits.orR } val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard || s2_store_merge) val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit val s2_uncached = !s2_pma.cacheable || s2_req.no_alloc && !s2_pma.must_alloc && !s2_hit_valid val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR dontTouch(s2_valid_cached_miss) val s2_want_victimize = (!usingDataScratchpad).B && (s2_valid_cached_miss || s2_valid_flush_line || s2_valid_data_error || s2_flush_valid) val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill val s2_victimize = s2_want_victimize && !s2_cannot_victimize val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked || s1_flush_valid)) val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way) val s2_victim_tag = Mux(s2_valid_data_error || s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag) val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh) val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) dontTouch(s2_victim_dirty) val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready val s2_dont_nack_misc = s2_valid_masked && !s2_meta_error && (supports_flush.B && s2_cmd_flush_all && flushed && !flushing || supports_flush.B && s2_cmd_flush_line && !s2_hit || s2_req.cmd === M_WOK) io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_misc && !s2_valid_hit when (io.cpu.s2_nack || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true.B } // tag updates on ECC errors val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected) metaArb.io.in(1).valid := s2_meta_error && (s2_valid_masked || s2_flush_valid_pre_tag_ecc || s2_probe) metaArb.io.in(1).bits.write := true.B metaArb.io.in(1).bits.way_en := s2_meta_uncorrectable_errors | Mux(s2_meta_error_uncorrectable, 0.U, PriorityEncoderOH(s2_meta_correctable_errors)) metaArb.io.in(1).bits.idx := Mux(s2_probe, probeIdx(probe_bits), s2_vaddr(idxMSB, idxLSB)) metaArb.io.in(1).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(1).bits.idx << blockOffBits) metaArb.io.in(1).bits.data := tECC.encode { val new_meta = WireDefault(s2_first_meta_corrected) when (s2_meta_error_uncorrectable) { new_meta.coh := ClientMetadata.onReset } new_meta.asUInt } // tag updates on hit metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta metaArb.io.in(2).bits.write := !io.cpu.s2_kill metaArb.io.in(2).bits.way_en := s2_victim_or_hit_way metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(2).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(2).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_new_hit_state).asUInt) // load reservations and TL error reporting val s2_lr = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XLR val s2_sc = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XSC val lrscCount = RegInit(0.U) val lrscValid = lrscCount > lrscBackoff.U val lrscBackingOff = lrscCount > 0.U && !lrscValid val lrscAddr = Reg(UInt()) val lrscAddrMatch = lrscAddr === (s2_req.addr >> blockOffBits) val s2_sc_fail = s2_sc && !(lrscValid && lrscAddrMatch) when ((s2_valid_hit && s2_lr && !cached_grant_wait || s2_valid_cached_miss) && !io.cpu.s2_kill) { lrscCount := Mux(s2_hit, (lrscCycles - 1).U, 0.U) lrscAddr := s2_req.addr >> blockOffBits } when (lrscCount > 0.U) { lrscCount := lrscCount - 1.U } when (s2_valid_not_killed && lrscValid) { lrscCount := lrscBackoff.U } when (s1_probe) { lrscCount := 0.U } // don't perform data correction if it might clobber a recent store val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid || s2_valid) && usingDataScratchpad.B // pending store buffer val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write) val pstore1_addr = RegEnable(s1_vaddr, s1_valid_not_nacked && s1_write) val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write) val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write) val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write) val pstore1_storegen_data = WireDefault(pstore1_data) val pstore1_rmw = usingRMW.B && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write) val pstore1_merge_likely = s2_valid_not_nacked_in_s1 && s2_write && s2_store_merge val pstore1_merge = s2_store_valid && s2_store_merge val pstore2_valid = RegInit(false.B) val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard) val pstore_drain_on_miss = releaseInFlight || RegNext(io.cpu.s2_nack) val pstore1_held = RegInit(false.B) val pstore1_valid_likely = s2_valid && s2_write || pstore1_held def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill || pstore1_held val pstore1_valid = s2_store_valid || pstore1_held any_pstore_valid := pstore1_held || pstore2_valid val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) || pstore1_rmw) assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid) ccover(pstore_drain_structural, "STORE_STRUCTURAL_HAZARD", "D$ read-modify-write structural hazard") ccover(pstore1_valid && pstore_drain_on_miss, "STORE_DRAIN_ON_MISS", "D$ store buffer drain on miss") ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") def should_pstore_drain(truly: Bool) = { val s2_kill = truly && io.cpu.s2_kill !pstore1_merge_likely && (usingRMW.B && pstore_drain_structural || (((pstore1_valid_not_rmw(s2_kill) && !pstore1_rmw) || pstore2_valid) && (pstore_drain_opportunistic || pstore_drain_on_miss))) } val pstore_drain = should_pstore_drain(true.B) pstore1_held := (s2_store_valid && !s2_store_merge || pstore1_held) && pstore2_valid && !pstore_drain val advance_pstore1 = (pstore1_valid || s2_valid_correct) && (pstore2_valid === pstore_drain) pstore2_valid := pstore2_valid && !pstore_drain || advance_pstore1 val pstore2_addr = RegEnable(Mux(s2_correct, s2_vaddr, pstore1_addr), advance_pstore1) val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1) val pstore2_storegen_data = { for (i <- 0 until wordBytes) yield RegEnable(pstore1_storegen_data(8*(i+1)-1, 8*i), advance_pstore1 || pstore1_merge && pstore1_mask(i)) }.asUInt val pstore2_storegen_mask = { val mask = Reg(UInt(wordBytes.W)) when (advance_pstore1 || pstore1_merge) { val mergedMask = pstore1_mask | Mux(pstore1_merge, mask, 0.U) mask := ~Mux(s2_correct, 0.U, ~mergedMask) } mask } s2_store_merge := (if (eccBytes == 1) false.B else { ccover(pstore1_merge, "STORE_MERGED", "D$ store merged") // only merge stores to ECC granules that are already stored-to, to avoid // WAW hazards val wordMatch = (eccMask(pstore2_storegen_mask) | ~eccMask(pstore1_mask)).andR val idxMatch = s2_vaddr(untagBits-1, log2Ceil(wordBytes)) === pstore2_addr(untagBits-1, log2Ceil(wordBytes)) val tagMatch = (s2_hit_way & pstore2_way).orR pstore2_valid && wordMatch && idxMatch && tagMatch }) dataArb.io.in(0).valid := should_pstore_drain(false.B) dataArb.io.in(0).bits.write := pstore_drain dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr) dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way) dataArb.io.in(0).bits.wdata := encodeData(Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data)), false.B) dataArb.io.in(0).bits.wordMask := { val eccMask = dataArb.io.in(0).bits.eccMask.asBools.grouped(subWordBytes/eccBytes).map(_.orR).toSeq.asUInt val wordMask = UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1, wordBytes.log2)) FillInterleaved(wordBytes/subWordBytes, wordMask) & Fill(rowBytes/wordBytes, eccMask) } dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)) // store->load RAW hazard detection def s1Depends(addr: UInt, mask: UInt) = addr(idxMSB, wordOffBits) === s1_vaddr(idxMSB, wordOffBits) && Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask_xwr)).orR, (mask & s1_mask_xwr).orR) val s1_hazard = (pstore1_valid_likely && s1Depends(pstore1_addr, pstore1_mask)) || (pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask)) val s1_raw_hazard = s1_read && s1_hazard s1_waw_hazard := (if (eccBytes == 1) false.B else { ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") s1_write && (s1_hazard || needsRead(s1_req) && !s1_did_read) }) when (s1_valid && s1_raw_hazard) { s1_nack := true.B } // performance hints to processor io.cpu.s2_nack_cause_raw := RegNext(s1_raw_hazard) || !(!s2_waw_hazard || s2_store_merge) // Prepare a TileLink request message that initiates a transaction val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR val acquire_address = (s2_req.addr >> idxLSB) << idxLSB val access_address = s2_req.addr val a_size = s2_req.size val a_data = Fill(beatWords, pstore1_data) val a_mask = pstore1_mask << (access_address.extract(beatBytes.log2-1, wordBytes.log2) << 3) val get = edge.Get(a_source, access_address, a_size)._2 val put = edge.Put(a_source, access_address, a_size, a_data)._2 val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array( M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached)) WireDefault(new TLBundleA(edge.bundle), DontCare) } tl_out_a.valid := !io.cpu.s2_kill && (s2_valid_uncached_pending || (s2_valid_cached_miss && !(release_ack_wait && (s2_req.addr ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U) && (cacheParams.acquireBeforeRelease.B && !release_ack_wait && release_queue_empty || !s2_victim_dirty))) tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param), Mux(!s2_write, get, Mux(s2_req.cmd === M_PWR, putpartial, Mux(!s2_read, put, atomics)))) // Drive APROT Bits tl_out_a.bits.user.lift(AMBAProt).foreach { x => val user_bit_cacheable = s2_pma.cacheable x.privileged := s2_req.dprv === PRV.M.U || user_bit_cacheable // if the address is cacheable, enable outer caches x.bufferable := user_bit_cacheable x.modifiable := user_bit_cacheable x.readalloc := user_bit_cacheable x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := false.B x.secure := true.B } // Set pending bits for outstanding TileLink transaction val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset when (tl_out_a.fire) { when (s2_uncached) { (a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) => when (s) { f := true.B r := s2_req r.cmd := Mux(s2_write, Mux(s2_req.cmd === M_PWR, M_PWR, M_XWR), M_XRD) } } }.otherwise { cached_grant_wait := true.B refill_way := s2_victim_or_hit_way } } // grant val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) val (d_opc, grantIsUncached, grantIsUncachedData) = { val uncachedGrantOpcodesSansData = Seq(AccessAck, HintAck) val uncachedGrantOpcodesWithData = Seq(AccessAckData) val uncachedGrantOpcodes = uncachedGrantOpcodesWithData ++ uncachedGrantOpcodesSansData val whole_opc = tl_out.d.bits.opcode if (usingDataScratchpad) { assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes)) // the only valid TL-D messages are uncached, so we can do some pruning val opc = whole_opc(uncachedGrantOpcodes.map(_.getWidth).max - 1, 0) val data = DecodeLogic(opc, uncachedGrantOpcodesWithData, uncachedGrantOpcodesSansData) (opc, true.B, data) } else { (whole_opc, whole_opc.isOneOf(uncachedGrantOpcodes), whole_opc.isOneOf(uncachedGrantOpcodesWithData)) } } tl_d_data_encoded := encodeData(tl_out.d.bits.data, tl_out.d.bits.corrupt && !io.ptw.customCSRs.suppressCorruptOnGrantData && !grantIsUncached) val grantIsCached = d_opc.isOneOf(Grant, GrantData) val grantIsVoluntary = d_opc === ReleaseAck // Clears a different pending bit val grantIsRefill = d_opc === GrantData // Writes the data array val grantInProgress = RegInit(false.B) val blockProbeAfterGrantCount = RegInit(0.U) when (blockProbeAfterGrantCount > 0.U) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1.U } val canAcceptCachedGrant = !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release) tl_out.d.ready := Mux(grantIsCached, (!d_first || tl_out.e.ready) && canAcceptCachedGrant, true.B) val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs) when (tl_out.d.fire) { when (grantIsCached) { grantInProgress := true.B assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") when(d_last) { cached_grant_wait := false.B grantInProgress := false.B blockProbeAfterGrantCount := (blockProbeAfterGrantCycles - 1).U replacer.miss } } .elsewhen (grantIsUncached) { (uncachedRespIdxOH.asBools zip uncachedInFlight) foreach { case (s, f) => when (s && d_last) { assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle! f := false.B } } when (grantIsUncachedData) { if (!cacheParams.separateUncachedResp) { if (!cacheParams.pipelineWayMux) s1_data_way := 1.U << nWays s2_req.cmd := M_XRD s2_req.size := uncachedResp.size s2_req.signed := uncachedResp.signed s2_req.tag := uncachedResp.tag s2_req.addr := { require(rowOffBits >= beatOffBits) val dontCareBits = s1_paddr >> rowOffBits << rowOffBits dontCareBits | uncachedResp.addr(beatOffBits-1, 0) } s2_uncached_resp_addr := uncachedResp.addr } } } .elsewhen (grantIsVoluntary) { assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle! release_ack_wait := false.B } } // Finish TileLink transaction by issuing a GrantAck tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant tl_out.e.bits := edge.GrantAck(tl_out.d.bits) assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached)) // data refill // note this ready-valid signaling ignores E-channel backpressure, which // benignly means the data RAM might occasionally be redundantly written dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.e.valid := false.B tl_out.d.ready := false.B } if (!usingDataScratchpad) { dataArb.io.in(1).bits.write := true.B dataArb.io.in(1).bits.addr := (s2_vaddr >> idxLSB) << idxLSB | d_address_inc dataArb.io.in(1).bits.way_en := refill_way dataArb.io.in(1).bits.wdata := tl_d_data_encoded dataArb.io.in(1).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(1).bits.eccMask := ~0.U((wordBytes / eccBytes).W) } else { dataArb.io.in(1).bits := dataArb.io.in(0).bits } // tag updates on refill // ignore backpressure from metaArb, which can only be caused by tag ECC // errors on hit-under-miss. failing to write the new tag will leave the // line invalid, so we'll simply request the line again later. metaArb.io.in(3).valid := grantIsCached && d_done && !tl_out.d.bits.denied metaArb.io.in(3).bits.write := true.B metaArb.io.in(3).bits.way_en := refill_way metaArb.io.in(3).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(3).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param)).asUInt) if (!cacheParams.separateUncachedResp) { // don't accept uncached grants if there's a structural hazard on s2_data... val blockUncachedGrant = Reg(Bool()) blockUncachedGrant := dataArb.io.out.valid when (grantIsUncachedData && (blockUncachedGrant || s1_valid)) { tl_out.d.ready := false.B // ...but insert bubble to guarantee grant's eventual forward progress when (tl_out.d.valid) { io.cpu.req.ready := false.B dataArb.io.in(1).valid := true.B dataArb.io.in(1).bits.write := false.B blockUncachedGrant := !dataArb.io.in(1).ready } } } ccover(tl_out.d.valid && !tl_out.d.ready, "BLOCK_D", "D$ D-channel blocked") // Handle an incoming TileLink Probe message val block_probe_for_core_progress = blockProbeAfterGrantCount > 0.U || lrscValid val block_probe_for_pending_release_ack = release_ack_wait && (tl_out.b.bits.address ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U val block_probe_for_ordering = releaseInFlight || block_probe_for_pending_release_ack || grantInProgress metaArb.io.in(6).valid := tl_out.b.valid && (!block_probe_for_core_progress || lrscBackingOff) tl_out.b.ready := metaArb.io.in(6).ready && !(block_probe_for_core_progress || block_probe_for_ordering || s1_valid || s2_valid) metaArb.io.in(6).bits.write := false.B metaArb.io.in(6).bits.idx := probeIdx(tl_out.b.bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, tl_out.b.bits.address) metaArb.io.in(6).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(6).bits.data := metaArb.io.in(4).bits.data // replacement policy s1_victim_way := (if (replacer.perSet && nWays > 1) { val repl_array = Mem(nSets, UInt(replacer.nBits.W)) val s1_repl_idx = s1_req.addr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_idx = s2_vaddr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_state = Reg(UInt(replacer.nBits.W)) val s2_new_repl_state = replacer.get_next_state(s2_repl_state, OHToUInt(s2_hit_way)) val s2_repl_wen = s2_valid_masked && s2_hit_way.orR && s2_repl_state =/= s2_new_repl_state val s1_repl_state = Mux(s2_repl_wen && s2_repl_idx === s1_repl_idx, s2_new_repl_state, repl_array(s1_repl_idx)) when (s1_valid_not_nacked) { s2_repl_state := s1_repl_state } val waddr = Mux(resetting, flushCounter(idxBits-1, 0), s2_repl_idx) val wdata = Mux(resetting, 0.U, s2_new_repl_state) val wen = resetting || s2_repl_wen when (wen) { repl_array(waddr) := wdata } replacer.get_replace_way(s1_repl_state) } else { replacer.way }) // release val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c) val releaseRejected = Wire(Bool()) val s1_release_data_valid = RegNext(dataArb.io.in(2).fire) val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected) releaseRejected := s2_release_data_valid && !tl_out_c.fire val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid)) val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN) val cleanReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param) val dirtyReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param, data = 0.U) tl_out_c.valid := (s2_release_data_valid || (!cacheParams.silentDrop.B && release_state === s_voluntary_release)) && !(c_first && release_ack_wait) tl_out_c.bits := nackResponseMessage val newCoh = WireDefault(probeNewCoh) releaseWay := s2_probe_way if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line || s2_flush_valid || io.cpu.s2_nack) val discard_line = s2_valid_flush_line && s2_req.size(1) || s2_flush_valid && flushing_req.size(1) release_state := Mux(s2_victim_dirty && !discard_line, s_voluntary_writeback, Mux(!cacheParams.silentDrop.B && !release_ack_wait && release_queue_empty && s2_victim_state.isValid() && (s2_valid_flush_line || s2_flush_valid || s2_readwrite && !s2_hit_valid), s_voluntary_release, s_voluntary_write_meta)) probe_bits := addressToProbe(s2_vaddr, Cat(s2_victim_tag, s2_req.addr(tagLSB-1, idxLSB)) << idxLSB) } when (s2_probe) { val probeNack = WireDefault(true.B) when (s2_meta_error) { release_state := s_probe_retry }.elsewhen (s2_prb_ack_data) { release_state := s_probe_rep_dirty }.elsewhen (s2_probe_state.isValid()) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean) }.otherwise { tl_out_c.valid := true.B probeNack := !releaseDone release_state := Mux(releaseDone, s_ready, s_probe_rep_miss) } when (probeNack) { s1_nack := true.B } } when (release_state === s_probe_retry) { metaArb.io.in(6).valid := true.B metaArb.io.in(6).bits.idx := probeIdx(probe_bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address) when (metaArb.io.in(6).ready) { release_state := s_ready s1_probe := true.B } } when (release_state === s_probe_rep_miss) { tl_out_c.valid := true.B when (releaseDone) { release_state := s_ready } } when (release_state === s_probe_rep_clean) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state === s_probe_rep_dirty) { tl_out_c.bits := dirtyReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)) { when (release_state === s_voluntary_release) { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param)._2 }.otherwise { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param, data = 0.U)._2 } newCoh := voluntaryNewCoh releaseWay := s2_victim_or_hit_way when (releaseDone) { release_state := s_voluntary_write_meta } when (tl_out_c.fire && c_first) { release_ack_wait := true.B release_ack_addr := probe_bits.address } } tl_out_c.bits.source := probe_bits.source tl_out_c.bits.address := probe_bits.address tl_out_c.bits.data := s2_data_corrected tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable } tl_out_c.bits.user.lift(AMBAProt).foreach { x => x.fetch := false.B x.secure := true.B x.privileged := true.B x.bufferable := true.B x.modifiable := true.B x.readalloc := true.B x.writealloc := true.B } dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles.U dataArb.io.in(2).bits := dataArb.io.in(1).bits dataArb.io.in(2).bits.write := false.B dataArb.io.in(2).bits.addr := (probeIdx(probe_bits) << blockOffBits) | (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits) dataArb.io.in(2).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(2).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(2).bits.way_en := ~0.U(nWays.W) metaArb.io.in(4).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta) metaArb.io.in(4).bits.write := true.B metaArb.io.in(4).bits.way_en := releaseWay metaArb.io.in(4).bits.idx := probeIdx(probe_bits) metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0)) metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt) when (metaArb.io.in(4).fire) { release_state := s_ready } // cached response (io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll io.cpu.resp.bits.has_data := s2_read io.cpu.resp.bits.replay := false.B io.cpu.s2_uncached := s2_uncached && !s2_hit io.cpu.s2_paddr := s2_req.addr io.cpu.s2_gpa := s2_tlb_xcpt.gpa io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte // report whether there are any outstanding accesses. disregard any // slave-port accesses, since they don't affect local memory ordering. val s1_isSlavePortAccess = s1_req.no_xcpt val s2_isSlavePortAccess = s2_req.no_xcpt io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess || s2_valid && !s2_isSlavePortAccess || cached_grant_wait || uncachedInFlight.asUInt.orR) io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) || uncachedInFlight.asUInt.orR val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt)) if (usingDataScratchpad) { assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC))) } else { ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked") } // uncached response val s1_uncached_data_word = { val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val words = tl_out.d.bits.data.grouped(wordBits) words(word_idx) } val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next) val doUncachedResp = RegNext(io.cpu.replay_next) io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc || doUncachedResp) && !s2_data_error io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B when (doUncachedResp) { assert(!s2_valid_hit) io.cpu.resp.bits.replay := true.B io.cpu.resp.bits.addr := s2_uncached_resp_addr } io.cpu.uncached_resp.map { resp => resp.valid := tl_out.d.valid && grantIsUncachedData resp.bits.tag := uncachedResp.tag resp.bits.size := uncachedResp.size resp.bits.signed := uncachedResp.signed resp.bits.data := new LoadGen(uncachedResp.size, uncachedResp.signed, uncachedResp.addr, s1_uncached_data_word, false.B, wordBytes).data resp.bits.data_raw := s1_uncached_data_word when (grantIsUncachedData && !resp.ready) { tl_out.d.ready := false.B } } // load data subword mux/sign extension val s2_data_word = (0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)).reduce(_|_) val s2_data_word_corrected = (0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)).reduce(_|_) val s2_data_word_possibly_uncached = Mux(cacheParams.pipelineWayMux.B && doUncachedResp, s2_uncached_data_word, 0.U) | s2_data_word val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word_possibly_uncached, s2_sc, wordBytes) io.cpu.resp.bits.data := loadgen.data | s2_sc_fail io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_raw := s2_data_word io.cpu.resp.bits.store_data := pstore1_data // AMOs if (usingRMW) { val amoalus = (0 until coreDataBits / xLen).map { i => val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := pstore1_mask >> (i * xBytes) amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR) amoalu.io.lhs := s2_data_word >> (i * xLen) amoalu.io.rhs := pstore1_data >> (i * xLen) amoalu } pstore1_storegen_data := (if (!usingDataScratchpad) amoalus.map(_.io.out).asUInt else { val mask = FillInterleaved(8, Mux(s2_correct, 0.U, pstore1_mask)) amoalus.map(_.io.out_unmasked).asUInt & mask | s2_data_word_corrected & ~mask }) } else if (!usingAtomics) { assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation") } if (coreParams.useVector) { edge.manager.managers.foreach { m => // Statically ensure that no-allocate accesses are permitted. // We could consider turning some of these into dynamic PMA checks. require(!m.supportsAcquireB || m.supportsGet, "With a vector unit, cacheable memory must support Get") require(!m.supportsAcquireT || m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial") } } // flushes if (!usingDataScratchpad) when (RegNext(reset.asBool)) { resetting := true.B } val flushCounterNext = flushCounter +& 1.U val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays.U val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0) ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush") ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush") s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait metaArb.io.in(5).valid := flushing && !flushed metaArb.io.in(5).bits.write := false.B metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0) metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits) metaArb.io.in(5).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. if (supports_flush) { when (s2_valid_masked && s2_cmd_flush_all) { when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) { flushing := true.B flushing_req := s2_req } } when (tl_out_a.fire && !s2_uncached) { flushed := false.B } when (flushing) { s1_victim_way := flushCounter >> log2Up(nSets) when (s2_flush_valid) { flushCounter := flushCounterNext when (flushDone) { flushed := true.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } when (flushed && release_state === s_ready && !release_ack_wait) { flushing := false.B } } } metaArb.io.in(0).valid := resetting metaArb.io.in(0).bits := metaArb.io.in(5).bits metaArb.io.in(0).bits.write := true.B metaArb.io.in(0).bits.way_en := ~0.U(nWays.W) metaArb.io.in(0).bits.data := tECC.encode(L1Metadata(0.U, ClientMetadata.onReset).asUInt) when (resetting) { flushCounter := flushCounterNext when (flushDone) { resetting := false.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } // gate the clock clock_en_reg := !cacheParams.clockGate.B || io.ptw.customCSRs.disableDCacheClockGate || io.cpu.keep_clock_enabled || metaArb.io.out.valid || // subsumes resetting || flushing s1_probe || s2_probe || s1_valid || s2_valid || io.tlb_port.req.valid || s1_tlb_req_valid || s2_tlb_req_valid || pstore1_held || pstore2_valid || release_state =/= s_ready || release_ack_wait || !release_queue_empty || !tlb.io.req.ready || cached_grant_wait || uncachedInFlight.asUInt.orR || lrscCount > 0.U || blockProbeAfterGrantCount > 0.U // performance events io.cpu.perf.acquire := edge.done(tl_out_a) io.cpu.perf.release := edge.done(tl_out_c) io.cpu.perf.grant := tl_out.d.valid && d_last io.cpu.perf.tlbMiss := io.ptw.req.fire io.cpu.perf.storeBufferEmptyAfterLoad := !( (s1_valid && s1_write) || ((s2_valid && s2_write && !s2_waw_hazard) || pstore1_held) || pstore2_valid) io.cpu.perf.storeBufferEmptyAfterStore := !( (s1_valid && s1_write) || (s2_valid && s2_write && pstore1_rmw) || ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) && pstore2_valid)) io.cpu.perf.canAcceptStoreThenLoad := !( ((s2_valid && s2_write && pstore1_rmw) && (s1_valid && s1_write && !s1_waw_hazard)) || (pstore2_valid && pstore1_valid_likely && (s1_valid && s1_write))) io.cpu.perf.canAcceptStoreThenRMW := io.cpu.perf.canAcceptStoreThenLoad && !pstore2_valid io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) || pstore2_valid)) io.cpu.perf.blocked := { // stop reporting blocked just before unblocking to avoid overly conservative stalling val beatsBeforeEnd = outer.crossing match { case SynchronousCrossing(_) => 2 case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2 case _: AsynchronousCrossing => 1 // likewise case _: CreditedCrossing => 1 // likewise } val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else { val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W)) when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U } refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U } cached_grant_wait && !near_end_of_refill } // report errors val (data_error, data_error_uncorrectable, data_error_addr) = if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else { (RegNext(tl_out_c.fire && inWriteback && s2_data_error), RegNext(s2_data_error_uncorrectable), probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register } { val error_addr = Mux(metaArb.io.in(1).valid, Cat(s2_first_meta_corrected.tag, metaArb.io.in(1).bits.addr(tagLSB-1, idxLSB)), data_error_addr >> idxLSB) << idxLSB io.errors.uncorrectable.foreach { u => u.valid := metaArb.io.in(1).valid && s2_meta_error_uncorrectable || data_error && data_error_uncorrectable u.bits := error_addr } io.errors.correctable.foreach { c => c.valid := metaArb.io.in(1).valid || data_error c.bits := error_addr io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } } } io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied || tl_out.d.bits.corrupt) io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U) ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached") } if (usingDataScratchpad) { val data_error_cover = Seq( property.CoverBoolean(!data_error, Seq("no_data_error")), property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) property.cover(new property.CrossProperty( Seq(data_error_cover, request_source), Seq(), "MemorySystem;;Scratchpad Memory Bit Flip Cross Covers")) } else { val data_error_type = Seq( property.CoverBoolean(!s2_valid_data_error, Seq("no_data_error")), property.CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error"))) val data_error_dirty = Seq( property.CoverBoolean(!s2_victim_dirty, Seq("data_clean")), property.CoverBoolean(s2_victim_dirty, Seq("data_dirty"))) val request_source = if (supports_flush) { Seq( property.CoverBoolean(!flushing, Seq("access")), property.CoverBoolean(flushing, Seq("during_flush"))) } else { Seq(property.CoverBoolean(true.B, Seq("never_flush"))) } val tag_error_cover = Seq( property.CoverBoolean( !s2_meta_error, Seq("no_tag_error")), property.CoverBoolean( s2_meta_error && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")), property.CoverBoolean( s2_meta_error && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error"))) property.cover(new property.CrossProperty( Seq(data_error_type, data_error_dirty, request_source, tag_error_cover), Seq(), "MemorySystem;;Cache Memory Bit Flip Cross Covers")) } } // leaving gated-clock domain val dcacheImpl = withClock (gated_clock) { new DCacheModuleImpl } def encodeData(x: UInt, poison: Bool) = x.grouped(eccBits).map(dECC.encode(_, if (dECC.canDetect) poison else false.B)).asUInt def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_)) def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask)) def likelyNeedsRead(req: HellaCacheReq) = { val res = !req.cmd.isOneOf(M_XWR, M_PFW) || req.size < log2Ceil(eccBytes).U assert(!needsRead(req) || res) res } def needsRead(req: HellaCacheReq) = isRead(req.cmd) || (isWrite(req.cmd) && (req.cmd === M_PWR || req.size < log2Ceil(eccBytes).U)) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc) def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (!usingDataScratchpad) ccover(cond, label, desc) require(!usingVM || tagLSB <= pgIdxBits, s"D$$ set size must not exceed ${1<<(pgIdxBits-10)} KiB; got ${(nSets * cacheBlockBytes)>>10} KiB") def tagLSB: Int = untagBits def probeIdx(b: TLBundleB): UInt = b.address(idxMSB, idxLSB) def addressToProbe(vaddr: UInt, paddr: UInt): TLBundleB = { val res = Wire(new TLBundleB(edge.bundle)) res :#= DontCare res.address := paddr res.source := (mmioOffset - 1).U res } def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = { if (!edge.manager.anySupportAcquireB) WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))) else edge.AcquireBlock(0.U, paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes.U, param)._2 } } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize*8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) | Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and || logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out | ~wmask & io.lhs io.out_unmasked := out }

module DCache( // @[DCache.scala:101:7] input clock, // @[DCache.scala:101:7] input reset, // @[DCache.scala:101:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output io_cpu_req_ready, // @[HellaCache.scala:243:14] input io_cpu_req_valid, // @[HellaCache.scala:243:14] input [39:0] io_cpu_req_bits_addr, // @[HellaCache.scala:243:14] input [7:0] io_cpu_req_bits_tag, // @[HellaCache.scala:243:14] input [4:0] io_cpu_req_bits_cmd, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_size, // @[HellaCache.scala:243:14] input io_cpu_req_bits_signed, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_dprv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_dv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_phys, // @[HellaCache.scala:243:14] input io_cpu_req_bits_no_resp, // @[HellaCache.scala:243:14] input io_cpu_s1_kill, // @[HellaCache.scala:243:14] input [63:0] io_cpu_s1_data_data, // @[HellaCache.scala:243:14] input [7:0] io_cpu_s1_data_mask, // @[HellaCache.scala:243:14] output io_cpu_s2_nack, // @[HellaCache.scala:243:14] output io_cpu_s2_nack_cause_raw, // @[HellaCache.scala:243:14] output io_cpu_s2_uncached, // @[HellaCache.scala:243:14] output [31:0] io_cpu_s2_paddr, // @[HellaCache.scala:243:14] output io_cpu_resp_valid, // @[HellaCache.scala:243:14] output [39:0] io_cpu_resp_bits_addr, // @[HellaCache.scala:243:14] output [7:0] io_cpu_resp_bits_tag, // @[HellaCache.scala:243:14] output [4:0] io_cpu_resp_bits_cmd, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_size, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_signed, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_dprv, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_dv, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data, // @[HellaCache.scala:243:14] output [7:0] io_cpu_resp_bits_mask, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_replay, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_has_data, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_word_bypass, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_raw, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_store_data, // @[HellaCache.scala:243:14] output io_cpu_replay_next, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_st, // @[HellaCache.scala:243:14] output [39:0] io_cpu_s2_gpa, // @[HellaCache.scala:243:14] output io_cpu_ordered, // @[HellaCache.scala:243:14] output io_cpu_store_pending, // @[HellaCache.scala:243:14] output io_cpu_perf_acquire, // @[HellaCache.scala:243:14] output io_cpu_perf_release, // @[HellaCache.scala:243:14] output io_cpu_perf_grant, // @[HellaCache.scala:243:14] output io_cpu_perf_tlbMiss, // @[HellaCache.scala:243:14] output io_cpu_perf_blocked, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenRMW, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptLoadThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterStore, // @[HellaCache.scala:243:14] input io_cpu_keep_clock_enabled, // @[HellaCache.scala:243:14] input io_ptw_req_ready, // @[HellaCache.scala:243:14] output io_ptw_req_valid, // @[HellaCache.scala:243:14] output [26:0] io_ptw_req_bits_bits_addr, // @[HellaCache.scala:243:14] output io_ptw_req_bits_bits_need_gpa, // @[HellaCache.scala:243:14] input io_ptw_resp_valid, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_ptw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_final, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hr, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hx, // @[HellaCache.scala:243:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[HellaCache.scala:243:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_d, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_a, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_g, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_u, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_x, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_w, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_r, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_v, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_level, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_homogeneous, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_valid, // @[HellaCache.scala:243:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_is_pte, // @[HellaCache.scala:243:14] input [3:0] io_ptw_ptbr_mode, // @[HellaCache.scala:243:14] input [43:0] io_ptw_ptbr_ppn, // @[HellaCache.scala:243:14] input io_ptw_status_debug, // @[HellaCache.scala:243:14] input io_ptw_status_cease, // @[HellaCache.scala:243:14] input io_ptw_status_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_status_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_dprv, // @[HellaCache.scala:243:14] input io_ptw_status_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_prv, // @[HellaCache.scala:243:14] input io_ptw_status_v, // @[HellaCache.scala:243:14] input io_ptw_status_mpv, // @[HellaCache.scala:243:14] input io_ptw_status_gva, // @[HellaCache.scala:243:14] input io_ptw_status_tsr, // @[HellaCache.scala:243:14] input io_ptw_status_tw, // @[HellaCache.scala:243:14] input io_ptw_status_tvm, // @[HellaCache.scala:243:14] input io_ptw_status_mxr, // @[HellaCache.scala:243:14] input io_ptw_status_sum, // @[HellaCache.scala:243:14] input io_ptw_status_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_mpp, // @[HellaCache.scala:243:14] input io_ptw_status_spp, // @[HellaCache.scala:243:14] input io_ptw_status_mpie, // @[HellaCache.scala:243:14] input io_ptw_status_spie, // @[HellaCache.scala:243:14] input io_ptw_status_mie, // @[HellaCache.scala:243:14] input io_ptw_status_sie, // @[HellaCache.scala:243:14] input io_ptw_hstatus_spvp, // @[HellaCache.scala:243:14] input io_ptw_hstatus_spv, // @[HellaCache.scala:243:14] input io_ptw_hstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_debug, // @[HellaCache.scala:243:14] input io_ptw_gstatus_cease, // @[HellaCache.scala:243:14] input io_ptw_gstatus_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_gstatus_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_dprv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_prv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_v, // @[HellaCache.scala:243:14] input [22:0] io_ptw_gstatus_zero2, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mbe, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sbe, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_sxl, // @[HellaCache.scala:243:14] input [7:0] io_ptw_gstatus_zero1, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tsr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tw, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tvm, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mxr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sum, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_mpp, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_vs, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spp, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_ube, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_upie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_hie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_uie, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_0_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_0_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_1_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_1_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_2_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_2_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_3_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_3_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_4_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_4_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_5_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_5_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_6_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_6_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_7_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_7_mask, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[HellaCache.scala:243:14] ); wire [19:0] s2_meta_corrected_7_tag; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_7_coh_state; // @[DCache.scala:361:99] wire rockettile_dcache_tag_array_MPORT_en; // @[DCache.scala:310:27] wire s0_req_phys; // @[DCache.scala:192:24] wire [39:0] s0_req_addr; // @[DCache.scala:192:24] wire tl_out_a_valid; // @[DCache.scala:159:22] wire [127:0] tl_out_a_bits_data; // @[DCache.scala:159:22] wire [15:0] tl_out_a_bits_mask; // @[DCache.scala:159:22] wire [31:0] tl_out_a_bits_address; // @[DCache.scala:159:22] wire tl_out_a_bits_source; // @[DCache.scala:159:22] wire [3:0] tl_out_a_bits_size; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_param; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_opcode; // @[DCache.scala:159:22] wire [5:0] metaArb_io_out_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_in_0_valid; // @[DCache.scala:135:28] wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [175:0] _rockettile_dcache_tag_array_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22] wire [19:0] _pma_checker_entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_checker_pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_eff; // @[TLB.scala:422:19] wire [19:0] _pma_checker_mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire _tlb_io_req_ready; // @[DCache.scala:119:19] wire _tlb_io_resp_miss; // @[DCache.scala:119:19] wire [31:0] _tlb_io_resp_paddr; // @[DCache.scala:119:19] wire [39:0] _tlb_io_resp_gpa; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_st; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_st; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_st; // @[DCache.scala:119:19] wire _tlb_io_resp_cacheable; // @[DCache.scala:119:19] wire _tlb_io_resp_must_alloc; // @[DCache.scala:119:19] wire _tlb_io_resp_prefetchable; // @[DCache.scala:119:19] wire [1:0] _tlb_io_resp_size; // @[DCache.scala:119:19] wire [4:0] _tlb_io_resp_cmd; // @[DCache.scala:119:19] wire auto_out_a_ready_0 = auto_out_a_ready; // @[DCache.scala:101:7] wire auto_out_b_valid_0 = auto_out_b_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[DCache.scala:101:7] wire auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[DCache.scala:101:7] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[DCache.scala:101:7] wire [15:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[DCache.scala:101:7] wire [127:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[DCache.scala:101:7] wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[DCache.scala:101:7] wire auto_out_c_ready_0 = auto_out_c_ready; // @[DCache.scala:101:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DCache.scala:101:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DCache.scala:101:7] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DCache.scala:101:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DCache.scala:101:7] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DCache.scala:101:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DCache.scala:101:7] wire auto_out_e_ready_0 = auto_out_e_ready; // @[DCache.scala:101:7] wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[DCache.scala:101:7] wire [39:0] io_cpu_req_bits_addr_0 = io_cpu_req_bits_addr; // @[DCache.scala:101:7] wire [7:0] io_cpu_req_bits_tag_0 = io_cpu_req_bits_tag; // @[DCache.scala:101:7] wire [4:0] io_cpu_req_bits_cmd_0 = io_cpu_req_bits_cmd; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_size_0 = io_cpu_req_bits_size; // @[DCache.scala:101:7] wire io_cpu_req_bits_signed_0 = io_cpu_req_bits_signed; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_dprv_0 = io_cpu_req_bits_dprv; // @[DCache.scala:101:7] wire io_cpu_req_bits_dv_0 = io_cpu_req_bits_dv; // @[DCache.scala:101:7] wire io_cpu_req_bits_phys_0 = io_cpu_req_bits_phys; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_resp_0 = io_cpu_req_bits_no_resp; // @[DCache.scala:101:7] wire io_cpu_s1_kill_0 = io_cpu_s1_kill; // @[DCache.scala:101:7] wire [63:0] io_cpu_s1_data_data_0 = io_cpu_s1_data_data; // @[DCache.scala:101:7] wire [7:0] io_cpu_s1_data_mask_0 = io_cpu_s1_data_mask; // @[DCache.scala:101:7] wire io_cpu_keep_clock_enabled_0 = io_cpu_keep_clock_enabled; // @[DCache.scala:101:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[DCache.scala:101:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[DCache.scala:101:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[DCache.scala:101:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[DCache.scala:101:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[DCache.scala:101:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[DCache.scala:101:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[DCache.scala:101:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[DCache.scala:101:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[DCache.scala:101:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[DCache.scala:101:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[DCache.scala:101:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[DCache.scala:101:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[DCache.scala:101:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[DCache.scala:101:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[DCache.scala:101:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[DCache.scala:101:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[DCache.scala:101:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[DCache.scala:101:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[DCache.scala:101:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[DCache.scala:101:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[DCache.scala:101:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[DCache.scala:101:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[DCache.scala:101:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[DCache.scala:101:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[DCache.scala:101:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[DCache.scala:101:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[DCache.scala:101:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[DCache.scala:101:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[DCache.scala:101:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[DCache.scala:101:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[DCache.scala:101:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[DCache.scala:101:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[DCache.scala:101:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[DCache.scala:101:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[DCache.scala:101:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[DCache.scala:101:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[DCache.scala:101:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[DCache.scala:101:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[DCache.scala:101:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[DCache.scala:101:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[DCache.scala:101:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[DCache.scala:101:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[DCache.scala:101:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[DCache.scala:101:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[DCache.scala:101:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[DCache.scala:101:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[DCache.scala:101:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[DCache.scala:101:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[DCache.scala:101:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[DCache.scala:101:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_55 = reset; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_55 = reset; // @[DCache.scala:1186:11] wire auto_out_a_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire auto_out_c_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_alloc = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_xcpt = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_kill = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_mbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_ube = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_upie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_hie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_uie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_valid = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_passthrough = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_v = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s2_kill = 1'h0; // @[DCache.scala:101:7] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire pma_checker_io_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_miss = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_ld = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_st = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_asid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hg = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_ready = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_need_gpa = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_ptw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_final = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hx = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_d = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_a = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_g = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_u = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_homogeneous = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_kill = 1'h0; // @[DCache.scala:120:32] wire pma_checker_priv_v = 1'h0; // @[TLB.scala:369:34] wire pma_checker__stage1_en_T = 1'h0; // @[TLB.scala:374:41] wire pma_checker_stage1_en = 1'h0; // @[TLB.scala:374:29] wire pma_checker__vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire pma_checker__vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire pma_checker_vstage1_en = 1'h0; // @[TLB.scala:376:48] wire pma_checker__stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire pma_checker__stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire pma_checker_stage2_en = 1'h0; // @[TLB.scala:378:48] wire pma_checker__vm_enabled_T = 1'h0; // @[TLB.scala:399:31] wire pma_checker__vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45] wire pma_checker__vm_enabled_T_2 = 1'h0; // @[TLB.scala:399:64] wire pma_checker_vm_enabled = 1'h0; // @[TLB.scala:399:61] wire pma_checker__vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire pma_checker__vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire pma_checker__vsatp_mode_mismatch_T_2 = 1'h0; // @[TLB.scala:403:81] wire pma_checker_vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire pma_checker_do_refill = 1'h0; // @[TLB.scala:408:29] wire pma_checker__invalidate_refill_T = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_invalidate_refill = 1'h0; // @[TLB.scala:410:88] wire pma_checker__mpu_ppn_T = 1'h0; // @[TLB.scala:413:32] wire pma_checker_prot_r = 1'h0; // @[TLB.scala:429:55] wire pma_checker_prot_w = 1'h0; // @[TLB.scala:430:55] wire pma_checker_prot_x = 1'h0; // @[TLB.scala:434:55] wire pma_checker__sector_hits_T = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_0 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_9 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_10 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_1 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_17 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_18 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_2 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_24 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_25 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_26 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_3 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_32 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_33 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_34 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_4 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_40 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_41 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_42 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_5 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_48 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_49 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_50 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_6 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_56 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_57 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_58 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_7 = 1'h0; // @[TLB.scala:172:55] wire pma_checker_superpage_hits_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_4 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_9 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_0 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_18 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_23 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_1 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_32 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_37 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_2 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_46 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_51 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_3 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_0 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_1 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_2 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_3 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_4 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_5 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_6 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_7 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_52 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_57 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_62 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_8 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_67 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_72 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_77 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_9 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_82 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_87 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_92 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_10 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_97 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_102 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_107 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_11 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_4 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_112 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_117 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_122 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_12 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_refill_v = 1'h0; // @[TLB.scala:448:33] wire pma_checker_newEntry_u = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_g = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_ptw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_final = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_gf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_px = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire pma_checker__newEntry_g_T = 1'h0; // @[TLB.scala:453:25] wire pma_checker__newEntry_ae_stage2_T = 1'h0; // @[TLB.scala:456:53] wire pma_checker__newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire pma_checker__newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sr_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sr_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sr_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sr_T_5 = 1'h0; // @[PTW.scala:149:35] wire pma_checker__newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sw_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sw_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sw_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sw_T_5 = 1'h0; // @[PTW.scala:151:35] wire pma_checker__newEntry_sw_T_6 = 1'h0; // @[PTW.scala:151:40] wire pma_checker__newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sx_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sx_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sx_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35] wire pma_checker__waddr_T = 1'h0; // @[TLB.scala:477:45] wire pma_checker__superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker_sum = 1'h0; // @[TLB.scala:510:16] wire pma_checker__mxr_T = 1'h0; // @[TLB.scala:518:36] wire pma_checker_mxr = 1'h0; // @[TLB.scala:518:31] wire pma_checker__bad_va_T = 1'h0; // @[TLB.scala:568:21] wire pma_checker_bad_va = 1'h0; // @[TLB.scala:568:34] wire pma_checker_cmd_readx = 1'h0; // @[TLB.scala:575:37] wire pma_checker__gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire pma_checker__gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire pma_checker__gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60] wire pma_checker_tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43] wire pma_checker_tlb_hit = 1'h0; // @[TLB.scala:611:40] wire pma_checker__tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29] wire pma_checker__tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53] wire pma_checker_tlb_miss = 1'h0; // @[TLB.scala:613:64] wire pma_checker__state_vec_0_set_left_older_T = 1'h0; // @[Replacement.scala:196:43] wire pma_checker__state_vec_0_set_left_older_T_1 = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_vec_0_T_1 = 1'h0; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_2 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_T_4 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_vec_0_T_5 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_vec_0_T_6 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_set_left_older_T_2 = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_vec_0_T_12 = 1'h0; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_13 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_T_15 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_vec_0_T_16 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_vec_0_T_17 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_reg_set_left_older_T = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_reg_T = 1'h0; // @[package.scala:163:13] wire pma_checker__state_reg_T_1 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_reg_T_3 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_reg_T_4 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_reg_T_5 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits = 1'h0; // @[Misc.scala:183:49] wire pma_checker__io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28] wire pma_checker__io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire pma_checker__io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire pma_checker__io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire pma_checker__io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire pma_checker__io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire pma_checker__io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire pma_checker__io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire pma_checker__io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire pma_checker__io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire pma_checker__io_resp_miss_T = 1'h0; // @[TLB.scala:651:29] wire pma_checker__io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52] wire pma_checker__io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64] wire pma_checker__io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire pma_checker__io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29] wire pma_checker_r_superpage_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_superpage_repl_addr_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_r_superpage_repl_addr_right_subtree_state = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_superpage_repl_addr_T = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_superpage_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_superpage_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker__r_superpage_repl_addr_T_4 = 1'h0; // @[TLB.scala:757:16] wire pma_checker_r_sectored_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_older_1 = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_r_sectored_repl_addr_right_subtree_state_1 = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_sectored_repl_addr_T = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker_r_sectored_repl_addr_left_subtree_older_2 = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_r_sectored_repl_addr_right_subtree_state_2 = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_sectored_repl_addr_T_4 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_5 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_6 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker__r_sectored_repl_addr_valids_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_3 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_4 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_5 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_6 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_7 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_9 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_10 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_11 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_12 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_13 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_14 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_15 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_17 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_18 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_19 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_20 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_21 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_22 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_23 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_T_10 = 1'h0; // @[TLB.scala:757:16] wire pma_checker__r_sectored_hit_valid_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_3 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_4 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_5 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_6 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_sectored_hit_bits_T_3 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_sectored_hit_bits_T_5 = 1'h0; // @[CircuitMath.scala:28:8] wire pma_checker__r_superpage_hit_valid_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_valid_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_valid_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_superpage_hit_bits_T_3 = 1'h0; // @[CircuitMath.scala:28:8] wire pma_checker_hv = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_1 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_1 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_2 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_2 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_3 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_3 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_4 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_4 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_5 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_5 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_6 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_6 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_7 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_7 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_8 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_8 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_9 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_9 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_10 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_10 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_11 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_11 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_12 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_12 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_4 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire metaArb_io_in_1_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_6_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_7_bits_write = 1'h0; // @[DCache.scala:135:28] wire dataArb_io_in_2_bits_write = 1'h0; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_write = 1'h0; // @[DCache.scala:152:28] wire tl_out_a_bits_corrupt = 1'h0; // @[DCache.scala:159:22] wire nodeOut_a_deq_bits_corrupt = 1'h0; // @[Decoupled.scala:356:21] wire _s1_tlb_req_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire s0_req_no_alloc = 1'h0; // @[DCache.scala:192:24] wire s0_req_no_xcpt = 1'h0; // @[DCache.scala:192:24] wire s1_waw_hazard = 1'h0; // @[DCache.scala:216:27] wire _uncachedInFlight_WIRE_0 = 1'h0; // @[DCache.scala:236:41] wire _dataArb_io_in_3_valid_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _dataArb_io_in_3_valid_T_49 = 1'h0; // @[DCache.scala:1191:57] wire dataArb_io_in_3_bits_wordMask_mask_upper_mask = 1'h0; // @[DCache.scala:248:27] wire _s1_did_read_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _tlb_io_kill_T = 1'h0; // @[DCache.scala:272:53] wire _tlb_io_kill_T_1 = 1'h0; // @[DCache.scala:272:33] wire _s2_pma_T_gpa_is_pte = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_ld = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_st = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_inst = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_ma_inst = 1'h0; // @[DCache.scala:349:18] wire s2_meta_error_uncorrectable = 1'h0; // @[DCache.scala:360:66] wire s2_meta_error = 1'h0; // @[DCache.scala:362:83] wire s2_store_merge = 1'h0; // @[DCache.scala:388:28] wire _r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _s2_data_error_T = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_1 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_2 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_3 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_4 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_5 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_6 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_7 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_8 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_9 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_10 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_11 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_12 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_13 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_14 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_15 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_16 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_17 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_18 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_19 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_20 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_21 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_22 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_23 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_24 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_25 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_26 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_27 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_28 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_29 = 1'h0; // @[package.scala:81:59] wire s2_data_error = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_1 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_2 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_3 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_4 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_5 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_6 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_7 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_8 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_9 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_10 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_11 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_12 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_13 = 1'h0; // @[package.scala:81:59] wire s2_data_error_uncorrectable = 1'h0; // @[package.scala:81:59] wire s2_valid_data_error = 1'h0; // @[DCache.scala:421:63] wire s2_cannot_victimize = 1'h0; // @[DCache.scala:428:45] wire _r_T_73 = 1'h0; // @[Misc.scala:38:9] wire _r_T_77 = 1'h0; // @[Misc.scala:38:9] wire _r_T_81 = 1'h0; // @[Misc.scala:38:9] wire _r_T_119 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_121 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_137 = 1'h0; // @[Misc.scala:38:9] wire _r_T_141 = 1'h0; // @[Misc.scala:38:9] wire _r_T_145 = 1'h0; // @[Misc.scala:38:9] wire _s2_dont_nack_misc_T_2 = 1'h0; // @[DCache.scala:442:23] wire _s2_dont_nack_misc_T_3 = 1'h0; // @[DCache.scala:442:43] wire _s2_dont_nack_misc_T_5 = 1'h0; // @[DCache.scala:442:54] wire _s2_dont_nack_misc_T_6 = 1'h0; // @[DCache.scala:443:23] wire _s2_dont_nack_misc_T_8 = 1'h0; // @[DCache.scala:443:44] wire _s2_dont_nack_misc_T_9 = 1'h0; // @[DCache.scala:442:67] wire _s2_first_meta_corrected_T = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_1 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_2 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_3 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_4 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_5 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_6 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_7 = 1'h0; // @[Mux.scala:52:83] wire _metaArb_io_in_1_valid_T_2 = 1'h0; // @[DCache.scala:450:43] wire _metaArb_io_in_1_bits_way_en_T = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_1 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_2 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_3 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_4 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_5 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_6 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_7 = 1'h0; // @[OneHot.scala:85:71] wire _s2_correct_T_1 = 1'h0; // @[DCache.scala:487:34] wire _s2_correct_T_4 = 1'h0; // @[DCache.scala:487:55] wire s2_correct = 1'h0; // @[DCache.scala:487:97] wire _s2_valid_correct_T = 1'h0; // @[DCache.scala:489:60] wire s2_valid_correct = 1'h0; // @[DCache.scala:489:74] wire _pstore1_rmw_T_49 = 1'h0; // @[DCache.scala:1191:57] wire pstore1_merge_likely = 1'h0; // @[DCache.scala:499:68] wire pstore1_merge = 1'h0; // @[DCache.scala:500:38] wire _pstore_drain_opportunistic_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _pstore_drain_opportunistic_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _pstore_drain_opportunistic_T_60 = 1'h0; // @[DCache.scala:502:106] wire pstore_drain_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _pstore2_storegen_data_T_2 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_6 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_10 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_14 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_18 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_22 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_26 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_30 = 1'h0; // @[DCache.scala:528:95] wire dataArb_io_in_0_valid_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _io_cpu_s2_nack_cause_raw_T_2 = 1'h0; // @[DCache.scala:574:57] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire get_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire put_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _putpartial_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _putpartial_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire putpartial_corrupt = 1'h0; // @[Edges.scala:500:17] wire _atomics_WIRE_source = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_corrupt = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_1_source = 1'h0; // @[DCache.scala:587:38] wire _atomics_WIRE_1_corrupt = 1'h0; // @[DCache.scala:587:38] wire _atomics_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_40 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_93 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_99 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_152 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_158 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_2 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_211 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_217 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_3 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_270 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_276 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_4 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_329 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_335 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_5 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_388 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_394 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_6 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_447 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_453 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_7 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_506 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_512 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_8 = 1'h0; // @[Misc.scala:206:21] wire _atomics_T_1_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_3_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_5_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_7_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_9_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_11_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_13_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_15_corrupt = 1'h0; // @[DCache.scala:587:81] wire atomics_corrupt = 1'h0; // @[DCache.scala:587:81] wire _tl_out_a_valid_T_8 = 1'h0; // @[DCache.scala:607:44] wire _tl_out_a_valid_T_9 = 1'h0; // @[DCache.scala:607:65] wire _tl_out_a_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _tl_out_a_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _tl_out_a_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire tl_out_a_bits_a_source = 1'h0; // @[Edges.scala:346:17] wire tl_out_a_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire tl_out_a_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _tl_out_a_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire tl_out_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _tl_out_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_T_6_corrupt = 1'h0; // @[DCache.scala:611:8] wire _tl_out_a_bits_T_7_corrupt = 1'h0; // @[DCache.scala:610:8] wire _tl_out_a_bits_T_8_corrupt = 1'h0; // @[DCache.scala:609:8] wire _tl_out_a_bits_T_9_corrupt = 1'h0; // @[DCache.scala:608:23] wire nackResponseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire cleanReleaseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire dirtyReleaseMessage_corrupt = 1'h0; // @[Edges.scala:433:17] wire _nodeOut_c_valid_T = 1'h0; // @[DCache.scala:810:48] wire _nodeOut_c_valid_T_2 = 1'h0; // @[DCache.scala:810:74] wire _discard_line_T_2 = 1'h0; // @[DCache.scala:818:102] wire _release_state_T_2 = 1'h0; // @[DCache.scala:820:28] wire _release_state_T_4 = 1'h0; // @[DCache.scala:820:54] wire _release_state_T_5 = 1'h0; // @[DCache.scala:820:75] wire _release_state_T_7 = 1'h0; // @[DCache.scala:820:98] wire _release_state_T_12 = 1'h0; // @[DCache.scala:820:127] wire probe_bits_res_source = 1'h0; // @[DCache.scala:1202:19] wire probe_bits_res_corrupt = 1'h0; // @[DCache.scala:1202:19] wire _nodeOut_c_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_1 = 1'h0; // @[Parameters.scala:137:31] wire _nodeOut_c_bits_legal_T_10 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_15 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_25 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_30 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_31 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_32 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_legal = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_c_source = 1'h0; // @[Edges.scala:380:17] wire nodeOut_c_bits_c_corrupt = 1'h0; // @[Edges.scala:380:17] wire _nodeOut_c_bits_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_35 = 1'h0; // @[Parameters.scala:137:31] wire _nodeOut_c_bits_legal_T_44 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_49 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_52 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_59 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_64 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_65 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_66 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_67 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_legal_1 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_c_1_source = 1'h0; // @[Edges.scala:396:17] wire nodeOut_c_bits_c_1_corrupt = 1'h0; // @[Edges.scala:396:17] wire _nodeOut_c_bits_corrupt_T = 1'h0; // @[DCache.scala:887:42] wire _io_cpu_s2_xcpt_WIRE_miss = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gpa_is_pte = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_cacheable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_must_alloc = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_prefetchable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_T_gpa_is_pte = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_ld = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_st = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_inst = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_inst = 1'h0; // @[DCache.scala:933:24] wire _s2_data_word_possibly_uncached_T = 1'h0; // @[DCache.scala:972:73] wire io_cpu_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_word_bypass_doZero = 1'h0; // @[AMOALU.scala:43:31] wire _s1_flush_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire _s1_flush_valid_T_2 = 1'h0; // @[DCache.scala:1014:43] wire _s1_flush_valid_T_4 = 1'h0; // @[DCache.scala:1014:62] wire _s1_flush_valid_T_6 = 1'h0; // @[DCache.scala:1014:93] wire _s1_flush_valid_T_8 = 1'h0; // @[DCache.scala:1014:122] wire _metaArb_io_in_5_valid_T = 1'h0; // @[DCache.scala:1015:41] wire _metaArb_io_in_5_valid_T_1 = 1'h0; // @[DCache.scala:1015:38] wire _clock_en_reg_T_17 = 1'h0; // @[DCache.scala:1070:25] wire _io_cpu_perf_canAcceptLoadThenLoad_T_50 = 1'h0; // @[DCache.scala:1191:57] wire [63:0] io_cpu_req_bits_data = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] s0_req_data = 64'h0; // @[DCache.scala:192:24] wire [63:0] _s2_data_word_possibly_uncached_T_1 = 64'h0; // @[DCache.scala:972:43] wire [7:0] io_cpu_req_bits_mask = 8'h0; // @[DCache.scala:101:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[DCache.scala:101:7] wire [7:0] pma_checker_io_ptw_status_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_io_ptw_gstatus_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_r_sectored_repl_addr_valids = 8'h0; // @[package.scala:45:27] wire [7:0] pma_checker__r_sectored_hit_bits_T = 8'h0; // @[OneHot.scala:21:45] wire [7:0] metaArb_io_in_1_bits_way_en = 8'h0; // @[DCache.scala:135:28] wire [7:0] s0_req_mask = 8'h0; // @[DCache.scala:192:24] wire [7:0] s2_meta_correctable_errors = 8'h0; // @[package.scala:45:27] wire [7:0] s2_meta_uncorrectable_errors = 8'h0; // @[package.scala:45:27] wire [7:0] _s2_meta_error_T = 8'h0; // @[DCache.scala:362:53] wire [7:0] _metaArb_io_in_1_bits_way_en_T_8 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_9 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_10 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_11 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_12 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_13 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_14 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_15 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_16 = 8'h0; // @[DCache.scala:452:69] wire [7:0] _metaArb_io_in_1_bits_way_en_T_17 = 8'h0; // @[DCache.scala:452:64] wire [7:0] _pstore2_storegen_mask_mergedMask_T = 8'h0; // @[DCache.scala:533:42] wire io_cpu_clock_enabled = 1'h1; // @[DCache.scala:101:7] wire io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:101:7] wire io_ptw_status_sd = 1'h1; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd = 1'h1; // @[DCache.scala:101:7] wire io_tlb_port_req_ready = 1'h1; // @[DCache.scala:101:7] wire pma_checker_io_req_ready = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_passthrough = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:120:32] wire pma_checker__mpu_ppn_ignore_T = 1'h1; // @[TLB.scala:197:28] wire pma_checker_mpu_ppn_ignore = 1'h1; // @[TLB.scala:197:34] wire pma_checker__mpu_ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_mpu_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__mpu_priv_T = 1'h1; // @[TLB.scala:415:52] wire pma_checker__mpu_priv_T_1 = 1'h1; // @[TLB.scala:415:38] wire pma_checker__homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire pma_checker__deny_access_to_debug_T = 1'h1; // @[TLB.scala:428:39] wire pma_checker__sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_13 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_13 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_116 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_ignore_T_14 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_14 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_121 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hits_T = 1'h1; // @[TLB.scala:442:18] wire pma_checker__newEntry_sr_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sw_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sx_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__ppn_T = 1'h1; // @[TLB.scala:502:30] wire pma_checker__ppn_ignore_T = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_2 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_3 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_4 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_5 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_6 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_7 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_8 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_8 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_9 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_9 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83] wire pma_checker__stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire pma_checker__bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire pma_checker__gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire pma_checker__tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire pma_checker__tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56] wire pma_checker__tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67] wire pma_checker_state_vec_0_set_left_older = 1'h1; // @[Replacement.scala:196:33] wire pma_checker_state_vec_0_set_left_older_1 = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_vec_0_T_3 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_7 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_8 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker_state_vec_0_set_left_older_2 = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_vec_0_T_14 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_18 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_19 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker_state_reg_set_left_older = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_reg_T_2 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_reg_T_6 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_reg_T_7 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker__io_req_ready_T = 1'h1; // @[TLB.scala:631:25] wire pma_checker__io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire pma_checker__io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire pma_checker__r_superpage_repl_addr_T_6 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_7 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_8 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_9 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_12 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_13 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_14 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_15 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_16 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_17 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_18 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_19 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_13 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_13 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__ignore_T_14 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_14 = 1'h1; // @[TLB.scala:182:34] wire metaArb_io_in_0_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_0_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_1_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_2_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_3_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_4_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_out_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire dataArb_io_in_0_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_out_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire _dataArb_io_in_3_bits_wordMask_mask_upper_mask_T = 1'h1; // @[DCache.scala:248:76] wire _dataArb_io_in_3_bits_wordMask_mask_upper_mask_T_1 = 1'h1; // @[DCache.scala:248:52] wire _s2_valid_not_killed_T = 1'h1; // @[DCache.scala:338:48] wire _s2_flush_valid_T = 1'h1; // @[DCache.scala:363:54] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = 1'h1; // @[DCache.scala:397:74] wire _s2_valid_hit_pre_data_ecc_and_waw_T_1 = 1'h1; // @[DCache.scala:418:108] wire _s2_valid_hit_pre_data_ecc_T = 1'h1; // @[DCache.scala:420:73] wire _s2_valid_hit_pre_data_ecc_T_1 = 1'h1; // @[DCache.scala:420:88] wire _s2_valid_hit_T = 1'h1; // @[DCache.scala:422:51] wire _s2_valid_miss_T_1 = 1'h1; // @[DCache.scala:423:58] wire _s2_victimize_T = 1'h1; // @[DCache.scala:429:43] wire _r_T_117 = 1'h1; // @[Metadata.scala:140:24] wire _s2_dont_nack_misc_T = 1'h1; // @[DCache.scala:441:46] wire _s2_dont_nack_misc_T_4 = 1'h1; // @[DCache.scala:442:57] wire _metaArb_io_in_2_bits_write_T = 1'h1; // @[DCache.scala:463:34] wire _s2_valid_correct_T_1 = 1'h1; // @[DCache.scala:489:77] wire _pstore1_merge_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_opportunistic_T_61 = 1'h1; // @[DCache.scala:502:95] wire _pstore1_valid_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_T = 1'h1; // @[DCache.scala:516:5] wire _pstore_drain_T_3 = 1'h1; // @[DCache.scala:506:87] wire _pstore1_held_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore1_held_T_5 = 1'h1; // @[DCache.scala:521:38] wire _dataArb_io_in_0_valid_T = 1'h1; // @[DCache.scala:516:5] wire _dataArb_io_in_0_valid_T_3 = 1'h1; // @[DCache.scala:506:87] wire _io_cpu_s2_nack_cause_raw_T = 1'h1; // @[DCache.scala:574:59] wire _io_cpu_s2_nack_cause_raw_T_1 = 1'h1; // @[DCache.scala:574:74] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_41 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_42 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_43 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_44 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_59 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_100 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_101 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_102 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_103 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_118 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_119 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_120 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_121 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_159 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_160 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_161 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_177 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_178 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_179 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_180 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_220 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_221 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_236 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_237 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_238 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_239 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_277 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_278 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_279 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_280 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_295 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_296 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_297 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_298 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_336 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_337 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_338 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_339 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_354 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_355 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_356 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_357 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_395 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_396 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_397 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_398 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_413 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_414 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_415 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_416 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_454 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_455 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_456 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_457 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_472 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_473 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_474 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_475 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_513 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_514 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_515 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_516 = 1'h1; // @[Parameters.scala:684:29] wire _tl_out_a_valid_T = 1'h1; // @[DCache.scala:603:21] wire _tl_out_a_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _tl_out_a_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire tl_out_a_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire tl_out_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire tl_out_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire tl_out_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _nodeOut_c_bits_legal_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_16 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_17 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _nodeOut_c_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_39 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_50 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_51 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_53 = 1'h1; // @[Parameters.scala:91:44] wire _nodeOut_c_bits_legal_T_54 = 1'h1; // @[Parameters.scala:684:29] wire _io_cpu_resp_valid_T_1 = 1'h1; // @[DCache.scala:949:73] wire _io_cpu_replay_next_T_2 = 1'h1; // @[DCache.scala:950:65] wire _clock_en_reg_T = 1'h1; // @[DCache.scala:1060:19] wire _clock_en_reg_T_2 = 1'h1; // @[DCache.scala:1060:44] wire _clock_en_reg_T_3 = 1'h1; // @[DCache.scala:1061:46] wire _clock_en_reg_T_4 = 1'h1; // @[DCache.scala:1062:31] wire _clock_en_reg_T_5 = 1'h1; // @[DCache.scala:1063:26] wire _clock_en_reg_T_6 = 1'h1; // @[DCache.scala:1064:14] wire _clock_en_reg_T_7 = 1'h1; // @[DCache.scala:1064:26] wire _clock_en_reg_T_8 = 1'h1; // @[DCache.scala:1065:14] wire _clock_en_reg_T_9 = 1'h1; // @[DCache.scala:1065:26] wire _clock_en_reg_T_10 = 1'h1; // @[DCache.scala:1066:27] wire _clock_en_reg_T_11 = 1'h1; // @[DCache.scala:1067:22] wire _clock_en_reg_T_12 = 1'h1; // @[DCache.scala:1067:42] wire _clock_en_reg_T_13 = 1'h1; // @[DCache.scala:1068:18] wire _clock_en_reg_T_15 = 1'h1; // @[DCache.scala:1068:35] wire _clock_en_reg_T_16 = 1'h1; // @[DCache.scala:1069:31] wire _clock_en_reg_T_18 = 1'h1; // @[DCache.scala:1070:22] wire _clock_en_reg_T_20 = 1'h1; // @[DCache.scala:1070:46] wire _clock_en_reg_T_21 = 1'h1; // @[DCache.scala:1071:23] wire _clock_en_reg_T_23 = 1'h1; // @[DCache.scala:1072:23] wire _clock_en_reg_T_25 = 1'h1; // @[DCache.scala:1072:54] wire _clock_en_reg_T_27 = 1'h1; // @[DCache.scala:1073:21] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = 1'h1; // @[DCache.scala:1082:31] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = 1'h1; // @[DCache.scala:1087:31] wire _io_cpu_perf_canAcceptStoreThenLoad_T_3 = 1'h1; // @[DCache.scala:1089:72] wire _io_cpu_perf_canAcceptLoadThenLoad_T_56 = 1'h1; // @[DCache.scala:1092:115] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] pma_checker_io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_satp_asid = 16'h0; // @[TLB.scala:373:17] wire [15:0] _atomics_WIRE_mask = 16'h0; // @[DCache.scala:587:51] wire [15:0] _atomics_WIRE_1_mask = 16'h0; // @[DCache.scala:587:38] wire [15:0] probe_bits_res_mask = 16'h0; // @[DCache.scala:1202:19] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] pma_checker_io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_satp_mode = 4'h0; // @[TLB.scala:373:17] wire [3:0] pma_checker_real_hits_hi_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_lo = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi_1 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] pma_checker_lo_1 = 4'h0; // @[OneHot.scala:31:18] wire [3:0] pma_checker__multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39] wire [3:0] pma_checker_r_superpage_repl_addr_valids = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_repl_addr_valids_lo = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_repl_addr_valids_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_hit_bits_lo = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_r_sectored_hit_bits_hi = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_r_sectored_hit_bits_hi_1 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] pma_checker_r_sectored_hit_bits_lo_1 = 4'h0; // @[OneHot.scala:31:18] wire [3:0] pma_checker__r_sectored_hit_bits_T_2 = 4'h0; // @[OneHot.scala:32:28] wire [3:0] pma_checker__r_superpage_hit_bits_T = 4'h0; // @[OneHot.scala:21:45] wire [3:0] s2_meta_correctable_errors_lo = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_correctable_errors_hi = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_uncorrectable_errors_lo = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_uncorrectable_errors_hi = 4'h0; // @[package.scala:45:27] wire [3:0] _r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_63 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_127 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _atomics_WIRE_size = 4'h0; // @[DCache.scala:587:51] wire [3:0] _atomics_WIRE_1_size = 4'h0; // @[DCache.scala:587:38] wire [3:0] _metaArb_io_in_3_bits_data_T_5 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] probe_bits_res_size = 4'h0; // @[DCache.scala:1202:19] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] pma_checker_io_ptw_resp_bits_pte_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_satp_ppn = 44'h0; // @[TLB.scala:373:17] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[DCache.scala:101:7] wire [22:0] pma_checker_io_ptw_status_zero2 = 23'h0; // @[DCache.scala:120:32] wire [22:0] pma_checker_io_ptw_gstatus_zero2 = 23'h0; // @[DCache.scala:120:32] wire [1:0] io_ptw_status_xs = 2'h3; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[DCache.scala:101:7] wire [1:0] dataArb_io_in_1_bits_wordMask = 2'h3; // @[DCache.scala:152:28] wire [1:0] dataArb_io_in_2_bits_wordMask = 2'h3; // @[DCache.scala:152:28] wire [1:0] _s2_data_word_en_T = 2'h3; // @[DCache.scala:367:40] wire [1:0] _r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] tl_out_a_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _dataArb_io_in_1_bits_wordMask_T = 2'h3; // @[DCache.scala:731:39] wire [1:0] _metaArb_io_in_3_bits_data_T_8 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dataArb_io_in_2_bits_wordMask_T = 2'h3; // @[DCache.scala:904:37] wire [1:0] io_ptw_status_vs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_size = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_prv = 2'h0; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_resp_bits_level = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__special_entry_level_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_special_entry_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_waddr = 2'h0; // @[TLB.scala:477:22] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_1 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_2 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_3 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_4 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_5 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_6 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_7 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker__pr_array_T = 2'h0; // @[TLB.scala:529:26] wire [1:0] pma_checker__pw_array_T = 2'h0; // @[TLB.scala:531:26] wire [1:0] pma_checker__px_array_T = 2'h0; // @[TLB.scala:533:26] wire [1:0] pma_checker_lo_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_lo_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_2 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_lo_2 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__state_vec_0_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker__state_vec_0_T_11 = 2'h0; // @[Replacement.scala:207:62] wire [1:0] pma_checker_lo_3 = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_3 = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_4 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_lo_4 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker_state_reg_touch_way_sized = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker__multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37] wire [1:0] pma_checker__multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__r_superpage_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker_r_superpage_repl_addr_valids_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_superpage_repl_addr_valids_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__r_superpage_repl_addr_T_12 = 2'h0; // @[Mux.scala:50:70] wire [1:0] pma_checker__r_superpage_repl_addr_T_13 = 2'h0; // @[TLB.scala:757:8] wire [1:0] pma_checker__r_sectored_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker__r_sectored_repl_addr_T_7 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker__r_sectored_repl_addr_T_8 = 2'h0; // @[Replacement.scala:250:16] wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_hit_bits_lo_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_lo_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_2 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_r_sectored_hit_bits_lo_2 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__r_sectored_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:28] wire [1:0] pma_checker__r_sectored_hit_bits_T_6 = 2'h0; // @[OneHot.scala:32:10] wire [1:0] pma_checker_r_superpage_hit_bits_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_superpage_hit_bits_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_superpage_hit_bits_hi_1 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_r_superpage_hit_bits_lo_1 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__r_superpage_hit_bits_T_2 = 2'h0; // @[OneHot.scala:32:28] wire [1:0] pma_checker__r_superpage_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:10] wire [1:0] s1_meta_hit_state_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _s2_valid_no_xcpt_T_1 = 2'h0; // @[DCache.scala:332:54] wire [1:0] s2_meta_correctable_errors_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] _r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_75 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_79 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_83 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_87 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_91 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_139 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_143 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_147 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_151 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_155 = 2'h0; // @[Misc.scala:38:63] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _metaArb_io_in_3_bits_data_T_2 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _metaArb_io_in_3_bits_data_T_4 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] probe_bits_res_param = 2'h0; // @[DCache.scala:1202:19] wire [1:0] _nodeOut_c_bits_legal_T_2 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _nodeOut_c_bits_legal_T_36 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _io_cpu_s2_xcpt_WIRE_size = 2'h0; // @[DCache.scala:933:74] wire [1:0] metaArb_io_in_0_bits_data_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] metaArb_io_in_0_bits_data_meta_1_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:101:7] wire [29:0] pma_checker_io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_0_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_1_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_2_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_3_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_4_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_5_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_6_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_7_addr = 30'h0; // @[DCache.scala:120:32] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:101:7] wire [8:0] pma_checker_io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:120:32] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:101:7] wire [5:0] pma_checker_io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:120:32] wire [5:0] pma_checker_real_hits_lo = 6'h0; // @[package.scala:45:27] wire [5:0] pma_checker_special_entry_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker__multipleHits_T = 6'h0; // @[Misc.scala:181:37] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_req_bits_cmd = 5'h0; // @[DCache.scala:101:7] wire [4:0] pma_checker_io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:120:32] wire [4:0] _io_cpu_s2_xcpt_WIRE_cmd = 5'h0; // @[DCache.scala:933:74] wire [7:0] pma_checker__r_sectored_repl_addr_T_11 = 8'hFF; // @[TLB.scala:757:43] wire [7:0] metaArb_io_in_0_bits_way_en = 8'hFF; // @[DCache.scala:135:28] wire [7:0] dataArb_io_in_1_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_2_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_2_bits_way_en = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_way_en = 8'hFF; // @[DCache.scala:152:28] wire [7:0] _dataArb_io_in_3_bits_eccMask_T = 8'hFF; // @[DCache.scala:256:36] wire [7:0] _dataArb_io_in_3_bits_way_en_T = 8'hFF; // @[DCache.scala:257:35] wire [7:0] tl_out_a_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] tl_out_a_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] _dataArb_io_in_1_bits_eccMask_T = 8'hFF; // @[DCache.scala:732:38] wire [7:0] _dataArb_io_in_2_bits_eccMask_T = 8'hFF; // @[DCache.scala:905:36] wire [7:0] _dataArb_io_in_2_bits_way_en_T = 8'hFF; // @[DCache.scala:906:35] wire [7:0] _metaArb_io_in_0_bits_way_en_T = 8'hFF; // @[DCache.scala:1049:35] wire [2:0] pma_checker__r_sectored_repl_addr_T_20 = 3'h6; // @[Mux.scala:50:70] wire [2:0] tl_out_a_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] nodeOut_c_bits_c_opcode = 3'h6; // @[Edges.scala:380:17] wire [2:0] pma_checker_real_hits_lo_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_lo_hi = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_hi_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_special_entry_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_waddr_1 = 3'h0; // @[TLB.scala:485:22] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_state_vec_0_touch_way_sized = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38] wire [2:0] pma_checker__state_vec_0_T_10 = 3'h0; // @[Replacement.scala:203:16] wire [2:0] pma_checker__multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker__multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39] wire [2:0] pma_checker__multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker_r_sectored_repl_addr_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_r_sectored_repl_addr_right_subtree_state = 3'h0; // @[Replacement.scala:245:38] wire [2:0] pma_checker__r_sectored_repl_addr_T_9 = 3'h0; // @[Replacement.scala:249:12] wire [2:0] pma_checker__r_sectored_repl_addr_T_26 = 3'h0; // @[Mux.scala:50:70] wire [2:0] pma_checker__r_sectored_repl_addr_T_27 = 3'h0; // @[TLB.scala:757:8] wire [2:0] pma_checker__r_sectored_hit_bits_T_7 = 3'h0; // @[OneHot.scala:32:10] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] putpartial_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_param = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_1_opcode = 3'h0; // @[DCache.scala:587:38] wire [2:0] _atomics_WIRE_1_param = 3'h0; // @[DCache.scala:587:38] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] probe_bits_res_opcode = 3'h0; // @[DCache.scala:1202:19] wire [2:0] pma_checker__state_vec_0_T_9 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__state_vec_0_T_20 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__state_vec_0_T_21 = 3'h5; // @[Replacement.scala:206:16] wire [2:0] pma_checker__state_reg_T_8 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__r_sectored_repl_addr_T_21 = 3'h5; // @[Mux.scala:50:70] wire [2:0] nackResponseMessage_param = 3'h5; // @[Edges.scala:416:17] wire [2:0] dirtyReleaseMessage_opcode = 3'h5; // @[Edges.scala:433:17] wire [2:0] pma_checker__r_sectored_repl_addr_T_22 = 3'h4; // @[Mux.scala:50:70] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [2:0] nackResponseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [2:0] cleanReleaseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [1:0] pma_checker__r_superpage_repl_addr_T_11 = 2'h1; // @[Mux.scala:50:70] wire [1:0] _r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _metaArb_io_in_3_bits_data_T_6 = 2'h1; // @[Metadata.scala:25:15] wire [3:0] pma_checker__r_superpage_repl_addr_T_5 = 4'hF; // @[TLB.scala:757:43] wire [3:0] _r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] tl_out_a_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] tl_out_a_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] tl_out_a_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] tl_out_a_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [1:0] io_ptw_status_sxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] pma_checker_state_vec_0_hi = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker_state_vec_0_hi_1 = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker_state_reg_hi = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker__r_superpage_repl_addr_T_10 = 2'h2; // @[Mux.scala:50:70] wire [1:0] pma_checker__state_T = 2'h2; // @[TLB.scala:704:45] wire [1:0] _r_T_118 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_120 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_122 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] tl_out_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [2:0] pma_checker__r_sectored_repl_addr_T_23 = 3'h3; // @[Mux.scala:50:70] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] pma_checker__r_sectored_repl_addr_T_24 = 3'h2; // @[Mux.scala:50:70] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] pma_checker_mpu_priv = 3'h1; // @[TLB.scala:415:27] wire [2:0] pma_checker__r_sectored_repl_addr_T_25 = 3'h1; // @[Mux.scala:50:70] wire [2:0] putpartial_opcode = 3'h1; // @[Edges.scala:500:17] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [3:0] pma_checker_state_vec_0_hi_2 = 4'h8; // @[Replacement.scala:202:12] wire [3:0] _r_T_71 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_135 = 4'h8; // @[Metadata.scala:133:10] wire [11:0] pma_checker__gpa_hits_hit_mask_T_2 = 12'h0; // @[TLB.scala:606:24] wire [11:0] pma_checker__io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47] wire [26:0] pma_checker_io_ptw_req_bits_bits_addr = 27'h0; // @[DCache.scala:120:32] wire [26:0] pma_checker__io_resp_gpa_page_T_2 = 27'h0; // @[TLB.scala:657:58] wire [6:0] pma_checker__state_vec_0_T_22 = 7'h45; // @[Replacement.scala:202:12] wire [38:0] pma_checker_io_sfence_bits_addr = 39'h0; // @[DCache.scala:120:32] wire [38:0] pma_checker_io_ptw_resp_bits_gpa_bits = 39'h0; // @[DCache.scala:120:32] wire [39:0] io_tlb_port_req_bits_vaddr = 40'h0; // @[DCache.scala:101:7] wire [39:0] _io_cpu_s2_xcpt_WIRE_gpa = 40'h0; // @[DCache.scala:933:74] wire [21:0] pma_checker_special_entry_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] metaArb_io_in_0_bits_data = 22'h0; // @[DCache.scala:135:28] wire [21:0] _metaArb_io_in_0_bits_data_T = 22'h0; // @[DCache.scala:1050:85] wire [19:0] pma_checker_refill_ppn = 20'h0; // @[TLB.scala:406:44] wire [19:0] pma_checker_newEntry_ppn = 20'h0; // @[TLB.scala:449:24] wire [19:0] pma_checker__ppn_T_42 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_43 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_44 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_45 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_46 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_47 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_48 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_49 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_50 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_51 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_52 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_53 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_54 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_56 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_57 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_58 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_59 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_60 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_61 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_62 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_63 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_64 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_65 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_66 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_67 = 20'h0; // @[Mux.scala:30:73] wire [19:0] metaArb_io_in_0_bits_data_meta_1_tag = 20'h0; // @[HellaCache.scala:305:20] wire [31:0] pma_checker_io_ptw_status_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_gstatus_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_0_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_1_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_2_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_3_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_4_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_5_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_6_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_7_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] _atomics_WIRE_address = 32'h0; // @[DCache.scala:587:51] wire [31:0] _atomics_WIRE_1_address = 32'h0; // @[DCache.scala:587:38] wire [31:0] nodeOut_c_bits_c_address = 32'h0; // @[Edges.scala:380:17] wire [31:0] nodeOut_c_bits_c_1_address = 32'h0; // @[Edges.scala:396:17] wire [31:0] _io_cpu_s2_xcpt_WIRE_paddr = 32'h0; // @[DCache.scala:933:74] wire [3:0] _r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_65 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_129 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] tl_out_a_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [3:0] _release_state_T_13 = 4'h6; // @[DCache.scala:820:27] wire [3:0] nodeOut_c_bits_c_size = 4'h6; // @[Edges.scala:380:17] wire [3:0] nodeOut_c_bits_c_1_size = 4'h6; // @[Edges.scala:396:17] wire [127:0] get_data = 128'h0; // @[Edges.scala:460:17] wire [127:0] _atomics_WIRE_data = 128'h0; // @[DCache.scala:587:51] wire [127:0] _atomics_WIRE_1_data = 128'h0; // @[DCache.scala:587:38] wire [127:0] tl_out_a_bits_a_data = 128'h0; // @[Edges.scala:346:17] wire [127:0] nackResponseMessage_data = 128'h0; // @[Edges.scala:416:17] wire [127:0] cleanReleaseMessage_data = 128'h0; // @[Edges.scala:416:17] wire [127:0] dirtyReleaseMessage_data = 128'h0; // @[Edges.scala:433:17] wire [127:0] probe_bits_res_data = 128'h0; // @[DCache.scala:1202:19] wire [127:0] nodeOut_c_bits_c_data = 128'h0; // @[Edges.scala:380:17] wire [127:0] nodeOut_c_bits_c_1_data = 128'h0; // @[Edges.scala:396:17] wire [2:0] nodeOut_c_bits_c_1_opcode = 3'h7; // @[Edges.scala:396:17] wire [32:0] _nodeOut_c_bits_legal_T_27 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_28 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_29 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_61 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_62 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_63 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_23 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_24 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_57 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_58 = 33'h8000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_c_bits_legal_T_22 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _nodeOut_c_bits_legal_T_56 = 29'h8000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_13 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_14 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_47 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_48 = 33'hC000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_c_bits_legal_T_12 = 29'hC000000; // @[Parameters.scala:137:41] wire [28:0] _nodeOut_c_bits_legal_T_46 = 29'hC000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_8 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_9 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_42 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_43 = 33'h10000; // @[Parameters.scala:137:46] wire [17:0] _nodeOut_c_bits_legal_T_7 = 18'h10000; // @[Parameters.scala:137:41] wire [17:0] _nodeOut_c_bits_legal_T_41 = 18'h10000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_4 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_37 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_38 = 33'h0; // @[Parameters.scala:137:46] wire [3:0] _r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _metaArb_io_in_3_bits_data_T_9 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_67 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_131 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _metaArb_io_in_3_bits_data_T_7 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_62 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_126 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _metaArb_io_in_3_bits_data_T_3 = 4'h1; // @[Metadata.scala:86:10] wire [8:0] _s1_data_way_T_1 = 9'h100; // @[DCache.scala:694:32] wire [15:0] tl_out_a_bits_a_mask = 16'hFFFF; // @[Edges.scala:346:17] wire [15:0] _tl_out_a_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10] wire [3:0] _r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_66 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_130 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] tl_out_a_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [3:0] _r_T_70 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_134 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_69 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_133 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_68 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_132 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_64 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_128 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_61 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_125 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_60 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_124 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [13:0] pma_checker__gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] pma_checker_gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] pma_checker__gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] pma_checker_gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] pma_checker__gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] pma_checker_gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] pma_checker_gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] pma_checker__io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] pma_checker__io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] pma_checker__io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [6:0] pma_checker_real_hits_hi = 7'h0; // @[package.scala:45:27] wire [6:0] pma_checker__state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [6:0] pma_checker__multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39] wire [12:0] pma_checker_real_hits = 13'h0; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] pma_checker_stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] pma_checker__r_array_T_2 = 13'h0; // @[TLB.scala:520:74] wire [12:0] pma_checker__hr_array_T_2 = 13'h0; // @[TLB.scala:524:60] wire [12:0] pma_checker__gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [12:0] pma_checker__tlb_hit_T = 13'h0; // @[TLB.scala:611:28] wire [12:0] pma_checker__stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:68] wire [12:0] pma_checker__stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:95] wire [12:0] pma_checker_stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] pma_checker__hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] pma_checker__hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] pma_checker__hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] pma_checker__gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] pma_checker_gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] pma_checker__gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] pma_checker_gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [13:0] pma_checker_hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] pma_checker_hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] pma_checker_hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] pma_checker__must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] pma_checker__gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [30:0] pma_checker_special_entry_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_0_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_1_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_2_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_3_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_0_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_1_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_2_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_3_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_4_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_5_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_6_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_7_data_hi = 31'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_special_entry_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_0_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_1_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_2_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_3_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_0_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_1_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_2_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_3_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_4_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_5_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_6_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_7_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_special_entry_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [13:0] pma_checker_hits = 14'h2000; // @[TLB.scala:442:17] wire [9:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[DCache.scala:120:32] wire [31:0] _nodeOut_c_bits_legal_T_26 = 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _nodeOut_c_bits_legal_T_60 = 32'h80000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_11 = 28'hC000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_45 = 28'hC000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_21 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_55 = 28'h8000000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_c_bits_legal_T_6 = 17'h10000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_c_bits_legal_T_40 = 17'h10000; // @[Parameters.scala:137:31] wire [41:0] pma_checker__mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DCache.scala:101:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[DCache.scala:101:7] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[DCache.scala:101:7] wire [15:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[DCache.scala:101:7] wire [127:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[DCache.scala:101:7] wire nodeOut_c_ready = auto_out_c_ready_0; // @[DCache.scala:101:7] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DCache.scala:101:7] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DCache.scala:101:7] wire nodeOut_e_ready = auto_out_e_ready_0; // @[DCache.scala:101:7] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire metaArb_io_in_7_valid = io_cpu_req_valid_0; // @[DCache.scala:101:7, :135:28] wire [39:0] metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr_0; // @[DCache.scala:101:7, :135:28] wire [7:0] s0_req_tag = io_cpu_req_bits_tag_0; // @[DCache.scala:101:7, :192:24] wire [4:0] s0_req_cmd = io_cpu_req_bits_cmd_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_size = io_cpu_req_bits_size_0; // @[DCache.scala:101:7, :192:24] wire s0_req_signed = io_cpu_req_bits_signed_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_dprv = io_cpu_req_bits_dprv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_dv = io_cpu_req_bits_dv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_no_resp = io_cpu_req_bits_no_resp_0; // @[DCache.scala:101:7, :192:24] wire _io_cpu_s2_nack_T_5; // @[DCache.scala:445:86] wire _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:574:54] wire _io_cpu_s2_uncached_T_1; // @[DCache.scala:920:37] wire _io_cpu_resp_valid_T_2; // @[DCache.scala:949:70] wire [63:0] _io_cpu_resp_bits_data_T_24; // @[DCache.scala:974:41] wire s2_read; // @[Consts.scala:89:68] wire [63:0] _io_cpu_resp_bits_data_word_bypass_T_7; // @[AMOALU.scala:45:16] wire [63:0] s2_data_word; // @[DCache.scala:970:106] wire _io_cpu_replay_next_T_3; // @[DCache.scala:950:62] wire _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:933:24] wire _io_cpu_ordered_T_8; // @[DCache.scala:929:21] wire _io_cpu_store_pending_T_25; // @[DCache.scala:930:70] wire io_cpu_perf_acquire_done; // @[Edges.scala:233:22] wire io_cpu_perf_release_done; // @[Edges.scala:233:22] wire _io_cpu_perf_grant_T; // @[DCache.scala:1078:39] wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_T_1; // @[DCache.scala:1106:23] wire _io_cpu_perf_canAcceptStoreThenLoad_T_10; // @[DCache.scala:1088:41] wire _io_cpu_perf_canAcceptStoreThenRMW_T_1; // @[DCache.scala:1091:75] wire _io_cpu_perf_canAcceptLoadThenLoad_T_61; // @[DCache.scala:1092:40] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_7; // @[DCache.scala:1080:44] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_10; // @[DCache.scala:1084:45] wire _io_errors_bus_valid_T_2; // @[DCache.scala:1129:42] wire [2:0] auto_out_a_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_a_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_a_bits_size_0; // @[DCache.scala:101:7] wire auto_out_a_bits_source_0; // @[DCache.scala:101:7] wire [31:0] auto_out_a_bits_address_0; // @[DCache.scala:101:7] wire [15:0] auto_out_a_bits_mask_0; // @[DCache.scala:101:7] wire [127:0] auto_out_a_bits_data_0; // @[DCache.scala:101:7] wire auto_out_a_valid_0; // @[DCache.scala:101:7] wire auto_out_b_ready_0; // @[DCache.scala:101:7] wire [2:0] auto_out_c_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_c_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_c_bits_size_0; // @[DCache.scala:101:7] wire auto_out_c_bits_source_0; // @[DCache.scala:101:7] wire [31:0] auto_out_c_bits_address_0; // @[DCache.scala:101:7] wire [127:0] auto_out_c_bits_data_0; // @[DCache.scala:101:7] wire auto_out_c_valid_0; // @[DCache.scala:101:7] wire auto_out_d_ready_0; // @[DCache.scala:101:7] wire [3:0] auto_out_e_bits_sink_0; // @[DCache.scala:101:7] wire auto_out_e_valid_0; // @[DCache.scala:101:7] wire io_cpu_req_ready_0; // @[DCache.scala:101:7] wire [39:0] io_cpu_resp_bits_addr_0; // @[DCache.scala:101:7] wire [7:0] io_cpu_resp_bits_tag_0; // @[DCache.scala:101:7] wire [4:0] io_cpu_resp_bits_cmd_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_size_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_signed_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_dprv_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_dv_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_0; // @[DCache.scala:101:7] wire [7:0] io_cpu_resp_bits_mask_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_replay_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_has_data_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_word_bypass_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_raw_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_store_data_0; // @[DCache.scala:101:7] wire io_cpu_resp_valid_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_st_0; // @[DCache.scala:101:7] wire io_cpu_perf_acquire_0; // @[DCache.scala:101:7] wire io_cpu_perf_release_0; // @[DCache.scala:101:7] wire io_cpu_perf_grant_0; // @[DCache.scala:101:7] wire io_cpu_perf_tlbMiss_0; // @[DCache.scala:101:7] wire io_cpu_perf_blocked_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenRMW_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptLoadThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterStore_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_cause_raw_0; // @[DCache.scala:101:7] wire io_cpu_s2_uncached_0; // @[DCache.scala:101:7] wire [31:0] io_cpu_s2_paddr_0; // @[DCache.scala:101:7] wire io_cpu_replay_next_0; // @[DCache.scala:101:7] wire [39:0] io_cpu_s2_gpa_0; // @[DCache.scala:101:7] wire io_cpu_ordered_0; // @[DCache.scala:101:7] wire io_cpu_store_pending_0; // @[DCache.scala:101:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[DCache.scala:101:7] wire io_ptw_req_valid_0; // @[DCache.scala:101:7] wire io_errors_bus_valid; // @[DCache.scala:101:7] wire [31:0] io_errors_bus_bits; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_miss; // @[DCache.scala:101:7] wire [31:0] io_tlb_port_s1_resp_paddr; // @[DCache.scala:101:7] wire [39:0] io_tlb_port_s1_resp_gpa; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_cacheable; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_must_alloc; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_prefetchable; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_s1_resp_size; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_s1_resp_cmd; // @[DCache.scala:101:7] wire nodeOut_a_deq_ready = nodeOut_a_ready; // @[Decoupled.scala:356:21] wire nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DCache.scala:101:7] wire [3:0] nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DCache.scala:101:7] wire nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DCache.scala:101:7] wire [31:0] nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DCache.scala:101:7] wire [15:0] nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DCache.scala:101:7] wire [127:0] nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DCache.scala:101:7] wire _nodeOut_b_ready_T_4; // @[DCache.scala:770:44] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[DCache.scala:101:7] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[DCache.scala:101:7] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[DCache.scala:101:7] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[DCache.scala:101:7] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[DCache.scala:101:7] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[DCache.scala:101:7] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[DCache.scala:101:7] wire [127:0] s2_data_corrected; // @[package.scala:45:27] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[DCache.scala:101:7] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DCache.scala:101:7] wire uncachedRespIdxOH_shiftAmount = nodeOut_d_bits_source; // @[OneHot.scala:64:49] wire [3:0] nodeOut_e_bits_e_sink = nodeOut_d_bits_sink; // @[Edges.scala:451:17] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[DCache.scala:101:7] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_resp_size = pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [4:0] pma_checker_io_resp_cmd = pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [31:0] pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] wire pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire [39:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_v; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_st; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_resp_paddr; // @[DCache.scala:120:32] wire [39:0] pma_checker_io_resp_gpa; // @[DCache.scala:120:32] wire pma_checker_io_resp_cacheable; // @[DCache.scala:120:32] wire pma_checker_io_resp_must_alloc; // @[DCache.scala:120:32] wire pma_checker_io_resp_prefetchable; // @[DCache.scala:120:32] wire [26:0] pma_checker_vpn = pma_checker_io_req_bits_vaddr[38:12]; // @[TLB.scala:335:30] wire [26:0] pma_checker__mpu_ppn_T_24 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__mpu_ppn_T_28 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__sector_hits_T_3 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_11 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_19 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_27 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_35 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_43 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_51 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_59 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__superpage_hits_T = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_5 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_10 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_14 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_19 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_24 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_28 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_33 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_38 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_42 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_47 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_52 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_6 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_12 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_18 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_24 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_30 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_36 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_42 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_48 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_53 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_58 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_63 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_68 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_73 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_78 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_83 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_88 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_93 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_98 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_103 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_108 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_113 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_118 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__ppn_T_5 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_13 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_21 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_29 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_33 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_37 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire pma_checker_priv_s = pma_checker_io_req_bits_prv[0]; // @[TLB.scala:370:20] wire pma_checker_priv_uses_vm = ~(pma_checker_io_req_bits_prv[1]); // @[TLB.scala:372:27] wire [19:0] pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_1 = pma_checker__mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_fragmented_superpage = pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_2 = pma_checker__mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_c = pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_3 = pma_checker__mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_eff = pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_4 = pma_checker__mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_paa = pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_5 = pma_checker__mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pal = pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_6 = pma_checker__mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ppp = pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_7 = pma_checker__mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pr = pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_8 = pma_checker__mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_px = pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_9 = pma_checker__mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pw = pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_10 = pma_checker__mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hr = pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_11 = pma_checker__mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hx = pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_12 = pma_checker__mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hw = pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_13 = pma_checker__mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sr = pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_14 = pma_checker__mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sx = pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_15 = pma_checker__mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sw = pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_16 = pma_checker__mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_gf = pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_17 = pma_checker__mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pf = pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_18 = pma_checker__mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_stage2 = pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_19 = pma_checker__mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_final = pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_20 = pma_checker__mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_ptw = pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_21 = pma_checker__mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_g = pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_22 = pma_checker__mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_u = pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_23 = pma_checker__mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__mpu_ppn_WIRE_ppn = pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] pma_checker_mpu_ppn_res = _pma_checker_mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire [26:0] pma_checker__mpu_ppn_T_25 = {pma_checker__mpu_ppn_T_24[26:20], pma_checker__mpu_ppn_T_24[19:0] | _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__mpu_ppn_T_26 = pma_checker__mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__mpu_ppn_T_27 = {pma_checker_mpu_ppn_res, pma_checker__mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__mpu_ppn_T_29 = {pma_checker__mpu_ppn_T_28[26:20], pma_checker__mpu_ppn_T_28[19:0] | _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__mpu_ppn_T_30 = pma_checker__mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__mpu_ppn_T_31 = {pma_checker__mpu_ppn_T_27, pma_checker__mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] pma_checker__mpu_ppn_T_32 = pma_checker_io_req_bits_vaddr[39:12]; // @[TLB.scala:413:146] wire [27:0] pma_checker__mpu_ppn_T_33 = pma_checker__mpu_ppn_T_32; // @[TLB.scala:413:{20,146}] wire [27:0] pma_checker_mpu_ppn = pma_checker__mpu_ppn_T_33; // @[TLB.scala:412:20, :413:20] wire [11:0] pma_checker__mpu_physaddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52] wire [11:0] pma_checker__io_resp_paddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :652:46] wire [11:0] pma_checker__io_resp_gpa_offset_T_1 = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :658:82] wire [39:0] pma_checker_mpu_physaddr = {pma_checker_mpu_ppn, pma_checker__mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] pma_checker__homogeneous_T = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_67 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] pma_checker__deny_access_to_debug_T_1 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [2:0] pma_checker__mpu_priv_T_2 = {1'h0, pma_checker_io_req_bits_prv}; // @[TLB.scala:415:103] wire pma_checker_cacheable; // @[TLB.scala:425:41] wire pma_checker_newEntry_c = pma_checker_cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] pma_checker__homogeneous_T_1 = {1'h0, pma_checker__homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_2 = pma_checker__homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_3 = pma_checker__homogeneous_T_2; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_4 = pma_checker__homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_50 = pma_checker__homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN = {pma_checker_mpu_physaddr[39:14], pma_checker_mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_5; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_72; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_72 = _GEN; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_6 = {1'h0, pma_checker__homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_7 = pma_checker__homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_8 = pma_checker__homogeneous_T_7; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_9 = pma_checker__homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {pma_checker_mpu_physaddr[39:17], pma_checker_mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_10; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_60; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_60 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_77; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_77 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_109; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_109 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_116; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_116 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_11 = {1'h0, pma_checker__homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_12 = pma_checker__homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_13 = pma_checker__homogeneous_T_12; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_14 = pma_checker__homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_15 = {pma_checker_mpu_physaddr[39:21], pma_checker_mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_16 = {1'h0, pma_checker__homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_17 = pma_checker__homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_18 = pma_checker__homogeneous_T_17; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_19 = pma_checker__homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_20 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_21 = {1'h0, pma_checker__homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_22 = pma_checker__homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_23 = pma_checker__homogeneous_T_22; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_24 = pma_checker__homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_25 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_26 = {1'h0, pma_checker__homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_27 = pma_checker__homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_28 = pma_checker__homogeneous_T_27; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_29 = pma_checker__homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_30; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_30 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_82; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_82 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_97; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_97 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_31 = {1'h0, pma_checker__homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_32 = pma_checker__homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_33 = pma_checker__homogeneous_T_32; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_34 = pma_checker__homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_35 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_36 = {1'h0, pma_checker__homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_37 = pma_checker__homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_38 = pma_checker__homogeneous_T_37; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_39 = pma_checker__homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_40 = {pma_checker_mpu_physaddr[39:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_41 = {1'h0, pma_checker__homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_42 = pma_checker__homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_43 = pma_checker__homogeneous_T_42; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_44 = pma_checker__homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {pma_checker_mpu_physaddr[39:32], pma_checker_mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] pma_checker__homogeneous_T_45; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_45 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_87; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_87 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_102; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_102 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_46 = {1'h0, pma_checker__homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_47 = pma_checker__homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_48 = pma_checker__homogeneous_T_47; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_49 = pma_checker__homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_51 = pma_checker__homogeneous_T_50 | pma_checker__homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_52 = pma_checker__homogeneous_T_51 | pma_checker__homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_53 = pma_checker__homogeneous_T_52 | pma_checker__homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_54 = pma_checker__homogeneous_T_53 | pma_checker__homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_55 = pma_checker__homogeneous_T_54 | pma_checker__homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_56 = pma_checker__homogeneous_T_55 | pma_checker__homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_57 = pma_checker__homogeneous_T_56 | pma_checker__homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_58 = pma_checker__homogeneous_T_57 | pma_checker__homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire pma_checker_homogeneous = pma_checker__homogeneous_T_58 | pma_checker__homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] pma_checker__homogeneous_T_61 = {1'h0, pma_checker__homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_62 = pma_checker__homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_63 = pma_checker__homogeneous_T_62; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_64 = pma_checker__homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_65 = pma_checker__homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_66 = ~pma_checker__homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__homogeneous_T_68 = {1'h0, pma_checker__homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_69 = pma_checker__homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_70 = pma_checker__homogeneous_T_69; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_71 = pma_checker__homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_92 = pma_checker__homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_73 = {1'h0, pma_checker__homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_74 = pma_checker__homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_75 = pma_checker__homogeneous_T_74; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_76 = pma_checker__homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_78 = {1'h0, pma_checker__homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_79 = pma_checker__homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_80 = pma_checker__homogeneous_T_79; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_81 = pma_checker__homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_83 = {1'h0, pma_checker__homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_84 = pma_checker__homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_85 = pma_checker__homogeneous_T_84; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_86 = pma_checker__homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_88 = {1'h0, pma_checker__homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_89 = pma_checker__homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_90 = pma_checker__homogeneous_T_89; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_91 = pma_checker__homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_93 = pma_checker__homogeneous_T_92 | pma_checker__homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_94 = pma_checker__homogeneous_T_93 | pma_checker__homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_95 = pma_checker__homogeneous_T_94 | pma_checker__homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_96 = pma_checker__homogeneous_T_95 | pma_checker__homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_98 = {1'h0, pma_checker__homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_99 = pma_checker__homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_100 = pma_checker__homogeneous_T_99; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_101 = pma_checker__homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_107 = pma_checker__homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_103 = {1'h0, pma_checker__homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_104 = pma_checker__homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_105 = pma_checker__homogeneous_T_104; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_106 = pma_checker__homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_108 = pma_checker__homogeneous_T_107 | pma_checker__homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_110 = {1'h0, pma_checker__homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_111 = pma_checker__homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_112 = pma_checker__homogeneous_T_111; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_113 = pma_checker__homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_114 = pma_checker__homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_115 = ~pma_checker__homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__homogeneous_T_117 = {1'h0, pma_checker__homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_118 = pma_checker__homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_119 = pma_checker__homogeneous_T_118; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_120 = pma_checker__homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_121 = pma_checker__homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_122 = ~pma_checker__homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__deny_access_to_debug_T_2 = {1'h0, pma_checker__deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__deny_access_to_debug_T_3 = pma_checker__deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__deny_access_to_debug_T_4 = pma_checker__deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire pma_checker__deny_access_to_debug_T_5 = pma_checker__deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker_deny_access_to_debug = pma_checker__deny_access_to_debug_T_5; // @[TLB.scala:428:50] wire pma_checker__prot_r_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire pma_checker__prot_r_T_1 = _pma_checker_pma_io_resp_r & pma_checker__prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire pma_checker__prot_w_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire pma_checker__prot_w_T_1 = _pma_checker_pma_io_resp_w & pma_checker__prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire pma_checker__prot_x_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire pma_checker__prot_x_T_1 = _pma_checker_pma_io_resp_x & pma_checker__prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire [24:0] pma_checker__sector_hits_T_4 = pma_checker__sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_5 = pma_checker__sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_7 = pma_checker__sector_hits_T_5 & pma_checker__sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_12 = pma_checker__sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_13 = pma_checker__sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_15 = pma_checker__sector_hits_T_13 & pma_checker__sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_20 = pma_checker__sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_21 = pma_checker__sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_23 = pma_checker__sector_hits_T_21 & pma_checker__sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_28 = pma_checker__sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_29 = pma_checker__sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_31 = pma_checker__sector_hits_T_29 & pma_checker__sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_36 = pma_checker__sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_37 = pma_checker__sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_39 = pma_checker__sector_hits_T_37 & pma_checker__sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_44 = pma_checker__sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_45 = pma_checker__sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_47 = pma_checker__sector_hits_T_45 & pma_checker__sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_52 = pma_checker__sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_53 = pma_checker__sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_55 = pma_checker__sector_hits_T_53 & pma_checker__sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_60 = pma_checker__sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_61 = pma_checker__sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_63 = pma_checker__sector_hits_T_61 & pma_checker__sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire [8:0] pma_checker__superpage_hits_T_1 = pma_checker__superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_2 = pma_checker__superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_3 = pma_checker__superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_1 = pma_checker__superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_6 = pma_checker__superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_7 = pma_checker__superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_8 = pma_checker_superpage_hits_ignore_1 | pma_checker__superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_11 = pma_checker__superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_12 = pma_checker__superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_15 = pma_checker__superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_16 = pma_checker__superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_17 = pma_checker__superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_4 = pma_checker__superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_20 = pma_checker__superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_21 = pma_checker__superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_22 = pma_checker_superpage_hits_ignore_4 | pma_checker__superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_25 = pma_checker__superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_26 = pma_checker__superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_29 = pma_checker__superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_30 = pma_checker__superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_31 = pma_checker__superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_7 = pma_checker__superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_34 = pma_checker__superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_35 = pma_checker__superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_36 = pma_checker_superpage_hits_ignore_7 | pma_checker__superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_39 = pma_checker__superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_40 = pma_checker__superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_43 = pma_checker__superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_44 = pma_checker__superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_45 = pma_checker__superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_10 = pma_checker__superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_48 = pma_checker__superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_49 = pma_checker__superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_50 = pma_checker_superpage_hits_ignore_10 | pma_checker__superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_53 = pma_checker__superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_54 = pma_checker__superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] pma_checker_hitsVec_idx = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_1 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_2 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_3 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_4 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_5 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_6 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_7 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_24 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_48 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_72 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_96 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_120 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_144 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_168 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [24:0] pma_checker__hitsVec_T_1 = pma_checker__hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_2 = pma_checker__hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_4 = pma_checker__hitsVec_T_2 & pma_checker__hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_7 = pma_checker__hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_8 = pma_checker__hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_10 = pma_checker__hitsVec_T_8 & pma_checker__hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_13 = pma_checker__hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_14 = pma_checker__hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_16 = pma_checker__hitsVec_T_14 & pma_checker__hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_19 = pma_checker__hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_20 = pma_checker__hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_22 = pma_checker__hitsVec_T_20 & pma_checker__hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_25 = pma_checker__hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_26 = pma_checker__hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_28 = pma_checker__hitsVec_T_26 & pma_checker__hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_31 = pma_checker__hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_32 = pma_checker__hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_34 = pma_checker__hitsVec_T_32 & pma_checker__hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_37 = pma_checker__hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_38 = pma_checker__hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_40 = pma_checker__hitsVec_T_38 & pma_checker__hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_43 = pma_checker__hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_44 = pma_checker__hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_46 = pma_checker__hitsVec_T_44 & pma_checker__hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [8:0] pma_checker__hitsVec_T_49 = pma_checker__hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_50 = pma_checker__hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_51 = pma_checker__hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_1 = pma_checker__hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_54 = pma_checker__hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_55 = pma_checker__hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_56 = pma_checker_hitsVec_ignore_1 | pma_checker__hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_59 = pma_checker__hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_60 = pma_checker__hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_64 = pma_checker__hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_65 = pma_checker__hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_66 = pma_checker__hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_4 = pma_checker__hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_69 = pma_checker__hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_70 = pma_checker__hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_71 = pma_checker_hitsVec_ignore_4 | pma_checker__hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_74 = pma_checker__hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_75 = pma_checker__hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_79 = pma_checker__hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_80 = pma_checker__hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_81 = pma_checker__hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_7 = pma_checker__hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_84 = pma_checker__hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_85 = pma_checker__hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_86 = pma_checker_hitsVec_ignore_7 | pma_checker__hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_89 = pma_checker__hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_90 = pma_checker__hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_94 = pma_checker__hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_95 = pma_checker__hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_96 = pma_checker__hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_10 = pma_checker__hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_99 = pma_checker__hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_100 = pma_checker__hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_101 = pma_checker_hitsVec_ignore_10 | pma_checker__hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_104 = pma_checker__hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_105 = pma_checker__hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_109 = pma_checker__hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_110 = pma_checker__hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_111 = pma_checker__hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire [8:0] pma_checker__hitsVec_T_114 = pma_checker__hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_115 = pma_checker__hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_119 = pma_checker__hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_120 = pma_checker__hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker_newEntry_ppp; // @[TLB.scala:449:24] wire pma_checker_newEntry_pal; // @[TLB.scala:449:24] wire pma_checker_newEntry_paa; // @[TLB.scala:449:24] wire pma_checker_newEntry_eff; // @[TLB.scala:449:24] wire [1:0] _GEN_3 = {pma_checker_newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] _GEN_4 = {pma_checker_newEntry_pal, pma_checker_newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_lo_lo_hi = {pma_checker_special_entry_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_special_entry_data_0_lo_lo = {pma_checker_special_entry_data_0_lo_lo_hi, pma_checker_special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] _GEN_5 = {2'h0, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] pma_checker_special_entry_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [5:0] pma_checker_special_entry_data_0_lo_hi = {3'h0, pma_checker_special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_special_entry_data_0_lo = {pma_checker_special_entry_data_0_lo_hi, pma_checker_special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__special_entry_data_0_T = {31'h0, pma_checker_special_entry_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_0_data_0_lo_lo = {pma_checker_superpage_entries_0_data_0_lo_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_0_data_0_lo = {pma_checker_superpage_entries_0_data_0_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_0_data_0_T = {31'h0, pma_checker_superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_1_data_0_lo_lo = {pma_checker_superpage_entries_1_data_0_lo_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_1_data_0_lo = {pma_checker_superpage_entries_1_data_0_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_1_data_0_T = {31'h0, pma_checker_superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_2_data_0_lo_lo = {pma_checker_superpage_entries_2_data_0_lo_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_2_data_0_lo = {pma_checker_superpage_entries_2_data_0_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_2_data_0_T = {31'h0, pma_checker_superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_3_data_0_lo_lo = {pma_checker_superpage_entries_3_data_0_lo_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_3_data_0_lo = {pma_checker_superpage_entries_3_data_0_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_3_data_0_T = {31'h0, pma_checker_superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_0_data_lo_lo = {pma_checker_sectored_entries_0_0_data_lo_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_0_data_lo = {pma_checker_sectored_entries_0_0_data_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_0_data_T = {31'h0, pma_checker_sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_1_data_lo_lo = {pma_checker_sectored_entries_0_1_data_lo_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_1_data_lo = {pma_checker_sectored_entries_0_1_data_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_1_data_T = {31'h0, pma_checker_sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_2_data_lo_lo = {pma_checker_sectored_entries_0_2_data_lo_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_2_data_lo = {pma_checker_sectored_entries_0_2_data_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_2_data_T = {31'h0, pma_checker_sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_3_data_lo_lo = {pma_checker_sectored_entries_0_3_data_lo_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_3_data_lo = {pma_checker_sectored_entries_0_3_data_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_3_data_T = {31'h0, pma_checker_sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_4_data_lo_lo = {pma_checker_sectored_entries_0_4_data_lo_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_4_data_lo = {pma_checker_sectored_entries_0_4_data_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_4_data_T = {31'h0, pma_checker_sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_5_data_lo_lo = {pma_checker_sectored_entries_0_5_data_lo_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_5_data_lo = {pma_checker_sectored_entries_0_5_data_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_5_data_T = {31'h0, pma_checker_sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_6_data_lo_lo = {pma_checker_sectored_entries_0_6_data_lo_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_6_data_lo = {pma_checker_sectored_entries_0_6_data_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_6_data_T = {31'h0, pma_checker_sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_7_data_lo_lo = {pma_checker_sectored_entries_0_7_data_lo_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_7_data_lo = {pma_checker_sectored_entries_0_7_data_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_7_data_T = {31'h0, pma_checker_sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] pma_checker__entries_T_23; // @[TLB.scala:170:77] wire pma_checker__entries_T_22; // @[TLB.scala:170:77] wire pma_checker__entries_T_21; // @[TLB.scala:170:77] wire pma_checker__entries_T_20; // @[TLB.scala:170:77] wire pma_checker__entries_T_19; // @[TLB.scala:170:77] wire pma_checker__entries_T_18; // @[TLB.scala:170:77] wire pma_checker__entries_T_17; // @[TLB.scala:170:77] wire pma_checker__entries_T_16; // @[TLB.scala:170:77] wire pma_checker__entries_T_15; // @[TLB.scala:170:77] wire pma_checker__entries_T_14; // @[TLB.scala:170:77] wire pma_checker__entries_T_13; // @[TLB.scala:170:77] wire pma_checker__entries_T_12; // @[TLB.scala:170:77] wire pma_checker__entries_T_11; // @[TLB.scala:170:77] wire pma_checker__entries_T_10; // @[TLB.scala:170:77] wire pma_checker__entries_T_9; // @[TLB.scala:170:77] wire pma_checker__entries_T_8; // @[TLB.scala:170:77] wire pma_checker__entries_T_7; // @[TLB.scala:170:77] wire pma_checker__entries_T_6; // @[TLB.scala:170:77] wire pma_checker__entries_T_5; // @[TLB.scala:170:77] wire pma_checker__entries_T_4; // @[TLB.scala:170:77] wire pma_checker__entries_T_3; // @[TLB.scala:170:77] wire pma_checker__entries_T_2; // @[TLB.scala:170:77] wire pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_1 = pma_checker__entries_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_fragmented_superpage = pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_2 = pma_checker__entries_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_c = pma_checker__entries_T_2; // @[TLB.scala:170:77] assign pma_checker__entries_T_3 = pma_checker__entries_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_eff = pma_checker__entries_T_3; // @[TLB.scala:170:77] assign pma_checker__entries_T_4 = pma_checker__entries_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_paa = pma_checker__entries_T_4; // @[TLB.scala:170:77] assign pma_checker__entries_T_5 = pma_checker__entries_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pal = pma_checker__entries_T_5; // @[TLB.scala:170:77] assign pma_checker__entries_T_6 = pma_checker__entries_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ppp = pma_checker__entries_T_6; // @[TLB.scala:170:77] assign pma_checker__entries_T_7 = pma_checker__entries_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pr = pma_checker__entries_T_7; // @[TLB.scala:170:77] assign pma_checker__entries_T_8 = pma_checker__entries_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_px = pma_checker__entries_T_8; // @[TLB.scala:170:77] assign pma_checker__entries_T_9 = pma_checker__entries_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pw = pma_checker__entries_T_9; // @[TLB.scala:170:77] assign pma_checker__entries_T_10 = pma_checker__entries_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hr = pma_checker__entries_T_10; // @[TLB.scala:170:77] assign pma_checker__entries_T_11 = pma_checker__entries_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hx = pma_checker__entries_T_11; // @[TLB.scala:170:77] assign pma_checker__entries_T_12 = pma_checker__entries_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hw = pma_checker__entries_T_12; // @[TLB.scala:170:77] assign pma_checker__entries_T_13 = pma_checker__entries_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sr = pma_checker__entries_T_13; // @[TLB.scala:170:77] assign pma_checker__entries_T_14 = pma_checker__entries_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sx = pma_checker__entries_T_14; // @[TLB.scala:170:77] assign pma_checker__entries_T_15 = pma_checker__entries_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sw = pma_checker__entries_T_15; // @[TLB.scala:170:77] assign pma_checker__entries_T_16 = pma_checker__entries_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_gf = pma_checker__entries_T_16; // @[TLB.scala:170:77] assign pma_checker__entries_T_17 = pma_checker__entries_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pf = pma_checker__entries_T_17; // @[TLB.scala:170:77] assign pma_checker__entries_T_18 = pma_checker__entries_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_stage2 = pma_checker__entries_T_18; // @[TLB.scala:170:77] assign pma_checker__entries_T_19 = pma_checker__entries_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_final = pma_checker__entries_T_19; // @[TLB.scala:170:77] assign pma_checker__entries_T_20 = pma_checker__entries_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_ptw = pma_checker__entries_T_20; // @[TLB.scala:170:77] assign pma_checker__entries_T_21 = pma_checker__entries_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_g = pma_checker__entries_T_21; // @[TLB.scala:170:77] assign pma_checker__entries_T_22 = pma_checker__entries_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_u = pma_checker__entries_T_22; // @[TLB.scala:170:77] assign pma_checker__entries_T_23 = pma_checker__entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_ppn = pma_checker__entries_T_23; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_47; // @[TLB.scala:170:77] wire pma_checker__entries_T_46; // @[TLB.scala:170:77] wire pma_checker__entries_T_45; // @[TLB.scala:170:77] wire pma_checker__entries_T_44; // @[TLB.scala:170:77] wire pma_checker__entries_T_43; // @[TLB.scala:170:77] wire pma_checker__entries_T_42; // @[TLB.scala:170:77] wire pma_checker__entries_T_41; // @[TLB.scala:170:77] wire pma_checker__entries_T_40; // @[TLB.scala:170:77] wire pma_checker__entries_T_39; // @[TLB.scala:170:77] wire pma_checker__entries_T_38; // @[TLB.scala:170:77] wire pma_checker__entries_T_37; // @[TLB.scala:170:77] wire pma_checker__entries_T_36; // @[TLB.scala:170:77] wire pma_checker__entries_T_35; // @[TLB.scala:170:77] wire pma_checker__entries_T_34; // @[TLB.scala:170:77] wire pma_checker__entries_T_33; // @[TLB.scala:170:77] wire pma_checker__entries_T_32; // @[TLB.scala:170:77] wire pma_checker__entries_T_31; // @[TLB.scala:170:77] wire pma_checker__entries_T_30; // @[TLB.scala:170:77] wire pma_checker__entries_T_29; // @[TLB.scala:170:77] wire pma_checker__entries_T_28; // @[TLB.scala:170:77] wire pma_checker__entries_T_27; // @[TLB.scala:170:77] wire pma_checker__entries_T_26; // @[TLB.scala:170:77] wire pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_25 = pma_checker__entries_WIRE_3[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_fragmented_superpage = pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_26 = pma_checker__entries_WIRE_3[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_c = pma_checker__entries_T_26; // @[TLB.scala:170:77] assign pma_checker__entries_T_27 = pma_checker__entries_WIRE_3[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_eff = pma_checker__entries_T_27; // @[TLB.scala:170:77] assign pma_checker__entries_T_28 = pma_checker__entries_WIRE_3[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_paa = pma_checker__entries_T_28; // @[TLB.scala:170:77] assign pma_checker__entries_T_29 = pma_checker__entries_WIRE_3[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pal = pma_checker__entries_T_29; // @[TLB.scala:170:77] assign pma_checker__entries_T_30 = pma_checker__entries_WIRE_3[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ppp = pma_checker__entries_T_30; // @[TLB.scala:170:77] assign pma_checker__entries_T_31 = pma_checker__entries_WIRE_3[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pr = pma_checker__entries_T_31; // @[TLB.scala:170:77] assign pma_checker__entries_T_32 = pma_checker__entries_WIRE_3[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_px = pma_checker__entries_T_32; // @[TLB.scala:170:77] assign pma_checker__entries_T_33 = pma_checker__entries_WIRE_3[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pw = pma_checker__entries_T_33; // @[TLB.scala:170:77] assign pma_checker__entries_T_34 = pma_checker__entries_WIRE_3[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hr = pma_checker__entries_T_34; // @[TLB.scala:170:77] assign pma_checker__entries_T_35 = pma_checker__entries_WIRE_3[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hx = pma_checker__entries_T_35; // @[TLB.scala:170:77] assign pma_checker__entries_T_36 = pma_checker__entries_WIRE_3[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hw = pma_checker__entries_T_36; // @[TLB.scala:170:77] assign pma_checker__entries_T_37 = pma_checker__entries_WIRE_3[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sr = pma_checker__entries_T_37; // @[TLB.scala:170:77] assign pma_checker__entries_T_38 = pma_checker__entries_WIRE_3[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sx = pma_checker__entries_T_38; // @[TLB.scala:170:77] assign pma_checker__entries_T_39 = pma_checker__entries_WIRE_3[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sw = pma_checker__entries_T_39; // @[TLB.scala:170:77] assign pma_checker__entries_T_40 = pma_checker__entries_WIRE_3[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_gf = pma_checker__entries_T_40; // @[TLB.scala:170:77] assign pma_checker__entries_T_41 = pma_checker__entries_WIRE_3[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pf = pma_checker__entries_T_41; // @[TLB.scala:170:77] assign pma_checker__entries_T_42 = pma_checker__entries_WIRE_3[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_stage2 = pma_checker__entries_T_42; // @[TLB.scala:170:77] assign pma_checker__entries_T_43 = pma_checker__entries_WIRE_3[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_final = pma_checker__entries_T_43; // @[TLB.scala:170:77] assign pma_checker__entries_T_44 = pma_checker__entries_WIRE_3[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_ptw = pma_checker__entries_T_44; // @[TLB.scala:170:77] assign pma_checker__entries_T_45 = pma_checker__entries_WIRE_3[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_g = pma_checker__entries_T_45; // @[TLB.scala:170:77] assign pma_checker__entries_T_46 = pma_checker__entries_WIRE_3[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_u = pma_checker__entries_T_46; // @[TLB.scala:170:77] assign pma_checker__entries_T_47 = pma_checker__entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_2_ppn = pma_checker__entries_T_47; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_71; // @[TLB.scala:170:77] wire pma_checker__entries_T_70; // @[TLB.scala:170:77] wire pma_checker__entries_T_69; // @[TLB.scala:170:77] wire pma_checker__entries_T_68; // @[TLB.scala:170:77] wire pma_checker__entries_T_67; // @[TLB.scala:170:77] wire pma_checker__entries_T_66; // @[TLB.scala:170:77] wire pma_checker__entries_T_65; // @[TLB.scala:170:77] wire pma_checker__entries_T_64; // @[TLB.scala:170:77] wire pma_checker__entries_T_63; // @[TLB.scala:170:77] wire pma_checker__entries_T_62; // @[TLB.scala:170:77] wire pma_checker__entries_T_61; // @[TLB.scala:170:77] wire pma_checker__entries_T_60; // @[TLB.scala:170:77] wire pma_checker__entries_T_59; // @[TLB.scala:170:77] wire pma_checker__entries_T_58; // @[TLB.scala:170:77] wire pma_checker__entries_T_57; // @[TLB.scala:170:77] wire pma_checker__entries_T_56; // @[TLB.scala:170:77] wire pma_checker__entries_T_55; // @[TLB.scala:170:77] wire pma_checker__entries_T_54; // @[TLB.scala:170:77] wire pma_checker__entries_T_53; // @[TLB.scala:170:77] wire pma_checker__entries_T_52; // @[TLB.scala:170:77] wire pma_checker__entries_T_51; // @[TLB.scala:170:77] wire pma_checker__entries_T_50; // @[TLB.scala:170:77] wire pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_49 = pma_checker__entries_WIRE_5[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_fragmented_superpage = pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_50 = pma_checker__entries_WIRE_5[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_c = pma_checker__entries_T_50; // @[TLB.scala:170:77] assign pma_checker__entries_T_51 = pma_checker__entries_WIRE_5[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_eff = pma_checker__entries_T_51; // @[TLB.scala:170:77] assign pma_checker__entries_T_52 = pma_checker__entries_WIRE_5[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_paa = pma_checker__entries_T_52; // @[TLB.scala:170:77] assign pma_checker__entries_T_53 = pma_checker__entries_WIRE_5[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pal = pma_checker__entries_T_53; // @[TLB.scala:170:77] assign pma_checker__entries_T_54 = pma_checker__entries_WIRE_5[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ppp = pma_checker__entries_T_54; // @[TLB.scala:170:77] assign pma_checker__entries_T_55 = pma_checker__entries_WIRE_5[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pr = pma_checker__entries_T_55; // @[TLB.scala:170:77] assign pma_checker__entries_T_56 = pma_checker__entries_WIRE_5[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_px = pma_checker__entries_T_56; // @[TLB.scala:170:77] assign pma_checker__entries_T_57 = pma_checker__entries_WIRE_5[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pw = pma_checker__entries_T_57; // @[TLB.scala:170:77] assign pma_checker__entries_T_58 = pma_checker__entries_WIRE_5[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hr = pma_checker__entries_T_58; // @[TLB.scala:170:77] assign pma_checker__entries_T_59 = pma_checker__entries_WIRE_5[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hx = pma_checker__entries_T_59; // @[TLB.scala:170:77] assign pma_checker__entries_T_60 = pma_checker__entries_WIRE_5[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hw = pma_checker__entries_T_60; // @[TLB.scala:170:77] assign pma_checker__entries_T_61 = pma_checker__entries_WIRE_5[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sr = pma_checker__entries_T_61; // @[TLB.scala:170:77] assign pma_checker__entries_T_62 = pma_checker__entries_WIRE_5[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sx = pma_checker__entries_T_62; // @[TLB.scala:170:77] assign pma_checker__entries_T_63 = pma_checker__entries_WIRE_5[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sw = pma_checker__entries_T_63; // @[TLB.scala:170:77] assign pma_checker__entries_T_64 = pma_checker__entries_WIRE_5[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_gf = pma_checker__entries_T_64; // @[TLB.scala:170:77] assign pma_checker__entries_T_65 = pma_checker__entries_WIRE_5[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pf = pma_checker__entries_T_65; // @[TLB.scala:170:77] assign pma_checker__entries_T_66 = pma_checker__entries_WIRE_5[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_stage2 = pma_checker__entries_T_66; // @[TLB.scala:170:77] assign pma_checker__entries_T_67 = pma_checker__entries_WIRE_5[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_final = pma_checker__entries_T_67; // @[TLB.scala:170:77] assign pma_checker__entries_T_68 = pma_checker__entries_WIRE_5[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_ptw = pma_checker__entries_T_68; // @[TLB.scala:170:77] assign pma_checker__entries_T_69 = pma_checker__entries_WIRE_5[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_g = pma_checker__entries_T_69; // @[TLB.scala:170:77] assign pma_checker__entries_T_70 = pma_checker__entries_WIRE_5[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_u = pma_checker__entries_T_70; // @[TLB.scala:170:77] assign pma_checker__entries_T_71 = pma_checker__entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_4_ppn = pma_checker__entries_T_71; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_95; // @[TLB.scala:170:77] wire pma_checker__entries_T_94; // @[TLB.scala:170:77] wire pma_checker__entries_T_93; // @[TLB.scala:170:77] wire pma_checker__entries_T_92; // @[TLB.scala:170:77] wire pma_checker__entries_T_91; // @[TLB.scala:170:77] wire pma_checker__entries_T_90; // @[TLB.scala:170:77] wire pma_checker__entries_T_89; // @[TLB.scala:170:77] wire pma_checker__entries_T_88; // @[TLB.scala:170:77] wire pma_checker__entries_T_87; // @[TLB.scala:170:77] wire pma_checker__entries_T_86; // @[TLB.scala:170:77] wire pma_checker__entries_T_85; // @[TLB.scala:170:77] wire pma_checker__entries_T_84; // @[TLB.scala:170:77] wire pma_checker__entries_T_83; // @[TLB.scala:170:77] wire pma_checker__entries_T_82; // @[TLB.scala:170:77] wire pma_checker__entries_T_81; // @[TLB.scala:170:77] wire pma_checker__entries_T_80; // @[TLB.scala:170:77] wire pma_checker__entries_T_79; // @[TLB.scala:170:77] wire pma_checker__entries_T_78; // @[TLB.scala:170:77] wire pma_checker__entries_T_77; // @[TLB.scala:170:77] wire pma_checker__entries_T_76; // @[TLB.scala:170:77] wire pma_checker__entries_T_75; // @[TLB.scala:170:77] wire pma_checker__entries_T_74; // @[TLB.scala:170:77] wire pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_73 = pma_checker__entries_WIRE_7[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_fragmented_superpage = pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_74 = pma_checker__entries_WIRE_7[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_c = pma_checker__entries_T_74; // @[TLB.scala:170:77] assign pma_checker__entries_T_75 = pma_checker__entries_WIRE_7[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_eff = pma_checker__entries_T_75; // @[TLB.scala:170:77] assign pma_checker__entries_T_76 = pma_checker__entries_WIRE_7[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_paa = pma_checker__entries_T_76; // @[TLB.scala:170:77] assign pma_checker__entries_T_77 = pma_checker__entries_WIRE_7[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pal = pma_checker__entries_T_77; // @[TLB.scala:170:77] assign pma_checker__entries_T_78 = pma_checker__entries_WIRE_7[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ppp = pma_checker__entries_T_78; // @[TLB.scala:170:77] assign pma_checker__entries_T_79 = pma_checker__entries_WIRE_7[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pr = pma_checker__entries_T_79; // @[TLB.scala:170:77] assign pma_checker__entries_T_80 = pma_checker__entries_WIRE_7[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_px = pma_checker__entries_T_80; // @[TLB.scala:170:77] assign pma_checker__entries_T_81 = pma_checker__entries_WIRE_7[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pw = pma_checker__entries_T_81; // @[TLB.scala:170:77] assign pma_checker__entries_T_82 = pma_checker__entries_WIRE_7[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hr = pma_checker__entries_T_82; // @[TLB.scala:170:77] assign pma_checker__entries_T_83 = pma_checker__entries_WIRE_7[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hx = pma_checker__entries_T_83; // @[TLB.scala:170:77] assign pma_checker__entries_T_84 = pma_checker__entries_WIRE_7[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hw = pma_checker__entries_T_84; // @[TLB.scala:170:77] assign pma_checker__entries_T_85 = pma_checker__entries_WIRE_7[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sr = pma_checker__entries_T_85; // @[TLB.scala:170:77] assign pma_checker__entries_T_86 = pma_checker__entries_WIRE_7[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sx = pma_checker__entries_T_86; // @[TLB.scala:170:77] assign pma_checker__entries_T_87 = pma_checker__entries_WIRE_7[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sw = pma_checker__entries_T_87; // @[TLB.scala:170:77] assign pma_checker__entries_T_88 = pma_checker__entries_WIRE_7[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_gf = pma_checker__entries_T_88; // @[TLB.scala:170:77] assign pma_checker__entries_T_89 = pma_checker__entries_WIRE_7[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pf = pma_checker__entries_T_89; // @[TLB.scala:170:77] assign pma_checker__entries_T_90 = pma_checker__entries_WIRE_7[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_stage2 = pma_checker__entries_T_90; // @[TLB.scala:170:77] assign pma_checker__entries_T_91 = pma_checker__entries_WIRE_7[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_final = pma_checker__entries_T_91; // @[TLB.scala:170:77] assign pma_checker__entries_T_92 = pma_checker__entries_WIRE_7[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_ptw = pma_checker__entries_T_92; // @[TLB.scala:170:77] assign pma_checker__entries_T_93 = pma_checker__entries_WIRE_7[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_g = pma_checker__entries_T_93; // @[TLB.scala:170:77] assign pma_checker__entries_T_94 = pma_checker__entries_WIRE_7[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_u = pma_checker__entries_T_94; // @[TLB.scala:170:77] assign pma_checker__entries_T_95 = pma_checker__entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_6_ppn = pma_checker__entries_T_95; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_119; // @[TLB.scala:170:77] wire pma_checker__entries_T_118; // @[TLB.scala:170:77] wire pma_checker__entries_T_117; // @[TLB.scala:170:77] wire pma_checker__entries_T_116; // @[TLB.scala:170:77] wire pma_checker__entries_T_115; // @[TLB.scala:170:77] wire pma_checker__entries_T_114; // @[TLB.scala:170:77] wire pma_checker__entries_T_113; // @[TLB.scala:170:77] wire pma_checker__entries_T_112; // @[TLB.scala:170:77] wire pma_checker__entries_T_111; // @[TLB.scala:170:77] wire pma_checker__entries_T_110; // @[TLB.scala:170:77] wire pma_checker__entries_T_109; // @[TLB.scala:170:77] wire pma_checker__entries_T_108; // @[TLB.scala:170:77] wire pma_checker__entries_T_107; // @[TLB.scala:170:77] wire pma_checker__entries_T_106; // @[TLB.scala:170:77] wire pma_checker__entries_T_105; // @[TLB.scala:170:77] wire pma_checker__entries_T_104; // @[TLB.scala:170:77] wire pma_checker__entries_T_103; // @[TLB.scala:170:77] wire pma_checker__entries_T_102; // @[TLB.scala:170:77] wire pma_checker__entries_T_101; // @[TLB.scala:170:77] wire pma_checker__entries_T_100; // @[TLB.scala:170:77] wire pma_checker__entries_T_99; // @[TLB.scala:170:77] wire pma_checker__entries_T_98; // @[TLB.scala:170:77] wire pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_97 = pma_checker__entries_WIRE_9[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_fragmented_superpage = pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_98 = pma_checker__entries_WIRE_9[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_c = pma_checker__entries_T_98; // @[TLB.scala:170:77] assign pma_checker__entries_T_99 = pma_checker__entries_WIRE_9[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_eff = pma_checker__entries_T_99; // @[TLB.scala:170:77] assign pma_checker__entries_T_100 = pma_checker__entries_WIRE_9[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_paa = pma_checker__entries_T_100; // @[TLB.scala:170:77] assign pma_checker__entries_T_101 = pma_checker__entries_WIRE_9[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pal = pma_checker__entries_T_101; // @[TLB.scala:170:77] assign pma_checker__entries_T_102 = pma_checker__entries_WIRE_9[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ppp = pma_checker__entries_T_102; // @[TLB.scala:170:77] assign pma_checker__entries_T_103 = pma_checker__entries_WIRE_9[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pr = pma_checker__entries_T_103; // @[TLB.scala:170:77] assign pma_checker__entries_T_104 = pma_checker__entries_WIRE_9[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_px = pma_checker__entries_T_104; // @[TLB.scala:170:77] assign pma_checker__entries_T_105 = pma_checker__entries_WIRE_9[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pw = pma_checker__entries_T_105; // @[TLB.scala:170:77] assign pma_checker__entries_T_106 = pma_checker__entries_WIRE_9[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hr = pma_checker__entries_T_106; // @[TLB.scala:170:77] assign pma_checker__entries_T_107 = pma_checker__entries_WIRE_9[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hx = pma_checker__entries_T_107; // @[TLB.scala:170:77] assign pma_checker__entries_T_108 = pma_checker__entries_WIRE_9[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hw = pma_checker__entries_T_108; // @[TLB.scala:170:77] assign pma_checker__entries_T_109 = pma_checker__entries_WIRE_9[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sr = pma_checker__entries_T_109; // @[TLB.scala:170:77] assign pma_checker__entries_T_110 = pma_checker__entries_WIRE_9[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sx = pma_checker__entries_T_110; // @[TLB.scala:170:77] assign pma_checker__entries_T_111 = pma_checker__entries_WIRE_9[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sw = pma_checker__entries_T_111; // @[TLB.scala:170:77] assign pma_checker__entries_T_112 = pma_checker__entries_WIRE_9[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_gf = pma_checker__entries_T_112; // @[TLB.scala:170:77] assign pma_checker__entries_T_113 = pma_checker__entries_WIRE_9[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pf = pma_checker__entries_T_113; // @[TLB.scala:170:77] assign pma_checker__entries_T_114 = pma_checker__entries_WIRE_9[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_stage2 = pma_checker__entries_T_114; // @[TLB.scala:170:77] assign pma_checker__entries_T_115 = pma_checker__entries_WIRE_9[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_final = pma_checker__entries_T_115; // @[TLB.scala:170:77] assign pma_checker__entries_T_116 = pma_checker__entries_WIRE_9[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_ptw = pma_checker__entries_T_116; // @[TLB.scala:170:77] assign pma_checker__entries_T_117 = pma_checker__entries_WIRE_9[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_g = pma_checker__entries_T_117; // @[TLB.scala:170:77] assign pma_checker__entries_T_118 = pma_checker__entries_WIRE_9[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_u = pma_checker__entries_T_118; // @[TLB.scala:170:77] assign pma_checker__entries_T_119 = pma_checker__entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_8_ppn = pma_checker__entries_T_119; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_143; // @[TLB.scala:170:77] wire pma_checker__entries_T_142; // @[TLB.scala:170:77] wire pma_checker__entries_T_141; // @[TLB.scala:170:77] wire pma_checker__entries_T_140; // @[TLB.scala:170:77] wire pma_checker__entries_T_139; // @[TLB.scala:170:77] wire pma_checker__entries_T_138; // @[TLB.scala:170:77] wire pma_checker__entries_T_137; // @[TLB.scala:170:77] wire pma_checker__entries_T_136; // @[TLB.scala:170:77] wire pma_checker__entries_T_135; // @[TLB.scala:170:77] wire pma_checker__entries_T_134; // @[TLB.scala:170:77] wire pma_checker__entries_T_133; // @[TLB.scala:170:77] wire pma_checker__entries_T_132; // @[TLB.scala:170:77] wire pma_checker__entries_T_131; // @[TLB.scala:170:77] wire pma_checker__entries_T_130; // @[TLB.scala:170:77] wire pma_checker__entries_T_129; // @[TLB.scala:170:77] wire pma_checker__entries_T_128; // @[TLB.scala:170:77] wire pma_checker__entries_T_127; // @[TLB.scala:170:77] wire pma_checker__entries_T_126; // @[TLB.scala:170:77] wire pma_checker__entries_T_125; // @[TLB.scala:170:77] wire pma_checker__entries_T_124; // @[TLB.scala:170:77] wire pma_checker__entries_T_123; // @[TLB.scala:170:77] wire pma_checker__entries_T_122; // @[TLB.scala:170:77] wire pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_121 = pma_checker__entries_WIRE_11[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_fragmented_superpage = pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_122 = pma_checker__entries_WIRE_11[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_c = pma_checker__entries_T_122; // @[TLB.scala:170:77] assign pma_checker__entries_T_123 = pma_checker__entries_WIRE_11[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_eff = pma_checker__entries_T_123; // @[TLB.scala:170:77] assign pma_checker__entries_T_124 = pma_checker__entries_WIRE_11[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_paa = pma_checker__entries_T_124; // @[TLB.scala:170:77] assign pma_checker__entries_T_125 = pma_checker__entries_WIRE_11[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pal = pma_checker__entries_T_125; // @[TLB.scala:170:77] assign pma_checker__entries_T_126 = pma_checker__entries_WIRE_11[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ppp = pma_checker__entries_T_126; // @[TLB.scala:170:77] assign pma_checker__entries_T_127 = pma_checker__entries_WIRE_11[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pr = pma_checker__entries_T_127; // @[TLB.scala:170:77] assign pma_checker__entries_T_128 = pma_checker__entries_WIRE_11[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_px = pma_checker__entries_T_128; // @[TLB.scala:170:77] assign pma_checker__entries_T_129 = pma_checker__entries_WIRE_11[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pw = pma_checker__entries_T_129; // @[TLB.scala:170:77] assign pma_checker__entries_T_130 = pma_checker__entries_WIRE_11[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hr = pma_checker__entries_T_130; // @[TLB.scala:170:77] assign pma_checker__entries_T_131 = pma_checker__entries_WIRE_11[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hx = pma_checker__entries_T_131; // @[TLB.scala:170:77] assign pma_checker__entries_T_132 = pma_checker__entries_WIRE_11[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hw = pma_checker__entries_T_132; // @[TLB.scala:170:77] assign pma_checker__entries_T_133 = pma_checker__entries_WIRE_11[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sr = pma_checker__entries_T_133; // @[TLB.scala:170:77] assign pma_checker__entries_T_134 = pma_checker__entries_WIRE_11[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sx = pma_checker__entries_T_134; // @[TLB.scala:170:77] assign pma_checker__entries_T_135 = pma_checker__entries_WIRE_11[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sw = pma_checker__entries_T_135; // @[TLB.scala:170:77] assign pma_checker__entries_T_136 = pma_checker__entries_WIRE_11[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_gf = pma_checker__entries_T_136; // @[TLB.scala:170:77] assign pma_checker__entries_T_137 = pma_checker__entries_WIRE_11[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pf = pma_checker__entries_T_137; // @[TLB.scala:170:77] assign pma_checker__entries_T_138 = pma_checker__entries_WIRE_11[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_stage2 = pma_checker__entries_T_138; // @[TLB.scala:170:77] assign pma_checker__entries_T_139 = pma_checker__entries_WIRE_11[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_final = pma_checker__entries_T_139; // @[TLB.scala:170:77] assign pma_checker__entries_T_140 = pma_checker__entries_WIRE_11[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_ptw = pma_checker__entries_T_140; // @[TLB.scala:170:77] assign pma_checker__entries_T_141 = pma_checker__entries_WIRE_11[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_g = pma_checker__entries_T_141; // @[TLB.scala:170:77] assign pma_checker__entries_T_142 = pma_checker__entries_WIRE_11[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_u = pma_checker__entries_T_142; // @[TLB.scala:170:77] assign pma_checker__entries_T_143 = pma_checker__entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_10_ppn = pma_checker__entries_T_143; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_167; // @[TLB.scala:170:77] wire pma_checker__entries_T_166; // @[TLB.scala:170:77] wire pma_checker__entries_T_165; // @[TLB.scala:170:77] wire pma_checker__entries_T_164; // @[TLB.scala:170:77] wire pma_checker__entries_T_163; // @[TLB.scala:170:77] wire pma_checker__entries_T_162; // @[TLB.scala:170:77] wire pma_checker__entries_T_161; // @[TLB.scala:170:77] wire pma_checker__entries_T_160; // @[TLB.scala:170:77] wire pma_checker__entries_T_159; // @[TLB.scala:170:77] wire pma_checker__entries_T_158; // @[TLB.scala:170:77] wire pma_checker__entries_T_157; // @[TLB.scala:170:77] wire pma_checker__entries_T_156; // @[TLB.scala:170:77] wire pma_checker__entries_T_155; // @[TLB.scala:170:77] wire pma_checker__entries_T_154; // @[TLB.scala:170:77] wire pma_checker__entries_T_153; // @[TLB.scala:170:77] wire pma_checker__entries_T_152; // @[TLB.scala:170:77] wire pma_checker__entries_T_151; // @[TLB.scala:170:77] wire pma_checker__entries_T_150; // @[TLB.scala:170:77] wire pma_checker__entries_T_149; // @[TLB.scala:170:77] wire pma_checker__entries_T_148; // @[TLB.scala:170:77] wire pma_checker__entries_T_147; // @[TLB.scala:170:77] wire pma_checker__entries_T_146; // @[TLB.scala:170:77] wire pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_145 = pma_checker__entries_WIRE_13[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_fragmented_superpage = pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_146 = pma_checker__entries_WIRE_13[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_c = pma_checker__entries_T_146; // @[TLB.scala:170:77] assign pma_checker__entries_T_147 = pma_checker__entries_WIRE_13[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_eff = pma_checker__entries_T_147; // @[TLB.scala:170:77] assign pma_checker__entries_T_148 = pma_checker__entries_WIRE_13[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_paa = pma_checker__entries_T_148; // @[TLB.scala:170:77] assign pma_checker__entries_T_149 = pma_checker__entries_WIRE_13[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pal = pma_checker__entries_T_149; // @[TLB.scala:170:77] assign pma_checker__entries_T_150 = pma_checker__entries_WIRE_13[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ppp = pma_checker__entries_T_150; // @[TLB.scala:170:77] assign pma_checker__entries_T_151 = pma_checker__entries_WIRE_13[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pr = pma_checker__entries_T_151; // @[TLB.scala:170:77] assign pma_checker__entries_T_152 = pma_checker__entries_WIRE_13[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_px = pma_checker__entries_T_152; // @[TLB.scala:170:77] assign pma_checker__entries_T_153 = pma_checker__entries_WIRE_13[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pw = pma_checker__entries_T_153; // @[TLB.scala:170:77] assign pma_checker__entries_T_154 = pma_checker__entries_WIRE_13[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hr = pma_checker__entries_T_154; // @[TLB.scala:170:77] assign pma_checker__entries_T_155 = pma_checker__entries_WIRE_13[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hx = pma_checker__entries_T_155; // @[TLB.scala:170:77] assign pma_checker__entries_T_156 = pma_checker__entries_WIRE_13[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hw = pma_checker__entries_T_156; // @[TLB.scala:170:77] assign pma_checker__entries_T_157 = pma_checker__entries_WIRE_13[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sr = pma_checker__entries_T_157; // @[TLB.scala:170:77] assign pma_checker__entries_T_158 = pma_checker__entries_WIRE_13[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sx = pma_checker__entries_T_158; // @[TLB.scala:170:77] assign pma_checker__entries_T_159 = pma_checker__entries_WIRE_13[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sw = pma_checker__entries_T_159; // @[TLB.scala:170:77] assign pma_checker__entries_T_160 = pma_checker__entries_WIRE_13[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_gf = pma_checker__entries_T_160; // @[TLB.scala:170:77] assign pma_checker__entries_T_161 = pma_checker__entries_WIRE_13[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pf = pma_checker__entries_T_161; // @[TLB.scala:170:77] assign pma_checker__entries_T_162 = pma_checker__entries_WIRE_13[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_stage2 = pma_checker__entries_T_162; // @[TLB.scala:170:77] assign pma_checker__entries_T_163 = pma_checker__entries_WIRE_13[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_final = pma_checker__entries_T_163; // @[TLB.scala:170:77] assign pma_checker__entries_T_164 = pma_checker__entries_WIRE_13[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_ptw = pma_checker__entries_T_164; // @[TLB.scala:170:77] assign pma_checker__entries_T_165 = pma_checker__entries_WIRE_13[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_g = pma_checker__entries_T_165; // @[TLB.scala:170:77] assign pma_checker__entries_T_166 = pma_checker__entries_WIRE_13[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_u = pma_checker__entries_T_166; // @[TLB.scala:170:77] assign pma_checker__entries_T_167 = pma_checker__entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_12_ppn = pma_checker__entries_T_167; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_191; // @[TLB.scala:170:77] wire pma_checker__entries_T_190; // @[TLB.scala:170:77] wire pma_checker__entries_T_189; // @[TLB.scala:170:77] wire pma_checker__entries_T_188; // @[TLB.scala:170:77] wire pma_checker__entries_T_187; // @[TLB.scala:170:77] wire pma_checker__entries_T_186; // @[TLB.scala:170:77] wire pma_checker__entries_T_185; // @[TLB.scala:170:77] wire pma_checker__entries_T_184; // @[TLB.scala:170:77] wire pma_checker__entries_T_183; // @[TLB.scala:170:77] wire pma_checker__entries_T_182; // @[TLB.scala:170:77] wire pma_checker__entries_T_181; // @[TLB.scala:170:77] wire pma_checker__entries_T_180; // @[TLB.scala:170:77] wire pma_checker__entries_T_179; // @[TLB.scala:170:77] wire pma_checker__entries_T_178; // @[TLB.scala:170:77] wire pma_checker__entries_T_177; // @[TLB.scala:170:77] wire pma_checker__entries_T_176; // @[TLB.scala:170:77] wire pma_checker__entries_T_175; // @[TLB.scala:170:77] wire pma_checker__entries_T_174; // @[TLB.scala:170:77] wire pma_checker__entries_T_173; // @[TLB.scala:170:77] wire pma_checker__entries_T_172; // @[TLB.scala:170:77] wire pma_checker__entries_T_171; // @[TLB.scala:170:77] wire pma_checker__entries_T_170; // @[TLB.scala:170:77] wire pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_169 = pma_checker__entries_WIRE_15[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_fragmented_superpage = pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_170 = pma_checker__entries_WIRE_15[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_c = pma_checker__entries_T_170; // @[TLB.scala:170:77] assign pma_checker__entries_T_171 = pma_checker__entries_WIRE_15[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_eff = pma_checker__entries_T_171; // @[TLB.scala:170:77] assign pma_checker__entries_T_172 = pma_checker__entries_WIRE_15[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_paa = pma_checker__entries_T_172; // @[TLB.scala:170:77] assign pma_checker__entries_T_173 = pma_checker__entries_WIRE_15[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pal = pma_checker__entries_T_173; // @[TLB.scala:170:77] assign pma_checker__entries_T_174 = pma_checker__entries_WIRE_15[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ppp = pma_checker__entries_T_174; // @[TLB.scala:170:77] assign pma_checker__entries_T_175 = pma_checker__entries_WIRE_15[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pr = pma_checker__entries_T_175; // @[TLB.scala:170:77] assign pma_checker__entries_T_176 = pma_checker__entries_WIRE_15[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_px = pma_checker__entries_T_176; // @[TLB.scala:170:77] assign pma_checker__entries_T_177 = pma_checker__entries_WIRE_15[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pw = pma_checker__entries_T_177; // @[TLB.scala:170:77] assign pma_checker__entries_T_178 = pma_checker__entries_WIRE_15[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hr = pma_checker__entries_T_178; // @[TLB.scala:170:77] assign pma_checker__entries_T_179 = pma_checker__entries_WIRE_15[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hx = pma_checker__entries_T_179; // @[TLB.scala:170:77] assign pma_checker__entries_T_180 = pma_checker__entries_WIRE_15[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hw = pma_checker__entries_T_180; // @[TLB.scala:170:77] assign pma_checker__entries_T_181 = pma_checker__entries_WIRE_15[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sr = pma_checker__entries_T_181; // @[TLB.scala:170:77] assign pma_checker__entries_T_182 = pma_checker__entries_WIRE_15[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sx = pma_checker__entries_T_182; // @[TLB.scala:170:77] assign pma_checker__entries_T_183 = pma_checker__entries_WIRE_15[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sw = pma_checker__entries_T_183; // @[TLB.scala:170:77] assign pma_checker__entries_T_184 = pma_checker__entries_WIRE_15[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_gf = pma_checker__entries_T_184; // @[TLB.scala:170:77] assign pma_checker__entries_T_185 = pma_checker__entries_WIRE_15[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pf = pma_checker__entries_T_185; // @[TLB.scala:170:77] assign pma_checker__entries_T_186 = pma_checker__entries_WIRE_15[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_stage2 = pma_checker__entries_T_186; // @[TLB.scala:170:77] assign pma_checker__entries_T_187 = pma_checker__entries_WIRE_15[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_final = pma_checker__entries_T_187; // @[TLB.scala:170:77] assign pma_checker__entries_T_188 = pma_checker__entries_WIRE_15[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_ptw = pma_checker__entries_T_188; // @[TLB.scala:170:77] assign pma_checker__entries_T_189 = pma_checker__entries_WIRE_15[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_g = pma_checker__entries_T_189; // @[TLB.scala:170:77] assign pma_checker__entries_T_190 = pma_checker__entries_WIRE_15[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_u = pma_checker__entries_T_190; // @[TLB.scala:170:77] assign pma_checker__entries_T_191 = pma_checker__entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_14_ppn = pma_checker__entries_T_191; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_214; // @[TLB.scala:170:77] wire pma_checker__entries_T_213; // @[TLB.scala:170:77] wire pma_checker__entries_T_212; // @[TLB.scala:170:77] wire pma_checker__entries_T_211; // @[TLB.scala:170:77] wire pma_checker__entries_T_210; // @[TLB.scala:170:77] wire pma_checker__entries_T_209; // @[TLB.scala:170:77] wire pma_checker__entries_T_208; // @[TLB.scala:170:77] wire pma_checker__entries_T_207; // @[TLB.scala:170:77] wire pma_checker__entries_T_206; // @[TLB.scala:170:77] wire pma_checker__entries_T_205; // @[TLB.scala:170:77] wire pma_checker__entries_T_204; // @[TLB.scala:170:77] wire pma_checker__entries_T_203; // @[TLB.scala:170:77] wire pma_checker__entries_T_202; // @[TLB.scala:170:77] wire pma_checker__entries_T_201; // @[TLB.scala:170:77] wire pma_checker__entries_T_200; // @[TLB.scala:170:77] wire pma_checker__entries_T_199; // @[TLB.scala:170:77] wire pma_checker__entries_T_198; // @[TLB.scala:170:77] wire pma_checker__entries_T_197; // @[TLB.scala:170:77] wire pma_checker__entries_T_196; // @[TLB.scala:170:77] wire pma_checker__entries_T_195; // @[TLB.scala:170:77] wire pma_checker__entries_T_194; // @[TLB.scala:170:77] wire pma_checker__entries_T_193; // @[TLB.scala:170:77] wire pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_192 = pma_checker__entries_WIRE_17[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_fragmented_superpage = pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_193 = pma_checker__entries_WIRE_17[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_c = pma_checker__entries_T_193; // @[TLB.scala:170:77] assign pma_checker__entries_T_194 = pma_checker__entries_WIRE_17[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_eff = pma_checker__entries_T_194; // @[TLB.scala:170:77] assign pma_checker__entries_T_195 = pma_checker__entries_WIRE_17[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_paa = pma_checker__entries_T_195; // @[TLB.scala:170:77] assign pma_checker__entries_T_196 = pma_checker__entries_WIRE_17[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pal = pma_checker__entries_T_196; // @[TLB.scala:170:77] assign pma_checker__entries_T_197 = pma_checker__entries_WIRE_17[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ppp = pma_checker__entries_T_197; // @[TLB.scala:170:77] assign pma_checker__entries_T_198 = pma_checker__entries_WIRE_17[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pr = pma_checker__entries_T_198; // @[TLB.scala:170:77] assign pma_checker__entries_T_199 = pma_checker__entries_WIRE_17[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_px = pma_checker__entries_T_199; // @[TLB.scala:170:77] assign pma_checker__entries_T_200 = pma_checker__entries_WIRE_17[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pw = pma_checker__entries_T_200; // @[TLB.scala:170:77] assign pma_checker__entries_T_201 = pma_checker__entries_WIRE_17[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hr = pma_checker__entries_T_201; // @[TLB.scala:170:77] assign pma_checker__entries_T_202 = pma_checker__entries_WIRE_17[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hx = pma_checker__entries_T_202; // @[TLB.scala:170:77] assign pma_checker__entries_T_203 = pma_checker__entries_WIRE_17[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hw = pma_checker__entries_T_203; // @[TLB.scala:170:77] assign pma_checker__entries_T_204 = pma_checker__entries_WIRE_17[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sr = pma_checker__entries_T_204; // @[TLB.scala:170:77] assign pma_checker__entries_T_205 = pma_checker__entries_WIRE_17[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sx = pma_checker__entries_T_205; // @[TLB.scala:170:77] assign pma_checker__entries_T_206 = pma_checker__entries_WIRE_17[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sw = pma_checker__entries_T_206; // @[TLB.scala:170:77] assign pma_checker__entries_T_207 = pma_checker__entries_WIRE_17[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_gf = pma_checker__entries_T_207; // @[TLB.scala:170:77] assign pma_checker__entries_T_208 = pma_checker__entries_WIRE_17[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pf = pma_checker__entries_T_208; // @[TLB.scala:170:77] assign pma_checker__entries_T_209 = pma_checker__entries_WIRE_17[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_stage2 = pma_checker__entries_T_209; // @[TLB.scala:170:77] assign pma_checker__entries_T_210 = pma_checker__entries_WIRE_17[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_final = pma_checker__entries_T_210; // @[TLB.scala:170:77] assign pma_checker__entries_T_211 = pma_checker__entries_WIRE_17[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_ptw = pma_checker__entries_T_211; // @[TLB.scala:170:77] assign pma_checker__entries_T_212 = pma_checker__entries_WIRE_17[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_g = pma_checker__entries_T_212; // @[TLB.scala:170:77] assign pma_checker__entries_T_213 = pma_checker__entries_WIRE_17[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_u = pma_checker__entries_T_213; // @[TLB.scala:170:77] assign pma_checker__entries_T_214 = pma_checker__entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_16_ppn = pma_checker__entries_T_214; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_237; // @[TLB.scala:170:77] wire pma_checker__entries_T_236; // @[TLB.scala:170:77] wire pma_checker__entries_T_235; // @[TLB.scala:170:77] wire pma_checker__entries_T_234; // @[TLB.scala:170:77] wire pma_checker__entries_T_233; // @[TLB.scala:170:77] wire pma_checker__entries_T_232; // @[TLB.scala:170:77] wire pma_checker__entries_T_231; // @[TLB.scala:170:77] wire pma_checker__entries_T_230; // @[TLB.scala:170:77] wire pma_checker__entries_T_229; // @[TLB.scala:170:77] wire pma_checker__entries_T_228; // @[TLB.scala:170:77] wire pma_checker__entries_T_227; // @[TLB.scala:170:77] wire pma_checker__entries_T_226; // @[TLB.scala:170:77] wire pma_checker__entries_T_225; // @[TLB.scala:170:77] wire pma_checker__entries_T_224; // @[TLB.scala:170:77] wire pma_checker__entries_T_223; // @[TLB.scala:170:77] wire pma_checker__entries_T_222; // @[TLB.scala:170:77] wire pma_checker__entries_T_221; // @[TLB.scala:170:77] wire pma_checker__entries_T_220; // @[TLB.scala:170:77] wire pma_checker__entries_T_219; // @[TLB.scala:170:77] wire pma_checker__entries_T_218; // @[TLB.scala:170:77] wire pma_checker__entries_T_217; // @[TLB.scala:170:77] wire pma_checker__entries_T_216; // @[TLB.scala:170:77] wire pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_215 = pma_checker__entries_WIRE_19[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_fragmented_superpage = pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_216 = pma_checker__entries_WIRE_19[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_c = pma_checker__entries_T_216; // @[TLB.scala:170:77] assign pma_checker__entries_T_217 = pma_checker__entries_WIRE_19[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_eff = pma_checker__entries_T_217; // @[TLB.scala:170:77] assign pma_checker__entries_T_218 = pma_checker__entries_WIRE_19[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_paa = pma_checker__entries_T_218; // @[TLB.scala:170:77] assign pma_checker__entries_T_219 = pma_checker__entries_WIRE_19[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pal = pma_checker__entries_T_219; // @[TLB.scala:170:77] assign pma_checker__entries_T_220 = pma_checker__entries_WIRE_19[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ppp = pma_checker__entries_T_220; // @[TLB.scala:170:77] assign pma_checker__entries_T_221 = pma_checker__entries_WIRE_19[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pr = pma_checker__entries_T_221; // @[TLB.scala:170:77] assign pma_checker__entries_T_222 = pma_checker__entries_WIRE_19[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_px = pma_checker__entries_T_222; // @[TLB.scala:170:77] assign pma_checker__entries_T_223 = pma_checker__entries_WIRE_19[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pw = pma_checker__entries_T_223; // @[TLB.scala:170:77] assign pma_checker__entries_T_224 = pma_checker__entries_WIRE_19[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hr = pma_checker__entries_T_224; // @[TLB.scala:170:77] assign pma_checker__entries_T_225 = pma_checker__entries_WIRE_19[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hx = pma_checker__entries_T_225; // @[TLB.scala:170:77] assign pma_checker__entries_T_226 = pma_checker__entries_WIRE_19[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hw = pma_checker__entries_T_226; // @[TLB.scala:170:77] assign pma_checker__entries_T_227 = pma_checker__entries_WIRE_19[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sr = pma_checker__entries_T_227; // @[TLB.scala:170:77] assign pma_checker__entries_T_228 = pma_checker__entries_WIRE_19[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sx = pma_checker__entries_T_228; // @[TLB.scala:170:77] assign pma_checker__entries_T_229 = pma_checker__entries_WIRE_19[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sw = pma_checker__entries_T_229; // @[TLB.scala:170:77] assign pma_checker__entries_T_230 = pma_checker__entries_WIRE_19[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_gf = pma_checker__entries_T_230; // @[TLB.scala:170:77] assign pma_checker__entries_T_231 = pma_checker__entries_WIRE_19[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pf = pma_checker__entries_T_231; // @[TLB.scala:170:77] assign pma_checker__entries_T_232 = pma_checker__entries_WIRE_19[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_stage2 = pma_checker__entries_T_232; // @[TLB.scala:170:77] assign pma_checker__entries_T_233 = pma_checker__entries_WIRE_19[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_final = pma_checker__entries_T_233; // @[TLB.scala:170:77] assign pma_checker__entries_T_234 = pma_checker__entries_WIRE_19[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_ptw = pma_checker__entries_T_234; // @[TLB.scala:170:77] assign pma_checker__entries_T_235 = pma_checker__entries_WIRE_19[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_g = pma_checker__entries_T_235; // @[TLB.scala:170:77] assign pma_checker__entries_T_236 = pma_checker__entries_WIRE_19[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_u = pma_checker__entries_T_236; // @[TLB.scala:170:77] assign pma_checker__entries_T_237 = pma_checker__entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_18_ppn = pma_checker__entries_T_237; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_260; // @[TLB.scala:170:77] wire pma_checker__entries_T_259; // @[TLB.scala:170:77] wire pma_checker__entries_T_258; // @[TLB.scala:170:77] wire pma_checker__entries_T_257; // @[TLB.scala:170:77] wire pma_checker__entries_T_256; // @[TLB.scala:170:77] wire pma_checker__entries_T_255; // @[TLB.scala:170:77] wire pma_checker__entries_T_254; // @[TLB.scala:170:77] wire pma_checker__entries_T_253; // @[TLB.scala:170:77] wire pma_checker__entries_T_252; // @[TLB.scala:170:77] wire pma_checker__entries_T_251; // @[TLB.scala:170:77] wire pma_checker__entries_T_250; // @[TLB.scala:170:77] wire pma_checker__entries_T_249; // @[TLB.scala:170:77] wire pma_checker__entries_T_248; // @[TLB.scala:170:77] wire pma_checker__entries_T_247; // @[TLB.scala:170:77] wire pma_checker__entries_T_246; // @[TLB.scala:170:77] wire pma_checker__entries_T_245; // @[TLB.scala:170:77] wire pma_checker__entries_T_244; // @[TLB.scala:170:77] wire pma_checker__entries_T_243; // @[TLB.scala:170:77] wire pma_checker__entries_T_242; // @[TLB.scala:170:77] wire pma_checker__entries_T_241; // @[TLB.scala:170:77] wire pma_checker__entries_T_240; // @[TLB.scala:170:77] wire pma_checker__entries_T_239; // @[TLB.scala:170:77] wire pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_238 = pma_checker__entries_WIRE_21[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_fragmented_superpage = pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_239 = pma_checker__entries_WIRE_21[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_c = pma_checker__entries_T_239; // @[TLB.scala:170:77] assign pma_checker__entries_T_240 = pma_checker__entries_WIRE_21[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_eff = pma_checker__entries_T_240; // @[TLB.scala:170:77] assign pma_checker__entries_T_241 = pma_checker__entries_WIRE_21[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_paa = pma_checker__entries_T_241; // @[TLB.scala:170:77] assign pma_checker__entries_T_242 = pma_checker__entries_WIRE_21[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pal = pma_checker__entries_T_242; // @[TLB.scala:170:77] assign pma_checker__entries_T_243 = pma_checker__entries_WIRE_21[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ppp = pma_checker__entries_T_243; // @[TLB.scala:170:77] assign pma_checker__entries_T_244 = pma_checker__entries_WIRE_21[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pr = pma_checker__entries_T_244; // @[TLB.scala:170:77] assign pma_checker__entries_T_245 = pma_checker__entries_WIRE_21[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_px = pma_checker__entries_T_245; // @[TLB.scala:170:77] assign pma_checker__entries_T_246 = pma_checker__entries_WIRE_21[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pw = pma_checker__entries_T_246; // @[TLB.scala:170:77] assign pma_checker__entries_T_247 = pma_checker__entries_WIRE_21[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hr = pma_checker__entries_T_247; // @[TLB.scala:170:77] assign pma_checker__entries_T_248 = pma_checker__entries_WIRE_21[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hx = pma_checker__entries_T_248; // @[TLB.scala:170:77] assign pma_checker__entries_T_249 = pma_checker__entries_WIRE_21[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hw = pma_checker__entries_T_249; // @[TLB.scala:170:77] assign pma_checker__entries_T_250 = pma_checker__entries_WIRE_21[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sr = pma_checker__entries_T_250; // @[TLB.scala:170:77] assign pma_checker__entries_T_251 = pma_checker__entries_WIRE_21[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sx = pma_checker__entries_T_251; // @[TLB.scala:170:77] assign pma_checker__entries_T_252 = pma_checker__entries_WIRE_21[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sw = pma_checker__entries_T_252; // @[TLB.scala:170:77] assign pma_checker__entries_T_253 = pma_checker__entries_WIRE_21[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_gf = pma_checker__entries_T_253; // @[TLB.scala:170:77] assign pma_checker__entries_T_254 = pma_checker__entries_WIRE_21[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pf = pma_checker__entries_T_254; // @[TLB.scala:170:77] assign pma_checker__entries_T_255 = pma_checker__entries_WIRE_21[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_stage2 = pma_checker__entries_T_255; // @[TLB.scala:170:77] assign pma_checker__entries_T_256 = pma_checker__entries_WIRE_21[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_final = pma_checker__entries_T_256; // @[TLB.scala:170:77] assign pma_checker__entries_T_257 = pma_checker__entries_WIRE_21[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_ptw = pma_checker__entries_T_257; // @[TLB.scala:170:77] assign pma_checker__entries_T_258 = pma_checker__entries_WIRE_21[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_g = pma_checker__entries_T_258; // @[TLB.scala:170:77] assign pma_checker__entries_T_259 = pma_checker__entries_WIRE_21[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_u = pma_checker__entries_T_259; // @[TLB.scala:170:77] assign pma_checker__entries_T_260 = pma_checker__entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_20_ppn = pma_checker__entries_T_260; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_283; // @[TLB.scala:170:77] wire pma_checker__entries_T_282; // @[TLB.scala:170:77] wire pma_checker__entries_T_281; // @[TLB.scala:170:77] wire pma_checker__entries_T_280; // @[TLB.scala:170:77] wire pma_checker__entries_T_279; // @[TLB.scala:170:77] wire pma_checker__entries_T_278; // @[TLB.scala:170:77] wire pma_checker__entries_T_277; // @[TLB.scala:170:77] wire pma_checker__entries_T_276; // @[TLB.scala:170:77] wire pma_checker__entries_T_275; // @[TLB.scala:170:77] wire pma_checker__entries_T_274; // @[TLB.scala:170:77] wire pma_checker__entries_T_273; // @[TLB.scala:170:77] wire pma_checker__entries_T_272; // @[TLB.scala:170:77] wire pma_checker__entries_T_271; // @[TLB.scala:170:77] wire pma_checker__entries_T_270; // @[TLB.scala:170:77] wire pma_checker__entries_T_269; // @[TLB.scala:170:77] wire pma_checker__entries_T_268; // @[TLB.scala:170:77] wire pma_checker__entries_T_267; // @[TLB.scala:170:77] wire pma_checker__entries_T_266; // @[TLB.scala:170:77] wire pma_checker__entries_T_265; // @[TLB.scala:170:77] wire pma_checker__entries_T_264; // @[TLB.scala:170:77] wire pma_checker__entries_T_263; // @[TLB.scala:170:77] wire pma_checker__entries_T_262; // @[TLB.scala:170:77] wire pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_261 = pma_checker__entries_WIRE_23[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_fragmented_superpage = pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_262 = pma_checker__entries_WIRE_23[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_c = pma_checker__entries_T_262; // @[TLB.scala:170:77] assign pma_checker__entries_T_263 = pma_checker__entries_WIRE_23[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_eff = pma_checker__entries_T_263; // @[TLB.scala:170:77] assign pma_checker__entries_T_264 = pma_checker__entries_WIRE_23[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_paa = pma_checker__entries_T_264; // @[TLB.scala:170:77] assign pma_checker__entries_T_265 = pma_checker__entries_WIRE_23[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pal = pma_checker__entries_T_265; // @[TLB.scala:170:77] assign pma_checker__entries_T_266 = pma_checker__entries_WIRE_23[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ppp = pma_checker__entries_T_266; // @[TLB.scala:170:77] assign pma_checker__entries_T_267 = pma_checker__entries_WIRE_23[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pr = pma_checker__entries_T_267; // @[TLB.scala:170:77] assign pma_checker__entries_T_268 = pma_checker__entries_WIRE_23[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_px = pma_checker__entries_T_268; // @[TLB.scala:170:77] assign pma_checker__entries_T_269 = pma_checker__entries_WIRE_23[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pw = pma_checker__entries_T_269; // @[TLB.scala:170:77] assign pma_checker__entries_T_270 = pma_checker__entries_WIRE_23[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hr = pma_checker__entries_T_270; // @[TLB.scala:170:77] assign pma_checker__entries_T_271 = pma_checker__entries_WIRE_23[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hx = pma_checker__entries_T_271; // @[TLB.scala:170:77] assign pma_checker__entries_T_272 = pma_checker__entries_WIRE_23[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hw = pma_checker__entries_T_272; // @[TLB.scala:170:77] assign pma_checker__entries_T_273 = pma_checker__entries_WIRE_23[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sr = pma_checker__entries_T_273; // @[TLB.scala:170:77] assign pma_checker__entries_T_274 = pma_checker__entries_WIRE_23[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sx = pma_checker__entries_T_274; // @[TLB.scala:170:77] assign pma_checker__entries_T_275 = pma_checker__entries_WIRE_23[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sw = pma_checker__entries_T_275; // @[TLB.scala:170:77] assign pma_checker__entries_T_276 = pma_checker__entries_WIRE_23[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_gf = pma_checker__entries_T_276; // @[TLB.scala:170:77] assign pma_checker__entries_T_277 = pma_checker__entries_WIRE_23[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pf = pma_checker__entries_T_277; // @[TLB.scala:170:77] assign pma_checker__entries_T_278 = pma_checker__entries_WIRE_23[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_stage2 = pma_checker__entries_T_278; // @[TLB.scala:170:77] assign pma_checker__entries_T_279 = pma_checker__entries_WIRE_23[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_final = pma_checker__entries_T_279; // @[TLB.scala:170:77] assign pma_checker__entries_T_280 = pma_checker__entries_WIRE_23[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_ptw = pma_checker__entries_T_280; // @[TLB.scala:170:77] assign pma_checker__entries_T_281 = pma_checker__entries_WIRE_23[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_g = pma_checker__entries_T_281; // @[TLB.scala:170:77] assign pma_checker__entries_T_282 = pma_checker__entries_WIRE_23[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_u = pma_checker__entries_T_282; // @[TLB.scala:170:77] assign pma_checker__entries_T_283 = pma_checker__entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_22_ppn = pma_checker__entries_T_283; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_306; // @[TLB.scala:170:77] wire pma_checker__entries_T_305; // @[TLB.scala:170:77] wire pma_checker__entries_T_304; // @[TLB.scala:170:77] wire pma_checker__entries_T_303; // @[TLB.scala:170:77] wire pma_checker__entries_T_302; // @[TLB.scala:170:77] wire pma_checker__entries_T_301; // @[TLB.scala:170:77] wire pma_checker__entries_T_300; // @[TLB.scala:170:77] wire pma_checker__entries_T_299; // @[TLB.scala:170:77] wire pma_checker__entries_T_298; // @[TLB.scala:170:77] wire pma_checker__entries_T_297; // @[TLB.scala:170:77] wire pma_checker__entries_T_296; // @[TLB.scala:170:77] wire pma_checker__entries_T_295; // @[TLB.scala:170:77] wire pma_checker__entries_T_294; // @[TLB.scala:170:77] wire pma_checker__entries_T_293; // @[TLB.scala:170:77] wire pma_checker__entries_T_292; // @[TLB.scala:170:77] wire pma_checker__entries_T_291; // @[TLB.scala:170:77] wire pma_checker__entries_T_290; // @[TLB.scala:170:77] wire pma_checker__entries_T_289; // @[TLB.scala:170:77] wire pma_checker__entries_T_288; // @[TLB.scala:170:77] wire pma_checker__entries_T_287; // @[TLB.scala:170:77] wire pma_checker__entries_T_286; // @[TLB.scala:170:77] wire pma_checker__entries_T_285; // @[TLB.scala:170:77] wire pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_284 = pma_checker__entries_WIRE_25[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_fragmented_superpage = pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_285 = pma_checker__entries_WIRE_25[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_c = pma_checker__entries_T_285; // @[TLB.scala:170:77] assign pma_checker__entries_T_286 = pma_checker__entries_WIRE_25[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_eff = pma_checker__entries_T_286; // @[TLB.scala:170:77] assign pma_checker__entries_T_287 = pma_checker__entries_WIRE_25[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_paa = pma_checker__entries_T_287; // @[TLB.scala:170:77] assign pma_checker__entries_T_288 = pma_checker__entries_WIRE_25[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pal = pma_checker__entries_T_288; // @[TLB.scala:170:77] assign pma_checker__entries_T_289 = pma_checker__entries_WIRE_25[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ppp = pma_checker__entries_T_289; // @[TLB.scala:170:77] assign pma_checker__entries_T_290 = pma_checker__entries_WIRE_25[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pr = pma_checker__entries_T_290; // @[TLB.scala:170:77] assign pma_checker__entries_T_291 = pma_checker__entries_WIRE_25[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_px = pma_checker__entries_T_291; // @[TLB.scala:170:77] assign pma_checker__entries_T_292 = pma_checker__entries_WIRE_25[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pw = pma_checker__entries_T_292; // @[TLB.scala:170:77] assign pma_checker__entries_T_293 = pma_checker__entries_WIRE_25[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hr = pma_checker__entries_T_293; // @[TLB.scala:170:77] assign pma_checker__entries_T_294 = pma_checker__entries_WIRE_25[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hx = pma_checker__entries_T_294; // @[TLB.scala:170:77] assign pma_checker__entries_T_295 = pma_checker__entries_WIRE_25[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hw = pma_checker__entries_T_295; // @[TLB.scala:170:77] assign pma_checker__entries_T_296 = pma_checker__entries_WIRE_25[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sr = pma_checker__entries_T_296; // @[TLB.scala:170:77] assign pma_checker__entries_T_297 = pma_checker__entries_WIRE_25[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sx = pma_checker__entries_T_297; // @[TLB.scala:170:77] assign pma_checker__entries_T_298 = pma_checker__entries_WIRE_25[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sw = pma_checker__entries_T_298; // @[TLB.scala:170:77] assign pma_checker__entries_T_299 = pma_checker__entries_WIRE_25[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_gf = pma_checker__entries_T_299; // @[TLB.scala:170:77] assign pma_checker__entries_T_300 = pma_checker__entries_WIRE_25[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pf = pma_checker__entries_T_300; // @[TLB.scala:170:77] assign pma_checker__entries_T_301 = pma_checker__entries_WIRE_25[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_stage2 = pma_checker__entries_T_301; // @[TLB.scala:170:77] assign pma_checker__entries_T_302 = pma_checker__entries_WIRE_25[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_final = pma_checker__entries_T_302; // @[TLB.scala:170:77] assign pma_checker__entries_T_303 = pma_checker__entries_WIRE_25[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_ptw = pma_checker__entries_T_303; // @[TLB.scala:170:77] assign pma_checker__entries_T_304 = pma_checker__entries_WIRE_25[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_g = pma_checker__entries_T_304; // @[TLB.scala:170:77] assign pma_checker__entries_T_305 = pma_checker__entries_WIRE_25[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_u = pma_checker__entries_T_305; // @[TLB.scala:170:77] assign pma_checker__entries_T_306 = pma_checker__entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_24_ppn = pma_checker__entries_T_306; // @[TLB.scala:170:77] wire [1:0] pma_checker_ppn_res = _pma_checker_entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore = pma_checker__ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_1 = pma_checker_ppn_ignore ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_2 = {pma_checker__ppn_T_1[26:20], pma_checker__ppn_T_1[19:0] | _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_3 = pma_checker__ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_4 = {pma_checker_ppn_res, pma_checker__ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_6 = {pma_checker__ppn_T_5[26:20], pma_checker__ppn_T_5[19:0] | _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_7 = pma_checker__ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_8 = {pma_checker__ppn_T_4, pma_checker__ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_1 = _pma_checker_entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_2 = pma_checker__ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_9 = pma_checker_ppn_ignore_2 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_10 = {pma_checker__ppn_T_9[26:20], pma_checker__ppn_T_9[19:0] | _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_11 = pma_checker__ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_12 = {pma_checker_ppn_res_1, pma_checker__ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_14 = {pma_checker__ppn_T_13[26:20], pma_checker__ppn_T_13[19:0] | _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_15 = pma_checker__ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_16 = {pma_checker__ppn_T_12, pma_checker__ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_2 = _pma_checker_entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_4 = pma_checker__ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_17 = pma_checker_ppn_ignore_4 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_18 = {pma_checker__ppn_T_17[26:20], pma_checker__ppn_T_17[19:0] | _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_19 = pma_checker__ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_20 = {pma_checker_ppn_res_2, pma_checker__ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_22 = {pma_checker__ppn_T_21[26:20], pma_checker__ppn_T_21[19:0] | _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_23 = pma_checker__ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_24 = {pma_checker__ppn_T_20, pma_checker__ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_3 = _pma_checker_entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_6 = pma_checker__ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_25 = pma_checker_ppn_ignore_6 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_26 = {pma_checker__ppn_T_25[26:20], pma_checker__ppn_T_25[19:0] | _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_27 = pma_checker__ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_28 = {pma_checker_ppn_res_3, pma_checker__ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_30 = {pma_checker__ppn_T_29[26:20], pma_checker__ppn_T_29[19:0] | _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_31 = pma_checker__ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_32 = {pma_checker__ppn_T_28, pma_checker__ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_4 = _pma_checker_entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire [26:0] pma_checker__ppn_T_34 = {pma_checker__ppn_T_33[26:20], pma_checker__ppn_T_33[19:0] | _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_35 = pma_checker__ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_36 = {pma_checker_ppn_res_4, pma_checker__ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_38 = {pma_checker__ppn_T_37[26:20], pma_checker__ppn_T_37[19:0] | _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_39 = pma_checker__ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_40 = {pma_checker__ppn_T_36, pma_checker__ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] pma_checker__ppn_T_41 = pma_checker_vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] pma_checker__ppn_T_55 = pma_checker__ppn_T_41; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_68 = pma_checker__ppn_T_55; // @[Mux.scala:30:73] wire [19:0] pma_checker_ppn = pma_checker__ppn_T_68; // @[Mux.scala:30:73] wire [1:0] pma_checker_ptw_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_ptw, _pma_checker_entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_lo = {pma_checker_ptw_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_ptw, _pma_checker_entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_hi = {pma_checker_ptw_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_ae_array_lo = {pma_checker_ptw_ae_array_lo_hi, pma_checker_ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_ptw, _pma_checker_entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_hi_lo = {pma_checker_ptw_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_ptw, _pma_checker_entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_ptw, _pma_checker_entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_ae_array_hi_hi = {pma_checker_ptw_ae_array_hi_hi_hi, pma_checker_ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_ae_array_hi = {pma_checker_ptw_ae_array_hi_hi, pma_checker_ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_ae_array_T = {pma_checker_ptw_ae_array_hi, pma_checker_ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_ae_array = {1'h0, pma_checker__ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_final, _pma_checker_entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_lo = {pma_checker_final_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_final, _pma_checker_entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_hi = {pma_checker_final_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_final_ae_array_lo = {pma_checker_final_ae_array_lo_hi, pma_checker_final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_final, _pma_checker_entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_hi_lo = {pma_checker_final_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_final, _pma_checker_entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_final, _pma_checker_entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_final_ae_array_hi_hi = {pma_checker_final_ae_array_hi_hi_hi, pma_checker_final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_final_ae_array_hi = {pma_checker_final_ae_array_hi_hi, pma_checker_final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__final_ae_array_T = {pma_checker_final_ae_array_hi, pma_checker_final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_final_ae_array = {1'h0, pma_checker__final_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pf, _pma_checker_entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_lo = {pma_checker_ptw_pf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pf, _pma_checker_entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_hi = {pma_checker_ptw_pf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_pf_array_lo = {pma_checker_ptw_pf_array_lo_hi, pma_checker_ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pf, _pma_checker_entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_hi_lo = {pma_checker_ptw_pf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_pf, _pma_checker_entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_pf, _pma_checker_entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_pf_array_hi_hi = {pma_checker_ptw_pf_array_hi_hi_hi, pma_checker_ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_pf_array_hi = {pma_checker_ptw_pf_array_hi_hi, pma_checker_ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_pf_array_T = {pma_checker_ptw_pf_array_hi, pma_checker_ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_pf_array = {1'h0, pma_checker__ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_gf, _pma_checker_entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_lo = {pma_checker_ptw_gf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_gf, _pma_checker_entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_hi = {pma_checker_ptw_gf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_gf_array_lo = {pma_checker_ptw_gf_array_lo_hi, pma_checker_ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_gf, _pma_checker_entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_hi_lo = {pma_checker_ptw_gf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_gf, _pma_checker_entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_gf, _pma_checker_entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_gf_array_hi_hi = {pma_checker_ptw_gf_array_hi_hi_hi, pma_checker_ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_gf_array_hi = {pma_checker_ptw_gf_array_hi_hi, pma_checker_ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_gf_array_T = {pma_checker_ptw_gf_array_hi, pma_checker_ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_gf_array = {1'h0, pma_checker__ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] pma_checker__gf_ld_array_T_3 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] pma_checker__gf_st_array_T_2 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] pma_checker__gf_inst_array_T_1 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire pma_checker__priv_rw_ok_T = ~pma_checker_priv_s; // @[TLB.scala:370:20, :513:24] wire pma_checker__priv_rw_ok_T_1 = pma_checker__priv_rw_ok_T; // @[TLB.scala:513:{24,32}] wire [1:0] _GEN_6 = {_pma_checker_entries_barrier_2_io_y_u, _pma_checker_entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo = {pma_checker_priv_rw_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_7 = {_pma_checker_entries_barrier_5_io_y_u, _pma_checker_entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_hi = {pma_checker_priv_rw_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo = {pma_checker_priv_rw_ok_lo_hi, pma_checker_priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_8 = {_pma_checker_entries_barrier_8_io_y_u, _pma_checker_entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo = {pma_checker_priv_rw_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_9 = {_pma_checker_entries_barrier_10_io_y_u, _pma_checker_entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] _GEN_10 = {_pma_checker_entries_barrier_12_io_y_u, _pma_checker_entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [3:0] pma_checker_priv_rw_ok_hi_hi = {pma_checker_priv_rw_ok_hi_hi_hi, pma_checker_priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi = {pma_checker_priv_rw_ok_hi_hi, pma_checker_priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_2 = {pma_checker_priv_rw_ok_hi, pma_checker_priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_3 = pma_checker__priv_rw_ok_T_1 ? pma_checker__priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo_1 = {pma_checker_priv_rw_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_rw_ok_lo_hi_1 = {pma_checker_priv_rw_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo_1 = {pma_checker_priv_rw_ok_lo_hi_1, pma_checker_priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo_1 = {pma_checker_priv_rw_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_rw_ok_hi_hi_1 = {pma_checker_priv_rw_ok_hi_hi_hi_1, pma_checker_priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi_1 = {pma_checker_priv_rw_ok_hi_hi_1, pma_checker_priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_4 = {pma_checker_priv_rw_ok_hi_1, pma_checker_priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_5 = ~pma_checker__priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_6 = pma_checker_priv_s ? pma_checker__priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] pma_checker_priv_rw_ok = pma_checker__priv_rw_ok_T_3 | pma_checker__priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] pma_checker_priv_x_ok_lo_lo = {pma_checker_priv_x_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi = {pma_checker_priv_x_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo = {pma_checker_priv_x_ok_lo_hi, pma_checker_priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo = {pma_checker_priv_x_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi = {pma_checker_priv_x_ok_hi_hi_hi, pma_checker_priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi = {pma_checker_priv_x_ok_hi_hi, pma_checker_priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T = {pma_checker_priv_x_ok_hi, pma_checker_priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_1 = ~pma_checker__priv_x_ok_T; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_lo_lo_1 = {pma_checker_priv_x_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi_1 = {pma_checker_priv_x_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo_1 = {pma_checker_priv_x_ok_lo_hi_1, pma_checker_priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo_1 = {pma_checker_priv_x_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi_1 = {pma_checker_priv_x_ok_hi_hi_hi_1, pma_checker_priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi_1 = {pma_checker_priv_x_ok_hi_hi_1, pma_checker_priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_2 = {pma_checker_priv_x_ok_hi_1, pma_checker_priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker_priv_x_ok = pma_checker_priv_s ? pma_checker__priv_x_ok_T_1 : pma_checker__priv_x_ok_T_2; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_stage2, _pma_checker_entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_lo = {pma_checker_stage1_bypass_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_stage2, _pma_checker_entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_hi = {pma_checker_stage1_bypass_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_stage1_bypass_lo = {pma_checker_stage1_bypass_lo_hi, pma_checker_stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_stage2, _pma_checker_entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_hi_lo = {pma_checker_stage1_bypass_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_stage2, _pma_checker_entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_stage2, _pma_checker_entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_stage1_bypass_hi_hi = {pma_checker_stage1_bypass_hi_hi_hi, pma_checker_stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_stage1_bypass_hi = {pma_checker_stage1_bypass_hi_hi, pma_checker_stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T_3 = {pma_checker_stage1_bypass_hi, pma_checker_stage1_bypass_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sr, _pma_checker_entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_lo = {pma_checker_r_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sr, _pma_checker_entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_hi = {pma_checker_r_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo = {pma_checker_r_array_lo_hi, pma_checker_r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sr, _pma_checker_entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_hi_lo = {pma_checker_r_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sr, _pma_checker_entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sr, _pma_checker_entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_r_array_hi_hi = {pma_checker_r_array_hi_hi_hi, pma_checker_r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi = {pma_checker_r_array_hi_hi, pma_checker_r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T = {pma_checker_r_array_hi, pma_checker_r_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_3 = pma_checker__r_array_T; // @[package.scala:45:27] wire [1:0] _GEN_11 = {_pma_checker_entries_barrier_2_io_y_sx, _pma_checker_entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_lo_hi_1 = _GEN_11; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_lo_hi = _GEN_11; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_lo_1 = {pma_checker_r_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_12 = {_pma_checker_entries_barrier_5_io_y_sx, _pma_checker_entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_hi_hi_1 = _GEN_12; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_hi_hi = _GEN_12; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_hi_1 = {pma_checker_r_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo_1 = {pma_checker_r_array_lo_hi_1, pma_checker_r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_13 = {_pma_checker_entries_barrier_8_io_y_sx, _pma_checker_entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_lo_hi_1 = _GEN_13; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_lo_hi = _GEN_13; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_hi_lo_1 = {pma_checker_r_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_14 = {_pma_checker_entries_barrier_10_io_y_sx, _pma_checker_entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_lo_1 = _GEN_14; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_lo = _GEN_14; // @[package.scala:45:27] wire [1:0] _GEN_15 = {_pma_checker_entries_barrier_12_io_y_sx, _pma_checker_entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_hi_1 = _GEN_15; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_hi = _GEN_15; // @[package.scala:45:27] wire [3:0] pma_checker_r_array_hi_hi_1 = {pma_checker_r_array_hi_hi_hi_1, pma_checker_r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi_1 = {pma_checker_r_array_hi_hi_1, pma_checker_r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_1 = {pma_checker_r_array_hi_1, pma_checker_r_array_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_4 = pma_checker_priv_rw_ok & pma_checker__r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] pma_checker__r_array_T_5 = pma_checker__r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] pma_checker_r_array = {1'h1, pma_checker__r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] pma_checker__pf_ld_array_T = pma_checker_r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] pma_checker_w_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sw, _pma_checker_entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_lo = {pma_checker_w_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sw, _pma_checker_entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_hi = {pma_checker_w_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_w_array_lo = {pma_checker_w_array_lo_hi, pma_checker_w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_w_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sw, _pma_checker_entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_hi_lo = {pma_checker_w_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sw, _pma_checker_entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sw, _pma_checker_entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_w_array_hi_hi = {pma_checker_w_array_hi_hi_hi, pma_checker_w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_w_array_hi = {pma_checker_w_array_hi_hi, pma_checker_w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T = {pma_checker_w_array_hi, pma_checker_w_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_1 = pma_checker_priv_rw_ok & pma_checker__w_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_2 = pma_checker__w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] pma_checker_w_array = {1'h1, pma_checker__w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] pma_checker_x_array_lo_lo = {pma_checker_x_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_x_array_lo_hi = {pma_checker_x_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_x_array_lo = {pma_checker_x_array_lo_hi, pma_checker_x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_x_array_hi_lo = {pma_checker_x_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_x_array_hi_hi = {pma_checker_x_array_hi_hi_hi, pma_checker_x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_x_array_hi = {pma_checker_x_array_hi_hi, pma_checker_x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T = {pma_checker_x_array_hi, pma_checker_x_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_1 = pma_checker_priv_x_ok & pma_checker__x_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_2 = pma_checker__x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] pma_checker_x_array = {1'h1, pma_checker__x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] pma_checker_hr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hr, _pma_checker_entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_lo = {pma_checker_hr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hr, _pma_checker_entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_hi = {pma_checker_hr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo = {pma_checker_hr_array_lo_hi, pma_checker_hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hr, _pma_checker_entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_hi_lo = {pma_checker_hr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hr, _pma_checker_entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hr, _pma_checker_entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hr_array_hi_hi = {pma_checker_hr_array_hi_hi_hi, pma_checker_hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi = {pma_checker_hr_array_hi_hi, pma_checker_hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T = {pma_checker_hr_array_hi, pma_checker_hr_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_3 = pma_checker__hr_array_T; // @[package.scala:45:27] wire [1:0] _GEN_16 = {_pma_checker_entries_barrier_2_io_y_hx, _pma_checker_entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_lo_hi_1 = _GEN_16; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_lo_hi = _GEN_16; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_lo_1 = {pma_checker_hr_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_17 = {_pma_checker_entries_barrier_5_io_y_hx, _pma_checker_entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_hi_hi_1 = _GEN_17; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_hi_hi = _GEN_17; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_hi_1 = {pma_checker_hr_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo_1 = {pma_checker_hr_array_lo_hi_1, pma_checker_hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_18 = {_pma_checker_entries_barrier_8_io_y_hx, _pma_checker_entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_lo_hi_1 = _GEN_18; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_lo_hi = _GEN_18; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_hi_lo_1 = {pma_checker_hr_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_19 = {_pma_checker_entries_barrier_10_io_y_hx, _pma_checker_entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_lo_1 = _GEN_19; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_lo = _GEN_19; // @[package.scala:45:27] wire [1:0] _GEN_20 = {_pma_checker_entries_barrier_12_io_y_hx, _pma_checker_entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_hi_1 = _GEN_20; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_hi = _GEN_20; // @[package.scala:45:27] wire [3:0] pma_checker_hr_array_hi_hi_1 = {pma_checker_hr_array_hi_hi_hi_1, pma_checker_hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi_1 = {pma_checker_hr_array_hi_hi_1, pma_checker_hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_1 = {pma_checker_hr_array_hi_1, pma_checker_hr_array_lo_1}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hw, _pma_checker_entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_lo = {pma_checker_hw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hw, _pma_checker_entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_hi = {pma_checker_hw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hw_array_lo = {pma_checker_hw_array_lo_hi, pma_checker_hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hw, _pma_checker_entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_hi_lo = {pma_checker_hw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hw, _pma_checker_entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hw, _pma_checker_entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hw_array_hi_hi = {pma_checker_hw_array_hi_hi_hi, pma_checker_hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hw_array_hi = {pma_checker_hw_array_hi_hi, pma_checker_hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hw_array_T = {pma_checker_hw_array_hi, pma_checker_hw_array_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_lo_lo = {pma_checker_hx_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hx_array_lo_hi = {pma_checker_hx_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hx_array_lo = {pma_checker_hx_array_lo_hi, pma_checker_hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_hi_lo = {pma_checker_hx_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hx_array_hi_hi = {pma_checker_hx_array_hi_hi_hi, pma_checker_hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hx_array_hi = {pma_checker_hx_array_hi_hi, pma_checker_hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hx_array_T = {pma_checker_hx_array_hi, pma_checker_hx_array_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pr, _pma_checker_entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_lo = {pma_checker_pr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pr, _pma_checker_entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_hi = {pma_checker_pr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_lo = {pma_checker_pr_array_lo_hi, pma_checker_pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pr, _pma_checker_entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_lo = {pma_checker_pr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pr, _pma_checker_entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_hi = {pma_checker_pr_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_hi = {pma_checker_pr_array_hi_hi, pma_checker_pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pr_array_T_1 = {pma_checker_pr_array_hi, pma_checker_pr_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pr_array_T_2 = {2'h0, pma_checker__pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_21 = pma_checker_ptw_ae_array | pma_checker_final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] pma_checker__pr_array_T_3; // @[TLB.scala:529:104] assign pma_checker__pr_array_T_3 = _GEN_21; // @[TLB.scala:529:104] wire [13:0] pma_checker__pw_array_T_3; // @[TLB.scala:531:104] assign pma_checker__pw_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :531:104] wire [13:0] pma_checker__px_array_T_3; // @[TLB.scala:533:104] assign pma_checker__px_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :533:104] wire [13:0] pma_checker__pr_array_T_4 = ~pma_checker__pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pma_checker_pr_array = pma_checker__pr_array_T_2 & pma_checker__pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] pma_checker_pw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pw, _pma_checker_entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_lo = {pma_checker_pw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pw, _pma_checker_entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_hi = {pma_checker_pw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_lo = {pma_checker_pw_array_lo_hi, pma_checker_pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pw, _pma_checker_entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_lo = {pma_checker_pw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pw, _pma_checker_entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_hi = {pma_checker_pw_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_hi = {pma_checker_pw_array_hi_hi, pma_checker_pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pw_array_T_1 = {pma_checker_pw_array_hi, pma_checker_pw_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_2 = {2'h0, pma_checker__pw_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_4 = ~pma_checker__pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pma_checker_pw_array = pma_checker__pw_array_T_2 & pma_checker__pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] pma_checker_px_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_px, _pma_checker_entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_lo = {pma_checker_px_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_px, _pma_checker_entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_hi = {pma_checker_px_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_lo = {pma_checker_px_array_lo_hi, pma_checker_px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_px_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_px, _pma_checker_entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_lo = {pma_checker_px_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_px, _pma_checker_entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_hi = {pma_checker_px_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_hi = {pma_checker_px_array_hi_hi, pma_checker_px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__px_array_T_1 = {pma_checker_px_array_hi, pma_checker_px_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_2 = {2'h0, pma_checker__px_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_4 = ~pma_checker__px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] pma_checker_px_array = pma_checker__px_array_T_2 & pma_checker__px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] pma_checker__eff_array_T = {2{_pma_checker_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] pma_checker_eff_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_eff, _pma_checker_entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_lo = {pma_checker_eff_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_eff, _pma_checker_entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_hi = {pma_checker_eff_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_lo = {pma_checker_eff_array_lo_hi, pma_checker_eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_eff_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_eff, _pma_checker_entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_lo = {pma_checker_eff_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_eff, _pma_checker_entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_hi = {pma_checker_eff_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_hi = {pma_checker_eff_array_hi_hi, pma_checker_eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__eff_array_T_1 = {pma_checker_eff_array_hi, pma_checker_eff_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_eff_array = {pma_checker__eff_array_T, pma_checker__eff_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__c_array_T = {2{pma_checker_cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_22 = {_pma_checker_entries_barrier_2_io_y_c, _pma_checker_entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_lo = {pma_checker_c_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_23 = {_pma_checker_entries_barrier_5_io_y_c, _pma_checker_entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_hi = {pma_checker_c_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_lo = {pma_checker_c_array_lo_hi, pma_checker_c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_24 = {_pma_checker_entries_barrier_8_io_y_c, _pma_checker_entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_lo = {pma_checker_c_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_25 = {_pma_checker_entries_barrier_11_io_y_c, _pma_checker_entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_hi = {pma_checker_c_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_hi = {pma_checker_c_array_hi_hi, pma_checker_c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__c_array_T_1 = {pma_checker_c_array_hi, pma_checker_c_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_c_array = {pma_checker__c_array_T, pma_checker__c_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_lrscAllowed = pma_checker_c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] pma_checker__ppp_array_T = {2{_pma_checker_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] pma_checker_ppp_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ppp, _pma_checker_entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_lo = {pma_checker_ppp_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ppp, _pma_checker_entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_hi = {pma_checker_ppp_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_lo = {pma_checker_ppp_array_lo_hi, pma_checker_ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ppp_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ppp, _pma_checker_entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_lo = {pma_checker_ppp_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_ppp, _pma_checker_entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_hi = {pma_checker_ppp_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_hi = {pma_checker_ppp_array_hi_hi, pma_checker_ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__ppp_array_T_1 = {pma_checker_ppp_array_hi, pma_checker_ppp_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array = {pma_checker__ppp_array_T, pma_checker__ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__paa_array_T = {2{_pma_checker_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] pma_checker_paa_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_paa, _pma_checker_entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_lo = {pma_checker_paa_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_paa, _pma_checker_entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_hi = {pma_checker_paa_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_lo = {pma_checker_paa_array_lo_hi, pma_checker_paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_paa_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_paa, _pma_checker_entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_lo = {pma_checker_paa_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_paa, _pma_checker_entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_hi = {pma_checker_paa_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_hi = {pma_checker_paa_array_hi_hi, pma_checker_paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__paa_array_T_1 = {pma_checker_paa_array_hi, pma_checker_paa_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_paa_array = {pma_checker__paa_array_T, pma_checker__paa_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__pal_array_T = {2{_pma_checker_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pma_checker_pal_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pal, _pma_checker_entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_lo = {pma_checker_pal_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pal, _pma_checker_entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_hi = {pma_checker_pal_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_lo = {pma_checker_pal_array_lo_hi, pma_checker_pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pal_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pal, _pma_checker_entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_lo = {pma_checker_pal_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pal, _pma_checker_entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_hi = {pma_checker_pal_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_hi = {pma_checker_pal_array_hi_hi, pma_checker_pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pal_array_T_1 = {pma_checker_pal_array_hi, pma_checker_pal_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_pal_array = {pma_checker__pal_array_T, pma_checker__pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array_if_cached = pma_checker_ppp_array | pma_checker_c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] pma_checker_paa_array_if_cached = pma_checker_paa_array | pma_checker_c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pma_checker_pal_array_if_cached = pma_checker_pal_array | pma_checker_c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire pma_checker__prefetchable_array_T = pma_checker_cacheable & pma_checker_homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] pma_checker__prefetchable_array_T_1 = {pma_checker__prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] pma_checker_prefetchable_array_lo_lo = {pma_checker_prefetchable_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_lo_hi = {pma_checker_prefetchable_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_lo = {pma_checker_prefetchable_array_lo_hi, pma_checker_prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_prefetchable_array_hi_lo = {pma_checker_prefetchable_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_hi_hi = {pma_checker_prefetchable_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_hi = {pma_checker_prefetchable_array_hi_hi, pma_checker_prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__prefetchable_array_T_2 = {pma_checker_prefetchable_array_hi, pma_checker_prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_prefetchable_array = {pma_checker__prefetchable_array_T_1, pma_checker__prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] pma_checker__misaligned_T = 4'h1 << pma_checker_io_req_bits_size; // @[OneHot.scala:58:35] wire [4:0] pma_checker__misaligned_T_1 = {1'h0, pma_checker__misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] pma_checker__misaligned_T_2 = pma_checker__misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] pma_checker__misaligned_T_3 = {36'h0, pma_checker_io_req_bits_vaddr[3:0] & pma_checker__misaligned_T_2}; // @[TLB.scala:550:{39,69}] wire pma_checker_misaligned = |pma_checker__misaligned_T_3; // @[TLB.scala:550:{39,77}] wire [39:0] pma_checker_bad_va_maskedVAddr = pma_checker_io_req_bits_vaddr & 40'hC000000000; // @[TLB.scala:559:43] wire pma_checker__bad_va_T_2 = pma_checker_bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire pma_checker__bad_va_T_3 = pma_checker_bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire pma_checker__bad_va_T_4 = pma_checker__bad_va_T_3; // @[TLB.scala:560:{71,86}] wire pma_checker__bad_va_T_5 = pma_checker__bad_va_T_2 | pma_checker__bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire pma_checker__bad_va_T_6 = ~pma_checker__bad_va_T_5; // @[TLB.scala:560:{37,59}] wire pma_checker__bad_va_T_7 = pma_checker__bad_va_T_6; // @[TLB.scala:560:{34,37}] wire _GEN_26 = pma_checker_io_req_bits_cmd == 5'h6; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T = _GEN_26; // @[package.scala:16:47] wire pma_checker__cmd_read_T_2; // @[package.scala:16:47] assign pma_checker__cmd_read_T_2 = _GEN_26; // @[package.scala:16:47] wire _GEN_27 = pma_checker_io_req_bits_cmd == 5'h7; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T_1 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_read_T_3; // @[package.scala:16:47] assign pma_checker__cmd_read_T_3 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_write_T_3; // @[Consts.scala:90:66] assign pma_checker__cmd_write_T_3 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_2 = pma_checker__cmd_lrsc_T | pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_lrsc = pma_checker__cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_28 = pma_checker_io_req_bits_cmd == 5'h4; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_read_T_7; // @[package.scala:16:47] assign pma_checker__cmd_read_T_7 = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_write_T_5; // @[package.scala:16:47] assign pma_checker__cmd_write_T_5 = _GEN_28; // @[package.scala:16:47] wire _GEN_29 = pma_checker_io_req_bits_cmd == 5'h9; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_1 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_read_T_8; // @[package.scala:16:47] assign pma_checker__cmd_read_T_8 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_write_T_6; // @[package.scala:16:47] assign pma_checker__cmd_write_T_6 = _GEN_29; // @[package.scala:16:47] wire _GEN_30 = pma_checker_io_req_bits_cmd == 5'hA; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_2 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_read_T_9; // @[package.scala:16:47] assign pma_checker__cmd_read_T_9 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_write_T_7; // @[package.scala:16:47] assign pma_checker__cmd_write_T_7 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = pma_checker_io_req_bits_cmd == 5'hB; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_3 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_read_T_10; // @[package.scala:16:47] assign pma_checker__cmd_read_T_10 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_write_T_8; // @[package.scala:16:47] assign pma_checker__cmd_write_T_8 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_4 = pma_checker__cmd_amo_logical_T | pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_5 = pma_checker__cmd_amo_logical_T_4 | pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_6 = pma_checker__cmd_amo_logical_T_5 | pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_logical = pma_checker__cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_32 = pma_checker_io_req_bits_cmd == 5'h8; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_read_T_14; // @[package.scala:16:47] assign pma_checker__cmd_read_T_14 = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_write_T_12; // @[package.scala:16:47] assign pma_checker__cmd_write_T_12 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = pma_checker_io_req_bits_cmd == 5'hC; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_1 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_read_T_15; // @[package.scala:16:47] assign pma_checker__cmd_read_T_15 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_write_T_13; // @[package.scala:16:47] assign pma_checker__cmd_write_T_13 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = pma_checker_io_req_bits_cmd == 5'hD; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_2 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_read_T_16; // @[package.scala:16:47] assign pma_checker__cmd_read_T_16 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_write_T_14; // @[package.scala:16:47] assign pma_checker__cmd_write_T_14 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = pma_checker_io_req_bits_cmd == 5'hE; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_3 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_read_T_17; // @[package.scala:16:47] assign pma_checker__cmd_read_T_17 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_write_T_15; // @[package.scala:16:47] assign pma_checker__cmd_write_T_15 = _GEN_35; // @[package.scala:16:47] wire _GEN_36 = pma_checker_io_req_bits_cmd == 5'hF; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_4 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_read_T_18; // @[package.scala:16:47] assign pma_checker__cmd_read_T_18 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_write_T_16; // @[package.scala:16:47] assign pma_checker__cmd_write_T_16 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_5 = pma_checker__cmd_amo_arithmetic_T | pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_6 = pma_checker__cmd_amo_arithmetic_T_5 | pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_7 = pma_checker__cmd_amo_arithmetic_T_6 | pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_8 = pma_checker__cmd_amo_arithmetic_T_7 | pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_arithmetic = pma_checker__cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_37 = pma_checker_io_req_bits_cmd == 5'h11; // @[TLB.scala:573:41] wire pma_checker_cmd_put_partial; // @[TLB.scala:573:41] assign pma_checker_cmd_put_partial = _GEN_37; // @[TLB.scala:573:41] wire pma_checker__cmd_write_T_1; // @[Consts.scala:90:49] assign pma_checker__cmd_write_T_1 = _GEN_37; // @[TLB.scala:573:41] wire pma_checker__cmd_read_T = pma_checker_io_req_bits_cmd == 5'h0; // @[package.scala:16:47] wire _GEN_38 = pma_checker_io_req_bits_cmd == 5'h10; // @[package.scala:16:47] wire pma_checker__cmd_read_T_1; // @[package.scala:16:47] assign pma_checker__cmd_read_T_1 = _GEN_38; // @[package.scala:16:47] wire pma_checker__cmd_readx_T; // @[TLB.scala:575:56] assign pma_checker__cmd_readx_T = _GEN_38; // @[package.scala:16:47] wire pma_checker__cmd_read_T_4 = pma_checker__cmd_read_T | pma_checker__cmd_read_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_5 = pma_checker__cmd_read_T_4 | pma_checker__cmd_read_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_6 = pma_checker__cmd_read_T_5 | pma_checker__cmd_read_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_11 = pma_checker__cmd_read_T_7 | pma_checker__cmd_read_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_12 = pma_checker__cmd_read_T_11 | pma_checker__cmd_read_T_9; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_13 = pma_checker__cmd_read_T_12 | pma_checker__cmd_read_T_10; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_19 = pma_checker__cmd_read_T_14 | pma_checker__cmd_read_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_20 = pma_checker__cmd_read_T_19 | pma_checker__cmd_read_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_21 = pma_checker__cmd_read_T_20 | pma_checker__cmd_read_T_17; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_22 = pma_checker__cmd_read_T_21 | pma_checker__cmd_read_T_18; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_23 = pma_checker__cmd_read_T_13 | pma_checker__cmd_read_T_22; // @[package.scala:81:59] wire pma_checker_cmd_read = pma_checker__cmd_read_T_6 | pma_checker__cmd_read_T_23; // @[package.scala:81:59] wire pma_checker__cmd_write_T = pma_checker_io_req_bits_cmd == 5'h1; // @[DCache.scala:120:32] wire pma_checker__cmd_write_T_2 = pma_checker__cmd_write_T | pma_checker__cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire pma_checker__cmd_write_T_4 = pma_checker__cmd_write_T_2 | pma_checker__cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire pma_checker__cmd_write_T_9 = pma_checker__cmd_write_T_5 | pma_checker__cmd_write_T_6; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_10 = pma_checker__cmd_write_T_9 | pma_checker__cmd_write_T_7; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_11 = pma_checker__cmd_write_T_10 | pma_checker__cmd_write_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_17 = pma_checker__cmd_write_T_12 | pma_checker__cmd_write_T_13; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_18 = pma_checker__cmd_write_T_17 | pma_checker__cmd_write_T_14; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_19 = pma_checker__cmd_write_T_18 | pma_checker__cmd_write_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_20 = pma_checker__cmd_write_T_19 | pma_checker__cmd_write_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_21 = pma_checker__cmd_write_T_11 | pma_checker__cmd_write_T_20; // @[package.scala:81:59] wire pma_checker_cmd_write = pma_checker__cmd_write_T_4 | pma_checker__cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire pma_checker__cmd_write_perms_T = pma_checker_io_req_bits_cmd == 5'h5; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_1 = pma_checker_io_req_bits_cmd == 5'h17; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_2 = pma_checker__cmd_write_perms_T | pma_checker__cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_write_perms = pma_checker_cmd_write | pma_checker__cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] pma_checker__ae_array_T = pma_checker_misaligned ? pma_checker_eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] pma_checker__ae_array_T_1 = ~pma_checker_lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] pma_checker__ae_array_T_2 = pma_checker_cmd_lrsc ? pma_checker__ae_array_T_1 : 14'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [13:0] pma_checker_ae_array = pma_checker__ae_array_T | pma_checker__ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [13:0] pma_checker__ae_ld_array_T = ~pma_checker_pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] pma_checker__ae_ld_array_T_1 = pma_checker_ae_array | pma_checker__ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] pma_checker_ae_ld_array = pma_checker_cmd_read ? pma_checker__ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] pma_checker__ae_st_array_T = ~pma_checker_pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] pma_checker__ae_st_array_T_1 = pma_checker_ae_array | pma_checker__ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] pma_checker__ae_st_array_T_2 = pma_checker_cmd_write_perms ? pma_checker__ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] pma_checker__ae_st_array_T_3 = ~pma_checker_ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] pma_checker__ae_st_array_T_4 = pma_checker_cmd_put_partial ? pma_checker__ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] pma_checker__ae_st_array_T_5 = pma_checker__ae_st_array_T_2 | pma_checker__ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] pma_checker__ae_st_array_T_6 = ~pma_checker_pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] pma_checker__ae_st_array_T_7 = pma_checker_cmd_amo_logical ? pma_checker__ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [13:0] pma_checker__ae_st_array_T_8 = pma_checker__ae_st_array_T_5 | pma_checker__ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [13:0] pma_checker__ae_st_array_T_9 = ~pma_checker_paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] pma_checker__ae_st_array_T_10 = pma_checker_cmd_amo_arithmetic ? pma_checker__ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [13:0] pma_checker_ae_st_array = pma_checker__ae_st_array_T_8 | pma_checker__ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [13:0] pma_checker__must_alloc_array_T = ~pma_checker_ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] pma_checker__must_alloc_array_T_1 = pma_checker_cmd_put_partial ? pma_checker__must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_2 = ~pma_checker_pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] pma_checker__must_alloc_array_T_3 = pma_checker_cmd_amo_logical ? pma_checker__must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_4 = pma_checker__must_alloc_array_T_1 | pma_checker__must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [13:0] pma_checker__must_alloc_array_T_5 = ~pma_checker_paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] pma_checker__must_alloc_array_T_6 = pma_checker_cmd_amo_arithmetic ? pma_checker__must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [13:0] pma_checker__must_alloc_array_T_7 = pma_checker__must_alloc_array_T_4 | pma_checker__must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [13:0] pma_checker__must_alloc_array_T_9 = {14{pma_checker_cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [13:0] pma_checker_must_alloc_array = pma_checker__must_alloc_array_T_7 | pma_checker__must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [13:0] pma_checker__pf_ld_array_T_1 = ~pma_checker__pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] pma_checker__pf_ld_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] pma_checker__pf_ld_array_T_3 = pma_checker__pf_ld_array_T_1 & pma_checker__pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] pma_checker__pf_ld_array_T_4 = pma_checker__pf_ld_array_T_3 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] pma_checker__pf_ld_array_T_5 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] pma_checker__pf_ld_array_T_6 = pma_checker__pf_ld_array_T_4 & pma_checker__pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pma_checker_pf_ld_array = pma_checker_cmd_read ? pma_checker__pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] pma_checker__pf_st_array_T = ~pma_checker_w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] pma_checker__pf_st_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] pma_checker__pf_st_array_T_2 = pma_checker__pf_st_array_T & pma_checker__pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] pma_checker__pf_st_array_T_3 = pma_checker__pf_st_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] pma_checker__pf_st_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] pma_checker__pf_st_array_T_5 = pma_checker__pf_st_array_T_3 & pma_checker__pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pma_checker_pf_st_array = pma_checker_cmd_write_perms ? pma_checker__pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] pma_checker__pf_inst_array_T = ~pma_checker_x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] pma_checker__pf_inst_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] pma_checker__pf_inst_array_T_2 = pma_checker__pf_inst_array_T & pma_checker__pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] pma_checker__pf_inst_array_T_3 = pma_checker__pf_inst_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] pma_checker__pf_inst_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pma_checker_pf_inst_array = pma_checker__pf_inst_array_T_3 & pma_checker__pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] pma_checker__gf_ld_array_T_4 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] pma_checker__gf_ld_array_T_5 = pma_checker__gf_ld_array_T_3 & pma_checker__gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] pma_checker__gf_st_array_T_3 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] pma_checker__gf_st_array_T_4 = pma_checker__gf_st_array_T_2 & pma_checker__gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] pma_checker__gf_inst_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] pma_checker__gf_inst_array_T_3 = pma_checker__gf_inst_array_T_1 & pma_checker__gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire pma_checker__gpa_hits_hit_mask_T = pma_checker_vpn == 27'h0; // @[TLB.scala:335:30, :606:73] wire [13:0] pma_checker__io_resp_pf_ld_T_1 = pma_checker_pf_ld_array & 14'h2000; // @[TLB.scala:597:24, :633:57] wire pma_checker__io_resp_pf_ld_T_2 = |pma_checker__io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign pma_checker__io_resp_pf_ld_T_3 = pma_checker__io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}] assign pma_checker_io_resp_pf_ld = pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire [13:0] pma_checker__io_resp_pf_st_T_1 = pma_checker_pf_st_array & 14'h2000; // @[TLB.scala:598:24, :634:64] wire pma_checker__io_resp_pf_st_T_2 = |pma_checker__io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign pma_checker__io_resp_pf_st_T_3 = pma_checker__io_resp_pf_st_T_2; // @[TLB.scala:634:{48,72}] assign pma_checker_io_resp_pf_st = pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire [13:0] pma_checker__io_resp_pf_inst_T = pma_checker_pf_inst_array & 14'h2000; // @[TLB.scala:599:67, :635:47] wire pma_checker__io_resp_pf_inst_T_1 = |pma_checker__io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign pma_checker__io_resp_pf_inst_T_2 = pma_checker__io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}] assign pma_checker_io_resp_pf_inst = pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire [13:0] pma_checker__io_resp_ae_ld_T = pma_checker_ae_ld_array & 14'h2000; // @[TLB.scala:586:24, :641:33] assign pma_checker__io_resp_ae_ld_T_1 = |pma_checker__io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign pma_checker_io_resp_ae_ld = pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire [13:0] pma_checker__io_resp_ae_st_T = pma_checker_ae_st_array & 14'h2000; // @[TLB.scala:590:53, :642:33] assign pma_checker__io_resp_ae_st_T_1 = |pma_checker__io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign pma_checker_io_resp_ae_st = pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire [13:0] pma_checker__io_resp_ae_inst_T = ~pma_checker_px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] pma_checker__io_resp_ae_inst_T_1 = pma_checker__io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:643:{23,33}] assign pma_checker__io_resp_ae_inst_T_2 = |pma_checker__io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign pma_checker_io_resp_ae_inst = pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] assign pma_checker__io_resp_ma_ld_T = pma_checker_misaligned & pma_checker_cmd_read; // @[TLB.scala:550:77, :645:31] assign pma_checker_io_resp_ma_ld = pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] assign pma_checker__io_resp_ma_st_T = pma_checker_misaligned & pma_checker_cmd_write; // @[TLB.scala:550:77, :646:31] assign pma_checker_io_resp_ma_st = pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire [13:0] pma_checker__io_resp_cacheable_T = pma_checker_c_array & 14'h2000; // @[TLB.scala:537:20, :648:33] assign pma_checker__io_resp_cacheable_T_1 = |pma_checker__io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign pma_checker_io_resp_cacheable = pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire [13:0] pma_checker__io_resp_must_alloc_T = pma_checker_must_alloc_array & 14'h2000; // @[TLB.scala:595:46, :649:43] assign pma_checker__io_resp_must_alloc_T_1 = |pma_checker__io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign pma_checker_io_resp_must_alloc = pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire [13:0] pma_checker__io_resp_prefetchable_T = pma_checker_prefetchable_array & 14'h2000; // @[TLB.scala:547:31, :650:47] wire pma_checker__io_resp_prefetchable_T_1 = |pma_checker__io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign pma_checker__io_resp_prefetchable_T_2 = pma_checker__io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign pma_checker_io_resp_prefetchable = pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] assign pma_checker__io_resp_paddr_T_1 = {pma_checker_ppn, pma_checker__io_resp_paddr_T}; // @[Mux.scala:30:73] assign pma_checker_io_resp_paddr = pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [27:0] pma_checker__io_resp_gpa_page_T_1 = {1'h0, pma_checker_vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] pma_checker_io_resp_gpa_page = pma_checker__io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [11:0] pma_checker_io_resp_gpa_offset = pma_checker__io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign pma_checker__io_resp_gpa_T = {pma_checker_io_resp_gpa_page, pma_checker_io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign pma_checker_io_resp_gpa = pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker_ignore_1 = pma_checker__ignore_T_1; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_4 = pma_checker__ignore_T_4; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_7 = pma_checker__ignore_T_7; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_10 = pma_checker__ignore_T_10; // @[TLB.scala:182:{28,34}] wire replace; // @[Replacement.scala:37:29] wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17] wire metaArb__grant_T = metaArb_io_in_0_valid; // @[Arbiter.scala:45:68] wire [39:0] _metaArb_io_in_5_bits_addr_T_2; // @[DCache.scala:1018:36] wire [5:0] _metaArb_io_in_5_bits_idx_T; // @[DCache.scala:1017:44] wire metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire [39:0] _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:454:36] wire [5:0] _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:453:35] wire [21:0] _metaArb_io_in_1_bits_data_T; // @[DCache.scala:458:14] wire metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_2_valid_T; // @[DCache.scala:462:63] wire [39:0] _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:466:36] wire [5:0] _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:465:40] wire [7:0] s2_victim_or_hit_way; // @[DCache.scala:432:33] wire [21:0] _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:467:97] wire metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_3_valid_T_2; // @[DCache.scala:741:53] wire [39:0] _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:745:36] wire [5:0] _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:744:40] wire [21:0] _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:746:134] wire metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59] wire [39:0] _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:912:36] wire [5:0] _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:1200:47] wire [7:0] releaseWay; // @[DCache.scala:232:24] wire [21:0] _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:913:97] wire metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire [5:0] _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:263:58] wire metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [5:0] _s1_meta_WIRE = metaArb_io_out_bits_idx; // @[DCache.scala:135:28, :314:35] wire [39:0] metaArb_io_in_0_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_0_bits_idx; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_1_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_1_bits_idx; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_1_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_1_ready; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_2_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_2_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_2_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_2_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_2_ready; // @[DCache.scala:135:28] wire metaArb_io_in_2_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_3_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_3_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_3_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_3_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_3_ready; // @[DCache.scala:135:28] wire metaArb_io_in_3_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_4_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_4_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_4_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_4_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_4_ready; // @[DCache.scala:135:28] wire metaArb_io_in_4_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_5_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_5_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_5_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_5_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_5_ready; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_6_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_6_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_6_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_6_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_6_ready; // @[DCache.scala:135:28] wire metaArb_io_in_6_valid; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_7_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_7_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_7_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_7_ready; // @[DCache.scala:135:28] wire metaArb_io_out_bits_write; // @[DCache.scala:135:28] wire [39:0] metaArb_io_out_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_out_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_out_bits_data; // @[DCache.scala:135:28] wire metaArb_io_out_valid; // @[DCache.scala:135:28] wire [2:0] metaArb_io_chosen; // @[DCache.scala:135:28] assign metaArb_io_chosen = metaArb_io_in_0_valid ? 3'h0 : metaArb_io_in_2_valid ? 3'h2 : metaArb_io_in_3_valid ? 3'h3 : metaArb_io_in_4_valid ? 3'h4 : {2'h3, ~metaArb_io_in_6_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17] assign metaArb_io_out_bits_write = metaArb_io_in_0_valid | metaArb_io_in_2_valid | metaArb_io_in_3_valid | metaArb_io_in_4_valid; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_addr = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_addr : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_addr : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_addr : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_addr : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_addr : metaArb_io_in_7_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_idx = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_idx : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_idx : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_idx : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_idx : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_idx : metaArb_io_in_7_bits_idx; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_way_en = metaArb_io_in_0_valid ? 8'hFF : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_way_en : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_way_en : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_way_en : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_way_en : metaArb_io_in_7_bits_way_en; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_data = metaArb_io_in_0_valid ? 22'h0 : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_data : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_data : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_data : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_data : metaArb_io_in_7_bits_data; // @[Arbiter.scala:143:15, :145:26, :147:19] wire metaArb__grant_T_1 = metaArb__grant_T | metaArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_2 = metaArb__grant_T_1 | metaArb_io_in_3_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_3 = metaArb__grant_T_2 | metaArb_io_in_4_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_4 = metaArb__grant_T_3; // @[Arbiter.scala:45:68] wire metaArb__grant_T_5 = metaArb__grant_T_4 | metaArb_io_in_6_valid; // @[Arbiter.scala:45:68] wire metaArb_grant_1 = ~metaArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign metaArb__io_in_1_ready_T = metaArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_2 = ~metaArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_2_ready_T = metaArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_3 = ~metaArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_3_ready_T = metaArb_grant_3; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_4 = ~metaArb__grant_T_2; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_4_ready_T = metaArb_grant_4; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_5 = ~metaArb__grant_T_3; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_5_ready_T = metaArb_grant_5; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_6 = ~metaArb__grant_T_4; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_6_ready_T = metaArb_grant_6; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_7 = ~metaArb__grant_T_5; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_7_ready_T = metaArb_grant_7; // @[Arbiter.scala:45:78, :153:19] assign metaArb_io_in_1_ready = metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_2_ready = metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_3_ready = metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_4_ready = metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_5_ready = metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_6_ready = metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_7_ready = metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_out_valid_T = ~metaArb_grant_7; // @[Arbiter.scala:45:78, :154:19] assign metaArb__io_out_valid_T_1 = metaArb__io_out_valid_T | metaArb_io_in_7_valid; // @[Arbiter.scala:154:{19,31}] assign metaArb_io_out_valid = metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _s1_meta_T_1; // @[DCache.scala:314:59] wire wmask_0; // @[DCache.scala:311:74] wire wmask_1; // @[DCache.scala:311:74] wire wmask_2; // @[DCache.scala:311:74] wire wmask_3; // @[DCache.scala:311:74] wire wmask_4; // @[DCache.scala:311:74] wire wmask_5; // @[DCache.scala:311:74] wire wmask_6; // @[DCache.scala:311:74] wire wmask_7; // @[DCache.scala:311:74] wire [21:0] _s1_meta_uncorrected_WIRE = _rockettile_dcache_tag_array_RW0_rdata[21:0]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_1 = _rockettile_dcache_tag_array_RW0_rdata[43:22]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_2 = _rockettile_dcache_tag_array_RW0_rdata[65:44]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_3 = _rockettile_dcache_tag_array_RW0_rdata[87:66]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_4 = _rockettile_dcache_tag_array_RW0_rdata[109:88]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_5 = _rockettile_dcache_tag_array_RW0_rdata[131:110]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_6 = _rockettile_dcache_tag_array_RW0_rdata[153:132]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_7 = _rockettile_dcache_tag_array_RW0_rdata[175:154]; // @[DescribedSRAM.scala:17:26] wire _dataArb_io_in_0_valid_T_12; // @[DCache.scala:516:27] wire pstore_drain; // @[DCache.scala:516:27] wire [127:0] _dataArb_io_in_0_bits_wdata_T_18; // @[package.scala:45:27] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_4; // @[DCache.scala:555:55] wire [7:0] _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:550:38] wire dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire [127:0] tl_d_data_encoded; // @[DCache.scala:324:31] wire dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_2_valid_T_1; // @[DCache.scala:900:41] wire [11:0] _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:903:72] wire dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_3_valid_T_58; // @[DCache.scala:242:46] wire dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [11:0] dataArb_io_in_0_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_write; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala:152:28] wire [1:0] dataArb_io_in_0_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_0_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_1_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_write; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_1_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_1_ready; // @[DCache.scala:152:28] wire dataArb_io_in_1_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_2_bits_addr; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_2_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_2_ready; // @[DCache.scala:152:28] wire dataArb_io_in_2_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_3_bits_addr; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala:152:28] wire [1:0] dataArb_io_in_3_bits_wordMask; // @[DCache.scala:152:28] wire dataArb_io_in_3_ready; // @[DCache.scala:152:28] wire dataArb_io_in_3_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_out_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_out_bits_write; // @[DCache.scala:152:28] wire [127:0] dataArb_io_out_bits_wdata; // @[DCache.scala:152:28] wire [1:0] dataArb_io_out_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_eccMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_out_valid; // @[DCache.scala:152:28] wire [1:0] dataArb_io_chosen; // @[DCache.scala:152:28] assign dataArb_io_chosen = dataArb_io_in_0_valid ? 2'h0 : dataArb_io_in_1_valid ? 2'h1 : {1'h1, ~dataArb_io_in_2_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17] assign dataArb_io_out_bits_addr = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_addr : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_addr : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_addr : dataArb_io_in_3_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_write = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_write : dataArb_io_in_1_valid & dataArb_io_in_1_bits_write; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_wdata = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wdata : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_wdata : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_wdata : dataArb_io_in_3_bits_wdata; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_wordMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wordMask : dataArb_io_in_1_valid | dataArb_io_in_2_valid ? 2'h3 : dataArb_io_in_3_bits_wordMask; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_eccMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_eccMask : 8'hFF; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_way_en = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_way_en : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_way_en : 8'hFF; // @[Arbiter.scala:145:26, :147:19] wire dataArb__grant_T = dataArb_io_in_0_valid | dataArb_io_in_1_valid; // @[Arbiter.scala:45:68] wire dataArb__grant_T_1 = dataArb__grant_T | dataArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire dataArb_grant_1 = ~dataArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign dataArb__io_in_1_ready_T = dataArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_2 = ~dataArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_2_ready_T = dataArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_3 = ~dataArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_3_ready_T = dataArb_grant_3; // @[Arbiter.scala:45:78, :153:19] assign dataArb_io_in_1_ready = dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_2_ready = dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_3_ready = dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire dataArb__io_out_valid_T = ~dataArb_grant_3; // @[Arbiter.scala:45:78, :154:19] assign dataArb__io_out_valid_T_1 = dataArb__io_out_valid_T | dataArb_io_in_3_valid; // @[Arbiter.scala:154:{19,31}] assign dataArb_io_out_valid = dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _tl_out_a_valid_T_14; // @[DCache.scala:603:37] assign nodeOut_a_deq_valid = tl_out_a_valid; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_9_opcode; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_opcode = tl_out_a_bits_opcode; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_9_param; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_param = tl_out_a_bits_param; // @[Decoupled.scala:356:21] wire [3:0] _tl_out_a_bits_T_9_size; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_size = tl_out_a_bits_size; // @[Decoupled.scala:356:21] wire _tl_out_a_bits_T_9_source; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_source = tl_out_a_bits_source; // @[Decoupled.scala:356:21] wire [31:0] _tl_out_a_bits_T_9_address; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_address = tl_out_a_bits_address; // @[Decoupled.scala:356:21] wire [15:0] _tl_out_a_bits_T_9_mask; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_mask = tl_out_a_bits_mask; // @[Decoupled.scala:356:21] wire [127:0] _tl_out_a_bits_T_9_data; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_data = tl_out_a_bits_data; // @[Decoupled.scala:356:21] wire tl_out_a_ready; // @[DCache.scala:159:22] assign tl_out_a_ready = nodeOut_a_deq_ready; // @[Decoupled.scala:356:21] assign nodeOut_a_valid = nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_opcode = nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_param = nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_size = nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_source = nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_address = nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_mask = nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_data = nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] wire _s1_valid_T = io_cpu_req_ready_0 & io_cpu_req_valid_0; // @[Decoupled.scala:51:35] reg s1_valid; // @[DCache.scala:182:25] wire _GEN_39 = nodeOut_b_ready & nodeOut_b_valid; // @[Decoupled.scala:51:35] wire _s1_probe_T; // @[Decoupled.scala:51:35] assign _s1_probe_T = _GEN_39; // @[Decoupled.scala:51:35] wire _probe_bits_T; // @[Decoupled.scala:51:35] assign _probe_bits_T = _GEN_39; // @[Decoupled.scala:51:35] reg s1_probe; // @[DCache.scala:183:25] reg [2:0] probe_bits_opcode; // @[DCache.scala:184:29] reg [1:0] probe_bits_param; // @[DCache.scala:184:29] reg [3:0] probe_bits_size; // @[DCache.scala:184:29] wire [3:0] nackResponseMessage_size = probe_bits_size; // @[Edges.scala:416:17] wire [3:0] cleanReleaseMessage_size = probe_bits_size; // @[Edges.scala:416:17] wire [3:0] dirtyReleaseMessage_size = probe_bits_size; // @[Edges.scala:433:17] reg probe_bits_source; // @[DCache.scala:184:29] assign nodeOut_c_bits_source = probe_bits_source; // @[DCache.scala:184:29] wire nackResponseMessage_source = probe_bits_source; // @[Edges.scala:416:17] wire cleanReleaseMessage_source = probe_bits_source; // @[Edges.scala:416:17] wire dirtyReleaseMessage_source = probe_bits_source; // @[Edges.scala:433:17] reg [31:0] probe_bits_address; // @[DCache.scala:184:29] assign nodeOut_c_bits_address = probe_bits_address; // @[DCache.scala:184:29] wire [31:0] nackResponseMessage_address = probe_bits_address; // @[Edges.scala:416:17] wire [31:0] cleanReleaseMessage_address = probe_bits_address; // @[Edges.scala:416:17] wire [31:0] dirtyReleaseMessage_address = probe_bits_address; // @[Edges.scala:433:17] reg [15:0] probe_bits_mask; // @[DCache.scala:184:29] reg [127:0] probe_bits_data; // @[DCache.scala:184:29] reg probe_bits_corrupt; // @[DCache.scala:184:29] wire s1_nack; // @[DCache.scala:185:28] wire _s1_valid_masked_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37] wire s1_valid_masked = s1_valid & _s1_valid_masked_T; // @[DCache.scala:182:25, :186:{34,37}] wire _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala:185:28, :187:41] wire s1_valid_not_nacked = s1_valid & _s1_valid_not_nacked_T; // @[DCache.scala:182:25, :187:{38,41}] wire _s0_clk_en_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43] wire s0_clk_en = metaArb_io_out_valid & _s0_clk_en_T; // @[DCache.scala:135:28, :190:{40,43}] wire _s1_tlb_req_T = s0_clk_en; // @[DCache.scala:190:40, :208:52] wire [39:0] _s0_req_addr_T_2; // @[DCache.scala:193:21] wire [39:0] s0_tlb_req_vaddr = s0_req_addr; // @[DCache.scala:192:24, :199:28] wire [4:0] s0_tlb_req_cmd = s0_req_cmd; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_size = s0_req_size; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_prv = s0_req_dprv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_v = s0_req_dv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_passthrough = s0_req_phys; // @[DCache.scala:192:24, :199:28] wire [33:0] _s0_req_addr_T = metaArb_io_out_bits_addr[39:6]; // @[DCache.scala:135:28, :193:47] wire [5:0] _s0_req_addr_T_1 = io_cpu_req_bits_addr_0[5:0]; // @[DCache.scala:101:7, :193:84] assign _s0_req_addr_T_2 = {_s0_req_addr_T, _s0_req_addr_T_1}; // @[DCache.scala:193:{21,47,84}] assign s0_req_addr = _s0_req_addr_T_2; // @[DCache.scala:192:24, :193:21] assign s0_req_phys = ~metaArb_io_in_7_ready | io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :135:28, :192:24, :195:{9,34,48}] reg [39:0] s1_req_addr; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_vaddr = s1_req_addr; // @[DCache.scala:120:32, :196:25] reg [7:0] s1_req_tag; // @[DCache.scala:196:25] reg [4:0] s1_req_cmd; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala:120:32, :196:25] reg [1:0] s1_req_size; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala:120:32, :196:25] wire [1:0] s1_mask_xwr_size = s1_req_size; // @[DCache.scala:196:25] reg s1_req_signed; // @[DCache.scala:196:25] reg [1:0] s1_req_dprv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_prv = s1_req_dprv; // @[DCache.scala:120:32, :196:25] reg s1_req_dv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_v = s1_req_dv; // @[DCache.scala:120:32, :196:25] reg s1_req_phys; // @[DCache.scala:196:25] reg s1_req_no_resp; // @[DCache.scala:196:25] reg s1_req_no_alloc; // @[DCache.scala:196:25] reg s1_req_no_xcpt; // @[DCache.scala:196:25] reg [63:0] s1_req_data; // @[DCache.scala:196:25] reg [7:0] s1_req_mask; // @[DCache.scala:196:25] wire [27:0] _s1_vaddr_T = s1_req_addr[39:12]; // @[DCache.scala:196:25, :197:56] wire [11:0] _s1_vaddr_T_1 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :197:78] wire [11:0] _s1_paddr_T_3 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :197:78, :298:125] wire [39:0] s1_vaddr = {_s1_vaddr_T, _s1_vaddr_T_1}; // @[DCache.scala:197:{21,56,78}] reg [39:0] s1_tlb_req_vaddr; // @[DCache.scala:208:29] reg s1_tlb_req_passthrough; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_size; // @[DCache.scala:208:29] reg [4:0] s1_tlb_req_cmd; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_prv; // @[DCache.scala:208:29] reg s1_tlb_req_v; // @[DCache.scala:208:29] wire _GEN_40 = s1_req_cmd == 5'h0; // @[package.scala:16:47] wire _s1_read_T; // @[package.scala:16:47] assign _s1_read_T = _GEN_40; // @[package.scala:16:47] wire _pstore1_rmw_T; // @[package.scala:16:47] assign _pstore1_rmw_T = _GEN_40; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_1; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_1 = _GEN_40; // @[package.scala:16:47] wire _GEN_41 = s1_req_cmd == 5'h10; // @[package.scala:16:47] wire _s1_read_T_1; // @[package.scala:16:47] assign _s1_read_T_1 = _GEN_41; // @[package.scala:16:47] wire _pstore1_rmw_T_1; // @[package.scala:16:47] assign _pstore1_rmw_T_1 = _GEN_41; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_2; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_2 = _GEN_41; // @[package.scala:16:47] wire _GEN_42 = s1_req_cmd == 5'h6; // @[package.scala:16:47] wire _s1_read_T_2; // @[package.scala:16:47] assign _s1_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _pstore1_rmw_T_2; // @[package.scala:16:47] assign _pstore1_rmw_T_2 = _GEN_42; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_3; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_3 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = s1_req_cmd == 5'h7; // @[package.scala:16:47] wire _s1_read_T_3; // @[package.scala:16:47] assign _s1_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _s1_write_T_3; // @[Consts.scala:90:66] assign _s1_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_3; // @[package.scala:16:47] assign _pstore1_rmw_T_3 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_28; // @[Consts.scala:90:66] assign _pstore1_rmw_T_28 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_4; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_4 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_29; // @[Consts.scala:90:66] assign _io_cpu_perf_canAcceptLoadThenLoad_T_29 = _GEN_43; // @[package.scala:16:47] wire _s1_read_T_4 = _s1_read_T | _s1_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_read_T_5 = _s1_read_T_4 | _s1_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_read_T_6 = _s1_read_T_5 | _s1_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_44 = s1_req_cmd == 5'h4; // @[package.scala:16:47] wire _s1_read_T_7; // @[package.scala:16:47] assign _s1_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _s1_write_T_5; // @[package.scala:16:47] assign _s1_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_7; // @[package.scala:16:47] assign _pstore1_rmw_T_7 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_30; // @[package.scala:16:47] assign _pstore1_rmw_T_30 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_8; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_8 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_31; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_31 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = s1_req_cmd == 5'h9; // @[package.scala:16:47] wire _s1_read_T_8; // @[package.scala:16:47] assign _s1_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _s1_write_T_6; // @[package.scala:16:47] assign _s1_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_8; // @[package.scala:16:47] assign _pstore1_rmw_T_8 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_31; // @[package.scala:16:47] assign _pstore1_rmw_T_31 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_9; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_9 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_32; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_32 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = s1_req_cmd == 5'hA; // @[package.scala:16:47] wire _s1_read_T_9; // @[package.scala:16:47] assign _s1_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _s1_write_T_7; // @[package.scala:16:47] assign _s1_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_9; // @[package.scala:16:47] assign _pstore1_rmw_T_9 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_32; // @[package.scala:16:47] assign _pstore1_rmw_T_32 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_10; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_10 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_33; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_33 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = s1_req_cmd == 5'hB; // @[package.scala:16:47] wire _s1_read_T_10; // @[package.scala:16:47] assign _s1_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _s1_write_T_8; // @[package.scala:16:47] assign _s1_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_10; // @[package.scala:16:47] assign _pstore1_rmw_T_10 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_33; // @[package.scala:16:47] assign _pstore1_rmw_T_33 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_11; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_11 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_34; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_34 = _GEN_47; // @[package.scala:16:47] wire _s1_read_T_11 = _s1_read_T_7 | _s1_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_read_T_12 = _s1_read_T_11 | _s1_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_read_T_13 = _s1_read_T_12 | _s1_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_48 = s1_req_cmd == 5'h8; // @[package.scala:16:47] wire _s1_read_T_14; // @[package.scala:16:47] assign _s1_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _s1_write_T_12; // @[package.scala:16:47] assign _s1_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_14; // @[package.scala:16:47] assign _pstore1_rmw_T_14 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_37; // @[package.scala:16:47] assign _pstore1_rmw_T_37 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_15; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_15 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_38; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_38 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = s1_req_cmd == 5'hC; // @[package.scala:16:47] wire _s1_read_T_15; // @[package.scala:16:47] assign _s1_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _s1_write_T_13; // @[package.scala:16:47] assign _s1_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_15; // @[package.scala:16:47] assign _pstore1_rmw_T_15 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_38; // @[package.scala:16:47] assign _pstore1_rmw_T_38 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_16; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_16 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_39; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_39 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = s1_req_cmd == 5'hD; // @[package.scala:16:47] wire _s1_read_T_16; // @[package.scala:16:47] assign _s1_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _s1_write_T_14; // @[package.scala:16:47] assign _s1_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_16; // @[package.scala:16:47] assign _pstore1_rmw_T_16 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_39; // @[package.scala:16:47] assign _pstore1_rmw_T_39 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_17; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_17 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_40; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_40 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = s1_req_cmd == 5'hE; // @[package.scala:16:47] wire _s1_read_T_17; // @[package.scala:16:47] assign _s1_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _s1_write_T_15; // @[package.scala:16:47] assign _s1_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_17; // @[package.scala:16:47] assign _pstore1_rmw_T_17 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_40; // @[package.scala:16:47] assign _pstore1_rmw_T_40 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_18; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_18 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_41; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_41 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = s1_req_cmd == 5'hF; // @[package.scala:16:47] wire _s1_read_T_18; // @[package.scala:16:47] assign _s1_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _s1_write_T_16; // @[package.scala:16:47] assign _s1_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _pstore1_rmw_T_18; // @[package.scala:16:47] assign _pstore1_rmw_T_18 = _GEN_52; // @[package.scala:16:47] wire _pstore1_rmw_T_41; // @[package.scala:16:47] assign _pstore1_rmw_T_41 = _GEN_52; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_19; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_19 = _GEN_52; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_42; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_42 = _GEN_52; // @[package.scala:16:47] wire _s1_read_T_19 = _s1_read_T_14 | _s1_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_read_T_20 = _s1_read_T_19 | _s1_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_read_T_21 = _s1_read_T_20 | _s1_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_read_T_22 = _s1_read_T_21 | _s1_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_read_T_23 = _s1_read_T_13 | _s1_read_T_22; // @[package.scala:81:59] wire s1_read = _s1_read_T_6 | _s1_read_T_23; // @[package.scala:81:59] wire _GEN_53 = s1_req_cmd == 5'h1; // @[DCache.scala:196:25] wire _s1_write_T; // @[Consts.scala:90:32] assign _s1_write_T = _GEN_53; // @[Consts.scala:90:32] wire _pstore1_rmw_T_25; // @[Consts.scala:90:32] assign _pstore1_rmw_T_25 = _GEN_53; // @[Consts.scala:90:32] wire _io_cpu_perf_canAcceptLoadThenLoad_T_26; // @[Consts.scala:90:32] assign _io_cpu_perf_canAcceptLoadThenLoad_T_26 = _GEN_53; // @[Consts.scala:90:32] wire _T_20 = s1_req_cmd == 5'h11; // @[DCache.scala:196:25] wire _s1_write_T_1; // @[Consts.scala:90:49] assign _s1_write_T_1 = _T_20; // @[Consts.scala:90:49] wire _s1_mask_T; // @[DCache.scala:327:32] assign _s1_mask_T = _T_20; // @[DCache.scala:327:32] wire _pstore1_rmw_T_26; // @[Consts.scala:90:49] assign _pstore1_rmw_T_26 = _T_20; // @[Consts.scala:90:49] wire _pstore1_rmw_T_48; // @[DCache.scala:1191:35] assign _pstore1_rmw_T_48 = _T_20; // @[DCache.scala:1191:35] wire _io_cpu_perf_canAcceptLoadThenLoad_T_27; // @[Consts.scala:90:49] assign _io_cpu_perf_canAcceptLoadThenLoad_T_27 = _T_20; // @[Consts.scala:90:49] wire _io_cpu_perf_canAcceptLoadThenLoad_T_49; // @[DCache.scala:1191:35] assign _io_cpu_perf_canAcceptLoadThenLoad_T_49 = _T_20; // @[DCache.scala:1191:35] wire _s1_write_T_2 = _s1_write_T | _s1_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s1_write_T_4 = _s1_write_T_2 | _s1_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s1_write_T_9 = _s1_write_T_5 | _s1_write_T_6; // @[package.scala:16:47, :81:59] wire _s1_write_T_10 = _s1_write_T_9 | _s1_write_T_7; // @[package.scala:16:47, :81:59] wire _s1_write_T_11 = _s1_write_T_10 | _s1_write_T_8; // @[package.scala:16:47, :81:59] wire _s1_write_T_17 = _s1_write_T_12 | _s1_write_T_13; // @[package.scala:16:47, :81:59] wire _s1_write_T_18 = _s1_write_T_17 | _s1_write_T_14; // @[package.scala:16:47, :81:59] wire _s1_write_T_19 = _s1_write_T_18 | _s1_write_T_15; // @[package.scala:16:47, :81:59] wire _s1_write_T_20 = _s1_write_T_19 | _s1_write_T_16; // @[package.scala:16:47, :81:59] wire _s1_write_T_21 = _s1_write_T_11 | _s1_write_T_20; // @[package.scala:81:59] wire s1_write = _s1_write_T_4 | _s1_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s1_readwrite = s1_read | s1_write; // @[DCache.scala:212:30] wire _s1_sfence_T = s1_req_cmd == 5'h14; // @[DCache.scala:196:25, :213:30] wire _GEN_54 = s1_req_cmd == 5'h15; // @[DCache.scala:196:25, :213:57] wire _s1_sfence_T_1; // @[DCache.scala:213:57] assign _s1_sfence_T_1 = _GEN_54; // @[DCache.scala:213:57] wire _tlb_io_sfence_bits_hv_T; // @[DCache.scala:283:39] assign _tlb_io_sfence_bits_hv_T = _GEN_54; // @[DCache.scala:213:57, :283:39] wire _s1_sfence_T_2 = _s1_sfence_T | _s1_sfence_T_1; // @[DCache.scala:213:{30,43,57}] wire _GEN_55 = s1_req_cmd == 5'h16; // @[DCache.scala:196:25, :213:85] wire _s1_sfence_T_3; // @[DCache.scala:213:85] assign _s1_sfence_T_3 = _GEN_55; // @[DCache.scala:213:85] wire _tlb_io_sfence_bits_hg_T; // @[DCache.scala:284:39] assign _tlb_io_sfence_bits_hg_T = _GEN_55; // @[DCache.scala:213:85, :284:39] wire s1_sfence = _s1_sfence_T_2 | _s1_sfence_T_3; // @[DCache.scala:213:{43,71,85}] wire _s1_flush_line_T = s1_req_cmd == 5'h5; // @[DCache.scala:196:25, :214:34] wire _s1_flush_line_T_1 = s1_req_size[0]; // @[DCache.scala:196:25, :214:64] wire _tlb_io_sfence_bits_rs1_T = s1_req_size[0]; // @[DCache.scala:196:25, :214:64, :279:40] wire s1_flush_line = _s1_flush_line_T & _s1_flush_line_T_1; // @[DCache.scala:214:{34,50,64}] reg s1_flush_valid; // @[DCache.scala:215:27] reg cached_grant_wait; // @[DCache.scala:223:34] reg resetting; // @[DCache.scala:224:26] assign metaArb_io_in_0_valid = resetting; // @[DCache.scala:135:28, :224:26] reg [8:0] flushCounter; // @[DCache.scala:225:29] reg release_ack_wait; // @[DCache.scala:226:33] reg [31:0] release_ack_addr; // @[DCache.scala:227:29] reg [3:0] release_state; // @[DCache.scala:228:30] reg [7:0] refill_way; // @[DCache.scala:229:23] assign metaArb_io_in_3_bits_way_en = refill_way; // @[DCache.scala:135:28, :229:23] assign dataArb_io_in_1_bits_way_en = refill_way; // @[DCache.scala:152:28, :229:23] wire _any_pstore_valid_T; // @[DCache.scala:508:36] wire any_pstore_valid; // @[DCache.scala:230:30] wire _T_114 = release_state == 4'h1; // @[package.scala:16:47] wire _inWriteback_T; // @[package.scala:16:47] assign _inWriteback_T = _T_114; // @[package.scala:16:47] wire _canAcceptCachedGrant_T; // @[package.scala:16:47] assign _canAcceptCachedGrant_T = _T_114; // @[package.scala:16:47] wire _inWriteback_T_1 = release_state == 4'h2; // @[package.scala:16:47] wire inWriteback = _inWriteback_T | _inWriteback_T_1; // @[package.scala:16:47, :81:59] assign metaArb_io_in_4_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_5_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_6_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_7_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] wire _io_cpu_req_ready_T = ~(|release_state); // @[DCache.scala:228:30, :233:38] wire _io_cpu_req_ready_T_1 = ~cached_grant_wait; // @[DCache.scala:223:34, :233:54] wire _io_cpu_req_ready_T_2 = _io_cpu_req_ready_T & _io_cpu_req_ready_T_1; // @[DCache.scala:233:{38,51,54}] wire _io_cpu_req_ready_T_3 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :233:76] wire _io_cpu_req_ready_T_4 = _io_cpu_req_ready_T_2 & _io_cpu_req_ready_T_3; // @[DCache.scala:233:{51,73,76}] reg uncachedInFlight_0; // @[DCache.scala:236:33] wire _s2_valid_cached_miss_T_2 = uncachedInFlight_0; // @[DCache.scala:236:33, :425:88] wire _s2_valid_uncached_pending_T_1 = uncachedInFlight_0; // @[DCache.scala:236:33, :430:92] wire _io_cpu_ordered_T_6 = uncachedInFlight_0; // @[DCache.scala:236:33, :929:142] wire _io_cpu_store_pending_T_24 = uncachedInFlight_0; // @[DCache.scala:236:33, :930:97] wire _clock_en_reg_T_22 = uncachedInFlight_0; // @[DCache.scala:236:33, :1072:50] reg [39:0] uncachedReqs_0_addr; // @[DCache.scala:237:25] wire [39:0] uncachedResp_addr = uncachedReqs_0_addr; // @[DCache.scala:237:25, :238:30] reg [7:0] uncachedReqs_0_tag; // @[DCache.scala:237:25] wire [7:0] uncachedResp_tag = uncachedReqs_0_tag; // @[DCache.scala:237:25, :238:30] reg [4:0] uncachedReqs_0_cmd; // @[DCache.scala:237:25] wire [4:0] uncachedResp_cmd = uncachedReqs_0_cmd; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_size; // @[DCache.scala:237:25] wire [1:0] uncachedResp_size = uncachedReqs_0_size; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_signed; // @[DCache.scala:237:25] wire uncachedResp_signed = uncachedReqs_0_signed; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_dprv; // @[DCache.scala:237:25] wire [1:0] uncachedResp_dprv = uncachedReqs_0_dprv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_dv; // @[DCache.scala:237:25] wire uncachedResp_dv = uncachedReqs_0_dv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_phys; // @[DCache.scala:237:25] wire uncachedResp_phys = uncachedReqs_0_phys; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_resp; // @[DCache.scala:237:25] wire uncachedResp_no_resp = uncachedReqs_0_no_resp; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_alloc; // @[DCache.scala:237:25] wire uncachedResp_no_alloc = uncachedReqs_0_no_alloc; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25] wire uncachedResp_no_xcpt = uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25, :238:30] reg [63:0] uncachedReqs_0_data; // @[DCache.scala:237:25] wire [63:0] uncachedResp_data = uncachedReqs_0_data; // @[DCache.scala:237:25, :238:30] reg [7:0] uncachedReqs_0_mask; // @[DCache.scala:237:25] wire [7:0] uncachedResp_mask = uncachedReqs_0_mask; // @[DCache.scala:237:25, :238:30] wire _GEN_56 = io_cpu_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _s0_read_T; // @[package.scala:16:47] assign _s0_read_T = _GEN_56; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T = _GEN_56; // @[package.scala:16:47] wire _s1_did_read_T; // @[package.scala:16:47] assign _s1_did_read_T = _GEN_56; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = io_cpu_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _s0_read_T_1; // @[package.scala:16:47] assign _s0_read_T_1 = _GEN_57; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_1 = _GEN_57; // @[package.scala:16:47] wire _s1_did_read_T_1; // @[package.scala:16:47] assign _s1_did_read_T_1 = _GEN_57; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_1 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = io_cpu_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _s0_read_T_2; // @[package.scala:16:47] assign _s0_read_T_2 = _GEN_58; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_2 = _GEN_58; // @[package.scala:16:47] wire _s1_did_read_T_2; // @[package.scala:16:47] assign _s1_did_read_T_2 = _GEN_58; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_2; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_2 = _GEN_58; // @[package.scala:16:47] wire _GEN_59 = io_cpu_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _s0_read_T_3; // @[package.scala:16:47] assign _s0_read_T_3 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_3 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:66] assign _dataArb_io_in_3_valid_T_28 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_3; // @[package.scala:16:47] assign _s1_did_read_T_3 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_28; // @[Consts.scala:90:66] assign _s1_did_read_T_28 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_3; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_3 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:66] assign _pstore_drain_opportunistic_T_28 = _GEN_59; // @[package.scala:16:47] wire _s0_read_T_4 = _s0_read_T | _s0_read_T_1; // @[package.scala:16:47, :81:59] wire _s0_read_T_5 = _s0_read_T_4 | _s0_read_T_2; // @[package.scala:16:47, :81:59] wire _s0_read_T_6 = _s0_read_T_5 | _s0_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_60 = io_cpu_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _s0_read_T_7; // @[package.scala:16:47] assign _s0_read_T_7 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_7; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_7 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_30; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_30 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_7; // @[package.scala:16:47] assign _s1_did_read_T_7 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_30; // @[package.scala:16:47] assign _s1_did_read_T_30 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_7; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_7 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_30; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_30 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_cpu_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _s0_read_T_8; // @[package.scala:16:47] assign _s0_read_T_8 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_8 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_31 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_8; // @[package.scala:16:47] assign _s1_did_read_T_8 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_31; // @[package.scala:16:47] assign _s1_did_read_T_31 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_8; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_8 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_31; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_31 = _GEN_61; // @[package.scala:16:47] wire _GEN_62 = io_cpu_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _s0_read_T_9; // @[package.scala:16:47] assign _s0_read_T_9 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_9 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_32 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_9; // @[package.scala:16:47] assign _s1_did_read_T_9 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_32; // @[package.scala:16:47] assign _s1_did_read_T_32 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_9; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_9 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_32; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_32 = _GEN_62; // @[package.scala:16:47] wire _GEN_63 = io_cpu_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _s0_read_T_10; // @[package.scala:16:47] assign _s0_read_T_10 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_10 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_33 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_10; // @[package.scala:16:47] assign _s1_did_read_T_10 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_33; // @[package.scala:16:47] assign _s1_did_read_T_33 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_10; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_10 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_33; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_33 = _GEN_63; // @[package.scala:16:47] wire _s0_read_T_11 = _s0_read_T_7 | _s0_read_T_8; // @[package.scala:16:47, :81:59] wire _s0_read_T_12 = _s0_read_T_11 | _s0_read_T_9; // @[package.scala:16:47, :81:59] wire _s0_read_T_13 = _s0_read_T_12 | _s0_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_64 = io_cpu_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _s0_read_T_14; // @[package.scala:16:47] assign _s0_read_T_14 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_14; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_14 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_37; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_37 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_14; // @[package.scala:16:47] assign _s1_did_read_T_14 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_37; // @[package.scala:16:47] assign _s1_did_read_T_37 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_14; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_14 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_37; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_37 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_cpu_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _s0_read_T_15; // @[package.scala:16:47] assign _s0_read_T_15 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_15 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_38 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_15; // @[package.scala:16:47] assign _s1_did_read_T_15 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_38; // @[package.scala:16:47] assign _s1_did_read_T_38 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_15; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_15 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_38; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_38 = _GEN_65; // @[package.scala:16:47] wire _GEN_66 = io_cpu_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _s0_read_T_16; // @[package.scala:16:47] assign _s0_read_T_16 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_16 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_39 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_16; // @[package.scala:16:47] assign _s1_did_read_T_16 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_39; // @[package.scala:16:47] assign _s1_did_read_T_39 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_16; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_16 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_39; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_39 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_cpu_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _s0_read_T_17; // @[package.scala:16:47] assign _s0_read_T_17 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_17 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_40 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_17; // @[package.scala:16:47] assign _s1_did_read_T_17 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_40; // @[package.scala:16:47] assign _s1_did_read_T_40 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_17; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_17 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_40; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_40 = _GEN_67; // @[package.scala:16:47] wire _GEN_68 = io_cpu_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _s0_read_T_18; // @[package.scala:16:47] assign _s0_read_T_18 = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_18 = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_41 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_18; // @[package.scala:16:47] assign _s1_did_read_T_18 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_41; // @[package.scala:16:47] assign _s1_did_read_T_41 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_18; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_18 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_41; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_41 = _GEN_68; // @[package.scala:16:47] wire _s0_read_T_19 = _s0_read_T_14 | _s0_read_T_15; // @[package.scala:16:47, :81:59] wire _s0_read_T_20 = _s0_read_T_19 | _s0_read_T_16; // @[package.scala:16:47, :81:59] wire _s0_read_T_21 = _s0_read_T_20 | _s0_read_T_17; // @[package.scala:16:47, :81:59] wire _s0_read_T_22 = _s0_read_T_21 | _s0_read_T_18; // @[package.scala:16:47, :81:59] wire _s0_read_T_23 = _s0_read_T_13 | _s0_read_T_22; // @[package.scala:81:59] wire s0_read = _s0_read_T_6 | _s0_read_T_23; // @[package.scala:81:59] wire _GEN_69 = io_cpu_req_bits_cmd_0 == 5'h1; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T = _GEN_69; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_25; // @[Consts.scala:90:32] assign _dataArb_io_in_3_valid_T_25 = _GEN_69; // @[package.scala:16:47] wire _s1_did_read_T_25; // @[Consts.scala:90:32] assign _s1_did_read_T_25 = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_25; // @[Consts.scala:90:32] assign _pstore_drain_opportunistic_T_25 = _GEN_69; // @[package.scala:16:47] wire _GEN_70 = io_cpu_req_bits_cmd_0 == 5'h3; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T_1 = _GEN_70; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T_1 = _GEN_70; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_2 = _dataArb_io_in_3_valid_res_T | _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_res_T_3 = ~_dataArb_io_in_3_valid_res_T_2; // @[package.scala:81:59] wire dataArb_io_in_3_valid_res = _dataArb_io_in_3_valid_res_T_3; // @[DCache.scala:1185:{15,46}] wire _dataArb_io_in_3_valid_T_4 = _dataArb_io_in_3_valid_T | _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_5 = _dataArb_io_in_3_valid_T_4 | _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_6 = _dataArb_io_in_3_valid_T_5 | _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_11 = _dataArb_io_in_3_valid_T_7 | _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_12 = _dataArb_io_in_3_valid_T_11 | _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_13 = _dataArb_io_in_3_valid_T_12 | _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_19 = _dataArb_io_in_3_valid_T_14 | _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_20 = _dataArb_io_in_3_valid_T_19 | _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_21 = _dataArb_io_in_3_valid_T_20 | _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_22 = _dataArb_io_in_3_valid_T_21 | _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_23 = _dataArb_io_in_3_valid_T_13 | _dataArb_io_in_3_valid_T_22; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_24 = _dataArb_io_in_3_valid_T_6 | _dataArb_io_in_3_valid_T_23; // @[package.scala:81:59] wire _GEN_71 = io_cpu_req_bits_cmd_0 == 5'h11; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:49] assign _dataArb_io_in_3_valid_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:35] assign _dataArb_io_in_3_valid_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _s1_did_read_T_26; // @[Consts.scala:90:49] assign _s1_did_read_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _s1_did_read_T_48; // @[DCache.scala:1191:35] assign _s1_did_read_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:49] assign _pstore_drain_opportunistic_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:35] assign _pstore_drain_opportunistic_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _dataArb_io_in_3_valid_T_27 = _dataArb_io_in_3_valid_T_25 | _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:{32,42,49}] wire _dataArb_io_in_3_valid_T_29 = _dataArb_io_in_3_valid_T_27 | _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:{42,59,66}] wire _dataArb_io_in_3_valid_T_34 = _dataArb_io_in_3_valid_T_30 | _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_35 = _dataArb_io_in_3_valid_T_34 | _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_36 = _dataArb_io_in_3_valid_T_35 | _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_42 = _dataArb_io_in_3_valid_T_37 | _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_43 = _dataArb_io_in_3_valid_T_42 | _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_44 = _dataArb_io_in_3_valid_T_43 | _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_45 = _dataArb_io_in_3_valid_T_44 | _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_46 = _dataArb_io_in_3_valid_T_36 | _dataArb_io_in_3_valid_T_45; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_47 = _dataArb_io_in_3_valid_T_29 | _dataArb_io_in_3_valid_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _dataArb_io_in_3_valid_T_50 = _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:{35,45}] wire _dataArb_io_in_3_valid_T_51 = _dataArb_io_in_3_valid_T_47 & _dataArb_io_in_3_valid_T_50; // @[DCache.scala:1191:{23,45}] wire _dataArb_io_in_3_valid_T_52 = _dataArb_io_in_3_valid_T_24 | _dataArb_io_in_3_valid_T_51; // @[DCache.scala:1190:21, :1191:23] wire _dataArb_io_in_3_valid_T_53 = ~_dataArb_io_in_3_valid_T_52; // @[DCache.scala:1186:12, :1190:21] wire _dataArb_io_in_3_valid_T_54 = _dataArb_io_in_3_valid_T_53 | dataArb_io_in_3_valid_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _dataArb_io_in_3_valid_T_56 = ~_dataArb_io_in_3_valid_T_55; // @[DCache.scala:1186:11] wire _dataArb_io_in_3_valid_T_57 = ~_dataArb_io_in_3_valid_T_54; // @[DCache.scala:1186:{11,28}] assign _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid_0 & dataArb_io_in_3_valid_res; // @[DCache.scala:101:7, :242:46, :1185:46] assign dataArb_io_in_3_valid = _dataArb_io_in_3_valid_T_58; // @[DCache.scala:152:28, :242:46] wire [27:0] _dataArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89] wire [27:0] _metaArb_io_in_1_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :454:58] wire [27:0] _metaArb_io_in_2_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :466:58] wire [27:0] _metaArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :745:58] wire [27:0] _metaArb_io_in_4_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :912:58] wire [27:0] _metaArb_io_in_5_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :1018:58] wire [11:0] _dataArb_io_in_3_bits_addr_T_1 = io_cpu_req_bits_addr_0[11:0]; // @[DCache.scala:101:7, :245:120] wire [39:0] _dataArb_io_in_3_bits_addr_T_2 = {_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:245:{36,89,120}] assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[11:0]; // @[DCache.scala:152:28, :245:{30,36}] wire _dataArb_io_in_3_bits_wordMask_mask_upper_T = io_cpu_req_bits_addr_0[3]; // @[DCache.scala:101:7, :250:43] wire _dataArb_io_in_3_bits_wordMask_mask_lower_T = io_cpu_req_bits_addr_0[3]; // @[DCache.scala:101:7, :250:43, :251:43] wire _dataArb_io_in_3_bits_wordMask_mask_upper_T_1 = _dataArb_io_in_3_bits_wordMask_mask_upper_T; // @[DCache.scala:250:{22,43}] wire dataArb_io_in_3_bits_wordMask_mask_upper = _dataArb_io_in_3_bits_wordMask_mask_upper_T_1; // @[DCache.scala:250:{22,57}] wire dataArb_io_in_3_bits_wordMask_mask_lower = ~_dataArb_io_in_3_bits_wordMask_mask_lower_T; // @[DCache.scala:251:{22,43}] wire [1:0] dataArb_io_in_3_bits_wordMask_mask = {dataArb_io_in_3_bits_wordMask_mask_upper, dataArb_io_in_3_bits_wordMask_mask_lower}; // @[DCache.scala:250:57, :251:22, :252:13] wire [3:0] _dataArb_io_in_3_bits_wordMask_T = {2{dataArb_io_in_3_bits_wordMask_mask}}; // @[DCache.scala:252:13, :254:9] wire [7:0] _dataArb_io_in_3_bits_wordMask_T_1 = {2{_dataArb_io_in_3_bits_wordMask_T}}; // @[DCache.scala:254:9] wire [15:0] _dataArb_io_in_3_bits_wordMask_T_2 = {2{_dataArb_io_in_3_bits_wordMask_T_1}}; // @[DCache.scala:254:9] assign dataArb_io_in_3_bits_wordMask = _dataArb_io_in_3_bits_wordMask_T_2[1:0]; // @[DCache.scala:152:28, :246:34, :254:9] wire _T_4 = ~dataArb_io_in_3_ready & s0_read; // @[DCache.scala:152:28, :258:{9,33}] wire _s1_did_read_T_4 = _s1_did_read_T | _s1_did_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_5 = _s1_did_read_T_4 | _s1_did_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_6 = _s1_did_read_T_5 | _s1_did_read_T_3; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_11 = _s1_did_read_T_7 | _s1_did_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_12 = _s1_did_read_T_11 | _s1_did_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_13 = _s1_did_read_T_12 | _s1_did_read_T_10; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_19 = _s1_did_read_T_14 | _s1_did_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_20 = _s1_did_read_T_19 | _s1_did_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_21 = _s1_did_read_T_20 | _s1_did_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_22 = _s1_did_read_T_21 | _s1_did_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_23 = _s1_did_read_T_13 | _s1_did_read_T_22; // @[package.scala:81:59] wire _s1_did_read_T_24 = _s1_did_read_T_6 | _s1_did_read_T_23; // @[package.scala:81:59] wire _s1_did_read_T_27 = _s1_did_read_T_25 | _s1_did_read_T_26; // @[Consts.scala:90:{32,42,49}] wire _s1_did_read_T_29 = _s1_did_read_T_27 | _s1_did_read_T_28; // @[Consts.scala:90:{42,59,66}] wire _s1_did_read_T_34 = _s1_did_read_T_30 | _s1_did_read_T_31; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_35 = _s1_did_read_T_34 | _s1_did_read_T_32; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_36 = _s1_did_read_T_35 | _s1_did_read_T_33; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_42 = _s1_did_read_T_37 | _s1_did_read_T_38; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_43 = _s1_did_read_T_42 | _s1_did_read_T_39; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_44 = _s1_did_read_T_43 | _s1_did_read_T_40; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_45 = _s1_did_read_T_44 | _s1_did_read_T_41; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_46 = _s1_did_read_T_36 | _s1_did_read_T_45; // @[package.scala:81:59] wire _s1_did_read_T_47 = _s1_did_read_T_29 | _s1_did_read_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _s1_did_read_T_50 = _s1_did_read_T_48; // @[DCache.scala:1191:{35,45}] wire _s1_did_read_T_51 = _s1_did_read_T_47 & _s1_did_read_T_50; // @[DCache.scala:1191:{23,45}] wire _s1_did_read_T_52 = _s1_did_read_T_24 | _s1_did_read_T_51; // @[DCache.scala:1190:21, :1191:23] wire _s1_did_read_T_53 = io_cpu_req_valid_0 & _s1_did_read_T_52; // @[DCache.scala:101:7, :259:75, :1190:21] wire _s1_did_read_T_54 = dataArb_io_in_3_ready & _s1_did_read_T_53; // @[DCache.scala:152:28, :259:{54,75}] reg s1_did_read; // @[DCache.scala:259:30] reg [1:0] s1_read_mask; // @[DCache.scala:260:31] assign _metaArb_io_in_7_bits_idx_T = _dataArb_io_in_3_bits_addr_T_2[11:6]; // @[DCache.scala:245:36, :263:58] assign metaArb_io_in_7_bits_idx = _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:135:28, :263:58] wire _s1_cmd_uses_tlb_T = s1_readwrite | s1_flush_line; // @[DCache.scala:212:30, :214:50, :270:38] wire _s1_cmd_uses_tlb_T_1 = s1_req_cmd == 5'h17; // @[DCache.scala:196:25, :270:69] wire s1_cmd_uses_tlb = _s1_cmd_uses_tlb_T | _s1_cmd_uses_tlb_T_1; // @[DCache.scala:270:{38,55,69}] wire _tlb_io_req_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :273:55] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[DCache.scala:182:25, :273:{52,55}] wire _tlb_io_req_valid_T_2 = _tlb_io_req_valid_T_1 & s1_cmd_uses_tlb; // @[DCache.scala:270:55, :273:{52,71}] wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_2; // @[DCache.scala:273:{40,71}] wire _T_10 = ~_tlb_io_req_ready & ~io_ptw_resp_valid_0 & ~io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :119:19, :275:{9,27,30,53,56}] wire _T_14 = s1_valid & s1_cmd_uses_tlb & _tlb_io_resp_miss; // @[DCache.scala:119:19, :182:25, :270:55, :276:{39,58}] wire _tlb_io_sfence_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :278:38] wire _tlb_io_sfence_valid_T_1 = s1_valid & _tlb_io_sfence_valid_T; // @[DCache.scala:182:25, :278:{35,38}] wire _tlb_io_sfence_valid_T_2 = _tlb_io_sfence_valid_T_1 & s1_sfence; // @[DCache.scala:213:71, :278:{35,54}] wire _tlb_io_sfence_bits_rs2_T = s1_req_size[1]; // @[DCache.scala:196:25, :280:40] wire [19:0] _s1_paddr_T = s1_req_addr[31:12]; // @[DCache.scala:196:25, :298:55] wire [19:0] _s1_paddr_T_1 = _tlb_io_resp_paddr[31:12]; // @[DCache.scala:119:19, :298:99] wire [19:0] _s1_paddr_T_2 = _s1_paddr_T_1; // @[DCache.scala:298:{25,99}] wire [31:0] s1_paddr = {_s1_paddr_T_2, _s1_paddr_T_3}; // @[DCache.scala:298:{21,25,125}] wire [2:0] _s1_victim_way_T; // @[package.scala:163:13] wire [2:0] s1_victim_way; // @[DCache.scala:299:27] assign rockettile_dcache_tag_array_MPORT_en = metaArb_io_out_valid & metaArb_io_out_bits_write; // @[DCache.scala:135:28, :310:27] assign wmask_0 = metaArb_io_out_bits_way_en[0]; // @[DCache.scala:135:28, :311:74] assign wmask_1 = metaArb_io_out_bits_way_en[1]; // @[DCache.scala:135:28, :311:74] assign wmask_2 = metaArb_io_out_bits_way_en[2]; // @[DCache.scala:135:28, :311:74] assign wmask_3 = metaArb_io_out_bits_way_en[3]; // @[DCache.scala:135:28, :311:74] assign wmask_4 = metaArb_io_out_bits_way_en[4]; // @[DCache.scala:135:28, :311:74] assign wmask_5 = metaArb_io_out_bits_way_en[5]; // @[DCache.scala:135:28, :311:74] assign wmask_6 = metaArb_io_out_bits_way_en[6]; // @[DCache.scala:135:28, :311:74] assign wmask_7 = metaArb_io_out_bits_way_en[7]; // @[DCache.scala:135:28, :311:74] wire _s1_meta_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43, :314:62] assign _s1_meta_T_1 = metaArb_io_out_valid & _s1_meta_T; // @[DCache.scala:135:28, :314:{59,62}] wire [1:0] _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_0_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_0_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T = _s1_meta_uncorrected_WIRE[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_0_tag = _s1_meta_uncorrected_T; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_1 = _s1_meta_uncorrected_WIRE[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_0_coh_state = _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_1_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_1_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_2 = _s1_meta_uncorrected_WIRE_1[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_1_tag = _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_3 = _s1_meta_uncorrected_WIRE_1[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_1_coh_state = _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_2_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_2_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_4 = _s1_meta_uncorrected_WIRE_2[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_2_tag = _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_5 = _s1_meta_uncorrected_WIRE_2[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_2_coh_state = _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_3_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_3_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_6 = _s1_meta_uncorrected_WIRE_3[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_3_tag = _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_7 = _s1_meta_uncorrected_WIRE_3[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_3_coh_state = _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_9; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_8; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_4_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_4_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_8 = _s1_meta_uncorrected_WIRE_4[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_4_tag = _s1_meta_uncorrected_T_8; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_9 = _s1_meta_uncorrected_WIRE_4[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_4_coh_state = _s1_meta_uncorrected_T_9; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_11; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_10; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_5_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_5_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_10 = _s1_meta_uncorrected_WIRE_5[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_5_tag = _s1_meta_uncorrected_T_10; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_11 = _s1_meta_uncorrected_WIRE_5[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_5_coh_state = _s1_meta_uncorrected_T_11; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_13; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_12; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_6_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_6_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_12 = _s1_meta_uncorrected_WIRE_6[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_6_tag = _s1_meta_uncorrected_T_12; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_13 = _s1_meta_uncorrected_WIRE_6[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_6_coh_state = _s1_meta_uncorrected_T_13; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_15; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_14; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_7_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_7_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_14 = _s1_meta_uncorrected_WIRE_7[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_7_tag = _s1_meta_uncorrected_T_14; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_15 = _s1_meta_uncorrected_WIRE_7[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_7_coh_state = _s1_meta_uncorrected_T_15; // @[DCache.scala:315:80] wire [19:0] s1_tag = s1_paddr[31:12]; // @[DCache.scala:298:21, :316:29] wire _s1_meta_hit_way_T = |s1_meta_uncorrected_0_coh_state; // @[Metadata.scala:50:45] wire _GEN_72 = s1_meta_uncorrected_0_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_1; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_1 = _GEN_72; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T = _GEN_72; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_2 = _s1_meta_hit_way_T & _s1_meta_hit_way_T_1; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_3 = |s1_meta_uncorrected_1_coh_state; // @[Metadata.scala:50:45] wire _GEN_73 = s1_meta_uncorrected_1_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_4; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_4 = _GEN_73; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_4; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_4 = _GEN_73; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_5 = _s1_meta_hit_way_T_3 & _s1_meta_hit_way_T_4; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_6 = |s1_meta_uncorrected_2_coh_state; // @[Metadata.scala:50:45] wire _GEN_74 = s1_meta_uncorrected_2_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_7; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_7 = _GEN_74; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_8; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_8 = _GEN_74; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_8 = _s1_meta_hit_way_T_6 & _s1_meta_hit_way_T_7; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_9 = |s1_meta_uncorrected_3_coh_state; // @[Metadata.scala:50:45] wire _GEN_75 = s1_meta_uncorrected_3_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_10; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_10 = _GEN_75; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_12; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_12 = _GEN_75; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_11 = _s1_meta_hit_way_T_9 & _s1_meta_hit_way_T_10; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_12 = |s1_meta_uncorrected_4_coh_state; // @[Metadata.scala:50:45] wire _GEN_76 = s1_meta_uncorrected_4_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_13; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_13 = _GEN_76; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_16; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_16 = _GEN_76; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_14 = _s1_meta_hit_way_T_12 & _s1_meta_hit_way_T_13; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_15 = |s1_meta_uncorrected_5_coh_state; // @[Metadata.scala:50:45] wire _GEN_77 = s1_meta_uncorrected_5_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_16; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_16 = _GEN_77; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_20; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_20 = _GEN_77; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_17 = _s1_meta_hit_way_T_15 & _s1_meta_hit_way_T_16; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_18 = |s1_meta_uncorrected_6_coh_state; // @[Metadata.scala:50:45] wire _GEN_78 = s1_meta_uncorrected_6_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_19; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_19 = _GEN_78; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_24; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_24 = _GEN_78; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_20 = _s1_meta_hit_way_T_18 & _s1_meta_hit_way_T_19; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_21 = |s1_meta_uncorrected_7_coh_state; // @[Metadata.scala:50:45] wire _GEN_79 = s1_meta_uncorrected_7_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_22; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_22 = _GEN_79; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_28; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_28 = _GEN_79; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_23 = _s1_meta_hit_way_T_21 & _s1_meta_hit_way_T_22; // @[Metadata.scala:50:45] wire [1:0] s1_meta_hit_way_lo_lo = {_s1_meta_hit_way_T_5, _s1_meta_hit_way_T_2}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_lo_hi = {_s1_meta_hit_way_T_11, _s1_meta_hit_way_T_8}; // @[package.scala:45:27] wire [3:0] s1_meta_hit_way_lo = {s1_meta_hit_way_lo_hi, s1_meta_hit_way_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_hi_lo = {_s1_meta_hit_way_T_17, _s1_meta_hit_way_T_14}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_hi_hi = {_s1_meta_hit_way_T_23, _s1_meta_hit_way_T_20}; // @[package.scala:45:27] wire [3:0] s1_meta_hit_way_hi = {s1_meta_hit_way_hi_hi, s1_meta_hit_way_hi_lo}; // @[package.scala:45:27] wire [7:0] s1_hit_way = {s1_meta_hit_way_hi, s1_meta_hit_way_lo}; // @[package.scala:45:27] wire _s1_meta_hit_state_T_1 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_2 = _s1_meta_hit_state_T & _s1_meta_hit_state_T_1; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_3 = _s1_meta_hit_state_T_2 ? s1_meta_uncorrected_0_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_5 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_6 = _s1_meta_hit_state_T_4 & _s1_meta_hit_state_T_5; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_7 = _s1_meta_hit_state_T_6 ? s1_meta_uncorrected_1_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_9 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_10 = _s1_meta_hit_state_T_8 & _s1_meta_hit_state_T_9; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_11 = _s1_meta_hit_state_T_10 ? s1_meta_uncorrected_2_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_13 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_14 = _s1_meta_hit_state_T_12 & _s1_meta_hit_state_T_13; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_15 = _s1_meta_hit_state_T_14 ? s1_meta_uncorrected_3_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_17 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_18 = _s1_meta_hit_state_T_16 & _s1_meta_hit_state_T_17; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_19 = _s1_meta_hit_state_T_18 ? s1_meta_uncorrected_4_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_21 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_22 = _s1_meta_hit_state_T_20 & _s1_meta_hit_state_T_21; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_23 = _s1_meta_hit_state_T_22 ? s1_meta_uncorrected_5_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_25 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_26 = _s1_meta_hit_state_T_24 & _s1_meta_hit_state_T_25; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_27 = _s1_meta_hit_state_T_26 ? s1_meta_uncorrected_6_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_29 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_30 = _s1_meta_hit_state_T_28 & _s1_meta_hit_state_T_29; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_31 = _s1_meta_hit_state_T_30 ? s1_meta_uncorrected_7_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire [1:0] _s1_meta_hit_state_T_32 = _s1_meta_hit_state_T_3 | _s1_meta_hit_state_T_7; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_33 = _s1_meta_hit_state_T_32 | _s1_meta_hit_state_T_11; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_34 = _s1_meta_hit_state_T_33 | _s1_meta_hit_state_T_15; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_35 = _s1_meta_hit_state_T_34 | _s1_meta_hit_state_T_19; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_36 = _s1_meta_hit_state_T_35 | _s1_meta_hit_state_T_23; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_37 = _s1_meta_hit_state_T_36 | _s1_meta_hit_state_T_27; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_38 = _s1_meta_hit_state_T_37 | _s1_meta_hit_state_T_31; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_WIRE = _s1_meta_hit_state_T_38; // @[DCache.scala:320:{19,32}] wire [1:0] _s1_meta_hit_state_T_39; // @[DCache.scala:320:32] wire [1:0] s1_hit_state_state; // @[DCache.scala:320:32] assign _s1_meta_hit_state_T_39 = _s1_meta_hit_state_WIRE; // @[DCache.scala:320:32] assign s1_hit_state_state = _s1_meta_hit_state_T_39; // @[DCache.scala:320:32] wire [7:0] _s1_data_way_T = inWriteback ? releaseWay : s1_hit_way; // @[package.scala:45:27, :81:59] wire [8:0] s1_data_way; // @[DCache.scala:323:32] wire [7:0] _tl_d_data_encoded_T = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_22 = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_1 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_23 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_2 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_24 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_3 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_25 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_4 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_26 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_5 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_27 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_6 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_28 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_7 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_29 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_8 = nodeOut_d_bits_data[71:64]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_30 = nodeOut_d_bits_data[71:64]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_9 = nodeOut_d_bits_data[79:72]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_31 = nodeOut_d_bits_data[79:72]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_10 = nodeOut_d_bits_data[87:80]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_32 = nodeOut_d_bits_data[87:80]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_11 = nodeOut_d_bits_data[95:88]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_33 = nodeOut_d_bits_data[95:88]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_12 = nodeOut_d_bits_data[103:96]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_34 = nodeOut_d_bits_data[103:96]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_13 = nodeOut_d_bits_data[111:104]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_35 = nodeOut_d_bits_data[111:104]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_14 = nodeOut_d_bits_data[119:112]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_36 = nodeOut_d_bits_data[119:112]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_15 = nodeOut_d_bits_data[127:120]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_37 = nodeOut_d_bits_data[127:120]; // @[package.scala:211:50] wire [15:0] tl_d_data_encoded_lo_lo_lo = {_tl_d_data_encoded_T_1, _tl_d_data_encoded_T}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_lo_hi = {_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_lo = {tl_d_data_encoded_lo_lo_hi, tl_d_data_encoded_lo_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_lo_hi_lo = {_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi_hi = {_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_hi = {tl_d_data_encoded_lo_hi_hi, tl_d_data_encoded_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_lo = {tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo_lo = {_tl_d_data_encoded_T_9, _tl_d_data_encoded_T_8}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_lo_hi = {_tl_d_data_encoded_T_11, _tl_d_data_encoded_T_10}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_lo = {tl_d_data_encoded_hi_lo_hi, tl_d_data_encoded_hi_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_hi_lo = {_tl_d_data_encoded_T_13, _tl_d_data_encoded_T_12}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi_hi = {_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_hi = {tl_d_data_encoded_hi_hi_hi, tl_d_data_encoded_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_hi = {tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo}; // @[package.scala:45:27] wire [127:0] _tl_d_data_encoded_T_16 = {tl_d_data_encoded_hi, tl_d_data_encoded_lo}; // @[package.scala:45:27] wire [127:0] _tl_d_data_encoded_T_38; // @[package.scala:45:27] assign dataArb_io_in_1_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] assign dataArb_io_in_2_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] assign dataArb_io_in_3_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] wire [127:0] s1_all_data_ways_8 = tl_d_data_encoded; // @[DCache.scala:324:31, :325:33] wire [127:0] s1_all_data_ways_0; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_1; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_2; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_3; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_4; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_5; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_6; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_7; // @[DCache.scala:325:33] wire _s1_mask_xwr_upper_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_upper_T_1 = _s1_mask_xwr_upper_T; // @[AMOALU.scala:20:{22,27}] wire _s1_mask_xwr_upper_T_2 = |s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire _s1_mask_xwr_upper_T_3 = _s1_mask_xwr_upper_T_2; // @[AMOALU.scala:20:{47,53}] wire s1_mask_xwr_upper = _s1_mask_xwr_upper_T_1 | _s1_mask_xwr_upper_T_3; // @[AMOALU.scala:20:{22,42,47}] wire s1_mask_xwr_lower = ~_s1_mask_xwr_lower_T; // @[AMOALU.scala:21:{22,27}] wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper, s1_mask_xwr_lower}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_4 = s1_req_addr[1]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_1 = s1_req_addr[1]; // @[DCache.scala:196:25] wire [1:0] _s1_mask_xwr_upper_T_5 = _s1_mask_xwr_upper_T_4 ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_6 = s1_mask_xwr_size[1]; // @[AMOALU.scala:11:18, :20:53] wire [1:0] _s1_mask_xwr_upper_T_7 = {2{_s1_mask_xwr_upper_T_6}}; // @[AMOALU.scala:20:{47,53}] wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 | _s1_mask_xwr_upper_T_7; // @[AMOALU.scala:20:{22,42,47}] wire [1:0] s1_mask_xwr_lower_1 = _s1_mask_xwr_lower_T_1 ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala:21:{22,27}, :22:16] wire [3:0] _s1_mask_xwr_T_1 = {s1_mask_xwr_upper_1, s1_mask_xwr_lower_1}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_8 = s1_req_addr[2]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_2 = s1_req_addr[2]; // @[DCache.scala:196:25] wire [3:0] _s1_mask_xwr_upper_T_9 = _s1_mask_xwr_upper_T_8 ? _s1_mask_xwr_T_1 : 4'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_10 = &s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire [3:0] _s1_mask_xwr_upper_T_11 = {4{_s1_mask_xwr_upper_T_10}}; // @[AMOALU.scala:20:{47,53}] wire [3:0] s1_mask_xwr_upper_2 = _s1_mask_xwr_upper_T_9 | _s1_mask_xwr_upper_T_11; // @[AMOALU.scala:20:{22,42,47}] wire [3:0] s1_mask_xwr_lower_2 = _s1_mask_xwr_lower_T_2 ? 4'h0 : _s1_mask_xwr_T_1; // @[AMOALU.scala:21:{22,27}, :22:16] wire [7:0] s1_mask_xwr = {s1_mask_xwr_upper_2, s1_mask_xwr_lower_2}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire [7:0] s1_mask = _s1_mask_T ? io_cpu_s1_data_mask_0 : s1_mask_xwr; // @[DCache.scala:101:7, :327:{20,32}] wire _s2_valid_T = ~s1_sfence; // @[DCache.scala:213:71, :331:45] wire _s2_valid_T_1 = s1_valid_masked & _s2_valid_T; // @[DCache.scala:186:34, :331:{42,45}] reg s2_valid; // @[DCache.scala:331:25] wire [1:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ae_ld_0, io_cpu_s2_xcpt_ae_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_2 = {io_cpu_s2_xcpt_pf_ld_0, io_cpu_s2_xcpt_pf_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_3 = {io_cpu_s2_xcpt_ma_ld_0, io_cpu_s2_xcpt_ma_st_0}; // @[DCache.scala:101:7, :332:54] wire [3:0] s2_valid_no_xcpt_lo = {2'h0, _s2_valid_no_xcpt_T}; // @[DCache.scala:332:54] wire [3:0] s2_valid_no_xcpt_hi = {_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2}; // @[DCache.scala:332:54] wire [7:0] _s2_valid_no_xcpt_T_4 = {s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo}; // @[DCache.scala:332:54] wire _s2_valid_no_xcpt_T_5 = |_s2_valid_no_xcpt_T_4; // @[DCache.scala:332:{54,61}] wire _s2_valid_no_xcpt_T_6 = ~_s2_valid_no_xcpt_T_5; // @[DCache.scala:332:{38,61}] wire s2_valid_no_xcpt = s2_valid & _s2_valid_no_xcpt_T_6; // @[DCache.scala:331:25, :332:{35,38}] reg s2_probe; // @[DCache.scala:333:25] wire _releaseInFlight_T = s1_probe | s2_probe; // @[DCache.scala:183:25, :333:25, :334:34] wire _releaseInFlight_T_1 = |release_state; // @[DCache.scala:228:30, :233:38, :334:63] wire releaseInFlight = _releaseInFlight_T | _releaseInFlight_T_1; // @[DCache.scala:334:{34,46,63}] wire _s2_not_nacked_in_s1_T = ~s1_nack; // @[DCache.scala:185:28, :187:41, :335:37] reg s2_not_nacked_in_s1; // @[DCache.scala:335:36] wire s2_valid_not_nacked_in_s1 = s2_valid & s2_not_nacked_in_s1; // @[DCache.scala:331:25, :335:36, :336:44] wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala:332:35, :335:36, :337:42] wire s2_valid_not_killed = s2_valid_masked; // @[DCache.scala:337:42, :338:45] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :397:71] wire _s2_dont_nack_misc_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :441:43] reg [39:0] s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _putpartial_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_4 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_63 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_122 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_181 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_240 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_299 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_358 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_417 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_476 = s2_req_addr; // @[DCache.scala:339:19] reg [7:0] s2_req_tag; // @[DCache.scala:339:19] assign io_cpu_resp_bits_tag_0 = s2_req_tag; // @[DCache.scala:101:7, :339:19] reg [4:0] s2_req_cmd; // @[DCache.scala:339:19] assign io_cpu_resp_bits_cmd_0 = s2_req_cmd; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_size; // @[DCache.scala:339:19] assign io_cpu_resp_bits_size_0 = s2_req_size; // @[DCache.scala:101:7, :339:19] wire [1:0] size = s2_req_size; // @[DCache.scala:339:19] reg s2_req_signed; // @[DCache.scala:339:19] assign io_cpu_resp_bits_signed_0 = s2_req_signed; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_dprv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dprv_0 = s2_req_dprv; // @[DCache.scala:101:7, :339:19] reg s2_req_dv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dv_0 = s2_req_dv; // @[DCache.scala:101:7, :339:19] reg s2_req_phys; // @[DCache.scala:339:19] reg s2_req_no_resp; // @[DCache.scala:339:19] reg s2_req_no_alloc; // @[DCache.scala:339:19] reg s2_req_no_xcpt; // @[DCache.scala:339:19] reg [63:0] s2_req_data; // @[DCache.scala:339:19] reg [7:0] s2_req_mask; // @[DCache.scala:339:19] assign io_cpu_resp_bits_mask_0 = s2_req_mask; // @[DCache.scala:101:7, :339:19] wire _GEN_80 = s2_req_cmd == 5'h5; // @[DCache.scala:339:19, :340:37] wire _s2_cmd_flush_all_T; // @[DCache.scala:340:37] assign _s2_cmd_flush_all_T = _GEN_80; // @[DCache.scala:340:37] wire _s2_cmd_flush_line_T; // @[DCache.scala:341:38] assign _s2_cmd_flush_line_T = _GEN_80; // @[DCache.scala:340:37, :341:38] wire _s2_cmd_flush_all_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68] wire _s2_cmd_flush_line_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68, :341:68] wire _s2_cmd_flush_all_T_2 = ~_s2_cmd_flush_all_T_1; // @[DCache.scala:340:{56,68}] wire s2_cmd_flush_all = _s2_cmd_flush_all_T & _s2_cmd_flush_all_T_2; // @[DCache.scala:340:{37,53,56}] wire s2_cmd_flush_line = _s2_cmd_flush_line_T & _s2_cmd_flush_line_T_1; // @[DCache.scala:341:{38,54,68}] reg s2_tlb_xcpt_miss; // @[DCache.scala:342:24] reg [31:0] s2_tlb_xcpt_paddr; // @[DCache.scala:342:24] reg [39:0] s2_tlb_xcpt_gpa; // @[DCache.scala:342:24] assign io_cpu_s2_gpa_0 = s2_tlb_xcpt_gpa; // @[DCache.scala:101:7, :342:24] reg s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24] reg s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24] reg s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24] reg [1:0] s2_tlb_xcpt_size; // @[DCache.scala:342:24] reg [4:0] s2_tlb_xcpt_cmd; // @[DCache.scala:342:24] reg s2_pma_miss; // @[DCache.scala:343:19] reg [31:0] s2_pma_paddr; // @[DCache.scala:343:19] reg [39:0] s2_pma_gpa; // @[DCache.scala:343:19] reg s2_pma_pf_ld; // @[DCache.scala:343:19] reg s2_pma_pf_st; // @[DCache.scala:343:19] reg s2_pma_pf_inst; // @[DCache.scala:343:19] reg s2_pma_ae_ld; // @[DCache.scala:343:19] reg s2_pma_ae_st; // @[DCache.scala:343:19] reg s2_pma_ae_inst; // @[DCache.scala:343:19] reg s2_pma_ma_ld; // @[DCache.scala:343:19] reg s2_pma_ma_st; // @[DCache.scala:343:19] reg s2_pma_cacheable; // @[DCache.scala:343:19] reg s2_pma_must_alloc; // @[DCache.scala:343:19] reg s2_pma_prefetchable; // @[DCache.scala:343:19] reg [1:0] s2_pma_size; // @[DCache.scala:343:19] reg [4:0] s2_pma_cmd; // @[DCache.scala:343:19] reg [39:0] s2_uncached_resp_addr; // @[DCache.scala:344:34] wire _T_30 = s1_valid_not_nacked | s1_flush_valid; // @[DCache.scala:187:38, :215:27, :345:29] wire _s2_vaddr_T; // @[DCache.scala:351:62] assign _s2_vaddr_T = _T_30; // @[DCache.scala:345:29, :351:62] wire _s1_meta_clk_en_T; // @[DCache.scala:357:44] assign _s1_meta_clk_en_T = _T_30; // @[DCache.scala:345:29, :357:44] wire _s2_hit_state_T; // @[DCache.scala:386:66] assign _s2_hit_state_T = _T_30; // @[DCache.scala:345:29, :386:66] wire _s2_victim_way_T; // @[DCache.scala:431:77] assign _s2_victim_way_T = _T_30; // @[DCache.scala:345:29, :431:77] reg [39:0] s2_vaddr_r; // @[DCache.scala:351:31] wire [27:0] _s2_vaddr_T_1 = s2_vaddr_r[39:12]; // @[DCache.scala:351:{31,81}] wire [11:0] _s2_vaddr_T_2 = s2_req_addr[11:0]; // @[DCache.scala:339:19, :351:103] wire [39:0] s2_vaddr = {_s2_vaddr_T_1, _s2_vaddr_T_2}; // @[DCache.scala:351:{21,81,103}] wire _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala:16:47] wire _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_81 = s2_req_cmd == 5'h6; // @[package.scala:16:47] wire _s2_read_T_2; // @[package.scala:16:47] assign _s2_read_T_2 = _GEN_81; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_81; // @[package.scala:16:47] wire _s2_lr_T; // @[DCache.scala:470:70] assign _s2_lr_T = _GEN_81; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:71] assign _metaArb_io_in_3_bits_data_c_cat_T_48 = _GEN_81; // @[package.scala:16:47] wire _GEN_82 = s2_req_cmd == 5'h7; // @[package.scala:16:47] wire _s2_read_T_3; // @[package.scala:16:47] assign _s2_read_T_3 = _GEN_82; // @[package.scala:16:47] wire _s2_write_T_3; // @[Consts.scala:90:66] assign _s2_write_T_3 = _GEN_82; // @[package.scala:16:47] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _GEN_82; // @[package.scala:16:47] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _GEN_82; // @[package.scala:16:47] wire _s2_sc_T; // @[DCache.scala:471:70] assign _s2_sc_T = _GEN_82; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_3 = _GEN_82; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_26 = _GEN_82; // @[package.scala:16:47] wire _io_cpu_store_pending_T_3; // @[Consts.scala:90:66] assign _io_cpu_store_pending_T_3 = _GEN_82; // @[package.scala:16:47] wire _s2_read_T_4 = _s2_read_T | _s2_read_T_1; // @[package.scala:16:47, :81:59] wire _s2_read_T_5 = _s2_read_T_4 | _s2_read_T_2; // @[package.scala:16:47, :81:59] wire _s2_read_T_6 = _s2_read_T_5 | _s2_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_83 = s2_req_cmd == 5'h4; // @[package.scala:16:47] wire _s2_read_T_7; // @[package.scala:16:47] assign _s2_read_T_7 = _GEN_83; // @[package.scala:16:47] wire _s2_write_T_5; // @[package.scala:16:47] assign _s2_write_T_5 = _GEN_83; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_83; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_83; // @[package.scala:16:47] wire _atomics_T; // @[DCache.scala:587:81] assign _atomics_T = _GEN_83; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_5; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_5 = _GEN_83; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_28; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_28 = _GEN_83; // @[package.scala:16:47] wire _io_cpu_store_pending_T_5; // @[package.scala:16:47] assign _io_cpu_store_pending_T_5 = _GEN_83; // @[package.scala:16:47] wire _GEN_84 = s2_req_cmd == 5'h9; // @[package.scala:16:47] wire _s2_read_T_8; // @[package.scala:16:47] assign _s2_read_T_8 = _GEN_84; // @[package.scala:16:47] wire _s2_write_T_6; // @[package.scala:16:47] assign _s2_write_T_6 = _GEN_84; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_84; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_84; // @[package.scala:16:47] wire _atomics_T_2; // @[DCache.scala:587:81] assign _atomics_T_2 = _GEN_84; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_6 = _GEN_84; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_29 = _GEN_84; // @[package.scala:16:47] wire _io_cpu_store_pending_T_6; // @[package.scala:16:47] assign _io_cpu_store_pending_T_6 = _GEN_84; // @[package.scala:16:47] wire _GEN_85 = s2_req_cmd == 5'hA; // @[package.scala:16:47] wire _s2_read_T_9; // @[package.scala:16:47] assign _s2_read_T_9 = _GEN_85; // @[package.scala:16:47] wire _s2_write_T_7; // @[package.scala:16:47] assign _s2_write_T_7 = _GEN_85; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_85; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_85; // @[package.scala:16:47] wire _atomics_T_4; // @[DCache.scala:587:81] assign _atomics_T_4 = _GEN_85; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_7 = _GEN_85; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_30 = _GEN_85; // @[package.scala:16:47] wire _io_cpu_store_pending_T_7; // @[package.scala:16:47] assign _io_cpu_store_pending_T_7 = _GEN_85; // @[package.scala:16:47] wire _GEN_86 = s2_req_cmd == 5'hB; // @[package.scala:16:47] wire _s2_read_T_10; // @[package.scala:16:47] assign _s2_read_T_10 = _GEN_86; // @[package.scala:16:47] wire _s2_write_T_8; // @[package.scala:16:47] assign _s2_write_T_8 = _GEN_86; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_86; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_86; // @[package.scala:16:47] wire _atomics_T_6; // @[DCache.scala:587:81] assign _atomics_T_6 = _GEN_86; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_8 = _GEN_86; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_31 = _GEN_86; // @[package.scala:16:47] wire _io_cpu_store_pending_T_8; // @[package.scala:16:47] assign _io_cpu_store_pending_T_8 = _GEN_86; // @[package.scala:16:47] wire _s2_read_T_11 = _s2_read_T_7 | _s2_read_T_8; // @[package.scala:16:47, :81:59] wire _s2_read_T_12 = _s2_read_T_11 | _s2_read_T_9; // @[package.scala:16:47, :81:59] wire _s2_read_T_13 = _s2_read_T_12 | _s2_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_87 = s2_req_cmd == 5'h8; // @[package.scala:16:47] wire _s2_read_T_14; // @[package.scala:16:47] assign _s2_read_T_14 = _GEN_87; // @[package.scala:16:47] wire _s2_write_T_12; // @[package.scala:16:47] assign _s2_write_T_12 = _GEN_87; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_87; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_87; // @[package.scala:16:47] wire _atomics_T_8; // @[DCache.scala:587:81] assign _atomics_T_8 = _GEN_87; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_12; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_12 = _GEN_87; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_35; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_35 = _GEN_87; // @[package.scala:16:47] wire _io_cpu_store_pending_T_12; // @[package.scala:16:47] assign _io_cpu_store_pending_T_12 = _GEN_87; // @[package.scala:16:47] wire _GEN_88 = s2_req_cmd == 5'hC; // @[package.scala:16:47] wire _s2_read_T_15; // @[package.scala:16:47] assign _s2_read_T_15 = _GEN_88; // @[package.scala:16:47] wire _s2_write_T_13; // @[package.scala:16:47] assign _s2_write_T_13 = _GEN_88; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_88; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_88; // @[package.scala:16:47] wire _atomics_T_10; // @[DCache.scala:587:81] assign _atomics_T_10 = _GEN_88; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_13 = _GEN_88; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_36 = _GEN_88; // @[package.scala:16:47] wire _io_cpu_store_pending_T_13; // @[package.scala:16:47] assign _io_cpu_store_pending_T_13 = _GEN_88; // @[package.scala:16:47] wire _GEN_89 = s2_req_cmd == 5'hD; // @[package.scala:16:47] wire _s2_read_T_16; // @[package.scala:16:47] assign _s2_read_T_16 = _GEN_89; // @[package.scala:16:47] wire _s2_write_T_14; // @[package.scala:16:47] assign _s2_write_T_14 = _GEN_89; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_89; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_89; // @[package.scala:16:47] wire _atomics_T_12; // @[DCache.scala:587:81] assign _atomics_T_12 = _GEN_89; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_14 = _GEN_89; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_37 = _GEN_89; // @[package.scala:16:47] wire _io_cpu_store_pending_T_14; // @[package.scala:16:47] assign _io_cpu_store_pending_T_14 = _GEN_89; // @[package.scala:16:47] wire _GEN_90 = s2_req_cmd == 5'hE; // @[package.scala:16:47] wire _s2_read_T_17; // @[package.scala:16:47] assign _s2_read_T_17 = _GEN_90; // @[package.scala:16:47] wire _s2_write_T_15; // @[package.scala:16:47] assign _s2_write_T_15 = _GEN_90; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_90; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_90; // @[package.scala:16:47] wire _atomics_T_14; // @[DCache.scala:587:81] assign _atomics_T_14 = _GEN_90; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_15 = _GEN_90; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_38 = _GEN_90; // @[package.scala:16:47] wire _io_cpu_store_pending_T_15; // @[package.scala:16:47] assign _io_cpu_store_pending_T_15 = _GEN_90; // @[package.scala:16:47] wire _GEN_91 = s2_req_cmd == 5'hF; // @[package.scala:16:47] wire _s2_read_T_18; // @[package.scala:16:47] assign _s2_read_T_18 = _GEN_91; // @[package.scala:16:47] wire _s2_write_T_16; // @[package.scala:16:47] assign _s2_write_T_16 = _GEN_91; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_91; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_91; // @[package.scala:16:47] wire _atomics_T_16; // @[DCache.scala:587:81] assign _atomics_T_16 = _GEN_91; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_16 = _GEN_91; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_39 = _GEN_91; // @[package.scala:16:47] wire _io_cpu_store_pending_T_16; // @[package.scala:16:47] assign _io_cpu_store_pending_T_16 = _GEN_91; // @[package.scala:16:47] wire _s2_read_T_19 = _s2_read_T_14 | _s2_read_T_15; // @[package.scala:16:47, :81:59] wire _s2_read_T_20 = _s2_read_T_19 | _s2_read_T_16; // @[package.scala:16:47, :81:59] wire _s2_read_T_21 = _s2_read_T_20 | _s2_read_T_17; // @[package.scala:16:47, :81:59] wire _s2_read_T_22 = _s2_read_T_21 | _s2_read_T_18; // @[package.scala:16:47, :81:59] wire _s2_read_T_23 = _s2_read_T_13 | _s2_read_T_22; // @[package.scala:81:59] assign s2_read = _s2_read_T_6 | _s2_read_T_23; // @[package.scala:81:59] assign io_cpu_resp_bits_has_data_0 = s2_read; // @[DCache.scala:101:7] wire _GEN_92 = s2_req_cmd == 5'h1; // @[DCache.scala:339:19] wire _s2_write_T; // @[Consts.scala:90:32] assign _s2_write_T = _GEN_92; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_92; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_92; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T = _GEN_92; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T_23; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T_23 = _GEN_92; // @[Consts.scala:90:32] wire _io_cpu_store_pending_T; // @[Consts.scala:90:32] assign _io_cpu_store_pending_T = _GEN_92; // @[Consts.scala:90:32] wire _GEN_93 = s2_req_cmd == 5'h11; // @[DCache.scala:339:19] wire _s2_write_T_1; // @[Consts.scala:90:49] assign _s2_write_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_93; // @[Consts.scala:90:49] wire _tl_out_a_bits_T_4; // @[DCache.scala:610:20] assign _tl_out_a_bits_T_4 = _GEN_93; // @[DCache.scala:610:20] wire _uncachedReqs_0_cmd_T; // @[DCache.scala:637:49] assign _uncachedReqs_0_cmd_T = _GEN_93; // @[DCache.scala:637:49] wire _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_24 = _GEN_93; // @[Consts.scala:90:49] wire _io_cpu_store_pending_T_1; // @[Consts.scala:90:49] assign _io_cpu_store_pending_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _s2_write_T_2 = _s2_write_T | _s2_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s2_write_T_4 = _s2_write_T_2 | _s2_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s2_write_T_9 = _s2_write_T_5 | _s2_write_T_6; // @[package.scala:16:47, :81:59] wire _s2_write_T_10 = _s2_write_T_9 | _s2_write_T_7; // @[package.scala:16:47, :81:59] wire _s2_write_T_11 = _s2_write_T_10 | _s2_write_T_8; // @[package.scala:16:47, :81:59] wire _s2_write_T_17 = _s2_write_T_12 | _s2_write_T_13; // @[package.scala:16:47, :81:59] wire _s2_write_T_18 = _s2_write_T_17 | _s2_write_T_14; // @[package.scala:16:47, :81:59] wire _s2_write_T_19 = _s2_write_T_18 | _s2_write_T_15; // @[package.scala:16:47, :81:59] wire _s2_write_T_20 = _s2_write_T_19 | _s2_write_T_16; // @[package.scala:16:47, :81:59] wire _s2_write_T_21 = _s2_write_T_11 | _s2_write_T_20; // @[package.scala:81:59] wire s2_write = _s2_write_T_4 | _s2_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s2_readwrite = s2_read | s2_write; // @[DCache.scala:354:30] reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43] wire s2_flush_valid = s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43, :363:51] wire s1_meta_clk_en = _s1_meta_clk_en_T | s1_probe; // @[DCache.scala:183:25, :357:{44,62}] reg [21:0] s2_meta_corrected_r; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE = s2_meta_corrected_r; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_1; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_0_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_0_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T = _s2_meta_corrected_WIRE[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_0_tag = _s2_meta_corrected_T; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_1 = _s2_meta_corrected_WIRE[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_0_coh_state = _s2_meta_corrected_T_1; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_1; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_1 = s2_meta_corrected_r_1; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_3; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_2; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_1_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_1_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_2 = _s2_meta_corrected_WIRE_1[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_1_tag = _s2_meta_corrected_T_2; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_3 = _s2_meta_corrected_WIRE_1[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_1_coh_state = _s2_meta_corrected_T_3; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_2; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_2 = s2_meta_corrected_r_2; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_5; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_4; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_2_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_2_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_4 = _s2_meta_corrected_WIRE_2[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_2_tag = _s2_meta_corrected_T_4; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_5 = _s2_meta_corrected_WIRE_2[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_2_coh_state = _s2_meta_corrected_T_5; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_3; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_3 = s2_meta_corrected_r_3; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_7; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_6; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_3_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_3_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_6 = _s2_meta_corrected_WIRE_3[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_3_tag = _s2_meta_corrected_T_6; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_7 = _s2_meta_corrected_WIRE_3[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_3_coh_state = _s2_meta_corrected_T_7; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_4; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_4 = s2_meta_corrected_r_4; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_9; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_8; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_4_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_4_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_8 = _s2_meta_corrected_WIRE_4[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_4_tag = _s2_meta_corrected_T_8; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_9 = _s2_meta_corrected_WIRE_4[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_4_coh_state = _s2_meta_corrected_T_9; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_5; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_5 = s2_meta_corrected_r_5; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_11; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_10; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_5_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_5_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_10 = _s2_meta_corrected_WIRE_5[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_5_tag = _s2_meta_corrected_T_10; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_11 = _s2_meta_corrected_WIRE_5[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_5_coh_state = _s2_meta_corrected_T_11; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_6; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_6 = s2_meta_corrected_r_6; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_13; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_12; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_6_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_6_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_12 = _s2_meta_corrected_WIRE_6[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_6_tag = _s2_meta_corrected_T_12; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_13 = _s2_meta_corrected_WIRE_6[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_6_coh_state = _s2_meta_corrected_T_13; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_7; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_7 = s2_meta_corrected_r_7; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_15; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_14; // @[DCache.scala:361:99] wire [1:0] _s2_first_meta_corrected_T_8_coh_state = s2_meta_corrected_7_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_8_tag = s2_meta_corrected_7_tag; // @[Mux.scala:50:70] assign _s2_meta_corrected_T_14 = _s2_meta_corrected_WIRE_7[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_7_tag = _s2_meta_corrected_T_14; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_15 = _s2_meta_corrected_WIRE_7[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_7_coh_state = _s2_meta_corrected_T_15; // @[DCache.scala:361:99] wire _s2_data_en_T = s1_valid | inWriteback; // @[package.scala:81:59] wire s2_data_en = _s2_data_en_T | io_cpu_replay_next_0; // @[DCache.scala:101:7, :366:{23,38}] wire [1:0] _s2_data_word_en_T_1 = s1_did_read ? s1_read_mask : 2'h0; // @[DCache.scala:259:30, :260:31, :367:63] wire [1:0] s2_data_word_en = inWriteback ? 2'h3 : _s2_data_word_en_T_1; // @[package.scala:81:59] wire [63:0] s2_data_s1_way_words_0_0 = s1_all_data_ways_0[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_0_1 = s1_all_data_ways_0[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_1_0 = s1_all_data_ways_1[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_1_1 = s1_all_data_ways_1[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_2_0 = s1_all_data_ways_2[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_2_1 = s1_all_data_ways_2[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_3_0 = s1_all_data_ways_3[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_3_1 = s1_all_data_ways_3[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_4_0 = s1_all_data_ways_4[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_4_1 = s1_all_data_ways_4[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_5_0 = s1_all_data_ways_5[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_5_1 = s1_all_data_ways_5[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_6_0 = s1_all_data_ways_6[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_6_1 = s1_all_data_ways_6[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_7_0 = s1_all_data_ways_7[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_7_1 = s1_all_data_ways_7[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_8_0 = s1_all_data_ways_8[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_8_1 = s1_all_data_ways_8[127:64]; // @[package.scala:211:50] wire _s2_data_s1_word_en_T = ~io_cpu_replay_next_0; // @[DCache.scala:101:7, :377:28] wire _s2_data_s1_word_en_T_1 = uncachedResp_addr[3]; // @[package.scala:163:13] wire s1_uncached_data_word_word_idx = uncachedResp_addr[3]; // @[package.scala:163:13] wire s2_data_s1_word_en_shiftAmount = _s2_data_s1_word_en_T_1; // @[OneHot.scala:64:49] wire [1:0] _s2_data_s1_word_en_T_2 = 2'h1 << s2_data_s1_word_en_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _s2_data_s1_word_en_T_3 = _s2_data_s1_word_en_T_2; // @[OneHot.scala:65:{12,27}] wire [1:0] s2_data_s1_word_en = _s2_data_s1_word_en_T ? s2_data_word_en : _s2_data_s1_word_en_T_3; // @[OneHot.scala:65:27] wire _s2_data_T = s2_data_s1_word_en[0]; // @[DCache.scala:377:27, :379:39] wire [8:0] _s2_data_T_1 = _s2_data_T ? s1_data_way : 9'h0; // @[DCache.scala:323:32, :379:{28,39}] wire _s2_data_T_2 = _s2_data_T_1[0]; // @[Mux.scala:32:36] wire _s2_data_T_3 = _s2_data_T_1[1]; // @[Mux.scala:32:36] wire _s2_data_T_4 = _s2_data_T_1[2]; // @[Mux.scala:32:36] wire _s2_data_T_5 = _s2_data_T_1[3]; // @[Mux.scala:32:36] wire _s2_data_T_6 = _s2_data_T_1[4]; // @[Mux.scala:32:36] wire _s2_data_T_7 = _s2_data_T_1[5]; // @[Mux.scala:32:36] wire _s2_data_T_8 = _s2_data_T_1[6]; // @[Mux.scala:32:36] wire _s2_data_T_9 = _s2_data_T_1[7]; // @[Mux.scala:32:36] wire _s2_data_T_10 = _s2_data_T_1[8]; // @[Mux.scala:32:36] wire [63:0] _s2_data_T_11 = _s2_data_T_2 ? s2_data_s1_way_words_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_12 = _s2_data_T_3 ? s2_data_s1_way_words_1_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_13 = _s2_data_T_4 ? s2_data_s1_way_words_2_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_14 = _s2_data_T_5 ? s2_data_s1_way_words_3_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_15 = _s2_data_T_6 ? s2_data_s1_way_words_4_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_16 = _s2_data_T_7 ? s2_data_s1_way_words_5_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_17 = _s2_data_T_8 ? s2_data_s1_way_words_6_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_18 = _s2_data_T_9 ? s2_data_s1_way_words_7_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_19 = _s2_data_T_10 ? s2_data_s1_way_words_8_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_20 = _s2_data_T_11 | _s2_data_T_12; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_21 = _s2_data_T_20 | _s2_data_T_13; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_22 = _s2_data_T_21 | _s2_data_T_14; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_23 = _s2_data_T_22 | _s2_data_T_15; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_24 = _s2_data_T_23 | _s2_data_T_16; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_25 = _s2_data_T_24 | _s2_data_T_17; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_26 = _s2_data_T_25 | _s2_data_T_18; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_27 = _s2_data_T_26 | _s2_data_T_19; // @[Mux.scala:30:73] wire [63:0] _s2_data_WIRE = _s2_data_T_27; // @[Mux.scala:30:73] reg [63:0] s2_data_r; // @[DCache.scala:379:18] wire _s2_data_T_28 = s2_data_s1_word_en[1]; // @[DCache.scala:377:27, :379:39] wire [8:0] _s2_data_T_29 = _s2_data_T_28 ? s1_data_way : 9'h0; // @[DCache.scala:323:32, :379:{28,39}] wire _s2_data_T_30 = _s2_data_T_29[0]; // @[Mux.scala:32:36] wire _s2_data_T_31 = _s2_data_T_29[1]; // @[Mux.scala:32:36] wire _s2_data_T_32 = _s2_data_T_29[2]; // @[Mux.scala:32:36] wire _s2_data_T_33 = _s2_data_T_29[3]; // @[Mux.scala:32:36] wire _s2_data_T_34 = _s2_data_T_29[4]; // @[Mux.scala:32:36] wire _s2_data_T_35 = _s2_data_T_29[5]; // @[Mux.scala:32:36] wire _s2_data_T_36 = _s2_data_T_29[6]; // @[Mux.scala:32:36] wire _s2_data_T_37 = _s2_data_T_29[7]; // @[Mux.scala:32:36] wire _s2_data_T_38 = _s2_data_T_29[8]; // @[Mux.scala:32:36] wire [63:0] _s2_data_T_39 = _s2_data_T_30 ? s2_data_s1_way_words_0_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_40 = _s2_data_T_31 ? s2_data_s1_way_words_1_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_41 = _s2_data_T_32 ? s2_data_s1_way_words_2_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_42 = _s2_data_T_33 ? s2_data_s1_way_words_3_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_43 = _s2_data_T_34 ? s2_data_s1_way_words_4_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_44 = _s2_data_T_35 ? s2_data_s1_way_words_5_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_45 = _s2_data_T_36 ? s2_data_s1_way_words_6_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_46 = _s2_data_T_37 ? s2_data_s1_way_words_7_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_47 = _s2_data_T_38 ? s2_data_s1_way_words_8_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_48 = _s2_data_T_39 | _s2_data_T_40; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_49 = _s2_data_T_48 | _s2_data_T_41; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_50 = _s2_data_T_49 | _s2_data_T_42; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_51 = _s2_data_T_50 | _s2_data_T_43; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_52 = _s2_data_T_51 | _s2_data_T_44; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_53 = _s2_data_T_52 | _s2_data_T_45; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_54 = _s2_data_T_53 | _s2_data_T_46; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_55 = _s2_data_T_54 | _s2_data_T_47; // @[Mux.scala:30:73] wire [63:0] _s2_data_WIRE_1 = _s2_data_T_55; // @[Mux.scala:30:73] reg [63:0] s2_data_r_1; // @[DCache.scala:379:18] wire [127:0] s2_data = {s2_data_r_1, s2_data_r}; // @[package.scala:45:27] reg [7:0] s2_probe_way; // @[DCache.scala:383:31] reg [1:0] s2_probe_state_state; // @[DCache.scala:384:33] reg [7:0] s2_hit_way; // @[DCache.scala:385:29] reg [1:0] s2_hit_state_state; // @[DCache.scala:386:31] wire s2_hit_valid = |s2_hit_state_state; // @[Metadata.scala:50:45] wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_94 = s2_req_cmd == 5'h3; // @[DCache.scala:339:19] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_94; // @[Consts.scala:91:54] wire _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:91:54] assign _metaArb_io_in_3_bits_data_c_cat_T_46 = _GEN_94; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T = {r_c, s2_hit_state_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_25 = _r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_27 = {1'h0, _r_T_25}; // @[Misc.scala:35:36, :49:20] wire _r_T_28 = _r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_30 = _r_T_28 ? 2'h2 : _r_T_27; // @[Misc.scala:35:36, :49:20] wire _r_T_31 = _r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_33 = _r_T_31 ? 2'h1 : _r_T_30; // @[Misc.scala:35:36, :49:20] wire _r_T_34 = _r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_36 = _r_T_34 ? 2'h2 : _r_T_33; // @[Misc.scala:35:36, :49:20] wire _r_T_37 = _r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_39 = _r_T_37 ? 2'h0 : _r_T_36; // @[Misc.scala:35:36, :49:20] wire _r_T_40 = _r_T == 4'hE; // @[Misc.scala:49:20] wire _r_T_41 = _r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_42 = _r_T_40 ? 2'h3 : _r_T_39; // @[Misc.scala:35:36, :49:20] wire _r_T_43 = &_r_T; // @[Misc.scala:49:20] wire _r_T_44 = _r_T_43 | _r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_45 = _r_T_43 ? 2'h3 : _r_T_42; // @[Misc.scala:35:36, :49:20] wire _r_T_46 = _r_T == 4'h6; // @[Misc.scala:49:20] wire _r_T_47 = _r_T_46 | _r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_48 = _r_T_46 ? 2'h2 : _r_T_45; // @[Misc.scala:35:36, :49:20] wire _r_T_49 = _r_T == 4'h7; // @[Misc.scala:49:20] wire _r_T_50 = _r_T_49 | _r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_51 = _r_T_49 ? 2'h3 : _r_T_48; // @[Misc.scala:35:36, :49:20] wire _r_T_52 = _r_T == 4'h1; // @[Misc.scala:49:20] wire _r_T_53 = _r_T_52 | _r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_54 = _r_T_52 ? 2'h1 : _r_T_51; // @[Misc.scala:35:36, :49:20] wire _r_T_55 = _r_T == 4'h2; // @[Misc.scala:49:20] wire _r_T_56 = _r_T_55 | _r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_57 = _r_T_55 ? 2'h2 : _r_T_54; // @[Misc.scala:35:36, :49:20] wire _r_T_58 = _r_T == 4'h3; // @[Misc.scala:49:20] wire s2_hit = _r_T_58 | _r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] s2_grow_param = _r_T_58 ? 2'h3 : _r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] s2_new_hit_state_state = s2_grow_param; // @[Misc.scala:35:36] wire [1:0] metaArb_io_in_2_bits_data_meta_coh_state = s2_new_hit_state_state; // @[Metadata.scala:160:20] wire s2_word_idx = s2_req_addr[3]; // @[package.scala:163:13] wire _a_mask_T = s2_req_addr[3]; // @[package.scala:163:13] wire get_a_mask_sub_sub_sub_bit = s2_req_addr[3]; // @[package.scala:163:13] wire put_a_mask_sub_sub_sub_bit = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_1 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_2 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_3 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_4 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_5 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_6 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_7 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_8 = s2_req_addr[3]; // @[package.scala:163:13] wire [15:0] s2_data_corrected_lo_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_lo_lo = {s2_data_corrected_lo_lo_hi, s2_data_corrected_lo_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_lo_hi = {s2_data_corrected_lo_hi_hi, s2_data_corrected_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_corrected_lo = {s2_data_corrected_lo_hi, s2_data_corrected_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_lo_lo = s2_data[79:64]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_lo_lo = s2_data[79:64]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_lo_hi = s2_data[95:80]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_lo_hi = s2_data[95:80]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_hi_lo = {s2_data_corrected_hi_lo_hi, s2_data_corrected_hi_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_hi_lo = s2_data[111:96]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_hi_lo = s2_data[111:96]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_hi_hi = s2_data[127:112]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_hi_hi = s2_data[127:112]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_hi_hi = {s2_data_corrected_hi_hi_hi, s2_data_corrected_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_corrected_hi = {s2_data_corrected_hi_hi, s2_data_corrected_hi_lo}; // @[package.scala:45:27] assign s2_data_corrected = {s2_data_corrected_hi, s2_data_corrected_lo}; // @[package.scala:45:27] assign nodeOut_c_bits_data = s2_data_corrected; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_lo_lo = {s2_data_uncorrected_lo_lo_hi, s2_data_uncorrected_lo_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_lo_hi = {s2_data_uncorrected_lo_hi_hi, s2_data_uncorrected_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_uncorrected_lo = {s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_hi_lo = {s2_data_uncorrected_hi_lo_hi, s2_data_uncorrected_hi_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_hi_hi = {s2_data_uncorrected_hi_hi_hi, s2_data_uncorrected_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_uncorrected_hi = {s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo}; // @[package.scala:45:27] wire [127:0] s2_data_uncorrected = {s2_data_uncorrected_hi, s2_data_uncorrected_lo}; // @[package.scala:45:27] wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 & s2_hit; // @[Misc.scala:35:9] wire _s2_valid_hit_pre_data_ecc_and_waw_T = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala:354:30, :397:89, :418:89] wire s2_valid_hit_pre_data_ecc_and_waw = _s2_valid_hit_pre_data_ecc_and_waw_T; // @[DCache.scala:418:{89,105}] wire s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala:418:105, :420:69] wire s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_cmd_flush_line; // @[DCache.scala:341:54, :397:89, :419:75] wire _s2_victim_tag_T = s2_valid_flush_line; // @[DCache.scala:419:75, :433:47] wire s2_valid_hit = s2_valid_hit_pre_data_ecc; // @[DCache.scala:420:69, :422:48] wire _s2_valid_miss_T = s2_valid_masked & s2_readwrite; // @[DCache.scala:337:42, :354:30, :423:39] wire _s2_valid_miss_T_2 = _s2_valid_miss_T; // @[DCache.scala:423:{39,55}] wire _s2_valid_miss_T_3 = ~s2_hit; // @[Misc.scala:35:9] wire s2_valid_miss = _s2_valid_miss_T_2 & _s2_valid_miss_T_3; // @[DCache.scala:423:{55,73,76}] wire _s2_uncached_T = ~s2_pma_cacheable; // @[DCache.scala:343:19, :424:21] wire _s2_uncached_T_1 = ~s2_pma_must_alloc; // @[DCache.scala:343:19, :424:61] wire _s2_uncached_T_2 = s2_req_no_alloc & _s2_uncached_T_1; // @[DCache.scala:339:19, :424:{58,61}] wire _s2_uncached_T_3 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _s2_uncached_T_4 = _s2_uncached_T_2 & _s2_uncached_T_3; // @[DCache.scala:424:{58,80,83}] wire s2_uncached = _s2_uncached_T | _s2_uncached_T_4; // @[DCache.scala:424:{21,39,80}] wire _s2_valid_cached_miss_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47] wire _s2_valid_cached_miss_T_1 = s2_valid_miss & _s2_valid_cached_miss_T; // @[DCache.scala:423:73, :425:{44,47}] wire _s2_valid_cached_miss_T_3 = ~_s2_valid_cached_miss_T_2; // @[DCache.scala:425:{63,88}] wire s2_valid_cached_miss = _s2_valid_cached_miss_T_1 & _s2_valid_cached_miss_T_3; // @[DCache.scala:425:{44,60,63}] wire _s2_want_victimize_T = s2_valid_cached_miss | s2_valid_flush_line; // @[DCache.scala:419:75, :425:60, :427:77] wire _s2_want_victimize_T_1 = _s2_want_victimize_T; // @[DCache.scala:427:{77,100}] wire _s2_want_victimize_T_2 = _s2_want_victimize_T_1 | s2_flush_valid; // @[DCache.scala:363:51, :427:{100,123}] wire s2_want_victimize = _s2_want_victimize_T_2; // @[DCache.scala:427:{52,123}] wire s2_victimize = s2_want_victimize; // @[DCache.scala:427:52, :429:40] wire _s2_cannot_victimize_T = ~s2_flush_valid; // @[DCache.scala:363:51, :428:29] wire _s2_valid_uncached_pending_T = s2_valid_miss & s2_uncached; // @[DCache.scala:423:73, :424:39, :430:49] wire _s2_valid_uncached_pending_T_2 = ~_s2_valid_uncached_pending_T_1; // @[DCache.scala:430:{67,92}] wire s2_valid_uncached_pending = _s2_valid_uncached_pending_T & _s2_valid_uncached_pending_T_2; // @[DCache.scala:430:{49,64,67}] reg [2:0] s2_victim_way_r; // @[DCache.scala:431:41] wire [7:0] s2_victim_way = 8'h1 << s2_victim_way_r; // @[OneHot.scala:58:35] assign s2_victim_or_hit_way = s2_hit_valid ? s2_hit_way : s2_victim_way; // @[OneHot.scala:58:35] assign metaArb_io_in_2_bits_way_en = s2_victim_or_hit_way; // @[DCache.scala:135:28, :432:33] wire [19:0] _s2_victim_tag_T_1 = s2_req_addr[31:12]; // @[DCache.scala:339:19, :433:82] wire _s2_victim_tag_T_2 = s2_victim_way[0]; // @[OneHot.scala:58:35] wire _s2_victim_state_T = s2_victim_way[0]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_3 = s2_victim_way[1]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_1 = s2_victim_way[1]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_4 = s2_victim_way[2]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_2 = s2_victim_way[2]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_5 = s2_victim_way[3]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_3 = s2_victim_way[3]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_6 = s2_victim_way[4]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_4 = s2_victim_way[4]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_7 = s2_victim_way[5]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_5 = s2_victim_way[5]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_8 = s2_victim_way[6]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_6 = s2_victim_way[6]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_9 = s2_victim_way[7]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_7 = s2_victim_way[7]; // @[OneHot.scala:58:35] wire [1:0] _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_10 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_11 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_12 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_13 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_14 = _s2_victim_tag_T_6 ? s2_meta_corrected_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_15 = _s2_victim_tag_T_7 ? s2_meta_corrected_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_16 = _s2_victim_tag_T_8 ? s2_meta_corrected_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_17 = _s2_victim_tag_T_9 ? s2_meta_corrected_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_18 = _s2_victim_tag_T_10 | _s2_victim_tag_T_11; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_19 = _s2_victim_tag_T_18 | _s2_victim_tag_T_12; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_20 = _s2_victim_tag_T_19 | _s2_victim_tag_T_13; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_21 = _s2_victim_tag_T_20 | _s2_victim_tag_T_14; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_22 = _s2_victim_tag_T_21 | _s2_victim_tag_T_15; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_23 = _s2_victim_tag_T_22 | _s2_victim_tag_T_16; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_24 = _s2_victim_tag_T_23 | _s2_victim_tag_T_17; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_1 = _s2_victim_tag_T_24; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_WIRE_tag = _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_WIRE_coh_state = _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_25 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_26 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_27 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_28 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_29 = _s2_victim_tag_T_6 ? s2_meta_corrected_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_30 = _s2_victim_tag_T_7 ? s2_meta_corrected_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_31 = _s2_victim_tag_T_8 ? s2_meta_corrected_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_32 = _s2_victim_tag_T_9 ? s2_meta_corrected_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_33 = _s2_victim_tag_T_25 | _s2_victim_tag_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_34 = _s2_victim_tag_T_33 | _s2_victim_tag_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_35 = _s2_victim_tag_T_34 | _s2_victim_tag_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_36 = _s2_victim_tag_T_35 | _s2_victim_tag_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_37 = _s2_victim_tag_T_36 | _s2_victim_tag_T_30; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_38 = _s2_victim_tag_T_37 | _s2_victim_tag_T_31; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_39 = _s2_victim_tag_T_38 | _s2_victim_tag_T_32; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_3 = _s2_victim_tag_T_39; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_2_state = _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73] wire [19:0] s2_victim_tag = _s2_victim_tag_T ? _s2_victim_tag_T_1 : _s2_victim_tag_WIRE_tag; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_WIRE_1; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_8 = _s2_victim_state_T ? s2_meta_corrected_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_9 = _s2_victim_state_T_1 ? s2_meta_corrected_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_10 = _s2_victim_state_T_2 ? s2_meta_corrected_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_11 = _s2_victim_state_T_3 ? s2_meta_corrected_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_12 = _s2_victim_state_T_4 ? s2_meta_corrected_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_13 = _s2_victim_state_T_5 ? s2_meta_corrected_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_14 = _s2_victim_state_T_6 ? s2_meta_corrected_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_15 = _s2_victim_state_T_7 ? s2_meta_corrected_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_16 = _s2_victim_state_T_8 | _s2_victim_state_T_9; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_17 = _s2_victim_state_T_16 | _s2_victim_state_T_10; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_18 = _s2_victim_state_T_17 | _s2_victim_state_T_11; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_19 = _s2_victim_state_T_18 | _s2_victim_state_T_12; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_20 = _s2_victim_state_T_19 | _s2_victim_state_T_13; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_21 = _s2_victim_state_T_20 | _s2_victim_state_T_14; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_22 = _s2_victim_state_T_21 | _s2_victim_state_T_15; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_1 = _s2_victim_state_T_22; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_WIRE_tag = _s2_victim_state_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_coh_state = _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_23 = _s2_victim_state_T ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_24 = _s2_victim_state_T_1 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_25 = _s2_victim_state_T_2 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_26 = _s2_victim_state_T_3 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_27 = _s2_victim_state_T_4 ? s2_meta_corrected_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_28 = _s2_victim_state_T_5 ? s2_meta_corrected_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_29 = _s2_victim_state_T_6 ? s2_meta_corrected_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_30 = _s2_victim_state_T_7 ? s2_meta_corrected_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_31 = _s2_victim_state_T_23 | _s2_victim_state_T_24; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_32 = _s2_victim_state_T_31 | _s2_victim_state_T_25; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_33 = _s2_victim_state_T_32 | _s2_victim_state_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_34 = _s2_victim_state_T_33 | _s2_victim_state_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_35 = _s2_victim_state_T_34 | _s2_victim_state_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_36 = _s2_victim_state_T_35 | _s2_victim_state_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_37 = _s2_victim_state_T_36 | _s2_victim_state_T_30; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_3 = _s2_victim_state_T_37; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_2_state = _s2_victim_state_WIRE_3; // @[Mux.scala:30:73] wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : _s2_victim_state_WIRE_coh_state; // @[Mux.scala:30:73] wire [3:0] _r_T_59 = {probe_bits_param, s2_probe_state_state}; // @[Metadata.scala:120:19] wire _r_T_72 = _r_T_59 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_74 = _r_T_72 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_76 = _r_T_59 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_78 = _r_T_76 ? 3'h2 : _r_T_74; // @[Misc.scala:38:36, :56:20] wire _r_T_80 = _r_T_59 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_82 = _r_T_80 ? 3'h1 : _r_T_78; // @[Misc.scala:38:36, :56:20] wire _r_T_84 = _r_T_59 == 4'hB; // @[Misc.scala:56:20] wire _r_T_85 = _r_T_84; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_86 = _r_T_84 ? 3'h1 : _r_T_82; // @[Misc.scala:38:36, :56:20] wire _r_T_88 = _r_T_59 == 4'h4; // @[Misc.scala:56:20] wire _r_T_89 = ~_r_T_88 & _r_T_85; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_90 = _r_T_88 ? 3'h5 : _r_T_86; // @[Misc.scala:38:36, :56:20] wire _r_T_92 = _r_T_59 == 4'h5; // @[Misc.scala:56:20] wire _r_T_93 = ~_r_T_92 & _r_T_89; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_94 = _r_T_92 ? 3'h4 : _r_T_90; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_95 = {1'h0, _r_T_92}; // @[Misc.scala:38:63, :56:20] wire _r_T_96 = _r_T_59 == 4'h6; // @[Misc.scala:56:20] wire _r_T_97 = ~_r_T_96 & _r_T_93; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_98 = _r_T_96 ? 3'h0 : _r_T_94; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_99 = _r_T_96 ? 2'h1 : _r_T_95; // @[Misc.scala:38:63, :56:20] wire _r_T_100 = _r_T_59 == 4'h7; // @[Misc.scala:56:20] wire _r_T_101 = _r_T_100 | _r_T_97; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_102 = _r_T_100 ? 3'h0 : _r_T_98; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_103 = _r_T_100 ? 2'h1 : _r_T_99; // @[Misc.scala:38:63, :56:20] wire _r_T_104 = _r_T_59 == 4'h0; // @[Misc.scala:56:20] wire _r_T_105 = ~_r_T_104 & _r_T_101; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_106 = _r_T_104 ? 3'h5 : _r_T_102; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_107 = _r_T_104 ? 2'h0 : _r_T_103; // @[Misc.scala:38:63, :56:20] wire _r_T_108 = _r_T_59 == 4'h1; // @[Misc.scala:56:20] wire _r_T_109 = ~_r_T_108 & _r_T_105; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_110 = _r_T_108 ? 3'h4 : _r_T_106; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_111 = _r_T_108 ? 2'h1 : _r_T_107; // @[Misc.scala:38:63, :56:20] wire _r_T_112 = _r_T_59 == 4'h2; // @[Misc.scala:56:20] wire _r_T_113 = ~_r_T_112 & _r_T_109; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_114 = _r_T_112 ? 3'h3 : _r_T_110; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_115 = _r_T_112 ? 2'h2 : _r_T_111; // @[Misc.scala:38:63, :56:20] wire _r_T_116 = _r_T_59 == 4'h3; // @[Misc.scala:56:20] wire s2_prb_ack_data = _r_T_116 | _r_T_113; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_report_param = _r_T_116 ? 3'h3 : _r_T_114; // @[Misc.scala:38:36, :56:20] wire [2:0] cleanReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [2:0] dirtyReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_116 ? 2'h2 : _r_T_115; // @[Misc.scala:38:63, :56:20] wire [1:0] probeNewCoh_state = r_3; // @[Misc.scala:38:63] wire [3:0] _r_T_123 = {2'h2, s2_victim_state_state}; // @[Metadata.scala:120:19] wire _r_T_136 = _r_T_123 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_138 = _r_T_136 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_140 = _r_T_123 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_142 = _r_T_140 ? 3'h2 : _r_T_138; // @[Misc.scala:38:36, :56:20] wire _r_T_144 = _r_T_123 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_146 = _r_T_144 ? 3'h1 : _r_T_142; // @[Misc.scala:38:36, :56:20] wire _r_T_148 = _r_T_123 == 4'hB; // @[Misc.scala:56:20] wire _r_T_149 = _r_T_148; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_150 = _r_T_148 ? 3'h1 : _r_T_146; // @[Misc.scala:38:36, :56:20] wire _r_T_152 = _r_T_123 == 4'h4; // @[Misc.scala:56:20] wire _r_T_153 = ~_r_T_152 & _r_T_149; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_154 = _r_T_152 ? 3'h5 : _r_T_150; // @[Misc.scala:38:36, :56:20] wire _r_T_156 = _r_T_123 == 4'h5; // @[Misc.scala:56:20] wire _r_T_157 = ~_r_T_156 & _r_T_153; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_158 = _r_T_156 ? 3'h4 : _r_T_154; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_159 = {1'h0, _r_T_156}; // @[Misc.scala:38:63, :56:20] wire _r_T_160 = _r_T_123 == 4'h6; // @[Misc.scala:56:20] wire _r_T_161 = ~_r_T_160 & _r_T_157; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_162 = _r_T_160 ? 3'h0 : _r_T_158; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_163 = _r_T_160 ? 2'h1 : _r_T_159; // @[Misc.scala:38:63, :56:20] wire _r_T_164 = _r_T_123 == 4'h7; // @[Misc.scala:56:20] wire _r_T_165 = _r_T_164 | _r_T_161; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_166 = _r_T_164 ? 3'h0 : _r_T_162; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_167 = _r_T_164 ? 2'h1 : _r_T_163; // @[Misc.scala:38:63, :56:20] wire _r_T_168 = _r_T_123 == 4'h0; // @[Misc.scala:56:20] wire _r_T_169 = ~_r_T_168 & _r_T_165; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_170 = _r_T_168 ? 3'h5 : _r_T_166; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_171 = _r_T_168 ? 2'h0 : _r_T_167; // @[Misc.scala:38:63, :56:20] wire _r_T_172 = _r_T_123 == 4'h1; // @[Misc.scala:56:20] wire _r_T_173 = ~_r_T_172 & _r_T_169; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_174 = _r_T_172 ? 3'h4 : _r_T_170; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_175 = _r_T_172 ? 2'h1 : _r_T_171; // @[Misc.scala:38:63, :56:20] wire _r_T_176 = _r_T_123 == 4'h2; // @[Misc.scala:56:20] wire _r_T_177 = ~_r_T_176 & _r_T_173; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_178 = _r_T_176 ? 3'h3 : _r_T_174; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_179 = _r_T_176 ? 2'h2 : _r_T_175; // @[Misc.scala:38:63, :56:20] wire _r_T_180 = _r_T_123 == 4'h3; // @[Misc.scala:56:20] wire s2_victim_dirty = _r_T_180 | _r_T_177; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_shrink_param = _r_T_180 ? 3'h3 : _r_T_178; // @[Misc.scala:38:36, :56:20] wire [2:0] nodeOut_c_bits_c_param = s2_shrink_param; // @[Misc.scala:38:36] wire [2:0] nodeOut_c_bits_c_1_param = s2_shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3_1 = _r_T_180 ? 2'h2 : _r_T_179; // @[Misc.scala:38:63, :56:20] wire [1:0] voluntaryNewCoh_state = r_3_1; // @[Misc.scala:38:63] wire _s2_update_meta_T = s2_hit_state_state == s2_new_hit_state_state; // @[Metadata.scala:46:46, :160:20] wire s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala:46:46, :47:40] wire s2_dont_nack_uncached = s2_valid_uncached_pending & tl_out_a_ready; // @[DCache.scala:159:22, :430:64, :440:57] wire _s2_dont_nack_misc_T_7 = ~s2_hit; // @[Misc.scala:35:9] wire _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala:339:19, :444:17] wire _s2_dont_nack_misc_T_11 = _s2_dont_nack_misc_T_10; // @[DCache.scala:443:55, :444:17] wire s2_dont_nack_misc = _s2_dont_nack_misc_T_1 & _s2_dont_nack_misc_T_11; // @[DCache.scala:441:{43,61}, :443:55] wire _io_cpu_s2_nack_T = ~s2_dont_nack_uncached; // @[DCache.scala:440:57, :445:41] wire _io_cpu_s2_nack_T_1 = s2_valid_no_xcpt & _io_cpu_s2_nack_T; // @[DCache.scala:332:35, :445:{38,41}] wire _io_cpu_s2_nack_T_2 = ~s2_dont_nack_misc; // @[DCache.scala:441:61, :445:67] wire _io_cpu_s2_nack_T_3 = _io_cpu_s2_nack_T_1 & _io_cpu_s2_nack_T_2; // @[DCache.scala:445:{38,64,67}] wire _io_cpu_s2_nack_T_4 = ~s2_valid_hit; // @[DCache.scala:422:48, :445:89] assign _io_cpu_s2_nack_T_5 = _io_cpu_s2_nack_T_3 & _io_cpu_s2_nack_T_4; // @[DCache.scala:445:{64,86,89}] assign io_cpu_s2_nack_0 = _io_cpu_s2_nack_T_5; // @[DCache.scala:101:7, :445:86] assign _metaArb_io_in_2_valid_T = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[Metadata.scala:47:40] wire _T_48 = io_cpu_s2_nack_0 | _metaArb_io_in_2_valid_T; // @[DCache.scala:101:7, :446:24, :462:63] wire [1:0] _s2_first_meta_corrected_T_9_coh_state = _s2_first_meta_corrected_T_8_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_9_tag = _s2_first_meta_corrected_T_8_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_10_coh_state = _s2_first_meta_corrected_T_9_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_10_tag = _s2_first_meta_corrected_T_9_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_11_coh_state = _s2_first_meta_corrected_T_10_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_11_tag = _s2_first_meta_corrected_T_10_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_12_coh_state = _s2_first_meta_corrected_T_11_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_12_tag = _s2_first_meta_corrected_T_11_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_13_coh_state = _s2_first_meta_corrected_T_12_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_13_tag = _s2_first_meta_corrected_T_12_tag; // @[Mux.scala:50:70] wire [1:0] s2_first_meta_corrected_coh_state = _s2_first_meta_corrected_T_13_coh_state; // @[Mux.scala:50:70] wire [19:0] s2_first_meta_corrected_tag = _s2_first_meta_corrected_T_13_tag; // @[Mux.scala:50:70] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_state = s2_first_meta_corrected_coh_state; // @[Mux.scala:50:70] wire [19:0] metaArb_io_in_1_bits_data_new_meta_tag = s2_first_meta_corrected_tag; // @[Mux.scala:50:70] wire _metaArb_io_in_1_valid_T = s2_valid_masked | s2_flush_valid_pre_tag_ecc; // @[DCache.scala:337:42, :355:43, :450:63] wire _metaArb_io_in_1_valid_T_1 = _metaArb_io_in_1_valid_T | s2_probe; // @[DCache.scala:333:25, :450:{63,93}] wire [5:0] _metaArb_io_in_1_bits_idx_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _metaArb_io_in_6_bits_idx_T_1 = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _dataArb_io_in_2_bits_addr_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] assign _metaArb_io_in_4_bits_idx_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _metaArb_io_in_1_bits_idx_T_1 = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76] assign _metaArb_io_in_2_bits_idx_T = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76, :465:40] assign _metaArb_io_in_3_bits_idx_T = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76, :744:40] assign _metaArb_io_in_1_bits_idx_T_2 = s2_probe ? _metaArb_io_in_1_bits_idx_T : _metaArb_io_in_1_bits_idx_T_1; // @[DCache.scala:333:25, :453:{35,76}, :1200:47] assign metaArb_io_in_1_bits_idx = _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:135:28, :453:35] wire [11:0] _metaArb_io_in_1_bits_addr_T_1 = {_metaArb_io_in_1_bits_idx_T_2, 6'h0}; // @[DCache.scala:453:35, :454:98] assign _metaArb_io_in_1_bits_addr_T_2 = {_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1}; // @[DCache.scala:454:{36,58,98}] assign metaArb_io_in_1_bits_addr = _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:135:28, :454:36] assign _metaArb_io_in_1_bits_data_T = {metaArb_io_in_1_bits_data_new_meta_coh_state, metaArb_io_in_1_bits_data_new_meta_tag}; // @[DCache.scala:456:31, :458:14] assign metaArb_io_in_1_bits_data = _metaArb_io_in_1_bits_data_T; // @[DCache.scala:135:28, :458:14] assign metaArb_io_in_2_valid = _metaArb_io_in_2_valid_T; // @[DCache.scala:135:28, :462:63] assign metaArb_io_in_2_bits_idx = _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:135:28, :465:40] wire [11:0] _metaArb_io_in_2_bits_addr_T_1 = s2_vaddr[11:0]; // @[DCache.scala:351:21, :466:80] wire [11:0] _metaArb_io_in_3_bits_addr_T_1 = s2_vaddr[11:0]; // @[DCache.scala:351:21, :466:80, :745:80] assign _metaArb_io_in_2_bits_addr_T_2 = {_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1}; // @[DCache.scala:466:{36,58,80}] assign metaArb_io_in_2_bits_addr = _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:135:28, :466:36] wire [27:0] _metaArb_io_in_2_bits_data_T = s2_req_addr[39:12]; // @[DCache.scala:339:19, :467:68] wire [27:0] _metaArb_io_in_3_bits_data_T = s2_req_addr[39:12]; // @[DCache.scala:339:19, :467:68, :746:68] wire [19:0] metaArb_io_in_2_bits_data_meta_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data_meta_tag = _metaArb_io_in_2_bits_data_T[19:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_2_bits_data_T_1 = {metaArb_io_in_2_bits_data_meta_coh_state, metaArb_io_in_2_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data = _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:135:28, :467:97] wire s2_lr = _s2_lr_T; // @[DCache.scala:470:{56,70}] wire s2_sc = _s2_sc_T; // @[DCache.scala:471:{56,70}] wire io_cpu_resp_bits_data_doZero_2 = s2_sc; // @[DCache.scala:471:56] reg [6:0] lrscCount; // @[DCache.scala:472:26] wire lrscValid = |(lrscCount[6:2]); // @[DCache.scala:472:26, :473:29] wire _lrscBackingOff_T = |lrscCount; // @[DCache.scala:472:26, :474:34] wire _lrscBackingOff_T_1 = ~lrscValid; // @[DCache.scala:473:29, :474:43] wire lrscBackingOff = _lrscBackingOff_T & _lrscBackingOff_T_1; // @[DCache.scala:474:{34,40,43}] reg [33:0] lrscAddr; // @[DCache.scala:475:21] wire [33:0] _lrscAddrMatch_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49] wire [33:0] _lrscAddr_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :480:29] wire [33:0] _acquire_address_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :578:38] wire [33:0] _tl_out_a_bits_T_1 = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1210:39] wire [33:0] _io_errors_bus_bits_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1130:58] wire lrscAddrMatch = lrscAddr == _lrscAddrMatch_T; // @[DCache.scala:475:21, :476:{32,49}] wire _s2_sc_fail_T = lrscValid & lrscAddrMatch; // @[DCache.scala:473:29, :476:32, :477:41] wire _s2_sc_fail_T_1 = ~_s2_sc_fail_T; // @[DCache.scala:477:{29,41}] wire s2_sc_fail = s2_sc & _s2_sc_fail_T_1; // @[DCache.scala:471:56, :477:{26,29}] wire [6:0] _lrscCount_T = s2_hit ? 7'h4F : 7'h0; // @[Misc.scala:35:9] wire [7:0] _lrscCount_T_1 = {1'h0, lrscCount} - 8'h1; // @[DCache.scala:472:26, :482:51] wire [6:0] _lrscCount_T_2 = _lrscCount_T_1[6:0]; // @[DCache.scala:482:51] wire _s2_correct_T = ~any_pstore_valid; // @[DCache.scala:230:30, :487:37] wire _s2_correct_T_2 = any_pstore_valid | s2_valid; // @[DCache.scala:230:30, :331:25, :487:84] reg s2_correct_REG; // @[DCache.scala:487:66] wire _s2_correct_T_3 = ~s2_correct_REG; // @[DCache.scala:487:{58,66}] wire _GEN_95 = s1_valid_not_nacked & s1_write; // @[DCache.scala:187:38, :492:63] wire _pstore1_cmd_T; // @[DCache.scala:492:63] assign _pstore1_cmd_T = _GEN_95; // @[DCache.scala:492:63] wire _pstore1_addr_T; // @[DCache.scala:493:62] assign _pstore1_addr_T = _GEN_95; // @[DCache.scala:492:63, :493:62] wire _pstore1_data_T; // @[DCache.scala:494:73] assign _pstore1_data_T = _GEN_95; // @[DCache.scala:492:63, :494:73] wire _pstore1_way_T; // @[DCache.scala:495:63] assign _pstore1_way_T = _GEN_95; // @[DCache.scala:492:63, :495:63] wire _pstore1_mask_T; // @[DCache.scala:496:61] assign _pstore1_mask_T = _GEN_95; // @[DCache.scala:492:63, :496:61] wire _pstore1_rmw_T_53; // @[DCache.scala:498:84] assign _pstore1_rmw_T_53 = _GEN_95; // @[DCache.scala:492:63, :498:84] reg [4:0] pstore1_cmd; // @[DCache.scala:492:30] reg [39:0] pstore1_addr; // @[DCache.scala:493:31] wire [39:0] _pstore2_addr_T = pstore1_addr; // @[DCache.scala:493:31, :524:35] reg [63:0] pstore1_data; // @[DCache.scala:494:31] assign io_cpu_resp_bits_store_data_0 = pstore1_data; // @[DCache.scala:101:7, :494:31] wire [63:0] _amoalu_io_rhs_T = pstore1_data; // @[DCache.scala:494:31, :986:37] reg [7:0] pstore1_way; // @[DCache.scala:495:30] wire [7:0] _pstore2_way_T = pstore1_way; // @[DCache.scala:495:30, :525:34] reg [7:0] pstore1_mask; // @[DCache.scala:496:31] wire [7:0] pstore2_storegen_mask_mergedMask = pstore1_mask; // @[DCache.scala:496:31, :533:37] wire [7:0] _amoalu_io_mask_T = pstore1_mask; // @[DCache.scala:496:31, :983:38] wire [63:0] pstore1_storegen_data; // @[DCache.scala:497:42] wire _pstore1_rmw_T_4 = _pstore1_rmw_T | _pstore1_rmw_T_1; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_5 = _pstore1_rmw_T_4 | _pstore1_rmw_T_2; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_6 = _pstore1_rmw_T_5 | _pstore1_rmw_T_3; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_11 = _pstore1_rmw_T_7 | _pstore1_rmw_T_8; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_12 = _pstore1_rmw_T_11 | _pstore1_rmw_T_9; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_13 = _pstore1_rmw_T_12 | _pstore1_rmw_T_10; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_19 = _pstore1_rmw_T_14 | _pstore1_rmw_T_15; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_20 = _pstore1_rmw_T_19 | _pstore1_rmw_T_16; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_21 = _pstore1_rmw_T_20 | _pstore1_rmw_T_17; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_22 = _pstore1_rmw_T_21 | _pstore1_rmw_T_18; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_23 = _pstore1_rmw_T_13 | _pstore1_rmw_T_22; // @[package.scala:81:59] wire _pstore1_rmw_T_24 = _pstore1_rmw_T_6 | _pstore1_rmw_T_23; // @[package.scala:81:59] wire _pstore1_rmw_T_27 = _pstore1_rmw_T_25 | _pstore1_rmw_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore1_rmw_T_29 = _pstore1_rmw_T_27 | _pstore1_rmw_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore1_rmw_T_34 = _pstore1_rmw_T_30 | _pstore1_rmw_T_31; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_35 = _pstore1_rmw_T_34 | _pstore1_rmw_T_32; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_36 = _pstore1_rmw_T_35 | _pstore1_rmw_T_33; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_42 = _pstore1_rmw_T_37 | _pstore1_rmw_T_38; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_43 = _pstore1_rmw_T_42 | _pstore1_rmw_T_39; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_44 = _pstore1_rmw_T_43 | _pstore1_rmw_T_40; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_45 = _pstore1_rmw_T_44 | _pstore1_rmw_T_41; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_46 = _pstore1_rmw_T_36 | _pstore1_rmw_T_45; // @[package.scala:81:59] wire _pstore1_rmw_T_47 = _pstore1_rmw_T_29 | _pstore1_rmw_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore1_rmw_T_50 = _pstore1_rmw_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore1_rmw_T_51 = _pstore1_rmw_T_47 & _pstore1_rmw_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore1_rmw_T_52 = _pstore1_rmw_T_24 | _pstore1_rmw_T_51; // @[DCache.scala:1190:21, :1191:23] reg pstore1_rmw_r; // @[DCache.scala:498:44] wire pstore1_rmw = pstore1_rmw_r; // @[DCache.scala:498:{32,44}] wire _pstore1_merge_likely_T = s2_valid_not_nacked_in_s1 & s2_write; // @[DCache.scala:336:44, :499:56] wire _GEN_96 = s2_valid_hit & s2_write; // @[DCache.scala:422:48, :490:46] wire _pstore1_merge_T; // @[DCache.scala:490:46] assign _pstore1_merge_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_valid_T; // @[DCache.scala:490:46] assign _pstore1_valid_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_held_T; // @[DCache.scala:490:46] assign _pstore1_held_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_merge_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_merge_T_2 = _pstore1_merge_T & _pstore1_merge_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_merge_T_4 = _pstore1_merge_T_2; // @[DCache.scala:490:58, :491:48] reg pstore2_valid; // @[DCache.scala:501:30] wire _pstore_drain_opportunistic_res_T_2 = _pstore_drain_opportunistic_res_T | _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_res_T_3 = ~_pstore_drain_opportunistic_res_T_2; // @[package.scala:81:59] wire pstore_drain_opportunistic_res = _pstore_drain_opportunistic_res_T_3; // @[DCache.scala:1185:{15,46}] wire _pstore_drain_opportunistic_T_4 = _pstore_drain_opportunistic_T | _pstore_drain_opportunistic_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_5 = _pstore_drain_opportunistic_T_4 | _pstore_drain_opportunistic_T_2; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_6 = _pstore_drain_opportunistic_T_5 | _pstore_drain_opportunistic_T_3; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_11 = _pstore_drain_opportunistic_T_7 | _pstore_drain_opportunistic_T_8; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_12 = _pstore_drain_opportunistic_T_11 | _pstore_drain_opportunistic_T_9; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_13 = _pstore_drain_opportunistic_T_12 | _pstore_drain_opportunistic_T_10; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_19 = _pstore_drain_opportunistic_T_14 | _pstore_drain_opportunistic_T_15; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_20 = _pstore_drain_opportunistic_T_19 | _pstore_drain_opportunistic_T_16; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_21 = _pstore_drain_opportunistic_T_20 | _pstore_drain_opportunistic_T_17; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_22 = _pstore_drain_opportunistic_T_21 | _pstore_drain_opportunistic_T_18; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_23 = _pstore_drain_opportunistic_T_13 | _pstore_drain_opportunistic_T_22; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_24 = _pstore_drain_opportunistic_T_6 | _pstore_drain_opportunistic_T_23; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_27 = _pstore_drain_opportunistic_T_25 | _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore_drain_opportunistic_T_29 = _pstore_drain_opportunistic_T_27 | _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore_drain_opportunistic_T_34 = _pstore_drain_opportunistic_T_30 | _pstore_drain_opportunistic_T_31; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_35 = _pstore_drain_opportunistic_T_34 | _pstore_drain_opportunistic_T_32; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_36 = _pstore_drain_opportunistic_T_35 | _pstore_drain_opportunistic_T_33; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_42 = _pstore_drain_opportunistic_T_37 | _pstore_drain_opportunistic_T_38; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_43 = _pstore_drain_opportunistic_T_42 | _pstore_drain_opportunistic_T_39; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_44 = _pstore_drain_opportunistic_T_43 | _pstore_drain_opportunistic_T_40; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_45 = _pstore_drain_opportunistic_T_44 | _pstore_drain_opportunistic_T_41; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_46 = _pstore_drain_opportunistic_T_36 | _pstore_drain_opportunistic_T_45; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_47 = _pstore_drain_opportunistic_T_29 | _pstore_drain_opportunistic_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore_drain_opportunistic_T_50 = _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore_drain_opportunistic_T_51 = _pstore_drain_opportunistic_T_47 & _pstore_drain_opportunistic_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore_drain_opportunistic_T_52 = _pstore_drain_opportunistic_T_24 | _pstore_drain_opportunistic_T_51; // @[DCache.scala:1190:21, :1191:23] wire _pstore_drain_opportunistic_T_53 = ~_pstore_drain_opportunistic_T_52; // @[DCache.scala:1186:12, :1190:21] wire _pstore_drain_opportunistic_T_54 = _pstore_drain_opportunistic_T_53 | pstore_drain_opportunistic_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _pstore_drain_opportunistic_T_56 = ~_pstore_drain_opportunistic_T_55; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_57 = ~_pstore_drain_opportunistic_T_54; // @[DCache.scala:1186:{11,28}] wire _pstore_drain_opportunistic_T_58 = io_cpu_req_valid_0 & pstore_drain_opportunistic_res; // @[DCache.scala:101:7, :502:55, :1185:46] wire _pstore_drain_opportunistic_T_59 = ~_pstore_drain_opportunistic_T_58; // @[DCache.scala:502:{36,55}] wire pstore_drain_opportunistic = _pstore_drain_opportunistic_T_59; // @[DCache.scala:502:{36,92}] reg pstore_drain_on_miss_REG; // @[DCache.scala:503:56] wire pstore_drain_on_miss = releaseInFlight | pstore_drain_on_miss_REG; // @[DCache.scala:334:46, :503:{46,56}] reg pstore1_held; // @[DCache.scala:504:29] wire _GEN_97 = s2_valid & s2_write; // @[DCache.scala:331:25, :505:39] wire _pstore1_valid_likely_T; // @[DCache.scala:505:39] assign _pstore1_valid_likely_T = _GEN_97; // @[DCache.scala:505:39] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_1; // @[DCache.scala:1082:16] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = _GEN_97; // @[DCache.scala:505:39, :1082:16] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_1; // @[DCache.scala:1086:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = _GEN_97; // @[DCache.scala:505:39, :1086:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_4; // @[DCache.scala:1087:16] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = _GEN_97; // @[DCache.scala:505:39, :1087:16] wire _io_cpu_perf_canAcceptStoreThenLoad_T; // @[DCache.scala:1089:16] assign _io_cpu_perf_canAcceptStoreThenLoad_T = _GEN_97; // @[DCache.scala:505:39, :1089:16] wire _io_cpu_perf_canAcceptLoadThenLoad_T_55; // @[DCache.scala:1092:100] assign _io_cpu_perf_canAcceptLoadThenLoad_T_55 = _GEN_97; // @[DCache.scala:505:39, :1092:100] wire pstore1_valid_likely = _pstore1_valid_likely_T | pstore1_held; // @[DCache.scala:504:29, :505:{39,51}] wire _pstore1_valid_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_valid_T_2 = _pstore1_valid_T & _pstore1_valid_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_valid_T_4 = _pstore1_valid_T_2; // @[DCache.scala:490:58, :491:48] wire pstore1_valid = _pstore1_valid_T_4 | pstore1_held; // @[DCache.scala:491:48, :504:29, :507:38] wire _advance_pstore1_T = pstore1_valid; // @[DCache.scala:507:38, :522:40] assign _any_pstore_valid_T = pstore1_held | pstore2_valid; // @[DCache.scala:501:30, :504:29, :508:36] assign any_pstore_valid = _any_pstore_valid_T; // @[DCache.scala:230:30, :508:36] wire _GEN_98 = pstore1_valid_likely & pstore2_valid; // @[DCache.scala:501:30, :505:51, :509:54] wire _pstore_drain_structural_T; // @[DCache.scala:509:54] assign _pstore_drain_structural_T = _GEN_98; // @[DCache.scala:509:54] wire _io_cpu_perf_canAcceptStoreThenLoad_T_6; // @[DCache.scala:1090:20] assign _io_cpu_perf_canAcceptStoreThenLoad_T_6 = _GEN_98; // @[DCache.scala:509:54, :1090:20] wire _GEN_99 = s1_valid & s1_write; // @[DCache.scala:182:25, :509:85] wire _pstore_drain_structural_T_1; // @[DCache.scala:509:85] assign _pstore_drain_structural_T_1 = _GEN_99; // @[DCache.scala:509:85] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T; // @[DCache.scala:1081:15] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T = _GEN_99; // @[DCache.scala:509:85, :1081:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T; // @[DCache.scala:1085:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T = _GEN_99; // @[DCache.scala:509:85, :1085:15] wire _io_cpu_perf_canAcceptStoreThenLoad_T_2; // @[DCache.scala:1089:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_2 = _GEN_99; // @[DCache.scala:509:85, :1089:57] wire _io_cpu_perf_canAcceptStoreThenLoad_T_7; // @[DCache.scala:1090:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_7 = _GEN_99; // @[DCache.scala:509:85, :1090:57] wire _io_cpu_perf_canAcceptLoadThenLoad_T; // @[DCache.scala:1092:52] assign _io_cpu_perf_canAcceptLoadThenLoad_T = _GEN_99; // @[DCache.scala:509:85, :1092:52] wire _pstore_drain_structural_T_2 = _pstore_drain_structural_T_1 | pstore1_rmw; // @[DCache.scala:498:32, :509:{85,98}] wire pstore_drain_structural = _pstore_drain_structural_T & _pstore_drain_structural_T_2; // @[DCache.scala:509:{54,71,98}] wire _pstore_drain_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _dataArb_io_in_0_valid_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _T_57 = s2_valid_hit_pre_data_ecc & s2_write; // @[DCache.scala:420:69, :506:72] wire _pstore_drain_T_2; // @[DCache.scala:506:72] assign _pstore_drain_T_2 = _T_57; // @[DCache.scala:506:72] wire _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:72] assign _dataArb_io_in_0_valid_T_2 = _T_57; // @[DCache.scala:506:72] wire _pstore_drain_T_4 = _pstore_drain_T_2; // @[DCache.scala:506:{72,84}] wire _pstore_drain_T_5 = _pstore_drain_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _pstore_drain_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _pstore_drain_T_7 = _pstore_drain_T_5 & _pstore_drain_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _pstore_drain_T_8 = _pstore_drain_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _GEN_100 = pstore_drain_opportunistic | pstore_drain_on_miss; // @[DCache.scala:502:92, :503:46, :518:107] wire _pstore_drain_T_9; // @[DCache.scala:518:107] assign _pstore_drain_T_9 = _GEN_100; // @[DCache.scala:518:107] wire _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:107] assign _dataArb_io_in_0_valid_T_9 = _GEN_100; // @[DCache.scala:518:107] wire _pstore_drain_T_10 = _pstore_drain_T_8 & _pstore_drain_T_9; // @[DCache.scala:518:{58,76,107}] wire _pstore_drain_T_11 = _pstore_drain_T_1 | _pstore_drain_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign pstore_drain = _pstore_drain_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_bits_write = pstore_drain; // @[DCache.scala:152:28, :516:27] wire _pstore1_held_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_held_T_2 = _pstore1_held_T & _pstore1_held_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_held_T_4 = _pstore1_held_T_2; // @[DCache.scala:490:58, :491:48] wire _pstore1_held_T_6 = _pstore1_held_T_4; // @[DCache.scala:491:48, :521:35] wire _pstore1_held_T_7 = _pstore1_held_T_6 | pstore1_held; // @[DCache.scala:504:29, :521:{35,54}] wire _pstore1_held_T_8 = _pstore1_held_T_7 & pstore2_valid; // @[DCache.scala:501:30, :521:{54,71}] wire _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala:516:27, :521:91] wire _pstore1_held_T_10 = _pstore1_held_T_8 & _pstore1_held_T_9; // @[DCache.scala:521:{71,88,91}] wire _advance_pstore1_T_1 = pstore2_valid == pstore_drain; // @[DCache.scala:501:30, :516:27, :522:79] wire advance_pstore1 = _advance_pstore1_T & _advance_pstore1_T_1; // @[DCache.scala:522:{40,61,79}] wire _pstore2_storegen_data_T_3 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_7 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_11 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_15 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_19 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_23 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_27 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_31 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_mask_T = advance_pstore1; // @[DCache.scala:522:61, :532:27] wire _pstore2_valid_T = ~pstore_drain; // @[DCache.scala:516:27, :521:91, :523:37] wire _pstore2_valid_T_1 = pstore2_valid & _pstore2_valid_T; // @[DCache.scala:501:30, :523:{34,37}] wire _pstore2_valid_T_2 = _pstore2_valid_T_1 | advance_pstore1; // @[DCache.scala:522:61, :523:{34,51}] reg [39:0] pstore2_addr; // @[DCache.scala:524:31] reg [7:0] pstore2_way; // @[DCache.scala:525:30] wire [7:0] _pstore2_storegen_data_T = pstore1_storegen_data[7:0]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_1 = pstore1_mask[0]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_3 = pstore1_mask[0]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_4 = pstore1_storegen_data[15:8]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_5 = pstore1_mask[1]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_4 = pstore1_mask[1]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_1; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_8 = pstore1_storegen_data[23:16]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_9 = pstore1_mask[2]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_5 = pstore1_mask[2]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_2; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_12 = pstore1_storegen_data[31:24]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_13 = pstore1_mask[3]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_6 = pstore1_mask[3]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_3; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_16 = pstore1_storegen_data[39:32]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_17 = pstore1_mask[4]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_7 = pstore1_mask[4]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_4; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_20 = pstore1_storegen_data[47:40]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_21 = pstore1_mask[5]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_8 = pstore1_mask[5]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_5; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_24 = pstore1_storegen_data[55:48]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_25 = pstore1_mask[6]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_9 = pstore1_mask[6]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_6; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_28 = pstore1_storegen_data[63:56]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_29 = pstore1_mask[7]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_10 = pstore1_mask[7]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_7; // @[DCache.scala:528:22] wire [15:0] pstore2_storegen_data_lo_lo = {pstore2_storegen_data_r_1, pstore2_storegen_data_r}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_lo_hi = {pstore2_storegen_data_r_3, pstore2_storegen_data_r_2}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_lo = {pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_lo = {pstore2_storegen_data_r_5, pstore2_storegen_data_r_4}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_hi = {pstore2_storegen_data_r_7, pstore2_storegen_data_r_6}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_hi = {pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo}; // @[package.scala:45:27] wire [63:0] pstore2_storegen_data = {pstore2_storegen_data_hi, pstore2_storegen_data_lo}; // @[package.scala:45:27] reg [7:0] pstore2_storegen_mask; // @[DCache.scala:531:19] wire [7:0] _pstore2_storegen_mask_mask_T = ~pstore2_storegen_mask_mergedMask; // @[DCache.scala:533:37, :534:37] wire [7:0] _pstore2_storegen_mask_mask_T_1 = _pstore2_storegen_mask_mask_T; // @[DCache.scala:534:{19,37}] wire [7:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T_1; // @[DCache.scala:534:{15,19}] wire _dataArb_io_in_0_valid_T_4 = _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:{72,84}] wire _dataArb_io_in_0_valid_T_5 = _dataArb_io_in_0_valid_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _dataArb_io_in_0_valid_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _dataArb_io_in_0_valid_T_7 = _dataArb_io_in_0_valid_T_5 & _dataArb_io_in_0_valid_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _dataArb_io_in_0_valid_T_8 = _dataArb_io_in_0_valid_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _dataArb_io_in_0_valid_T_10 = _dataArb_io_in_0_valid_T_8 & _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:{58,76,107}] wire _dataArb_io_in_0_valid_T_11 = _dataArb_io_in_0_valid_T_1 | _dataArb_io_in_0_valid_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign _dataArb_io_in_0_valid_T_12 = _dataArb_io_in_0_valid_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_valid = _dataArb_io_in_0_valid_T_12; // @[DCache.scala:152:28, :516:27] wire [39:0] _GEN_101 = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala:493:31, :501:30, :524:31, :549:36] wire [39:0] _dataArb_io_in_0_bits_addr_T; // @[DCache.scala:549:36] assign _dataArb_io_in_0_bits_addr_T = _GEN_101; // @[DCache.scala:549:36] wire [39:0] _dataArb_io_in_0_bits_wordMask_wordMask_T; // @[DCache.scala:554:32] assign _dataArb_io_in_0_bits_wordMask_wordMask_T = _GEN_101; // @[DCache.scala:549:36, :554:32] assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[11:0]; // @[DCache.scala:152:28, :549:{30,36}] assign _dataArb_io_in_0_bits_way_en_T = pstore2_valid ? pstore2_way : pstore1_way; // @[DCache.scala:495:30, :501:30, :525:30, :550:38] assign dataArb_io_in_0_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38] wire [63:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[package.scala:45:27] wire [127:0] _dataArb_io_in_0_bits_wdata_T_1 = {2{_dataArb_io_in_0_bits_wdata_T}}; // @[DCache.scala:551:{49,63}] wire [7:0] _dataArb_io_in_0_bits_wdata_T_2 = _dataArb_io_in_0_bits_wdata_T_1[7:0]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_3 = _dataArb_io_in_0_bits_wdata_T_1[15:8]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_4 = _dataArb_io_in_0_bits_wdata_T_1[23:16]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_5 = _dataArb_io_in_0_bits_wdata_T_1[31:24]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_6 = _dataArb_io_in_0_bits_wdata_T_1[39:32]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_7 = _dataArb_io_in_0_bits_wdata_T_1[47:40]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_8 = _dataArb_io_in_0_bits_wdata_T_1[55:48]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_9 = _dataArb_io_in_0_bits_wdata_T_1[63:56]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_10 = _dataArb_io_in_0_bits_wdata_T_1[71:64]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_11 = _dataArb_io_in_0_bits_wdata_T_1[79:72]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_12 = _dataArb_io_in_0_bits_wdata_T_1[87:80]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_13 = _dataArb_io_in_0_bits_wdata_T_1[95:88]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_14 = _dataArb_io_in_0_bits_wdata_T_1[103:96]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_15 = _dataArb_io_in_0_bits_wdata_T_1[111:104]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_16 = _dataArb_io_in_0_bits_wdata_T_1[119:112]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_17 = _dataArb_io_in_0_bits_wdata_T_1[127:120]; // @[package.scala:211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo_lo = {_dataArb_io_in_0_bits_wdata_T_3, _dataArb_io_in_0_bits_wdata_T_2}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo_hi = {_dataArb_io_in_0_bits_wdata_T_5, _dataArb_io_in_0_bits_wdata_T_4}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_lo_lo = {dataArb_io_in_0_bits_wdata_lo_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi_lo = {_dataArb_io_in_0_bits_wdata_T_7, _dataArb_io_in_0_bits_wdata_T_6}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi_hi = {_dataArb_io_in_0_bits_wdata_T_9, _dataArb_io_in_0_bits_wdata_T_8}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_lo_hi = {dataArb_io_in_0_bits_wdata_lo_hi_hi, dataArb_io_in_0_bits_wdata_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] dataArb_io_in_0_bits_wdata_lo = {dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo_lo = {_dataArb_io_in_0_bits_wdata_T_11, _dataArb_io_in_0_bits_wdata_T_10}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo_hi = {_dataArb_io_in_0_bits_wdata_T_13, _dataArb_io_in_0_bits_wdata_T_12}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_hi_lo = {dataArb_io_in_0_bits_wdata_hi_lo_hi, dataArb_io_in_0_bits_wdata_hi_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi_lo = {_dataArb_io_in_0_bits_wdata_T_15, _dataArb_io_in_0_bits_wdata_T_14}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi_hi = {_dataArb_io_in_0_bits_wdata_T_17, _dataArb_io_in_0_bits_wdata_T_16}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_hi_hi = {dataArb_io_in_0_bits_wdata_hi_hi_hi, dataArb_io_in_0_bits_wdata_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] dataArb_io_in_0_bits_wdata_hi = {dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_wdata_T_18 = {dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_wdata = _dataArb_io_in_0_bits_wdata_T_18; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T = _dataArb_io_in_0_bits_eccMask_T_17[0]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T_17[1]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T_17[2]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T_17[3]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T_17[4]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T_17[5]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T_17[6]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T_17[7]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = _dataArb_io_in_0_bits_wordMask_eccMask_T | _dataArb_io_in_0_bits_wordMask_eccMask_T_1; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = _dataArb_io_in_0_bits_wordMask_eccMask_T_8 | _dataArb_io_in_0_bits_wordMask_eccMask_T_2; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = _dataArb_io_in_0_bits_wordMask_eccMask_T_9 | _dataArb_io_in_0_bits_wordMask_eccMask_T_3; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = _dataArb_io_in_0_bits_wordMask_eccMask_T_10 | _dataArb_io_in_0_bits_wordMask_eccMask_T_4; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = _dataArb_io_in_0_bits_wordMask_eccMask_T_11 | _dataArb_io_in_0_bits_wordMask_eccMask_T_5; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = _dataArb_io_in_0_bits_wordMask_eccMask_T_12 | _dataArb_io_in_0_bits_wordMask_eccMask_T_6; // @[package.scala:81:59] wire dataArb_io_in_0_bits_wordMask_eccMask = _dataArb_io_in_0_bits_wordMask_eccMask_T_13 | _dataArb_io_in_0_bits_wordMask_eccMask_T_7; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_wordMask_T_1 = _dataArb_io_in_0_bits_wordMask_wordMask_T[3]; // @[package.scala:163:13] wire [1:0] dataArb_io_in_0_bits_wordMask_wordMask = 2'h1 << _dataArb_io_in_0_bits_wordMask_wordMask_T_1; // @[OneHot.scala:58:35] wire _dataArb_io_in_0_bits_wordMask_T = dataArb_io_in_0_bits_wordMask_wordMask[0]; // @[OneHot.scala:58:35] wire _dataArb_io_in_0_bits_wordMask_T_1 = dataArb_io_in_0_bits_wordMask_wordMask[1]; // @[OneHot.scala:58:35] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_2 = {_dataArb_io_in_0_bits_wordMask_T_1, _dataArb_io_in_0_bits_wordMask_T}; // @[DCache.scala:555:20] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_3 = {2{dataArb_io_in_0_bits_wordMask_eccMask}}; // @[package.scala:81:59] assign _dataArb_io_in_0_bits_wordMask_T_4 = _dataArb_io_in_0_bits_wordMask_T_2 & _dataArb_io_in_0_bits_wordMask_T_3; // @[DCache.scala:555:{20,55,61}] assign dataArb_io_in_0_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_4; // @[DCache.scala:152:28, :555:55] wire [7:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? pstore2_storegen_mask : pstore1_mask; // @[DCache.scala:496:31, :501:30, :531:19, :557:47] wire _dataArb_io_in_0_bits_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T[0]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_9 = _dataArb_io_in_0_bits_eccMask_T_1; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T[1]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_10 = _dataArb_io_in_0_bits_eccMask_T_2; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T[2]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_11 = _dataArb_io_in_0_bits_eccMask_T_3; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T[3]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_12 = _dataArb_io_in_0_bits_eccMask_T_4; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T[4]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_13 = _dataArb_io_in_0_bits_eccMask_T_5; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T[5]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_14 = _dataArb_io_in_0_bits_eccMask_T_6; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T[6]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_15 = _dataArb_io_in_0_bits_eccMask_T_7; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_8 = _dataArb_io_in_0_bits_eccMask_T[7]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_16 = _dataArb_io_in_0_bits_eccMask_T_8; // @[package.scala:211:50] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_lo = {_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_hi = {_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_lo = {dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_lo = {_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_hi = {_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_hi = {dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_eccMask_T_17 = {dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [8:0] _s1_hazard_T = pstore1_addr[11:3]; // @[DCache.scala:493:31, :561:9] wire [8:0] _s1_hazard_T_1 = s1_vaddr[11:3]; // @[DCache.scala:197:21, :561:43] wire [8:0] _s1_hazard_T_63 = s1_vaddr[11:3]; // @[DCache.scala:197:21, :561:43] wire _s1_hazard_T_2 = _s1_hazard_T == _s1_hazard_T_1; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_11 = _s1_hazard_T_3; // @[package.scala:211:50] wire _s1_hazard_T_12 = _s1_hazard_T_4; // @[package.scala:211:50] wire _s1_hazard_T_13 = _s1_hazard_T_5; // @[package.scala:211:50] wire _s1_hazard_T_14 = _s1_hazard_T_6; // @[package.scala:211:50] wire _s1_hazard_T_15 = _s1_hazard_T_7; // @[package.scala:211:50] wire _s1_hazard_T_16 = _s1_hazard_T_8; // @[package.scala:211:50] wire _s1_hazard_T_17 = _s1_hazard_T_9; // @[package.scala:211:50] wire _s1_hazard_T_18 = _s1_hazard_T_10; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo = {_s1_hazard_T_12, _s1_hazard_T_11}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi = {_s1_hazard_T_14, _s1_hazard_T_13}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo = {s1_hazard_lo_hi, s1_hazard_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo = {_s1_hazard_T_16, _s1_hazard_T_15}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi = {_s1_hazard_T_18, _s1_hazard_T_17}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi = {s1_hazard_hi_hi, s1_hazard_hi_lo}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_19 = {s1_hazard_hi, s1_hazard_lo}; // @[package.scala:45:27] wire _s1_hazard_T_20 = _s1_hazard_T_19[0]; // @[package.scala:45:27] wire _s1_hazard_T_21 = _s1_hazard_T_19[1]; // @[package.scala:45:27] wire _s1_hazard_T_22 = _s1_hazard_T_19[2]; // @[package.scala:45:27] wire _s1_hazard_T_23 = _s1_hazard_T_19[3]; // @[package.scala:45:27] wire _s1_hazard_T_24 = _s1_hazard_T_19[4]; // @[package.scala:45:27] wire _s1_hazard_T_25 = _s1_hazard_T_19[5]; // @[package.scala:45:27] wire _s1_hazard_T_26 = _s1_hazard_T_19[6]; // @[package.scala:45:27] wire _s1_hazard_T_27 = _s1_hazard_T_19[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_1 = {_s1_hazard_T_21, _s1_hazard_T_20}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_1 = {_s1_hazard_T_23, _s1_hazard_T_22}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_1 = {s1_hazard_lo_hi_1, s1_hazard_lo_lo_1}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_1 = {_s1_hazard_T_25, _s1_hazard_T_24}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_1 = {_s1_hazard_T_27, _s1_hazard_T_26}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_1 = {s1_hazard_hi_hi_1, s1_hazard_hi_lo_1}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_28 = {s1_hazard_hi_1, s1_hazard_lo_1}; // @[DCache.scala:1182:52] wire _s1_hazard_T_29 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_91 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_37 = _s1_hazard_T_29; // @[package.scala:211:50] wire _s1_hazard_T_30 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_92 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_38 = _s1_hazard_T_30; // @[package.scala:211:50] wire _s1_hazard_T_31 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_93 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_39 = _s1_hazard_T_31; // @[package.scala:211:50] wire _s1_hazard_T_32 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_94 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_40 = _s1_hazard_T_32; // @[package.scala:211:50] wire _s1_hazard_T_33 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_95 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_41 = _s1_hazard_T_33; // @[package.scala:211:50] wire _s1_hazard_T_34 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_96 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_42 = _s1_hazard_T_34; // @[package.scala:211:50] wire _s1_hazard_T_35 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_97 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_43 = _s1_hazard_T_35; // @[package.scala:211:50] wire _s1_hazard_T_36 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_98 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_44 = _s1_hazard_T_36; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_2 = {_s1_hazard_T_38, _s1_hazard_T_37}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_2 = {_s1_hazard_T_40, _s1_hazard_T_39}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_2 = {s1_hazard_lo_hi_2, s1_hazard_lo_lo_2}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_2 = {_s1_hazard_T_42, _s1_hazard_T_41}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_2 = {_s1_hazard_T_44, _s1_hazard_T_43}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_2 = {s1_hazard_hi_hi_2, s1_hazard_hi_lo_2}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_45 = {s1_hazard_hi_2, s1_hazard_lo_2}; // @[package.scala:45:27] wire _s1_hazard_T_46 = _s1_hazard_T_45[0]; // @[package.scala:45:27] wire _s1_hazard_T_47 = _s1_hazard_T_45[1]; // @[package.scala:45:27] wire _s1_hazard_T_48 = _s1_hazard_T_45[2]; // @[package.scala:45:27] wire _s1_hazard_T_49 = _s1_hazard_T_45[3]; // @[package.scala:45:27] wire _s1_hazard_T_50 = _s1_hazard_T_45[4]; // @[package.scala:45:27] wire _s1_hazard_T_51 = _s1_hazard_T_45[5]; // @[package.scala:45:27] wire _s1_hazard_T_52 = _s1_hazard_T_45[6]; // @[package.scala:45:27] wire _s1_hazard_T_53 = _s1_hazard_T_45[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_3 = {_s1_hazard_T_47, _s1_hazard_T_46}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_3 = {_s1_hazard_T_49, _s1_hazard_T_48}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_3 = {s1_hazard_lo_hi_3, s1_hazard_lo_lo_3}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_3 = {_s1_hazard_T_51, _s1_hazard_T_50}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_3 = {_s1_hazard_T_53, _s1_hazard_T_52}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_3 = {s1_hazard_hi_hi_3, s1_hazard_hi_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_54 = {s1_hazard_hi_3, s1_hazard_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_55 = _s1_hazard_T_28 & _s1_hazard_T_54; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_56 = |_s1_hazard_T_55; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_57 = pstore1_mask & s1_mask_xwr; // @[DCache.scala:496:31, :562:77] wire _s1_hazard_T_58 = |_s1_hazard_T_57; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_59 = s1_write ? _s1_hazard_T_56 : _s1_hazard_T_58; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_60 = _s1_hazard_T_2 & _s1_hazard_T_59; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_61 = pstore1_valid_likely & _s1_hazard_T_60; // @[DCache.scala:505:51, :561:65, :564:27] wire [8:0] _s1_hazard_T_62 = pstore2_addr[11:3]; // @[DCache.scala:524:31, :561:9] wire _s1_hazard_T_64 = _s1_hazard_T_62 == _s1_hazard_T_63; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_65 = pstore2_storegen_mask[0]; // @[package.scala:211:50] wire _s1_hazard_T_73 = _s1_hazard_T_65; // @[package.scala:211:50] wire _s1_hazard_T_66 = pstore2_storegen_mask[1]; // @[package.scala:211:50] wire _s1_hazard_T_74 = _s1_hazard_T_66; // @[package.scala:211:50] wire _s1_hazard_T_67 = pstore2_storegen_mask[2]; // @[package.scala:211:50] wire _s1_hazard_T_75 = _s1_hazard_T_67; // @[package.scala:211:50] wire _s1_hazard_T_68 = pstore2_storegen_mask[3]; // @[package.scala:211:50] wire _s1_hazard_T_76 = _s1_hazard_T_68; // @[package.scala:211:50] wire _s1_hazard_T_69 = pstore2_storegen_mask[4]; // @[package.scala:211:50] wire _s1_hazard_T_77 = _s1_hazard_T_69; // @[package.scala:211:50] wire _s1_hazard_T_70 = pstore2_storegen_mask[5]; // @[package.scala:211:50] wire _s1_hazard_T_78 = _s1_hazard_T_70; // @[package.scala:211:50] wire _s1_hazard_T_71 = pstore2_storegen_mask[6]; // @[package.scala:211:50] wire _s1_hazard_T_79 = _s1_hazard_T_71; // @[package.scala:211:50] wire _s1_hazard_T_72 = pstore2_storegen_mask[7]; // @[package.scala:211:50] wire _s1_hazard_T_80 = _s1_hazard_T_72; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_4 = {_s1_hazard_T_74, _s1_hazard_T_73}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_4 = {_s1_hazard_T_76, _s1_hazard_T_75}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_4 = {s1_hazard_lo_hi_4, s1_hazard_lo_lo_4}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_4 = {_s1_hazard_T_78, _s1_hazard_T_77}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_4 = {_s1_hazard_T_80, _s1_hazard_T_79}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_4 = {s1_hazard_hi_hi_4, s1_hazard_hi_lo_4}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_81 = {s1_hazard_hi_4, s1_hazard_lo_4}; // @[package.scala:45:27] wire _s1_hazard_T_82 = _s1_hazard_T_81[0]; // @[package.scala:45:27] wire _s1_hazard_T_83 = _s1_hazard_T_81[1]; // @[package.scala:45:27] wire _s1_hazard_T_84 = _s1_hazard_T_81[2]; // @[package.scala:45:27] wire _s1_hazard_T_85 = _s1_hazard_T_81[3]; // @[package.scala:45:27] wire _s1_hazard_T_86 = _s1_hazard_T_81[4]; // @[package.scala:45:27] wire _s1_hazard_T_87 = _s1_hazard_T_81[5]; // @[package.scala:45:27] wire _s1_hazard_T_88 = _s1_hazard_T_81[6]; // @[package.scala:45:27] wire _s1_hazard_T_89 = _s1_hazard_T_81[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_5 = {_s1_hazard_T_83, _s1_hazard_T_82}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_5 = {_s1_hazard_T_85, _s1_hazard_T_84}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_5 = {s1_hazard_lo_hi_5, s1_hazard_lo_lo_5}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_5 = {_s1_hazard_T_87, _s1_hazard_T_86}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_5 = {_s1_hazard_T_89, _s1_hazard_T_88}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_5 = {s1_hazard_hi_hi_5, s1_hazard_hi_lo_5}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_90 = {s1_hazard_hi_5, s1_hazard_lo_5}; // @[DCache.scala:1182:52] wire _s1_hazard_T_99 = _s1_hazard_T_91; // @[package.scala:211:50] wire _s1_hazard_T_100 = _s1_hazard_T_92; // @[package.scala:211:50] wire _s1_hazard_T_101 = _s1_hazard_T_93; // @[package.scala:211:50] wire _s1_hazard_T_102 = _s1_hazard_T_94; // @[package.scala:211:50] wire _s1_hazard_T_103 = _s1_hazard_T_95; // @[package.scala:211:50] wire _s1_hazard_T_104 = _s1_hazard_T_96; // @[package.scala:211:50] wire _s1_hazard_T_105 = _s1_hazard_T_97; // @[package.scala:211:50] wire _s1_hazard_T_106 = _s1_hazard_T_98; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_6 = {_s1_hazard_T_100, _s1_hazard_T_99}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_6 = {_s1_hazard_T_102, _s1_hazard_T_101}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_6 = {s1_hazard_lo_hi_6, s1_hazard_lo_lo_6}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_6 = {_s1_hazard_T_104, _s1_hazard_T_103}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_6 = {_s1_hazard_T_106, _s1_hazard_T_105}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_6 = {s1_hazard_hi_hi_6, s1_hazard_hi_lo_6}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_107 = {s1_hazard_hi_6, s1_hazard_lo_6}; // @[package.scala:45:27] wire _s1_hazard_T_108 = _s1_hazard_T_107[0]; // @[package.scala:45:27] wire _s1_hazard_T_109 = _s1_hazard_T_107[1]; // @[package.scala:45:27] wire _s1_hazard_T_110 = _s1_hazard_T_107[2]; // @[package.scala:45:27] wire _s1_hazard_T_111 = _s1_hazard_T_107[3]; // @[package.scala:45:27] wire _s1_hazard_T_112 = _s1_hazard_T_107[4]; // @[package.scala:45:27] wire _s1_hazard_T_113 = _s1_hazard_T_107[5]; // @[package.scala:45:27] wire _s1_hazard_T_114 = _s1_hazard_T_107[6]; // @[package.scala:45:27] wire _s1_hazard_T_115 = _s1_hazard_T_107[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_7 = {_s1_hazard_T_109, _s1_hazard_T_108}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_7 = {_s1_hazard_T_111, _s1_hazard_T_110}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_7 = {s1_hazard_lo_hi_7, s1_hazard_lo_lo_7}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_7 = {_s1_hazard_T_113, _s1_hazard_T_112}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_7 = {_s1_hazard_T_115, _s1_hazard_T_114}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_7 = {s1_hazard_hi_hi_7, s1_hazard_hi_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_116 = {s1_hazard_hi_7, s1_hazard_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_117 = _s1_hazard_T_90 & _s1_hazard_T_116; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_118 = |_s1_hazard_T_117; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_119 = pstore2_storegen_mask & s1_mask_xwr; // @[DCache.scala:531:19, :562:77] wire _s1_hazard_T_120 = |_s1_hazard_T_119; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_121 = s1_write ? _s1_hazard_T_118 : _s1_hazard_T_120; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_122 = _s1_hazard_T_64 & _s1_hazard_T_121; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_123 = pstore2_valid & _s1_hazard_T_122; // @[DCache.scala:501:30, :561:65, :565:21] wire s1_hazard = _s1_hazard_T_61 | _s1_hazard_T_123; // @[DCache.scala:564:{27,69}, :565:21] wire s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala:564:69, :566:31] wire _T_68 = s1_valid & s1_raw_hazard; // @[DCache.scala:182:25, :566:31, :571:18] reg io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:38] assign _io_cpu_s2_nack_cause_raw_T_3 = io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:{38,54}] assign io_cpu_s2_nack_cause_raw_0 = _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:101:7, :574:54] wire _a_source_T = ~uncachedInFlight_0; // @[DCache.scala:236:33, :577:34] wire [1:0] _a_source_T_1 = {_a_source_T, 1'h0}; // @[DCache.scala:577:{34,59}] wire _a_source_T_2 = _a_source_T_1[0]; // @[OneHot.scala:48:45] wire _a_source_T_3 = _a_source_T_1[1]; // @[OneHot.scala:48:45] wire a_source = ~_a_source_T_2; // @[OneHot.scala:48:45] wire get_source = a_source; // @[Mux.scala:50:70] wire put_source = a_source; // @[Mux.scala:50:70] wire putpartial_source = a_source; // @[Mux.scala:50:70] wire atomics_a_source = a_source; // @[Mux.scala:50:70] wire atomics_a_1_source = a_source; // @[Mux.scala:50:70] wire atomics_a_2_source = a_source; // @[Mux.scala:50:70] wire atomics_a_3_source = a_source; // @[Mux.scala:50:70] wire atomics_a_4_source = a_source; // @[Mux.scala:50:70] wire atomics_a_5_source = a_source; // @[Mux.scala:50:70] wire atomics_a_6_source = a_source; // @[Mux.scala:50:70] wire atomics_a_7_source = a_source; // @[Mux.scala:50:70] wire atomics_a_8_source = a_source; // @[Mux.scala:50:70] wire a_sel_shiftAmount = a_source; // @[OneHot.scala:64:49] wire [39:0] acquire_address = {_acquire_address_T, 6'h0}; // @[DCache.scala:578:{38,49}] wire [127:0] a_data = {2{pstore1_data}}; // @[DCache.scala:494:31, :581:20] wire [127:0] put_data = a_data; // @[Edges.scala:480:17] wire [127:0] putpartial_data = a_data; // @[Edges.scala:500:17] wire [127:0] atomics_a_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_1_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_2_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_3_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_4_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_5_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_6_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_7_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_8_data = a_data; // @[Edges.scala:517:17] wire [3:0] _a_mask_T_1 = {_a_mask_T, 3'h0}; // @[package.scala:163:13] wire [22:0] a_mask = {15'h0, pstore1_mask} << _a_mask_T_1; // @[DCache.scala:496:31, :582:{29,90}] wire [39:0] _GEN_102 = {s2_req_addr[39:14], s2_req_addr[13:0] ^ 14'h3000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_4; // @[Parameters.scala:137:31] assign _putpartial_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_103 = {s2_req_addr[39:17], s2_req_addr[16:0] ^ 17'h10000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31] assign _put_legal_T_63 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_63; // @[Parameters.scala:137:31] assign _putpartial_legal_T_63 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_35; // @[Parameters.scala:137:31] assign _atomics_legal_T_35 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_94; // @[Parameters.scala:137:31] assign _atomics_legal_T_94 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_153; // @[Parameters.scala:137:31] assign _atomics_legal_T_153 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_212; // @[Parameters.scala:137:31] assign _atomics_legal_T_212 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_271; // @[Parameters.scala:137:31] assign _atomics_legal_T_271 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_330; // @[Parameters.scala:137:31] assign _atomics_legal_T_330 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_389; // @[Parameters.scala:137:31] assign _atomics_legal_T_389 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_448; // @[Parameters.scala:137:31] assign _atomics_legal_T_448 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_507; // @[Parameters.scala:137:31] assign _atomics_legal_T_507 = _GEN_103; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_104 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_104; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_24; // @[Parameters.scala:137:31] assign _putpartial_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_105 = {s2_req_addr[39:28], s2_req_addr[27:0] ^ 28'h8000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_34; // @[Parameters.scala:137:31] assign _putpartial_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_39; // @[Parameters.scala:137:31] assign _putpartial_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_45; // @[Parameters.scala:137:31] assign _atomics_legal_T_45 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_104; // @[Parameters.scala:137:31] assign _atomics_legal_T_104 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_163; // @[Parameters.scala:137:31] assign _atomics_legal_T_163 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_222; // @[Parameters.scala:137:31] assign _atomics_legal_T_222 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_281; // @[Parameters.scala:137:31] assign _atomics_legal_T_281 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_340; // @[Parameters.scala:137:31] assign _atomics_legal_T_340 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_399; // @[Parameters.scala:137:31] assign _atomics_legal_T_399 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_458; // @[Parameters.scala:137:31] assign _atomics_legal_T_458 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_517; // @[Parameters.scala:137:31] assign _atomics_legal_T_517 = _GEN_105; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_106 = {s2_req_addr[39:29], s2_req_addr[28:0] ^ 29'h10000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_44; // @[Parameters.scala:137:31] assign _putpartial_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_201; // @[Parameters.scala:137:31] assign _atomics_legal_T_201 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_260; // @[Parameters.scala:137:31] assign _atomics_legal_T_260 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_319; // @[Parameters.scala:137:31] assign _atomics_legal_T_319 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_378; // @[Parameters.scala:137:31] assign _atomics_legal_T_378 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_437; // @[Parameters.scala:137:31] assign _atomics_legal_T_437 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_496; // @[Parameters.scala:137:31] assign _atomics_legal_T_496 = _GEN_106; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] assign io_cpu_s2_paddr_0 = s2_req_addr[31:0]; // @[DCache.scala:101:7, :339:19] wire [31:0] get_address = s2_req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = s2_req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] putpartial_address = s2_req_addr[31:0]; // @[Edges.scala:500:17] wire [31:0] atomics_a_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [39:0] _GEN_107 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ 32'h80000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_49; // @[Parameters.scala:137:31] assign _putpartial_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_50; // @[Parameters.scala:137:31] assign _atomics_legal_T_50 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_109; // @[Parameters.scala:137:31] assign _atomics_legal_T_109 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_168; // @[Parameters.scala:137:31] assign _atomics_legal_T_168 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_227; // @[Parameters.scala:137:31] assign _atomics_legal_T_227 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_286; // @[Parameters.scala:137:31] assign _atomics_legal_T_286 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_345; // @[Parameters.scala:137:31] assign _atomics_legal_T_345 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_404; // @[Parameters.scala:137:31] assign _atomics_legal_T_404 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_463; // @[Parameters.scala:137:31] assign _atomics_legal_T_463 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_522; // @[Parameters.scala:137:31] assign _atomics_legal_T_522 = _GEN_107; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_54 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_55 = _get_legal_T_54 | _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_56 = _get_legal_T_55 | _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_57 = _get_legal_T_56 | _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_58 = _get_legal_T_57 | _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_59 = _get_legal_T_58 | _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 | _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_62 | _get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [15:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [15:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_108 = {2'h0, s2_req_size}; // @[Edges.scala:463:15] assign get_size = _GEN_108; // @[Edges.scala:460:17, :463:15] wire [3:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_108; // @[Misc.scala:202:34] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_108; // @[Edges.scala:463:15, :480:17] wire [3:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_108; // @[Misc.scala:202:34] wire [3:0] putpartial_size; // @[Edges.scala:500:17] assign putpartial_size = _GEN_108; // @[Edges.scala:463:15, :500:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_108; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_size = get_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_sub_1_2 = get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_sub_nbit = ~get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_sub_0_2 = get_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_sub_acc_T = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_0_1 = _get_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _get_a_mask_sub_sub_sub_acc_T_1 = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_1_1 = _get_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_word_bypass_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_2_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T_2 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_2_1 = get_a_mask_sub_sub_sub_1_1 | _get_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_3_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_3 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_3_1 = get_a_mask_sub_sub_sub_1_1 | _get_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = s2_req_addr[1]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_4_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_4 = get_a_mask_sub_size & get_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_4_1 = get_a_mask_sub_sub_2_1 | _get_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_5_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_5 = get_a_mask_sub_size & get_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_5_1 = get_a_mask_sub_sub_2_1 | _get_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_6_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_6 = get_a_mask_sub_size & get_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_6_1 = get_a_mask_sub_sub_3_1 | _get_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_7_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_7 = get_a_mask_sub_size & get_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_7_1 = get_a_mask_sub_sub_3_1 | _get_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = s2_req_addr[0]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_8 = get_a_mask_sub_4_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_8 = get_a_mask_size & get_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_8 = get_a_mask_sub_4_1 | _get_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_9 = get_a_mask_sub_4_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_9 = get_a_mask_size & get_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_9 = get_a_mask_sub_4_1 | _get_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_10 = get_a_mask_sub_5_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_10 = get_a_mask_size & get_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_10 = get_a_mask_sub_5_1 | _get_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_11 = get_a_mask_sub_5_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_11 = get_a_mask_size & get_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_11 = get_a_mask_sub_5_1 | _get_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_12 = get_a_mask_sub_6_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_12 = get_a_mask_size & get_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_12 = get_a_mask_sub_6_1 | _get_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_13 = get_a_mask_sub_6_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_13 = get_a_mask_size & get_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_13 = get_a_mask_sub_6_1 | _get_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_14 = get_a_mask_sub_7_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_14 = get_a_mask_size & get_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_14 = get_a_mask_sub_7_1 | _get_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_15 = get_a_mask_sub_7_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_15 = get_a_mask_size & get_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_15 = get_a_mask_sub_7_1 | _get_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_lo = {get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_lo_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_hi = {get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo_lo = {get_a_mask_acc_9, get_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_lo_hi = {get_a_mask_acc_11, get_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_lo = {get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_hi_lo = {get_a_mask_acc_13, get_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi_hi = {get_a_mask_acc_15, get_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_hi = {get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_109 = {s2_req_addr[39:21], s2_req_addr[20:0] ^ 21'h100000}; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_19; // @[Parameters.scala:137:31] assign _putpartial_legal_T_19 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_363; // @[Parameters.scala:137:31] assign _atomics_legal_T_363 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_422; // @[Parameters.scala:137:31] assign _atomics_legal_T_422 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_481; // @[Parameters.scala:137:31] assign _atomics_legal_T_481 = _GEN_109; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_110 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2010000}; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_29; // @[Parameters.scala:137:31] assign _putpartial_legal_T_29 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_309; // @[Parameters.scala:137:31] assign _atomics_legal_T_309 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_368; // @[Parameters.scala:137:31] assign _atomics_legal_T_368 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_427; // @[Parameters.scala:137:31] assign _atomics_legal_T_427 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_486; // @[Parameters.scala:137:31] assign _atomics_legal_T_486 = _GEN_110; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_54 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_55 = _put_legal_T_54 | _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_56 = _put_legal_T_55 | _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_57 = _put_legal_T_56 | _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_58 = _put_legal_T_57 | _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_59 = _put_legal_T_58 | _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 | _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46] wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_70 = _put_legal_T_69 | _put_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26] wire [15:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [15:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_size = put_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_sub_1_2 = put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_sub_nbit = ~put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_sub_0_2 = put_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_sub_acc_T = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_0_1 = _put_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _put_a_mask_sub_sub_sub_acc_T_1 = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_1_1 = _put_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_2_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T_2 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_2_1 = put_a_mask_sub_sub_sub_1_1 | _put_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_3_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_3 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_3_1 = put_a_mask_sub_sub_sub_1_1 | _put_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_4_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_4 = put_a_mask_sub_size & put_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_4_1 = put_a_mask_sub_sub_2_1 | _put_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_5_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_5 = put_a_mask_sub_size & put_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_5_1 = put_a_mask_sub_sub_2_1 | _put_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_6_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_6 = put_a_mask_sub_size & put_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_6_1 = put_a_mask_sub_sub_3_1 | _put_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_7_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_7 = put_a_mask_sub_size & put_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_7_1 = put_a_mask_sub_sub_3_1 | _put_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_8 = put_a_mask_sub_4_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_8 = put_a_mask_size & put_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_8 = put_a_mask_sub_4_1 | _put_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_9 = put_a_mask_sub_4_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_9 = put_a_mask_size & put_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_9 = put_a_mask_sub_4_1 | _put_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_10 = put_a_mask_sub_5_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_10 = put_a_mask_size & put_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_10 = put_a_mask_sub_5_1 | _put_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_11 = put_a_mask_sub_5_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_11 = put_a_mask_size & put_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_11 = put_a_mask_sub_5_1 | _put_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_12 = put_a_mask_sub_6_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_12 = put_a_mask_size & put_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_12 = put_a_mask_sub_6_1 | _put_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_13 = put_a_mask_sub_6_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_13 = put_a_mask_size & put_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_13 = put_a_mask_sub_6_1 | _put_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_14 = put_a_mask_sub_7_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_14 = put_a_mask_size & put_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_14 = put_a_mask_sub_7_1 | _put_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_15 = put_a_mask_sub_7_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_15 = put_a_mask_size & put_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_15 = put_a_mask_sub_7_1 | _put_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_lo = {put_a_mask_lo_lo_hi, put_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_lo_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_hi = {put_a_mask_lo_hi_hi, put_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo_lo = {put_a_mask_acc_9, put_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_lo_hi = {put_a_mask_acc_11, put_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_lo = {put_a_mask_hi_lo_hi, put_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_hi_lo = {put_a_mask_acc_13, put_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi_hi = {put_a_mask_acc_15, put_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_hi = {put_a_mask_hi_hi_hi, put_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _putpartial_legal_T_5 = {1'h0, _putpartial_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_6 = _putpartial_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_7 = _putpartial_legal_T_6; // @[Parameters.scala:137:46] wire _putpartial_legal_T_8 = _putpartial_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_9 = _putpartial_legal_T_8; // @[Parameters.scala:684:54] wire _putpartial_legal_T_69 = _putpartial_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _putpartial_legal_T_15 = {1'h0, _putpartial_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_16 = _putpartial_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_17 = _putpartial_legal_T_16; // @[Parameters.scala:137:46] wire _putpartial_legal_T_18 = _putpartial_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_20 = {1'h0, _putpartial_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_21 = _putpartial_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_22 = _putpartial_legal_T_21; // @[Parameters.scala:137:46] wire _putpartial_legal_T_23 = _putpartial_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_25 = {1'h0, _putpartial_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_26 = _putpartial_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_27 = _putpartial_legal_T_26; // @[Parameters.scala:137:46] wire _putpartial_legal_T_28 = _putpartial_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_30 = {1'h0, _putpartial_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_31 = _putpartial_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_32 = _putpartial_legal_T_31; // @[Parameters.scala:137:46] wire _putpartial_legal_T_33 = _putpartial_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_35 = {1'h0, _putpartial_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_36 = _putpartial_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_37 = _putpartial_legal_T_36; // @[Parameters.scala:137:46] wire _putpartial_legal_T_38 = _putpartial_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_40 = {1'h0, _putpartial_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_41 = _putpartial_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_42 = _putpartial_legal_T_41; // @[Parameters.scala:137:46] wire _putpartial_legal_T_43 = _putpartial_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_45 = {1'h0, _putpartial_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_46 = _putpartial_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_47 = _putpartial_legal_T_46; // @[Parameters.scala:137:46] wire _putpartial_legal_T_48 = _putpartial_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_50 = {1'h0, _putpartial_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_51 = _putpartial_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_52 = _putpartial_legal_T_51; // @[Parameters.scala:137:46] wire _putpartial_legal_T_53 = _putpartial_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_54 = _putpartial_legal_T_18 | _putpartial_legal_T_23; // @[Parameters.scala:685:42] wire _putpartial_legal_T_55 = _putpartial_legal_T_54 | _putpartial_legal_T_28; // @[Parameters.scala:685:42] wire _putpartial_legal_T_56 = _putpartial_legal_T_55 | _putpartial_legal_T_33; // @[Parameters.scala:685:42] wire _putpartial_legal_T_57 = _putpartial_legal_T_56 | _putpartial_legal_T_38; // @[Parameters.scala:685:42] wire _putpartial_legal_T_58 = _putpartial_legal_T_57 | _putpartial_legal_T_43; // @[Parameters.scala:685:42] wire _putpartial_legal_T_59 = _putpartial_legal_T_58 | _putpartial_legal_T_48; // @[Parameters.scala:685:42] wire _putpartial_legal_T_60 = _putpartial_legal_T_59 | _putpartial_legal_T_53; // @[Parameters.scala:685:42] wire _putpartial_legal_T_61 = _putpartial_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _putpartial_legal_T_64 = {1'h0, _putpartial_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_65 = _putpartial_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_66 = _putpartial_legal_T_65; // @[Parameters.scala:137:46] wire _putpartial_legal_T_67 = _putpartial_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_70 = _putpartial_legal_T_69 | _putpartial_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire putpartial_legal = _putpartial_legal_T_70; // @[Parameters.scala:686:26] wire [15:0] putpartial_mask; // @[Edges.scala:500:17] assign putpartial_mask = a_mask[15:0]; // @[Edges.scala:500:17, :508:15] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_111 = {s2_req_addr[39:28], s2_req_addr[27:0] ^ 28'hC000000}; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_255; // @[Parameters.scala:137:31] assign _atomics_legal_T_255 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_314; // @[Parameters.scala:137:31] assign _atomics_legal_T_314 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_373; // @[Parameters.scala:137:31] assign _atomics_legal_T_373 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_432; // @[Parameters.scala:137:31] assign _atomics_legal_T_432 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_491; // @[Parameters.scala:137:31] assign _atomics_legal_T_491 = _GEN_111; // @[Parameters.scala:137:31] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_29 = _atomics_legal_T_8 | _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_30 = _atomics_legal_T_29 | _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_31 = _atomics_legal_T_30 | _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_32 = _atomics_legal_T_31 | _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_33 = _atomics_legal_T_32; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_57 = _atomics_legal_T_33; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_36 = {1'h0, _atomics_legal_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_38 = _atomics_legal_T_37; // @[Parameters.scala:137:46] wire _atomics_legal_T_39 = _atomics_legal_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_46 = {1'h0, _atomics_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_47 = _atomics_legal_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_48 = _atomics_legal_T_47; // @[Parameters.scala:137:46] wire _atomics_legal_T_49 = _atomics_legal_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_51 = {1'h0, _atomics_legal_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_52 = _atomics_legal_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_53 = _atomics_legal_T_52; // @[Parameters.scala:137:46] wire _atomics_legal_T_54 = _atomics_legal_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_55 = _atomics_legal_T_49 | _atomics_legal_T_54; // @[Parameters.scala:685:42] wire _atomics_legal_T_56 = _atomics_legal_T_55; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_58 = _atomics_legal_T_57; // @[Parameters.scala:686:26] wire atomics_legal = _atomics_legal_T_58 | _atomics_legal_T_56; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [15:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size = atomics_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit = ~atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1 = _atomics_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1 = atomics_a_mask_sub_sub_sub_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1 = atomics_a_mask_sub_sub_sub_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size & atomics_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1 = atomics_a_mask_sub_sub_2_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size & atomics_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1 = atomics_a_mask_sub_sub_2_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size & atomics_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1 = atomics_a_mask_sub_sub_3_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size & atomics_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1 = atomics_a_mask_sub_sub_3_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_4_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_4_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_4_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_4_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_5_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_5_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_5_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_5_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_6_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_6_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_6_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_6_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_7_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_7_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_7_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_7_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo = {atomics_a_mask_lo_lo_hi, atomics_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi = {atomics_a_mask_lo_hi_hi, atomics_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo = {atomics_a_mask_hi_lo_hi, atomics_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi = {atomics_a_mask_hi_hi_hi, atomics_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_88 = _atomics_legal_T_67 | _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_89 = _atomics_legal_T_88 | _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_90 = _atomics_legal_T_89 | _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_91 = _atomics_legal_T_90 | _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_92 = _atomics_legal_T_91; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_116 = _atomics_legal_T_92; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_95 = {1'h0, _atomics_legal_T_94}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_96 = _atomics_legal_T_95 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_97 = _atomics_legal_T_96; // @[Parameters.scala:137:46] wire _atomics_legal_T_98 = _atomics_legal_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_105 = {1'h0, _atomics_legal_T_104}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_106 = _atomics_legal_T_105 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_107 = _atomics_legal_T_106; // @[Parameters.scala:137:46] wire _atomics_legal_T_108 = _atomics_legal_T_107 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_110 = {1'h0, _atomics_legal_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_111 = _atomics_legal_T_110 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_112 = _atomics_legal_T_111; // @[Parameters.scala:137:46] wire _atomics_legal_T_113 = _atomics_legal_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_114 = _atomics_legal_T_108 | _atomics_legal_T_113; // @[Parameters.scala:685:42] wire _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_117 = _atomics_legal_T_116; // @[Parameters.scala:686:26] wire atomics_legal_1 = _atomics_legal_T_117 | _atomics_legal_T_115; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [15:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_1 = atomics_a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_1 = atomics_a_mask_sub_sub_2_1_1 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_1 = atomics_a_mask_sub_sub_2_1_1 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_1 = atomics_a_mask_sub_sub_3_1_1 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_1 = atomics_a_mask_sub_sub_3_1_1 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_1 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_1 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_1 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_1 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_1 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_1 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_1 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_1 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_1 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_4_1_1 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_1 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_4_1_1 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_1 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_5_1_1 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_1 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_5_1_1 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_1 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_6_1_1 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_1 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_6_1_1 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_1 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_7_1_1 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_1 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_7_1_1 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_1 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_1 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_lo_lo_hi_1, atomics_a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_1 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_1 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_lo_hi_hi_1, atomics_a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_1 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_1 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_hi_lo_hi_1, atomics_a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_1 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_1 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_hi_hi_hi_1, atomics_a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_126 | _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 | _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 | _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 | _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_175 = _atomics_legal_T_151; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_154 = {1'h0, _atomics_legal_T_153}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_155 = _atomics_legal_T_154 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_156 = _atomics_legal_T_155; // @[Parameters.scala:137:46] wire _atomics_legal_T_157 = _atomics_legal_T_156 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_164 = {1'h0, _atomics_legal_T_163}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_165 = _atomics_legal_T_164 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_166 = _atomics_legal_T_165; // @[Parameters.scala:137:46] wire _atomics_legal_T_167 = _atomics_legal_T_166 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_169 = {1'h0, _atomics_legal_T_168}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_170 = _atomics_legal_T_169 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_171 = _atomics_legal_T_170; // @[Parameters.scala:137:46] wire _atomics_legal_T_172 = _atomics_legal_T_171 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_173 = _atomics_legal_T_167 | _atomics_legal_T_172; // @[Parameters.scala:685:42] wire _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_176 = _atomics_legal_T_175; // @[Parameters.scala:686:26] wire atomics_legal_2 = _atomics_legal_T_176 | _atomics_legal_T_174; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [15:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_2 = atomics_a_mask_sizeOH_2[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_4_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_2 = atomics_a_mask_sub_sub_2_1_2 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_5_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_2 = atomics_a_mask_sub_sub_2_1_2 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_6_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_2 = atomics_a_mask_sub_sub_3_1_2 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_7_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_2 = atomics_a_mask_sub_sub_3_1_2 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_2 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_2 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_2 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_2 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_2 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_2 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_2 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_2 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_2 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_4_1_2 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_2 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_4_1_2 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_2 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_5_1_2 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_2 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_5_1_2 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_2 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_6_1_2 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_2 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_6_1_2 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_2 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_7_1_2 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_2 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_7_1_2 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_2 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_2 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_lo_lo_hi_2, atomics_a_mask_lo_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_2 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_2 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_lo_hi_hi_2, atomics_a_mask_lo_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_2 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_2 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_hi_lo_hi_2, atomics_a_mask_hi_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_2 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_2 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_hi_hi_hi_2, atomics_a_mask_hi_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_202 = {1'h0, _atomics_legal_T_201}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_203 = _atomics_legal_T_202 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_204 = _atomics_legal_T_203; // @[Parameters.scala:137:46] wire _atomics_legal_T_205 = _atomics_legal_T_204 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_206 = _atomics_legal_T_185 | _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206 | _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_208 = _atomics_legal_T_207 | _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_209 = _atomics_legal_T_208 | _atomics_legal_T_205; // @[Parameters.scala:685:42] wire _atomics_legal_T_210 = _atomics_legal_T_209; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_234 = _atomics_legal_T_210; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_213 = {1'h0, _atomics_legal_T_212}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_214 = _atomics_legal_T_213 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_215 = _atomics_legal_T_214; // @[Parameters.scala:137:46] wire _atomics_legal_T_216 = _atomics_legal_T_215 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_223 = {1'h0, _atomics_legal_T_222}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_224 = _atomics_legal_T_223 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_225 = _atomics_legal_T_224; // @[Parameters.scala:137:46] wire _atomics_legal_T_226 = _atomics_legal_T_225 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_228 = {1'h0, _atomics_legal_T_227}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_229 = _atomics_legal_T_228 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_230 = _atomics_legal_T_229; // @[Parameters.scala:137:46] wire _atomics_legal_T_231 = _atomics_legal_T_230 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_232 = _atomics_legal_T_226 | _atomics_legal_T_231; // @[Parameters.scala:685:42] wire _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_235 = _atomics_legal_T_234; // @[Parameters.scala:686:26] wire atomics_legal_3 = _atomics_legal_T_235 | _atomics_legal_T_233; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [15:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_3 = atomics_a_mask_sizeOH_3[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_4_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_3 = atomics_a_mask_sub_sub_2_1_3 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_5_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_3 = atomics_a_mask_sub_sub_2_1_3 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_6_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_3 = atomics_a_mask_sub_sub_3_1_3 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_7_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_3 = atomics_a_mask_sub_sub_3_1_3 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_3 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_3 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_3 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_3 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_3 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_3 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_3 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_3 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_3 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_4_1_3 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_3 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_4_1_3 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_3 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_5_1_3 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_3 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_5_1_3 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_3 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_6_1_3 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_3 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_6_1_3 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_3 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_7_1_3 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_3 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_7_1_3 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_3 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_3 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_lo_lo_hi_3, atomics_a_mask_lo_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_3 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_3 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_lo_hi_hi_3, atomics_a_mask_lo_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_3 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_3 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_hi_lo_hi_3, atomics_a_mask_hi_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_3 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_3 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_hi_hi_hi_3, atomics_a_mask_hi_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_256 = {1'h0, _atomics_legal_T_255}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_257 = _atomics_legal_T_256 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_258 = _atomics_legal_T_257; // @[Parameters.scala:137:46] wire _atomics_legal_T_259 = _atomics_legal_T_258 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_261 = {1'h0, _atomics_legal_T_260}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_262 = _atomics_legal_T_261 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_263 = _atomics_legal_T_262; // @[Parameters.scala:137:46] wire _atomics_legal_T_264 = _atomics_legal_T_263 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_265 = _atomics_legal_T_244 | _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_266 = _atomics_legal_T_265 | _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_267 = _atomics_legal_T_266 | _atomics_legal_T_259; // @[Parameters.scala:685:42] wire _atomics_legal_T_268 = _atomics_legal_T_267 | _atomics_legal_T_264; // @[Parameters.scala:685:42] wire _atomics_legal_T_269 = _atomics_legal_T_268; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_293 = _atomics_legal_T_269; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_272 = {1'h0, _atomics_legal_T_271}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_273 = _atomics_legal_T_272 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_274 = _atomics_legal_T_273; // @[Parameters.scala:137:46] wire _atomics_legal_T_275 = _atomics_legal_T_274 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_282 = {1'h0, _atomics_legal_T_281}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_283 = _atomics_legal_T_282 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_284 = _atomics_legal_T_283; // @[Parameters.scala:137:46] wire _atomics_legal_T_285 = _atomics_legal_T_284 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_287 = {1'h0, _atomics_legal_T_286}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_288 = _atomics_legal_T_287 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_289 = _atomics_legal_T_288; // @[Parameters.scala:137:46] wire _atomics_legal_T_290 = _atomics_legal_T_289 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_291 = _atomics_legal_T_285 | _atomics_legal_T_290; // @[Parameters.scala:685:42] wire _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_294 = _atomics_legal_T_293; // @[Parameters.scala:686:26] wire atomics_legal_4 = _atomics_legal_T_294 | _atomics_legal_T_292; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [15:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_4 = atomics_a_mask_sizeOH_4[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_18 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 | _atomics_a_mask_sub_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_19 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 | _atomics_a_mask_sub_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_36 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_4_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_4 = atomics_a_mask_sub_sub_2_1_4 | _atomics_a_mask_sub_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_37 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_5_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_4 = atomics_a_mask_sub_sub_2_1_4 | _atomics_a_mask_sub_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_38 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_6_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_4 = atomics_a_mask_sub_sub_3_1_4 | _atomics_a_mask_sub_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_39 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_7_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_4 = atomics_a_mask_sub_sub_3_1_4 | _atomics_a_mask_sub_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_4 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_4 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_4 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_4 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_4 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_4 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_4 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_4 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_72 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_72 = atomics_a_mask_size_4 & atomics_a_mask_eq_72; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_72 = atomics_a_mask_sub_4_1_4 | _atomics_a_mask_acc_T_72; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_73 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_73 = atomics_a_mask_size_4 & atomics_a_mask_eq_73; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_73 = atomics_a_mask_sub_4_1_4 | _atomics_a_mask_acc_T_73; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_74 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_74 = atomics_a_mask_size_4 & atomics_a_mask_eq_74; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_74 = atomics_a_mask_sub_5_1_4 | _atomics_a_mask_acc_T_74; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_75 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_75 = atomics_a_mask_size_4 & atomics_a_mask_eq_75; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_75 = atomics_a_mask_sub_5_1_4 | _atomics_a_mask_acc_T_75; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_76 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_76 = atomics_a_mask_size_4 & atomics_a_mask_eq_76; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_76 = atomics_a_mask_sub_6_1_4 | _atomics_a_mask_acc_T_76; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_77 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_77 = atomics_a_mask_size_4 & atomics_a_mask_eq_77; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_77 = atomics_a_mask_sub_6_1_4 | _atomics_a_mask_acc_T_77; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_78 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_78 = atomics_a_mask_size_4 & atomics_a_mask_eq_78; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_78 = atomics_a_mask_sub_7_1_4 | _atomics_a_mask_acc_T_78; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_79 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_79 = atomics_a_mask_size_4 & atomics_a_mask_eq_79; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_79 = atomics_a_mask_sub_7_1_4 | _atomics_a_mask_acc_T_79; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_4 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_4 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_lo_lo_hi_4, atomics_a_mask_lo_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_4 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_4 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_lo_hi_hi_4, atomics_a_mask_lo_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_4 = {atomics_a_mask_acc_73, atomics_a_mask_acc_72}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_4 = {atomics_a_mask_acc_75, atomics_a_mask_acc_74}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_hi_lo_hi_4, atomics_a_mask_hi_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_4 = {atomics_a_mask_acc_77, atomics_a_mask_acc_76}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_4 = {atomics_a_mask_acc_79, atomics_a_mask_acc_78}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_hi_hi_hi_4, atomics_a_mask_hi_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_310 = {1'h0, _atomics_legal_T_309}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_311 = _atomics_legal_T_310 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_312 = _atomics_legal_T_311; // @[Parameters.scala:137:46] wire _atomics_legal_T_313 = _atomics_legal_T_312 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_315 = {1'h0, _atomics_legal_T_314}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_316 = _atomics_legal_T_315 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_317 = _atomics_legal_T_316; // @[Parameters.scala:137:46] wire _atomics_legal_T_318 = _atomics_legal_T_317 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_320 = {1'h0, _atomics_legal_T_319}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_321 = _atomics_legal_T_320 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_322 = _atomics_legal_T_321; // @[Parameters.scala:137:46] wire _atomics_legal_T_323 = _atomics_legal_T_322 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_324 = _atomics_legal_T_303 | _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_325 = _atomics_legal_T_324 | _atomics_legal_T_313; // @[Parameters.scala:685:42] wire _atomics_legal_T_326 = _atomics_legal_T_325 | _atomics_legal_T_318; // @[Parameters.scala:685:42] wire _atomics_legal_T_327 = _atomics_legal_T_326 | _atomics_legal_T_323; // @[Parameters.scala:685:42] wire _atomics_legal_T_328 = _atomics_legal_T_327; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_352 = _atomics_legal_T_328; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_331 = {1'h0, _atomics_legal_T_330}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_332 = _atomics_legal_T_331 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_333 = _atomics_legal_T_332; // @[Parameters.scala:137:46] wire _atomics_legal_T_334 = _atomics_legal_T_333 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_341 = {1'h0, _atomics_legal_T_340}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_342 = _atomics_legal_T_341 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_343 = _atomics_legal_T_342; // @[Parameters.scala:137:46] wire _atomics_legal_T_344 = _atomics_legal_T_343 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_346 = {1'h0, _atomics_legal_T_345}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_347 = _atomics_legal_T_346 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_348 = _atomics_legal_T_347; // @[Parameters.scala:137:46] wire _atomics_legal_T_349 = _atomics_legal_T_348 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_350 = _atomics_legal_T_344 | _atomics_legal_T_349; // @[Parameters.scala:685:42] wire _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_353 = _atomics_legal_T_352; // @[Parameters.scala:686:26] wire atomics_legal_5 = _atomics_legal_T_353 | _atomics_legal_T_351; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [15:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_5 = atomics_a_mask_sizeOH_5[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_20 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_21 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_22 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 | _atomics_a_mask_sub_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_23 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 | _atomics_a_mask_sub_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_40 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_41 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_42 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_43 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_44 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_4_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_5 = atomics_a_mask_sub_sub_2_1_5 | _atomics_a_mask_sub_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_45 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_5_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_5 = atomics_a_mask_sub_sub_2_1_5 | _atomics_a_mask_sub_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_46 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_6_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_5 = atomics_a_mask_sub_sub_3_1_5 | _atomics_a_mask_sub_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_47 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_7_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_5 = atomics_a_mask_sub_sub_3_1_5 | _atomics_a_mask_sub_acc_T_47; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_80 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_80 = atomics_a_mask_size_5 & atomics_a_mask_eq_80; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_80 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_80; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_81 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_81 = atomics_a_mask_size_5 & atomics_a_mask_eq_81; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_81 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_81; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_82 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_82 = atomics_a_mask_size_5 & atomics_a_mask_eq_82; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_82 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_82; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_83 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_83 = atomics_a_mask_size_5 & atomics_a_mask_eq_83; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_83 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_83; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_84 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_84 = atomics_a_mask_size_5 & atomics_a_mask_eq_84; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_84 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_84; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_85 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_85 = atomics_a_mask_size_5 & atomics_a_mask_eq_85; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_85 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_85; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_86 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_86 = atomics_a_mask_size_5 & atomics_a_mask_eq_86; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_86 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_86; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_87 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_87 = atomics_a_mask_size_5 & atomics_a_mask_eq_87; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_87 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_87; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_88 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_88 = atomics_a_mask_size_5 & atomics_a_mask_eq_88; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_88 = atomics_a_mask_sub_4_1_5 | _atomics_a_mask_acc_T_88; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_89 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_89 = atomics_a_mask_size_5 & atomics_a_mask_eq_89; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_89 = atomics_a_mask_sub_4_1_5 | _atomics_a_mask_acc_T_89; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_90 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_90 = atomics_a_mask_size_5 & atomics_a_mask_eq_90; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_90 = atomics_a_mask_sub_5_1_5 | _atomics_a_mask_acc_T_90; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_91 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_91 = atomics_a_mask_size_5 & atomics_a_mask_eq_91; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_91 = atomics_a_mask_sub_5_1_5 | _atomics_a_mask_acc_T_91; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_92 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_92 = atomics_a_mask_size_5 & atomics_a_mask_eq_92; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_92 = atomics_a_mask_sub_6_1_5 | _atomics_a_mask_acc_T_92; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_93 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_93 = atomics_a_mask_size_5 & atomics_a_mask_eq_93; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_93 = atomics_a_mask_sub_6_1_5 | _atomics_a_mask_acc_T_93; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_94 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_94 = atomics_a_mask_size_5 & atomics_a_mask_eq_94; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_94 = atomics_a_mask_sub_7_1_5 | _atomics_a_mask_acc_T_94; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_95 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_95 = atomics_a_mask_size_5 & atomics_a_mask_eq_95; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_95 = atomics_a_mask_sub_7_1_5 | _atomics_a_mask_acc_T_95; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_5 = {atomics_a_mask_acc_81, atomics_a_mask_acc_80}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_5 = {atomics_a_mask_acc_83, atomics_a_mask_acc_82}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_lo_lo_hi_5, atomics_a_mask_lo_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_5 = {atomics_a_mask_acc_85, atomics_a_mask_acc_84}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_5 = {atomics_a_mask_acc_87, atomics_a_mask_acc_86}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_lo_hi_hi_5, atomics_a_mask_lo_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_5 = {atomics_a_mask_acc_89, atomics_a_mask_acc_88}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_5 = {atomics_a_mask_acc_91, atomics_a_mask_acc_90}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_hi_lo_hi_5, atomics_a_mask_hi_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_5 = {atomics_a_mask_acc_93, atomics_a_mask_acc_92}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_5 = {atomics_a_mask_acc_95, atomics_a_mask_acc_94}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_hi_hi_hi_5, atomics_a_mask_hi_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_364 = {1'h0, _atomics_legal_T_363}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_365 = _atomics_legal_T_364 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_366 = _atomics_legal_T_365; // @[Parameters.scala:137:46] wire _atomics_legal_T_367 = _atomics_legal_T_366 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_369 = {1'h0, _atomics_legal_T_368}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_370 = _atomics_legal_T_369 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_371 = _atomics_legal_T_370; // @[Parameters.scala:137:46] wire _atomics_legal_T_372 = _atomics_legal_T_371 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_374 = {1'h0, _atomics_legal_T_373}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_375 = _atomics_legal_T_374 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_376 = _atomics_legal_T_375; // @[Parameters.scala:137:46] wire _atomics_legal_T_377 = _atomics_legal_T_376 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_379 = {1'h0, _atomics_legal_T_378}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_380 = _atomics_legal_T_379 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_381 = _atomics_legal_T_380; // @[Parameters.scala:137:46] wire _atomics_legal_T_382 = _atomics_legal_T_381 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_383 = _atomics_legal_T_362 | _atomics_legal_T_367; // @[Parameters.scala:685:42] wire _atomics_legal_T_384 = _atomics_legal_T_383 | _atomics_legal_T_372; // @[Parameters.scala:685:42] wire _atomics_legal_T_385 = _atomics_legal_T_384 | _atomics_legal_T_377; // @[Parameters.scala:685:42] wire _atomics_legal_T_386 = _atomics_legal_T_385 | _atomics_legal_T_382; // @[Parameters.scala:685:42] wire _atomics_legal_T_387 = _atomics_legal_T_386; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_411 = _atomics_legal_T_387; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_390 = {1'h0, _atomics_legal_T_389}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_391 = _atomics_legal_T_390 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_392 = _atomics_legal_T_391; // @[Parameters.scala:137:46] wire _atomics_legal_T_393 = _atomics_legal_T_392 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_400 = {1'h0, _atomics_legal_T_399}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_401 = _atomics_legal_T_400 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_402 = _atomics_legal_T_401; // @[Parameters.scala:137:46] wire _atomics_legal_T_403 = _atomics_legal_T_402 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_405 = {1'h0, _atomics_legal_T_404}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_406 = _atomics_legal_T_405 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_407 = _atomics_legal_T_406; // @[Parameters.scala:137:46] wire _atomics_legal_T_408 = _atomics_legal_T_407 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_409 = _atomics_legal_T_403 | _atomics_legal_T_408; // @[Parameters.scala:685:42] wire _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_412 = _atomics_legal_T_411; // @[Parameters.scala:686:26] wire atomics_legal_6 = _atomics_legal_T_412 | _atomics_legal_T_410; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [15:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_6 = atomics_a_mask_sizeOH_6[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_24 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_25 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_26 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 | _atomics_a_mask_sub_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_27 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 | _atomics_a_mask_sub_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_48 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_49 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_50 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_51 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_52 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_4_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_6 = atomics_a_mask_sub_sub_2_1_6 | _atomics_a_mask_sub_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_53 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_5_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_6 = atomics_a_mask_sub_sub_2_1_6 | _atomics_a_mask_sub_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_54 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_6_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_6 = atomics_a_mask_sub_sub_3_1_6 | _atomics_a_mask_sub_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_55 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_7_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_6 = atomics_a_mask_sub_sub_3_1_6 | _atomics_a_mask_sub_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_96 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_96 = atomics_a_mask_size_6 & atomics_a_mask_eq_96; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_96 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_96; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_97 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_97 = atomics_a_mask_size_6 & atomics_a_mask_eq_97; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_97 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_97; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_98 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_98 = atomics_a_mask_size_6 & atomics_a_mask_eq_98; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_98 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_98; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_99 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_99 = atomics_a_mask_size_6 & atomics_a_mask_eq_99; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_99 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_99; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_100 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_100 = atomics_a_mask_size_6 & atomics_a_mask_eq_100; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_100 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_100; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_101 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_101 = atomics_a_mask_size_6 & atomics_a_mask_eq_101; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_101 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_101; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_102 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_102 = atomics_a_mask_size_6 & atomics_a_mask_eq_102; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_102 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_102; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_103 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_103 = atomics_a_mask_size_6 & atomics_a_mask_eq_103; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_103 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_103; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_104 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_104 = atomics_a_mask_size_6 & atomics_a_mask_eq_104; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_104 = atomics_a_mask_sub_4_1_6 | _atomics_a_mask_acc_T_104; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_105 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_105 = atomics_a_mask_size_6 & atomics_a_mask_eq_105; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_105 = atomics_a_mask_sub_4_1_6 | _atomics_a_mask_acc_T_105; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_106 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_106 = atomics_a_mask_size_6 & atomics_a_mask_eq_106; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_106 = atomics_a_mask_sub_5_1_6 | _atomics_a_mask_acc_T_106; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_107 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_107 = atomics_a_mask_size_6 & atomics_a_mask_eq_107; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_107 = atomics_a_mask_sub_5_1_6 | _atomics_a_mask_acc_T_107; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_108 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_108 = atomics_a_mask_size_6 & atomics_a_mask_eq_108; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_108 = atomics_a_mask_sub_6_1_6 | _atomics_a_mask_acc_T_108; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_109 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_109 = atomics_a_mask_size_6 & atomics_a_mask_eq_109; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_109 = atomics_a_mask_sub_6_1_6 | _atomics_a_mask_acc_T_109; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_110 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_110 = atomics_a_mask_size_6 & atomics_a_mask_eq_110; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_110 = atomics_a_mask_sub_7_1_6 | _atomics_a_mask_acc_T_110; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_111 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_111 = atomics_a_mask_size_6 & atomics_a_mask_eq_111; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_111 = atomics_a_mask_sub_7_1_6 | _atomics_a_mask_acc_T_111; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_6 = {atomics_a_mask_acc_97, atomics_a_mask_acc_96}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_6 = {atomics_a_mask_acc_99, atomics_a_mask_acc_98}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_lo_lo_hi_6, atomics_a_mask_lo_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_6 = {atomics_a_mask_acc_101, atomics_a_mask_acc_100}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_6 = {atomics_a_mask_acc_103, atomics_a_mask_acc_102}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_lo_hi_hi_6, atomics_a_mask_lo_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_6 = {atomics_a_mask_acc_105, atomics_a_mask_acc_104}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_6 = {atomics_a_mask_acc_107, atomics_a_mask_acc_106}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_hi_lo_hi_6, atomics_a_mask_hi_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_6 = {atomics_a_mask_acc_109, atomics_a_mask_acc_108}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_6 = {atomics_a_mask_acc_111, atomics_a_mask_acc_110}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_hi_hi_hi_6, atomics_a_mask_hi_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_418 = {1'h0, _atomics_legal_T_417}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_419 = _atomics_legal_T_418 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_420 = _atomics_legal_T_419; // @[Parameters.scala:137:46] wire _atomics_legal_T_421 = _atomics_legal_T_420 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_423 = {1'h0, _atomics_legal_T_422}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_424 = _atomics_legal_T_423 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_425 = _atomics_legal_T_424; // @[Parameters.scala:137:46] wire _atomics_legal_T_426 = _atomics_legal_T_425 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_428 = {1'h0, _atomics_legal_T_427}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_429 = _atomics_legal_T_428 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_430 = _atomics_legal_T_429; // @[Parameters.scala:137:46] wire _atomics_legal_T_431 = _atomics_legal_T_430 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_433 = {1'h0, _atomics_legal_T_432}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_434 = _atomics_legal_T_433 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_435 = _atomics_legal_T_434; // @[Parameters.scala:137:46] wire _atomics_legal_T_436 = _atomics_legal_T_435 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_438 = {1'h0, _atomics_legal_T_437}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_440 = _atomics_legal_T_439; // @[Parameters.scala:137:46] wire _atomics_legal_T_441 = _atomics_legal_T_440 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_442 = _atomics_legal_T_421 | _atomics_legal_T_426; // @[Parameters.scala:685:42] wire _atomics_legal_T_443 = _atomics_legal_T_442 | _atomics_legal_T_431; // @[Parameters.scala:685:42] wire _atomics_legal_T_444 = _atomics_legal_T_443 | _atomics_legal_T_436; // @[Parameters.scala:685:42] wire _atomics_legal_T_445 = _atomics_legal_T_444 | _atomics_legal_T_441; // @[Parameters.scala:685:42] wire _atomics_legal_T_446 = _atomics_legal_T_445; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_470 = _atomics_legal_T_446; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_449 = {1'h0, _atomics_legal_T_448}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_450 = _atomics_legal_T_449 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_451 = _atomics_legal_T_450; // @[Parameters.scala:137:46] wire _atomics_legal_T_452 = _atomics_legal_T_451 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_459 = {1'h0, _atomics_legal_T_458}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_460 = _atomics_legal_T_459 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_461 = _atomics_legal_T_460; // @[Parameters.scala:137:46] wire _atomics_legal_T_462 = _atomics_legal_T_461 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_464 = {1'h0, _atomics_legal_T_463}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_465 = _atomics_legal_T_464 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_466 = _atomics_legal_T_465; // @[Parameters.scala:137:46] wire _atomics_legal_T_467 = _atomics_legal_T_466 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_468 = _atomics_legal_T_462 | _atomics_legal_T_467; // @[Parameters.scala:685:42] wire _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_471 = _atomics_legal_T_470; // @[Parameters.scala:686:26] wire atomics_legal_7 = _atomics_legal_T_471 | _atomics_legal_T_469; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [15:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_7 = atomics_a_mask_sizeOH_7[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_28 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_29 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_30 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 | _atomics_a_mask_sub_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_31 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 | _atomics_a_mask_sub_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_56 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_57 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_58 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_59 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_60 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_4_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_7 = atomics_a_mask_sub_sub_2_1_7 | _atomics_a_mask_sub_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_61 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_5_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_7 = atomics_a_mask_sub_sub_2_1_7 | _atomics_a_mask_sub_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_62 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_6_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_7 = atomics_a_mask_sub_sub_3_1_7 | _atomics_a_mask_sub_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_63 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_7_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_7 = atomics_a_mask_sub_sub_3_1_7 | _atomics_a_mask_sub_acc_T_63; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_112 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_112 = atomics_a_mask_size_7 & atomics_a_mask_eq_112; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_112 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_112; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_113 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_113 = atomics_a_mask_size_7 & atomics_a_mask_eq_113; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_113 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_113; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_114 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_114 = atomics_a_mask_size_7 & atomics_a_mask_eq_114; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_114 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_114; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_115 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_115 = atomics_a_mask_size_7 & atomics_a_mask_eq_115; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_115 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_115; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_116 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_116 = atomics_a_mask_size_7 & atomics_a_mask_eq_116; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_116 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_116; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_117 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_117 = atomics_a_mask_size_7 & atomics_a_mask_eq_117; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_117 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_117; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_118 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_118 = atomics_a_mask_size_7 & atomics_a_mask_eq_118; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_118 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_118; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_119 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_119 = atomics_a_mask_size_7 & atomics_a_mask_eq_119; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_119 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_119; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_120 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_120 = atomics_a_mask_size_7 & atomics_a_mask_eq_120; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_120 = atomics_a_mask_sub_4_1_7 | _atomics_a_mask_acc_T_120; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_121 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_121 = atomics_a_mask_size_7 & atomics_a_mask_eq_121; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_121 = atomics_a_mask_sub_4_1_7 | _atomics_a_mask_acc_T_121; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_122 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_122 = atomics_a_mask_size_7 & atomics_a_mask_eq_122; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_122 = atomics_a_mask_sub_5_1_7 | _atomics_a_mask_acc_T_122; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_123 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_123 = atomics_a_mask_size_7 & atomics_a_mask_eq_123; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_123 = atomics_a_mask_sub_5_1_7 | _atomics_a_mask_acc_T_123; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_124 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_124 = atomics_a_mask_size_7 & atomics_a_mask_eq_124; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_124 = atomics_a_mask_sub_6_1_7 | _atomics_a_mask_acc_T_124; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_125 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_125 = atomics_a_mask_size_7 & atomics_a_mask_eq_125; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_125 = atomics_a_mask_sub_6_1_7 | _atomics_a_mask_acc_T_125; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_126 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_126 = atomics_a_mask_size_7 & atomics_a_mask_eq_126; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_126 = atomics_a_mask_sub_7_1_7 | _atomics_a_mask_acc_T_126; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_127 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_127 = atomics_a_mask_size_7 & atomics_a_mask_eq_127; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_127 = atomics_a_mask_sub_7_1_7 | _atomics_a_mask_acc_T_127; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_7 = {atomics_a_mask_acc_113, atomics_a_mask_acc_112}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_7 = {atomics_a_mask_acc_115, atomics_a_mask_acc_114}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_lo_lo_hi_7, atomics_a_mask_lo_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_7 = {atomics_a_mask_acc_117, atomics_a_mask_acc_116}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_7 = {atomics_a_mask_acc_119, atomics_a_mask_acc_118}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_lo_hi_hi_7, atomics_a_mask_lo_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_7 = {atomics_a_mask_acc_121, atomics_a_mask_acc_120}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_7 = {atomics_a_mask_acc_123, atomics_a_mask_acc_122}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_hi_lo_hi_7, atomics_a_mask_hi_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_7 = {atomics_a_mask_acc_125, atomics_a_mask_acc_124}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_7 = {atomics_a_mask_acc_127, atomics_a_mask_acc_126}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_hi_hi_hi_7, atomics_a_mask_hi_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_477 = {1'h0, _atomics_legal_T_476}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_478 = _atomics_legal_T_477 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_479 = _atomics_legal_T_478; // @[Parameters.scala:137:46] wire _atomics_legal_T_480 = _atomics_legal_T_479 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_482 = {1'h0, _atomics_legal_T_481}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_483 = _atomics_legal_T_482 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_484 = _atomics_legal_T_483; // @[Parameters.scala:137:46] wire _atomics_legal_T_485 = _atomics_legal_T_484 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_487 = {1'h0, _atomics_legal_T_486}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_488 = _atomics_legal_T_487 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_489 = _atomics_legal_T_488; // @[Parameters.scala:137:46] wire _atomics_legal_T_490 = _atomics_legal_T_489 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_492 = {1'h0, _atomics_legal_T_491}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_493 = _atomics_legal_T_492 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_494 = _atomics_legal_T_493; // @[Parameters.scala:137:46] wire _atomics_legal_T_495 = _atomics_legal_T_494 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_497 = {1'h0, _atomics_legal_T_496}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_498 = _atomics_legal_T_497 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_499 = _atomics_legal_T_498; // @[Parameters.scala:137:46] wire _atomics_legal_T_500 = _atomics_legal_T_499 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_501 = _atomics_legal_T_480 | _atomics_legal_T_485; // @[Parameters.scala:685:42] wire _atomics_legal_T_502 = _atomics_legal_T_501 | _atomics_legal_T_490; // @[Parameters.scala:685:42] wire _atomics_legal_T_503 = _atomics_legal_T_502 | _atomics_legal_T_495; // @[Parameters.scala:685:42] wire _atomics_legal_T_504 = _atomics_legal_T_503 | _atomics_legal_T_500; // @[Parameters.scala:685:42] wire _atomics_legal_T_505 = _atomics_legal_T_504; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_529 = _atomics_legal_T_505; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_508 = {1'h0, _atomics_legal_T_507}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_509 = _atomics_legal_T_508 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_510 = _atomics_legal_T_509; // @[Parameters.scala:137:46] wire _atomics_legal_T_511 = _atomics_legal_T_510 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_518 = {1'h0, _atomics_legal_T_517}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_519 = _atomics_legal_T_518 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_520 = _atomics_legal_T_519; // @[Parameters.scala:137:46] wire _atomics_legal_T_521 = _atomics_legal_T_520 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_523 = {1'h0, _atomics_legal_T_522}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_524 = _atomics_legal_T_523 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_525 = _atomics_legal_T_524; // @[Parameters.scala:137:46] wire _atomics_legal_T_526 = _atomics_legal_T_525 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_527 = _atomics_legal_T_521 | _atomics_legal_T_526; // @[Parameters.scala:685:42] wire _atomics_legal_T_528 = _atomics_legal_T_527; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_530 = _atomics_legal_T_529; // @[Parameters.scala:686:26] wire atomics_legal_8 = _atomics_legal_T_530 | _atomics_legal_T_528; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [15:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_8 = atomics_a_mask_sizeOH_8[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_32 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_33 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_34 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 | _atomics_a_mask_sub_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_35 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 | _atomics_a_mask_sub_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_64 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_65 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_66 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_67 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_68 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_4_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_8 = atomics_a_mask_sub_sub_2_1_8 | _atomics_a_mask_sub_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_69 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_5_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_8 = atomics_a_mask_sub_sub_2_1_8 | _atomics_a_mask_sub_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_70 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_6_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_8 = atomics_a_mask_sub_sub_3_1_8 | _atomics_a_mask_sub_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_71 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_7_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_8 = atomics_a_mask_sub_sub_3_1_8 | _atomics_a_mask_sub_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_128 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_128 = atomics_a_mask_size_8 & atomics_a_mask_eq_128; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_128 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_128; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_129 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_129 = atomics_a_mask_size_8 & atomics_a_mask_eq_129; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_129 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_129; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_130 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_130 = atomics_a_mask_size_8 & atomics_a_mask_eq_130; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_130 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_130; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_131 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_131 = atomics_a_mask_size_8 & atomics_a_mask_eq_131; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_131 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_131; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_132 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_132 = atomics_a_mask_size_8 & atomics_a_mask_eq_132; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_132 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_132; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_133 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_133 = atomics_a_mask_size_8 & atomics_a_mask_eq_133; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_133 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_133; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_134 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_134 = atomics_a_mask_size_8 & atomics_a_mask_eq_134; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_134 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_134; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_135 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_135 = atomics_a_mask_size_8 & atomics_a_mask_eq_135; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_135 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_135; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_136 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_136 = atomics_a_mask_size_8 & atomics_a_mask_eq_136; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_136 = atomics_a_mask_sub_4_1_8 | _atomics_a_mask_acc_T_136; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_137 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_137 = atomics_a_mask_size_8 & atomics_a_mask_eq_137; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_137 = atomics_a_mask_sub_4_1_8 | _atomics_a_mask_acc_T_137; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_138 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_138 = atomics_a_mask_size_8 & atomics_a_mask_eq_138; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_138 = atomics_a_mask_sub_5_1_8 | _atomics_a_mask_acc_T_138; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_139 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_139 = atomics_a_mask_size_8 & atomics_a_mask_eq_139; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_139 = atomics_a_mask_sub_5_1_8 | _atomics_a_mask_acc_T_139; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_140 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_140 = atomics_a_mask_size_8 & atomics_a_mask_eq_140; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_140 = atomics_a_mask_sub_6_1_8 | _atomics_a_mask_acc_T_140; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_141 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_141 = atomics_a_mask_size_8 & atomics_a_mask_eq_141; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_141 = atomics_a_mask_sub_6_1_8 | _atomics_a_mask_acc_T_141; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_142 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_142 = atomics_a_mask_size_8 & atomics_a_mask_eq_142; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_142 = atomics_a_mask_sub_7_1_8 | _atomics_a_mask_acc_T_142; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_143 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_143 = atomics_a_mask_size_8 & atomics_a_mask_eq_143; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_143 = atomics_a_mask_sub_7_1_8 | _atomics_a_mask_acc_T_143; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_8 = {atomics_a_mask_acc_129, atomics_a_mask_acc_128}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_8 = {atomics_a_mask_acc_131, atomics_a_mask_acc_130}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_lo_lo_hi_8, atomics_a_mask_lo_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_8 = {atomics_a_mask_acc_133, atomics_a_mask_acc_132}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_8 = {atomics_a_mask_acc_135, atomics_a_mask_acc_134}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_lo_hi_hi_8, atomics_a_mask_lo_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_8 = {atomics_a_mask_acc_137, atomics_a_mask_acc_136}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_8 = {atomics_a_mask_acc_139, atomics_a_mask_acc_138}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_hi_lo_hi_8, atomics_a_mask_hi_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_8 = {atomics_a_mask_acc_141, atomics_a_mask_acc_140}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_8 = {atomics_a_mask_acc_143, atomics_a_mask_acc_142}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_hi_hi_hi_8, atomics_a_mask_hi_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [2:0] _GEN_112 = _atomics_T ? 3'h3 : 3'h0; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_opcode; // @[DCache.scala:587:81] assign _atomics_T_1_opcode = _GEN_112; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_param; // @[DCache.scala:587:81] assign _atomics_T_1_param = _GEN_112; // @[DCache.scala:587:81] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire _atomics_T_1_source = _atomics_T & atomics_a_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [15:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 16'h0; // @[Edges.scala:534:17] wire [127:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 128'h0; // @[Edges.scala:534:17] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire _atomics_T_3_source = _atomics_T_2 ? atomics_a_1_source : _atomics_T_1_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire _atomics_T_5_source = _atomics_T_4 ? atomics_a_2_source : _atomics_T_3_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire _atomics_T_7_source = _atomics_T_6 ? atomics_a_3_source : _atomics_T_5_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire _atomics_T_9_source = _atomics_T_8 ? atomics_a_4_source : _atomics_T_7_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire _atomics_T_11_source = _atomics_T_10 ? atomics_a_5_source : _atomics_T_9_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire _atomics_T_13_source = _atomics_T_12 ? atomics_a_6_source : _atomics_T_11_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire _atomics_T_15_source = _atomics_T_14 ? atomics_a_7_source : _atomics_T_13_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[DCache.scala:587:81] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[DCache.scala:587:81] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire atomics_source = _atomics_T_16 ? atomics_a_8_source : _atomics_T_15_source; // @[Edges.scala:517:17] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [15:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [127:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17] wire [39:0] _tl_out_a_valid_T_1 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ release_ack_addr}; // @[DCache.scala:227:29, :339:19, :606:43] wire [14:0] _tl_out_a_valid_T_2 = _tl_out_a_valid_T_1[20:6]; // @[DCache.scala:606:{43,62}] wire _tl_out_a_valid_T_3 = _tl_out_a_valid_T_2 == 15'h0; // @[DCache.scala:582:29, :606:{62,118}] wire _tl_out_a_valid_T_4 = release_ack_wait & _tl_out_a_valid_T_3; // @[DCache.scala:226:33, :606:{27,118}] wire _tl_out_a_valid_T_5 = ~_tl_out_a_valid_T_4; // @[DCache.scala:606:{8,27}] wire _tl_out_a_valid_T_6 = s2_valid_cached_miss & _tl_out_a_valid_T_5; // @[DCache.scala:425:60, :605:29, :606:8] wire _tl_out_a_valid_T_7 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47] wire _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[Misc.scala:38:9] wire _tl_out_a_valid_T_11 = _tl_out_a_valid_T_10; // @[DCache.scala:607:{88,91}] wire _tl_out_a_valid_T_12 = _tl_out_a_valid_T_6 & _tl_out_a_valid_T_11; // @[DCache.scala:605:29, :606:127, :607:88] wire _tl_out_a_valid_T_13 = s2_valid_uncached_pending | _tl_out_a_valid_T_12; // @[DCache.scala:430:64, :604:32, :606:127] assign _tl_out_a_valid_T_14 = _tl_out_a_valid_T_13; // @[DCache.scala:603:37, :604:32] assign tl_out_a_valid = _tl_out_a_valid_T_14; // @[DCache.scala:159:22, :603:37] wire _tl_out_a_bits_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47, :608:24] wire [39:0] _tl_out_a_bits_T_2 = {_tl_out_a_bits_T_1, 6'h0}; // @[DCache.scala:1210:{39,60}] wire [39:0] _tl_out_a_bits_legal_T_1 = _tl_out_a_bits_T_2; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_2 = {1'h0, _tl_out_a_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_3 = _tl_out_a_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_4 = _tl_out_a_bits_legal_T_3; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_5 = _tl_out_a_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _tl_out_a_bits_legal_T_6 = {_tl_out_a_bits_T_2[39:17], _tl_out_a_bits_T_2[16:0] ^ 17'h10000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_7 = {1'h0, _tl_out_a_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_8 = _tl_out_a_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_9 = _tl_out_a_bits_legal_T_8; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_10 = _tl_out_a_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _tl_out_a_bits_legal_T_11 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'hC000000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_12 = {1'h0, _tl_out_a_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_13 = _tl_out_a_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_14 = _tl_out_a_bits_legal_T_13; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_15 = _tl_out_a_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _tl_out_a_bits_legal_T_16 = _tl_out_a_bits_legal_T_5 | _tl_out_a_bits_legal_T_10; // @[Parameters.scala:685:42] wire _tl_out_a_bits_legal_T_17 = _tl_out_a_bits_legal_T_16 | _tl_out_a_bits_legal_T_15; // @[Parameters.scala:685:42] wire [39:0] _tl_out_a_bits_legal_T_21 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'h8000000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_22 = {1'h0, _tl_out_a_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_23 = _tl_out_a_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_24 = _tl_out_a_bits_legal_T_23; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_25 = _tl_out_a_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] tl_out_a_bits_a_address = _tl_out_a_bits_T_2[31:0]; // @[Edges.scala:346:17] wire [39:0] _tl_out_a_bits_legal_T_26 = {_tl_out_a_bits_T_2[39:32], tl_out_a_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [40:0] _tl_out_a_bits_legal_T_27 = {1'h0, _tl_out_a_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_28 = _tl_out_a_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_29 = _tl_out_a_bits_legal_T_28; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_30 = _tl_out_a_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _tl_out_a_bits_legal_T_31 = _tl_out_a_bits_legal_T_25 | _tl_out_a_bits_legal_T_30; // @[Parameters.scala:685:42] wire _tl_out_a_bits_legal_T_32 = _tl_out_a_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire tl_out_a_bits_legal = _tl_out_a_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] wire [2:0] tl_out_a_bits_a_param; // @[Edges.scala:346:17] assign tl_out_a_bits_a_param = {1'h0, s2_grow_param}; // @[Misc.scala:35:36] wire tl_out_a_bits_a_mask_sub_sub_sub_bit = _tl_out_a_bits_T_2[3]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_sub_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_sub_sub_nbit = ~tl_out_a_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_sub_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_sub_bit = _tl_out_a_bits_T_2[2]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_sub_nbit = ~tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T = tl_out_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T_1 = tl_out_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_sub_2_2 = tl_out_a_bits_a_mask_sub_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T_2 = tl_out_a_bits_a_mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_sub_3_2 = tl_out_a_bits_a_mask_sub_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T_3 = tl_out_a_bits_a_mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_bit = _tl_out_a_bits_T_2[1]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_nbit = ~tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_2_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_3_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_4_2 = tl_out_a_bits_a_mask_sub_sub_2_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_5_2 = tl_out_a_bits_a_mask_sub_sub_2_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_6_2 = tl_out_a_bits_a_mask_sub_sub_3_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_7_2 = tl_out_a_bits_a_mask_sub_sub_3_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_bit = _tl_out_a_bits_T_2[0]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_nbit = ~tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_eq = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T = tl_out_a_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_1 = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_1 = tl_out_a_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_2 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_2 = tl_out_a_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_3 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_3 = tl_out_a_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_4 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_4 = tl_out_a_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_5 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_5 = tl_out_a_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_6 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_6 = tl_out_a_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_7 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_7 = tl_out_a_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_8 = tl_out_a_bits_a_mask_sub_4_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_8 = tl_out_a_bits_a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_9 = tl_out_a_bits_a_mask_sub_4_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_9 = tl_out_a_bits_a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_10 = tl_out_a_bits_a_mask_sub_5_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_10 = tl_out_a_bits_a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_11 = tl_out_a_bits_a_mask_sub_5_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_11 = tl_out_a_bits_a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_12 = tl_out_a_bits_a_mask_sub_6_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_12 = tl_out_a_bits_a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_13 = tl_out_a_bits_a_mask_sub_6_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_13 = tl_out_a_bits_a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_14 = tl_out_a_bits_a_mask_sub_7_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_14 = tl_out_a_bits_a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_15 = tl_out_a_bits_a_mask_sub_7_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_15 = tl_out_a_bits_a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _tl_out_a_bits_T_3 = ~s2_write; // @[DCache.scala:609:9] wire _tl_out_a_bits_T_5 = ~s2_read; // @[DCache.scala:611:9] wire [2:0] _tl_out_a_bits_T_6_opcode = _tl_out_a_bits_T_5 ? 3'h0 : atomics_opcode; // @[DCache.scala:587:81, :611:{8,9}] wire [2:0] _tl_out_a_bits_T_6_param = _tl_out_a_bits_T_5 ? 3'h0 : atomics_param; // @[DCache.scala:587:81, :611:{8,9}] wire [3:0] _tl_out_a_bits_T_6_size = _tl_out_a_bits_T_5 ? put_size : atomics_size; // @[Edges.scala:480:17] wire _tl_out_a_bits_T_6_source = _tl_out_a_bits_T_5 ? put_source : atomics_source; // @[Edges.scala:480:17] wire [31:0] _tl_out_a_bits_T_6_address = _tl_out_a_bits_T_5 ? put_address : atomics_address; // @[Edges.scala:480:17] wire [15:0] _tl_out_a_bits_T_6_mask = _tl_out_a_bits_T_5 ? put_mask : atomics_mask; // @[Edges.scala:480:17] wire [127:0] _tl_out_a_bits_T_6_data = _tl_out_a_bits_T_5 ? put_data : atomics_data; // @[Edges.scala:480:17] wire [2:0] _tl_out_a_bits_T_7_opcode = _tl_out_a_bits_T_4 ? 3'h1 : _tl_out_a_bits_T_6_opcode; // @[DCache.scala:610:{8,20}, :611:8] wire [2:0] _tl_out_a_bits_T_7_param = _tl_out_a_bits_T_4 ? 3'h0 : _tl_out_a_bits_T_6_param; // @[DCache.scala:610:{8,20}, :611:8] wire [3:0] _tl_out_a_bits_T_7_size = _tl_out_a_bits_T_4 ? putpartial_size : _tl_out_a_bits_T_6_size; // @[Edges.scala:500:17] wire _tl_out_a_bits_T_7_source = _tl_out_a_bits_T_4 ? putpartial_source : _tl_out_a_bits_T_6_source; // @[Edges.scala:500:17] wire [31:0] _tl_out_a_bits_T_7_address = _tl_out_a_bits_T_4 ? putpartial_address : _tl_out_a_bits_T_6_address; // @[Edges.scala:500:17] wire [15:0] _tl_out_a_bits_T_7_mask = _tl_out_a_bits_T_4 ? putpartial_mask : _tl_out_a_bits_T_6_mask; // @[Edges.scala:500:17] wire [127:0] _tl_out_a_bits_T_7_data = _tl_out_a_bits_T_4 ? putpartial_data : _tl_out_a_bits_T_6_data; // @[Edges.scala:500:17] wire [2:0] _tl_out_a_bits_T_8_opcode = _tl_out_a_bits_T_3 ? 3'h4 : _tl_out_a_bits_T_7_opcode; // @[DCache.scala:609:{8,9}, :610:8] wire [2:0] _tl_out_a_bits_T_8_param = _tl_out_a_bits_T_3 ? 3'h0 : _tl_out_a_bits_T_7_param; // @[DCache.scala:609:{8,9}, :610:8] wire [3:0] _tl_out_a_bits_T_8_size = _tl_out_a_bits_T_3 ? get_size : _tl_out_a_bits_T_7_size; // @[Edges.scala:460:17] wire _tl_out_a_bits_T_8_source = _tl_out_a_bits_T_3 ? get_source : _tl_out_a_bits_T_7_source; // @[Edges.scala:460:17] wire [31:0] _tl_out_a_bits_T_8_address = _tl_out_a_bits_T_3 ? get_address : _tl_out_a_bits_T_7_address; // @[Edges.scala:460:17] wire [15:0] _tl_out_a_bits_T_8_mask = _tl_out_a_bits_T_3 ? get_mask : _tl_out_a_bits_T_7_mask; // @[Edges.scala:460:17] wire [127:0] _tl_out_a_bits_T_8_data = _tl_out_a_bits_T_3 ? 128'h0 : _tl_out_a_bits_T_7_data; // @[DCache.scala:609:{8,9}, :610:8] assign _tl_out_a_bits_T_9_opcode = _tl_out_a_bits_T ? 3'h6 : _tl_out_a_bits_T_8_opcode; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_param = _tl_out_a_bits_T ? tl_out_a_bits_a_param : _tl_out_a_bits_T_8_param; // @[Edges.scala:346:17] assign _tl_out_a_bits_T_9_size = _tl_out_a_bits_T ? 4'h6 : _tl_out_a_bits_T_8_size; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_source = ~_tl_out_a_bits_T & _tl_out_a_bits_T_8_source; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_address = _tl_out_a_bits_T ? tl_out_a_bits_a_address : _tl_out_a_bits_T_8_address; // @[Edges.scala:346:17] assign _tl_out_a_bits_T_9_mask = _tl_out_a_bits_T ? 16'hFFFF : _tl_out_a_bits_T_8_mask; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_data = _tl_out_a_bits_T ? 128'h0 : _tl_out_a_bits_T_8_data; // @[DCache.scala:608:{23,24}, :609:8] assign tl_out_a_bits_opcode = _tl_out_a_bits_T_9_opcode; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_param = _tl_out_a_bits_T_9_param; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_size = _tl_out_a_bits_T_9_size; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_source = _tl_out_a_bits_T_9_source; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_address = _tl_out_a_bits_T_9_address; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_mask = _tl_out_a_bits_T_9_mask; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_data = _tl_out_a_bits_T_9_data; // @[DCache.scala:159:22, :608:23] wire [1:0] _a_sel_T = 2'h1 << a_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _a_sel_T_1 = _a_sel_T; // @[OneHot.scala:65:{12,27}] wire a_sel = _a_sel_T_1[1]; // @[OneHot.scala:65:27] wire _io_cpu_perf_acquire_T = tl_out_a_ready & tl_out_a_valid; // @[Decoupled.scala:51:35] wire [4:0] _uncachedReqs_0_cmd_T_1 = {_uncachedReqs_0_cmd_T, 4'h1}; // @[DCache.scala:637:{37,49}] wire [4:0] _uncachedReqs_0_cmd_T_2 = s2_write ? _uncachedReqs_0_cmd_T_1 : 5'h0; // @[DCache.scala:637:{23,37}] wire _T_90 = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire _io_cpu_replay_next_T; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T = _T_90; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_near_end_of_refill_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_blocked_near_end_of_refill_T = _T_90; // @[Decoupled.scala:51:35] wire _io_errors_bus_valid_T; // @[Decoupled.scala:51:35] assign _io_errors_bus_valid_T = _T_90; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire r_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] r_counter; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = d_last & _T_90; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T = d_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_address_inc = {r_4, 4'h0}; // @[Edges.scala:234:25, :269:29] wire grantIsUncachedData = nodeOut_d_bits_opcode == 3'h1; // @[package.scala:16:47] wire grantIsUncached = grantIsUncachedData | nodeOut_d_bits_opcode == 3'h0 | nodeOut_d_bits_opcode == 3'h2; // @[package.scala:16:47, :81:59] wire _tl_d_data_encoded_T_17 = io_ptw_customCSRs_csrs_0_value_0[9]; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_18 = ~_tl_d_data_encoded_T_17; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_19 = nodeOut_d_bits_corrupt & _tl_d_data_encoded_T_18; // @[DCache.scala:663:{77,80}] wire _tl_d_data_encoded_T_20 = ~grantIsUncached; // @[package.scala:81:59] wire _tl_d_data_encoded_T_21 = _tl_d_data_encoded_T_19 & _tl_d_data_encoded_T_20; // @[DCache.scala:663:{77,126,129}] wire [15:0] tl_d_data_encoded_lo_lo_lo_1 = {_tl_d_data_encoded_T_23, _tl_d_data_encoded_T_22}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_lo_hi_1 = {_tl_d_data_encoded_T_25, _tl_d_data_encoded_T_24}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_lo_1 = {tl_d_data_encoded_lo_lo_hi_1, tl_d_data_encoded_lo_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_lo_hi_lo_1 = {_tl_d_data_encoded_T_27, _tl_d_data_encoded_T_26}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi_hi_1 = {_tl_d_data_encoded_T_29, _tl_d_data_encoded_T_28}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_hi_1 = {tl_d_data_encoded_lo_hi_hi_1, tl_d_data_encoded_lo_hi_lo_1}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_lo_1 = {tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo_lo_1 = {_tl_d_data_encoded_T_31, _tl_d_data_encoded_T_30}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_lo_hi_1 = {_tl_d_data_encoded_T_33, _tl_d_data_encoded_T_32}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_lo_1 = {tl_d_data_encoded_hi_lo_hi_1, tl_d_data_encoded_hi_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_hi_lo_1 = {_tl_d_data_encoded_T_35, _tl_d_data_encoded_T_34}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi_hi_1 = {_tl_d_data_encoded_T_37, _tl_d_data_encoded_T_36}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_hi_1 = {tl_d_data_encoded_hi_hi_hi_1, tl_d_data_encoded_hi_hi_lo_1}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_hi_1 = {tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1}; // @[package.scala:45:27] assign _tl_d_data_encoded_T_38 = {tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1}; // @[package.scala:45:27] assign tl_d_data_encoded = _tl_d_data_encoded_T_38; // @[package.scala:45:27] wire _grantIsCached_T = nodeOut_d_bits_opcode == 3'h4; // @[package.scala:16:47] wire _GEN_113 = nodeOut_d_bits_opcode == 3'h5; // @[package.scala:16:47] wire _grantIsCached_T_1; // @[package.scala:16:47] assign _grantIsCached_T_1 = _GEN_113; // @[package.scala:16:47] wire grantIsRefill; // @[DCache.scala:666:29] assign grantIsRefill = _GEN_113; // @[package.scala:16:47] wire grantIsCached = _grantIsCached_T | _grantIsCached_T_1; // @[package.scala:16:47, :81:59] wire grantIsVoluntary = nodeOut_d_bits_opcode == 3'h6; // @[DCache.scala:665:32] reg grantInProgress; // @[DCache.scala:667:32] reg [2:0] blockProbeAfterGrantCount; // @[DCache.scala:668:42] wire [3:0] _blockProbeAfterGrantCount_T = {1'h0, blockProbeAfterGrantCount} - 4'h1; // @[DCache.scala:668:42, :669:99] wire [2:0] _blockProbeAfterGrantCount_T_1 = _blockProbeAfterGrantCount_T[2:0]; // @[DCache.scala:669:99] wire _T_115 = release_state == 4'h6; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_1; // @[package.scala:16:47] assign _canAcceptCachedGrant_T_1 = _T_115; // @[package.scala:16:47] wire _metaArb_io_in_4_valid_T; // @[package.scala:16:47] assign _metaArb_io_in_4_valid_T = _T_115; // @[package.scala:16:47] wire _T_119 = release_state == 4'h9; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_2; // @[package.scala:16:47] assign _canAcceptCachedGrant_T_2 = _T_119; // @[package.scala:16:47] wire _nodeOut_c_valid_T_1; // @[DCache.scala:810:91] assign _nodeOut_c_valid_T_1 = _T_119; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_3 = _canAcceptCachedGrant_T | _canAcceptCachedGrant_T_1; // @[package.scala:16:47, :81:59] wire _canAcceptCachedGrant_T_4 = _canAcceptCachedGrant_T_3 | _canAcceptCachedGrant_T_2; // @[package.scala:16:47, :81:59] wire canAcceptCachedGrant = ~_canAcceptCachedGrant_T_4; // @[package.scala:81:59] wire _nodeOut_d_ready_T = ~d_first; // @[Edges.scala:231:25] wire _nodeOut_d_ready_T_1 = _nodeOut_d_ready_T | nodeOut_e_ready; // @[DCache.scala:671:{41,50}] wire _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :671:{50,69}] wire _nodeOut_d_ready_T_3 = ~grantIsCached | _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [1:0] _uncachedRespIdxOH_T = 2'h1 << uncachedRespIdxOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _uncachedRespIdxOH_T_1 = _uncachedRespIdxOH_T; // @[OneHot.scala:65:{12,27}] wire uncachedRespIdxOH = _uncachedRespIdxOH_T_1[1]; // @[OneHot.scala:65:27] wire _uncachedResp_T = uncachedRespIdxOH; // @[Mux.scala:32:36] wire _GEN_114 = _T_90 & grantIsCached; // @[Decoupled.scala:51:35] assign replace = _GEN_114 & d_last; // @[Replacement.scala:37:29, :38:11] wire _T_82 = uncachedRespIdxOH & d_last; // @[Edges.scala:232:33] assign s1_data_way = ~_T_90 | grantIsCached | ~(grantIsUncached & grantIsUncachedData) ? {1'h0, _s1_data_way_T} : 9'h100; // @[Decoupled.scala:51:35] wire [27:0] _s2_req_addr_dontCareBits_T = s1_paddr[31:4]; // @[DCache.scala:298:21, :701:41] wire [31:0] s2_req_addr_dontCareBits = {_s2_req_addr_dontCareBits_T, 4'h0}; // @[DCache.scala:701:{41,55}] wire [3:0] _s2_req_addr_T = uncachedResp_addr[3:0]; // @[DCache.scala:238:30, :702:45] wire [31:0] _s2_req_addr_T_1 = {s2_req_addr_dontCareBits[31:4], s2_req_addr_dontCareBits[3:0] | _s2_req_addr_T}; // @[DCache.scala:701:55, :702:{26,45}] wire _nodeOut_e_valid_T = nodeOut_d_valid & d_first; // @[Edges.scala:231:25] wire _nodeOut_e_valid_T_1 = _nodeOut_e_valid_T & grantIsCached; // @[package.scala:81:59] wire _nodeOut_e_valid_T_2 = _nodeOut_e_valid_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :714:{47,64}] assign nodeOut_e_bits_sink = nodeOut_e_bits_e_sink; // @[Edges.scala:451:17] wire _dataArb_io_in_1_valid_T = nodeOut_d_valid & grantIsRefill; // @[DCache.scala:666:29, :721:44] wire _dataArb_io_in_1_valid_T_1 = _dataArb_io_in_1_valid_T & canAcceptCachedGrant; // @[DCache.scala:670:30, :721:{44,61}] wire _T_98 = grantIsRefill & ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :666:29, :722:{23,26}] assign nodeOut_e_valid = ~_T_98 & _nodeOut_e_valid_T_2; // @[DCache.scala:714:{18,64}, :722:{23,51}, :723:20] wire [33:0] _dataArb_io_in_1_bits_addr_T = s2_vaddr[39:6]; // @[DCache.scala:351:21, :728:46] wire [39:0] _dataArb_io_in_1_bits_addr_T_1 = {_dataArb_io_in_1_bits_addr_T, 6'h0}; // @[DCache.scala:728:{46,57}] wire [39:0] _dataArb_io_in_1_bits_addr_T_2 = {_dataArb_io_in_1_bits_addr_T_1[39:12], _dataArb_io_in_1_bits_addr_T_1[11:0] | d_address_inc}; // @[Edges.scala:269:29] assign dataArb_io_in_1_bits_addr = _dataArb_io_in_1_bits_addr_T_2[11:0]; // @[DCache.scala:152:28, :728:{32,67}] wire _metaArb_io_in_3_valid_T = grantIsCached & d_done; // @[package.scala:81:59] wire _metaArb_io_in_3_valid_T_1 = ~nodeOut_d_bits_denied; // @[DCache.scala:741:56] assign _metaArb_io_in_3_valid_T_2 = _metaArb_io_in_3_valid_T & _metaArb_io_in_3_valid_T_1; // @[DCache.scala:741:{43,53,56}] assign metaArb_io_in_3_valid = _metaArb_io_in_3_valid_T_2; // @[DCache.scala:135:28, :741:53] assign metaArb_io_in_3_bits_idx = _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:135:28, :744:40] assign _metaArb_io_in_3_bits_addr_T_2 = {_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:745:{36,58,80}] assign metaArb_io_in_3_bits_addr = _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:135:28, :745:36] wire _metaArb_io_in_3_bits_data_c_cat_T_2 = _metaArb_io_in_3_bits_data_c_cat_T | _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_4 = _metaArb_io_in_3_bits_data_c_cat_T_2 | _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_9 = _metaArb_io_in_3_bits_data_c_cat_T_5 | _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_10 = _metaArb_io_in_3_bits_data_c_cat_T_9 | _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_11 = _metaArb_io_in_3_bits_data_c_cat_T_10 | _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_17 = _metaArb_io_in_3_bits_data_c_cat_T_12 | _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_18 = _metaArb_io_in_3_bits_data_c_cat_T_17 | _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_19 = _metaArb_io_in_3_bits_data_c_cat_T_18 | _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_20 = _metaArb_io_in_3_bits_data_c_cat_T_19 | _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_21 = _metaArb_io_in_3_bits_data_c_cat_T_11 | _metaArb_io_in_3_bits_data_c_cat_T_20; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_22 = _metaArb_io_in_3_bits_data_c_cat_T_4 | _metaArb_io_in_3_bits_data_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_25 = _metaArb_io_in_3_bits_data_c_cat_T_23 | _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_27 = _metaArb_io_in_3_bits_data_c_cat_T_25 | _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_32 = _metaArb_io_in_3_bits_data_c_cat_T_28 | _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_33 = _metaArb_io_in_3_bits_data_c_cat_T_32 | _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_34 = _metaArb_io_in_3_bits_data_c_cat_T_33 | _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_40 = _metaArb_io_in_3_bits_data_c_cat_T_35 | _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_41 = _metaArb_io_in_3_bits_data_c_cat_T_40 | _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_42 = _metaArb_io_in_3_bits_data_c_cat_T_41 | _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_43 = _metaArb_io_in_3_bits_data_c_cat_T_42 | _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_44 = _metaArb_io_in_3_bits_data_c_cat_T_34 | _metaArb_io_in_3_bits_data_c_cat_T_43; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_45 = _metaArb_io_in_3_bits_data_c_cat_T_27 | _metaArb_io_in_3_bits_data_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_47 = _metaArb_io_in_3_bits_data_c_cat_T_45 | _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _metaArb_io_in_3_bits_data_c_cat_T_49 = _metaArb_io_in_3_bits_data_c_cat_T_47 | _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] metaArb_io_in_3_bits_data_c = {_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _metaArb_io_in_3_bits_data_T_1 = {metaArb_io_in_3_bits_data_c, nodeOut_d_bits_param}; // @[Metadata.scala:29:18, :84:18] wire _metaArb_io_in_3_bits_data_T_10 = _metaArb_io_in_3_bits_data_T_1 == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_11 = {1'h0, _metaArb_io_in_3_bits_data_T_10}; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_12 = _metaArb_io_in_3_bits_data_T_1 == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_13 = _metaArb_io_in_3_bits_data_T_12 ? 2'h2 : _metaArb_io_in_3_bits_data_T_11; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_14 = _metaArb_io_in_3_bits_data_T_1 == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_15 = _metaArb_io_in_3_bits_data_T_14 ? 2'h2 : _metaArb_io_in_3_bits_data_T_13; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_16 = _metaArb_io_in_3_bits_data_T_1 == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_17 = _metaArb_io_in_3_bits_data_T_16 ? 2'h3 : _metaArb_io_in_3_bits_data_T_15; // @[Metadata.scala:84:38] wire [1:0] metaArb_io_in_3_bits_data_meta_state = _metaArb_io_in_3_bits_data_T_17; // @[Metadata.scala:84:38, :160:20] wire [1:0] metaArb_io_in_3_bits_data_meta_1_coh_state = metaArb_io_in_3_bits_data_meta_state; // @[Metadata.scala:160:20] wire [19:0] metaArb_io_in_3_bits_data_meta_1_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data_meta_1_tag = _metaArb_io_in_3_bits_data_T[19:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_3_bits_data_T_18 = {metaArb_io_in_3_bits_data_meta_1_coh_state, metaArb_io_in_3_bits_data_meta_1_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data = _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:135:28, :746:134] reg blockUncachedGrant; // @[DCache.scala:750:33] wire _T_100 = grantIsUncachedData & (blockUncachedGrant | s1_valid); // @[package.scala:16:47] assign nodeOut_d_ready = ~(_T_100 | _T_98) & _nodeOut_d_ready_T_3; // @[DCache.scala:671:{18,24}, :722:{23,51}, :724:20, :752:{31,68}, :753:22] assign io_cpu_req_ready_0 = _T_100 ? ~(nodeOut_d_valid | _T_10 | ~metaArb_io_in_7_ready | _T_4) & _io_cpu_req_ready_T_4 : ~(_T_10 | ~metaArb_io_in_7_ready | _T_4) & _io_cpu_req_ready_T_4; // @[DCache.scala:101:7, :135:28, :195:9, :233:{20,73}, :258:{33,45,64}, :267:{34,53}, :275:{27,53,79,98}, :752:{31,68}, :755:29, :756:26] wire _GEN_115 = _T_100 & nodeOut_d_valid; // @[DCache.scala:721:26, :752:{31,68}, :755:29, :757:32] assign dataArb_io_in_1_valid = _GEN_115 | _dataArb_io_in_1_valid_T_1; // @[DCache.scala:152:28, :721:{26,61}, :752:68, :755:29, :757:32] assign dataArb_io_in_1_bits_write = ~_T_100 | ~nodeOut_d_valid; // @[DCache.scala:152:28, :727:33, :752:{31,68}, :755:29, :758:37] wire _blockUncachedGrant_T = ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :722:26, :759:31] wire _block_probe_for_core_progress_T = |blockProbeAfterGrantCount; // @[DCache.scala:668:42, :669:35, :766:65] wire block_probe_for_core_progress = _block_probe_for_core_progress_T | lrscValid; // @[DCache.scala:473:29, :766:{65,71}] wire [31:0] _block_probe_for_pending_release_ack_T = nodeOut_b_bits_address ^ release_ack_addr; // @[DCache.scala:227:29, :767:88] wire [14:0] _block_probe_for_pending_release_ack_T_1 = _block_probe_for_pending_release_ack_T[20:6]; // @[DCache.scala:767:{88,107}] wire _block_probe_for_pending_release_ack_T_2 = _block_probe_for_pending_release_ack_T_1 == 15'h0; // @[DCache.scala:582:29, :767:{107,163}] wire block_probe_for_pending_release_ack = release_ack_wait & _block_probe_for_pending_release_ack_T_2; // @[DCache.scala:226:33, :767:{62,163}] wire _block_probe_for_ordering_T = releaseInFlight | block_probe_for_pending_release_ack; // @[DCache.scala:334:46, :767:62, :768:50] wire block_probe_for_ordering = _block_probe_for_ordering_T | grantInProgress; // @[DCache.scala:667:32, :768:{50,89}] wire _metaArb_io_in_6_valid_T = ~block_probe_for_core_progress; // @[DCache.scala:766:71, :769:48] wire _metaArb_io_in_6_valid_T_1 = _metaArb_io_in_6_valid_T | lrscBackingOff; // @[DCache.scala:474:40, :769:{48,79}] wire _metaArb_io_in_6_valid_T_2 = nodeOut_b_valid & _metaArb_io_in_6_valid_T_1; // @[DCache.scala:769:{44,79}] wire _nodeOut_b_ready_T = block_probe_for_core_progress | block_probe_for_ordering; // @[DCache.scala:766:71, :768:89, :770:79] wire _nodeOut_b_ready_T_1 = _nodeOut_b_ready_T | s1_valid; // @[DCache.scala:182:25, :770:{79,107}] wire _nodeOut_b_ready_T_2 = _nodeOut_b_ready_T_1 | s2_valid; // @[DCache.scala:331:25, :770:{107,119}] wire _nodeOut_b_ready_T_3 = ~_nodeOut_b_ready_T_2; // @[DCache.scala:770:{47,119}] assign _nodeOut_b_ready_T_4 = metaArb_io_in_6_ready & _nodeOut_b_ready_T_3; // @[DCache.scala:135:28, :770:{44,47}] assign nodeOut_b_ready = _nodeOut_b_ready_T_4; // @[DCache.scala:770:44] wire [5:0] _metaArb_io_in_6_bits_idx_T = nodeOut_b_bits_address[11:6]; // @[DCache.scala:1200:47] wire [7:0] _metaArb_io_in_6_bits_addr_T = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58] wire [7:0] _metaArb_io_in_6_bits_addr_T_2 = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58, :844:62] wire [39:0] _metaArb_io_in_6_bits_addr_T_1 = {_metaArb_io_in_6_bits_addr_T, nodeOut_b_bits_address}; // @[DCache.scala:773:{36,58}] assign _s1_victim_way_T = lfsr[2:0]; // @[PRNG.scala:95:17] assign s1_victim_way = _s1_victim_way_T; // @[package.scala:163:13] wire _T_134 = nodeOut_c_ready & nodeOut_c_valid; // @[Decoupled.scala:51:35] wire _releaseRejected_T; // @[Decoupled.scala:51:35] assign _releaseRejected_T = _T_134; // @[Decoupled.scala:51:35] wire _io_cpu_perf_release_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_release_T = _T_134; // @[Decoupled.scala:51:35] wire [26:0] _GEN_116 = 27'hFFF << nodeOut_c_bits_size; // @[package.scala:243:71] wire [26:0] _r_beats1_decode_T_3; // @[package.scala:243:71] assign _r_beats1_decode_T_3 = _GEN_116; // @[package.scala:243:71] wire [26:0] _io_cpu_perf_release_beats1_decode_T; // @[package.scala:243:71] assign _io_cpu_perf_release_beats1_decode_T = _GEN_116; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_4 = _r_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_5 = ~_r_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode_1 = _r_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire r_beats1_opdata_1 = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36] wire io_cpu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36] wire [7:0] r_beats1_1 = r_beats1_opdata_1 ? r_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] r_counter_1; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T_1 = {1'h0, r_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1_1 = _r_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first = r_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T_2 = r_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_3 = r_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_last = _r_last_T_2 | _r_last_T_3; // @[Edges.scala:232:{25,33,43}] wire releaseDone = c_last & _T_134; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T_1 = ~r_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_count = r_beats1_1 & _r_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T_1 = c_first ? r_beats1_1 : r_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _releaseRejected_T_2; // @[DCache.scala:803:44] wire releaseRejected; // @[DCache.scala:800:29] wire _s1_release_data_valid_T = dataArb_io_in_2_ready & _dataArb_io_in_2_valid_T_1; // @[Decoupled.scala:51:35] reg s1_release_data_valid; // @[DCache.scala:801:38] wire _s2_release_data_valid_T = ~releaseRejected; // @[DCache.scala:800:29, :802:64] wire _s2_release_data_valid_T_1 = s1_release_data_valid & _s2_release_data_valid_T; // @[DCache.scala:801:38, :802:{61,64}] reg s2_release_data_valid; // @[DCache.scala:802:38] wire _nodeOut_c_valid_T_3 = s2_release_data_valid; // @[DCache.scala:802:38, :810:44] wire _releaseRejected_T_1 = ~_releaseRejected_T; // @[Decoupled.scala:51:35] assign _releaseRejected_T_2 = s2_release_data_valid & _releaseRejected_T_1; // @[DCache.scala:802:38, :803:{44,47}] assign releaseRejected = _releaseRejected_T_2; // @[DCache.scala:800:29, :803:44] wire [8:0] _releaseDataBeat_T = {1'h0, c_count}; // @[Edges.scala:234:25] wire [1:0] _releaseDataBeat_T_1 = {1'h0, s2_release_data_valid}; // @[DCache.scala:802:38, :804:98] wire [2:0] _releaseDataBeat_T_2 = {2'h0, s1_release_data_valid} + {1'h0, _releaseDataBeat_T_1}; // @[DCache.scala:801:38, :804:{93,98}] wire [1:0] _releaseDataBeat_T_3 = _releaseDataBeat_T_2[1:0]; // @[DCache.scala:804:93] wire [1:0] _releaseDataBeat_T_4 = releaseRejected ? 2'h0 : _releaseDataBeat_T_3; // @[DCache.scala:800:29, :804:{48,93}] wire [9:0] _releaseDataBeat_T_5 = {1'h0, _releaseDataBeat_T} + {8'h0, _releaseDataBeat_T_4}; // @[DCache.scala:804:{28,43,48}] wire [8:0] releaseDataBeat = _releaseDataBeat_T_5[8:0]; // @[DCache.scala:804:43] wire _nodeOut_c_valid_T_4 = c_first & release_ack_wait; // @[Edges.scala:231:25] wire _nodeOut_c_valid_T_5 = ~_nodeOut_c_valid_T_4; // @[DCache.scala:810:{120,130}] wire _nodeOut_c_valid_T_6 = _nodeOut_c_valid_T_3 & _nodeOut_c_valid_T_5; // @[DCache.scala:810:{44,117,120}] wire [1:0] newCoh_state; // @[DCache.scala:812:27] wire [1:0] metaArb_io_in_4_bits_data_meta_coh_state = newCoh_state; // @[HellaCache.scala:305:20] wire _release_state_T_8 = s2_valid_flush_line | s2_flush_valid; // @[DCache.scala:363:51, :419:75, :817:34, :820:151] wire _discard_line_T = s2_req_size[1]; // @[DCache.scala:339:19, :818:60] wire _discard_line_T_1 = s2_valid_flush_line & _discard_line_T; // @[DCache.scala:419:75, :818:{46,60}] wire _discard_line_T_3 = s2_flush_valid & _discard_line_T_2; // @[DCache.scala:363:51, :818:{82,102}] wire discard_line = _discard_line_T_1 | _discard_line_T_3; // @[DCache.scala:818:{46,64,82}] wire _release_state_T = ~discard_line; // @[DCache.scala:818:64, :819:47] wire _release_state_T_1 = s2_victim_dirty & _release_state_T; // @[Misc.scala:38:9] wire _release_state_T_3 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47, :820:57] wire _release_state_T_6 = |s2_victim_state_state; // @[Metadata.scala:50:45] wire _release_state_T_9 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _release_state_T_10 = s2_readwrite & _release_state_T_9; // @[DCache.scala:354:30, :820:{185,188}] wire _release_state_T_11 = _release_state_T_8 | _release_state_T_10; // @[DCache.scala:820:{151,169,185}] wire [3:0] _release_state_T_14 = _release_state_T_1 ? 4'h1 : 4'h6; // @[DCache.scala:819:{27,44}] wire [5:0] _probe_bits_T_1 = s2_req_addr[11:6]; // @[DCache.scala:339:19, :822:76] wire [25:0] _probe_bits_T_2 = {s2_victim_tag, _probe_bits_T_1}; // @[DCache.scala:433:26, :822:{49,76}] wire [31:0] _probe_bits_T_3 = {_probe_bits_T_2, 6'h0}; // @[DCache.scala:822:{49,96}] wire [31:0] probe_bits_res_address = _probe_bits_T_3; // @[DCache.scala:822:96, :1202:19] wire probeNack; // @[DCache.scala:825:34] wire [3:0] _release_state_T_15 = {1'h0, releaseDone, 2'h3}; // @[Edges.scala:233:22] wire _probeNack_T = ~releaseDone; // @[Edges.scala:233:22] assign probeNack = s2_prb_ack_data | (|s2_probe_state_state) | _probeNack_T; // @[Misc.scala:38:9] wire [3:0] _release_state_T_16 = releaseDone ? 4'h0 : 4'h5; // @[Edges.scala:233:22] assign s1_nack = s2_probe ? probeNack | _T_68 | _T_48 | _T_14 : _T_68 | _T_48 | _T_14; // @[DCache.scala:185:28, :276:{39,58,79}, :288:{75,85}, :333:25, :446:{24,82,92}, :571:{18,36,46}, :824:21, :825:34, :839:{24,34}] wire _T_110 = release_state == 4'h4; // @[DCache.scala:228:30, :841:25] assign metaArb_io_in_6_valid = _T_110 | _metaArb_io_in_6_valid_T_2; // @[DCache.scala:135:28, :769:{26,44}, :841:{25,44}, :842:30] assign metaArb_io_in_6_bits_idx = _T_110 ? _metaArb_io_in_6_bits_idx_T_1 : _metaArb_io_in_6_bits_idx_T; // @[DCache.scala:135:28, :772:29, :841:{25,44}, :843:33, :1200:47] wire [39:0] _metaArb_io_in_6_bits_addr_T_3 = {_metaArb_io_in_6_bits_addr_T_2, probe_bits_address}; // @[DCache.scala:184:29, :844:{40,62}] assign metaArb_io_in_6_bits_addr = _T_110 ? _metaArb_io_in_6_bits_addr_T_3 : _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:135:28, :773:{30,36}, :841:{25,44}, :844:{34,40}] wire _T_111 = release_state == 4'h5; // @[DCache.scala:228:30, :850:25] wire _T_112 = release_state == 4'h3; // @[DCache.scala:228:30, :854:25] assign nodeOut_c_valid = _T_112 | _T_111 | s2_probe & ~s2_prb_ack_data | _nodeOut_c_valid_T_6; // @[Misc.scala:38:9] wire _GEN_117 = _T_112 | ~(~s2_probe | s2_prb_ack_data | ~(|s2_probe_state_state)); // @[Misc.scala:38:9] wire _T_118 = _T_114 | _T_115 | _T_119; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_opcode = _T_118 ? {2'h3, ~_T_119} : {2'h2, _inWriteback_T_1}; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_param = _T_118 ? (_T_119 ? nodeOut_c_bits_c_param : nodeOut_c_bits_c_1_param) : _inWriteback_T_1 ? dirtyReleaseMessage_param : _GEN_117 ? cleanReleaseMessage_param : 3'h5; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_size = _T_118 ? 4'h6 : _inWriteback_T_1 ? dirtyReleaseMessage_size : _GEN_117 ? cleanReleaseMessage_size : nackResponseMessage_size; // @[package.scala:16:47, :81:59] assign newCoh_state = _T_118 ? voluntaryNewCoh_state : probeNewCoh_state; // @[package.scala:81:59] assign releaseWay = _T_118 ? s2_victim_or_hit_way : s2_probe_way; // @[package.scala:81:59] wire _dataArb_io_in_2_valid_T = releaseDataBeat < 9'h4; // @[DCache.scala:804:43, :900:60] assign _dataArb_io_in_2_valid_T_1 = inWriteback & _dataArb_io_in_2_valid_T; // @[package.scala:81:59] assign dataArb_io_in_2_valid = _dataArb_io_in_2_valid_T_1; // @[DCache.scala:152:28, :900:41] wire [11:0] _dataArb_io_in_2_bits_addr_T_1 = {_dataArb_io_in_2_bits_addr_T, 6'h0}; // @[DCache.scala:903:55, :1200:47] wire [1:0] _dataArb_io_in_2_bits_addr_T_2 = releaseDataBeat[1:0]; // @[DCache.scala:804:43, :903:90] wire [5:0] _dataArb_io_in_2_bits_addr_T_3 = {_dataArb_io_in_2_bits_addr_T_2, 4'h0}; // @[DCache.scala:903:{90,117}] assign _dataArb_io_in_2_bits_addr_T_4 = {_dataArb_io_in_2_bits_addr_T_1[11:6], _dataArb_io_in_2_bits_addr_T_1[5:0] | _dataArb_io_in_2_bits_addr_T_3}; // @[DCache.scala:903:{55,72,117}] assign dataArb_io_in_2_bits_addr = _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:152:28, :903:72] wire _metaArb_io_in_4_valid_T_1 = release_state == 4'h7; // @[package.scala:16:47] assign _metaArb_io_in_4_valid_T_2 = _metaArb_io_in_4_valid_T | _metaArb_io_in_4_valid_T_1; // @[package.scala:16:47, :81:59] assign metaArb_io_in_4_valid = _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59] assign metaArb_io_in_4_bits_idx = _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:135:28, :1200:47] wire [11:0] _metaArb_io_in_4_bits_addr_T_1 = probe_bits_address[11:0]; // @[DCache.scala:184:29, :912:90] assign _metaArb_io_in_4_bits_addr_T_2 = {_metaArb_io_in_4_bits_addr_T, _metaArb_io_in_4_bits_addr_T_1}; // @[DCache.scala:912:{36,58,90}] assign metaArb_io_in_4_bits_addr = _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:135:28, :912:36] wire [19:0] _metaArb_io_in_4_bits_data_T = nodeOut_c_bits_address[31:12]; // @[DCache.scala:913:78] wire [19:0] metaArb_io_in_4_bits_data_meta_tag = _metaArb_io_in_4_bits_data_T; // @[HellaCache.scala:305:20] assign _metaArb_io_in_4_bits_data_T_1 = {metaArb_io_in_4_bits_data_meta_coh_state, metaArb_io_in_4_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_4_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_5_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_6_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_7_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] wire _io_cpu_s2_uncached_T = ~s2_hit; // @[Misc.scala:35:9] assign _io_cpu_s2_uncached_T_1 = s2_uncached & _io_cpu_s2_uncached_T; // @[DCache.scala:424:39, :920:{37,40}] assign io_cpu_s2_uncached_0 = _io_cpu_s2_uncached_T_1; // @[DCache.scala:101:7, :920:37] wire _io_cpu_ordered_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35] wire _io_cpu_ordered_T_1 = s1_valid & _io_cpu_ordered_T; // @[DCache.scala:182:25, :929:{32,35}] wire _io_cpu_ordered_T_2 = ~s2_req_no_xcpt; // @[DCache.scala:339:19, :929:72] wire _io_cpu_ordered_T_3 = s2_valid & _io_cpu_ordered_T_2; // @[DCache.scala:331:25, :929:{69,72}] wire _io_cpu_ordered_T_4 = _io_cpu_ordered_T_1 | _io_cpu_ordered_T_3; // @[DCache.scala:929:{32,57,69}] wire _io_cpu_ordered_T_5 = _io_cpu_ordered_T_4 | cached_grant_wait; // @[DCache.scala:223:34, :929:{57,94}] wire _io_cpu_ordered_T_7 = _io_cpu_ordered_T_5 | _io_cpu_ordered_T_6; // @[DCache.scala:929:{94,115,142}] assign _io_cpu_ordered_T_8 = ~_io_cpu_ordered_T_7; // @[DCache.scala:929:{21,115}] assign io_cpu_ordered_0 = _io_cpu_ordered_T_8; // @[DCache.scala:101:7, :929:21] wire _io_cpu_store_pending_T_2 = _io_cpu_store_pending_T | _io_cpu_store_pending_T_1; // @[Consts.scala:90:{32,42,49}] wire _io_cpu_store_pending_T_4 = _io_cpu_store_pending_T_2 | _io_cpu_store_pending_T_3; // @[Consts.scala:90:{42,59,66}] wire _io_cpu_store_pending_T_9 = _io_cpu_store_pending_T_5 | _io_cpu_store_pending_T_6; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_10 = _io_cpu_store_pending_T_9 | _io_cpu_store_pending_T_7; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_11 = _io_cpu_store_pending_T_10 | _io_cpu_store_pending_T_8; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_17 = _io_cpu_store_pending_T_12 | _io_cpu_store_pending_T_13; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_18 = _io_cpu_store_pending_T_17 | _io_cpu_store_pending_T_14; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_19 = _io_cpu_store_pending_T_18 | _io_cpu_store_pending_T_15; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_20 = _io_cpu_store_pending_T_19 | _io_cpu_store_pending_T_16; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_21 = _io_cpu_store_pending_T_11 | _io_cpu_store_pending_T_20; // @[package.scala:81:59] wire _io_cpu_store_pending_T_22 = _io_cpu_store_pending_T_4 | _io_cpu_store_pending_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _io_cpu_store_pending_T_23 = cached_grant_wait & _io_cpu_store_pending_T_22; // @[DCache.scala:223:34, :930:46] assign _io_cpu_store_pending_T_25 = _io_cpu_store_pending_T_23 | _io_cpu_store_pending_T_24; // @[DCache.scala:930:{46,70,97}] assign io_cpu_store_pending_0 = _io_cpu_store_pending_T_25; // @[DCache.scala:101:7, :930:70] wire _s1_xcpt_valid_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35, :932:43] wire _s1_xcpt_valid_T_1 = _tlb_io_req_valid_T_3 & _s1_xcpt_valid_T; // @[DCache.scala:273:40, :932:{40,43}] wire _s1_xcpt_valid_T_2 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :932:68] wire s1_xcpt_valid = _s1_xcpt_valid_T_1 & _s1_xcpt_valid_T_2; // @[DCache.scala:932:{40,65,68}] reg io_cpu_s2_xcpt_REG; // @[DCache.scala:933:32] wire _io_cpu_s2_xcpt_T_miss = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_miss; // @[DCache.scala:342:24, :933:{24,32}] wire [31:0] _io_cpu_s2_xcpt_T_paddr = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_paddr : 32'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [39:0] _io_cpu_s2_xcpt_T_gpa = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_gpa : 40'h0; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_pf_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_ae_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_cacheable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_must_alloc = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_prefetchable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24, :933:{24,32}] wire [1:0] _io_cpu_s2_xcpt_T_size = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_size : 2'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [4:0] _io_cpu_s2_xcpt_T_cmd = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_cmd : 5'h0; // @[DCache.scala:342:24, :933:{24,32}] assign io_cpu_s2_xcpt_pf_ld_0 = _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_pf_st_0 = _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_ld_0 = _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_st_0 = _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_ld_0 = _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_st_0 = _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:101:7, :933:24] wire _s1_uncached_data_word_T = s1_uncached_data_word_word_idx; // @[package.scala:39:86, :163:13] wire [63:0] s1_uncached_data_word_words_0 = nodeOut_d_bits_data[63:0]; // @[package.scala:211:50] wire [63:0] s1_uncached_data_word_words_1 = nodeOut_d_bits_data[127:64]; // @[package.scala:211:50] wire [63:0] s1_uncached_data_word = _s1_uncached_data_word_T ? s1_uncached_data_word_words_1 : s1_uncached_data_word_words_0; // @[package.scala:39:{76,86}, :211:50] reg [63:0] s2_uncached_data_word; // @[DCache.scala:947:40] reg doUncachedResp; // @[DCache.scala:948:31] assign io_cpu_resp_bits_replay_0 = doUncachedResp; // @[DCache.scala:101:7, :948:31] wire _io_cpu_resp_valid_T = s2_valid_hit_pre_data_ecc | doUncachedResp; // @[DCache.scala:420:69, :948:31, :949:51] assign _io_cpu_resp_valid_T_2 = _io_cpu_resp_valid_T; // @[DCache.scala:949:{51,70}] assign io_cpu_resp_valid_0 = _io_cpu_resp_valid_T_2; // @[DCache.scala:101:7, :949:70] wire _io_cpu_replay_next_T_1 = _io_cpu_replay_next_T & grantIsUncachedData; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T_3 = _io_cpu_replay_next_T_1; // @[DCache.scala:950:{39,62}] assign io_cpu_replay_next_0 = _io_cpu_replay_next_T_3; // @[DCache.scala:101:7, :950:62]

Generate the Verilog code corresponding to the following Chisel files. File HellaCacheArbiter.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat,log2Up} import org.chipsalliance.cde.config.Parameters class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module { val io = IO(new Bundle { val requestor = Flipped(Vec(n, new HellaCacheIO)) val mem = new HellaCacheIO }) if (n == 1) { io.mem <> io.requestor.head } else { val s1_id = Reg(UInt()) val s2_id = RegNext(s1_id) io.mem.keep_clock_enabled := io.requestor.map(_.keep_clock_enabled).reduce(_||_) io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_) io.requestor(0).req.ready := io.mem.req.ready for (i <- 1 until n) io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid for (i <- n-1 to 0 by -1) { val req = io.requestor(i).req def connect_s0() = { io.mem.req.bits := req.bits io.mem.req.bits.tag := Cat(req.bits.tag, i.U(log2Up(n).W)) s1_id := i.U } def connect_s1() = { io.mem.s1_kill := io.requestor(i).s1_kill io.mem.s1_data := io.requestor(i).s1_data } def connect_s2() = { io.mem.s2_kill := io.requestor(i).s2_kill } if (i == n-1) { connect_s0() connect_s1() connect_s2() } else { when (req.valid) { connect_s0() } when (s1_id === i.U) { connect_s1() } when (s2_id === i.U) { connect_s2() } } } io.mem.uncached_resp.foreach(_.ready := false.B) for (i <- 0 until n) { val resp = io.requestor(i).resp val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === i.U resp.valid := io.mem.resp.valid && tag_hit io.requestor(i).s2_xcpt := io.mem.s2_xcpt io.requestor(i).s2_gpa := io.mem.s2_gpa io.requestor(i).s2_gpa_is_pte := io.mem.s2_gpa_is_pte io.requestor(i).ordered := io.mem.ordered io.requestor(i).store_pending := io.mem.store_pending io.requestor(i).perf := io.mem.perf io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === i.U io.requestor(i).s2_nack_cause_raw := io.mem.s2_nack_cause_raw io.requestor(i).s2_uncached := io.mem.s2_uncached io.requestor(i).s2_paddr := io.mem.s2_paddr io.requestor(i).clock_enabled := io.mem.clock_enabled resp.bits := io.mem.resp.bits resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n) io.requestor(i).replay_next := io.mem.replay_next io.requestor(i).uncached_resp.map { uncached_resp => val uncached_tag_hit = io.mem.uncached_resp.get.bits.tag(log2Up(n)-1,0) === i.U uncached_resp.valid := io.mem.uncached_resp.get.valid && uncached_tag_hit when (uncached_resp.ready && uncached_tag_hit) { io.mem.uncached_resp.get.ready := true.B } uncached_resp.bits := io.mem.uncached_resp.get.bits uncached_resp.bits.tag := io.mem.uncached_resp.get.bits.tag >> log2Up(n) } } } }

module HellaCacheArbiter( // @[HellaCacheArbiter.scala:10:7] input clock, // @[HellaCacheArbiter.scala:10:7] input reset, // @[HellaCacheArbiter.scala:10:7] output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_0_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_0_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_valid, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_1_s1_data_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_1_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_1_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_1_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_2_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_2_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_requestor_2_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_2_req_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_2_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_s1_kill, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_2_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_2_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_2_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_2_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_2_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_2_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_2_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_2_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_2_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_keep_clock_enabled, // @[HellaCacheArbiter.scala:12:14] input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_mem_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_phys, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_mem_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_uncached, // @[HellaCacheArbiter.scala:12:14] input [31:0] io_mem_s2_paddr, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_mem_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] input io_mem_replay_next, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_s2_gpa, // @[HellaCacheArbiter.scala:12:14] input io_mem_ordered, // @[HellaCacheArbiter.scala:12:14] input io_mem_store_pending, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_acquire, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_release, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_grant, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_blocked, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_mem_keep_clock_enabled // @[HellaCacheArbiter.scala:12:14] ); wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_s1_data_mask_0 = io_requestor_1_s1_data_mask; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_valid_0 = io_requestor_2_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_2_req_bits_addr_0 = io_requestor_2_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_req_bits_tag_0 = io_requestor_2_req_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_2_req_bits_cmd_0 = io_requestor_2_req_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_2_req_bits_size_0 = io_requestor_2_req_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_signed_0 = io_requestor_2_req_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_2_req_bits_dprv_0 = io_requestor_2_req_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_dv_0 = io_requestor_2_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_no_resp_0 = io_requestor_2_req_bits_no_resp; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s1_kill_0 = io_requestor_2_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_s1_data_data_0 = io_requestor_2_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_keep_clock_enabled_0 = io_requestor_2_keep_clock_enabled; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[HellaCacheArbiter.scala:10:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[HellaCacheArbiter.scala:10:7] wire io_mem_ordered_0 = io_mem_ordered; // @[HellaCacheArbiter.scala:10:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[HellaCacheArbiter.scala:10:7] wire [9:0] _io_mem_req_bits_tag_T_2 = 10'h0; // @[HellaCacheArbiter.scala:34:35] wire [1:0] io_requestor_0_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :51:21] wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [9:0] _io_mem_req_bits_tag_T_1 = 10'h1; // @[HellaCacheArbiter.scala:34:35] wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_size = 2'h0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_dprv = 2'h0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_req_bits_tag = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_req_bits_tag = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_req_bits_addr = 40'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire io_requestor_0_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_mem_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_dv = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s1_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_keep_clock_enabled_T = 1'h0; // @[HellaCacheArbiter.scala:23:81] wire io_mem_req_bits_phys_0 = io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64] wire _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_requestor_2_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64] wire _io_requestor_2_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_2_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_mem_keep_clock_enabled_T_1 = io_requestor_2_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7, :23:81] wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_req_valid_T_1; // @[HellaCacheArbiter.scala:25:63] wire io_requestor_0_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_0_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_1_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_2_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_2_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_2_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_2_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_2_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_2_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] reg [1:0] s1_id; // @[HellaCacheArbiter.scala:20:20] reg [1:0] s2_id; // @[HellaCacheArbiter.scala:21:24] assign io_mem_keep_clock_enabled_0 = _io_mem_keep_clock_enabled_T_1; // @[HellaCacheArbiter.scala:10:7, :23:81] wire _io_mem_req_valid_T = io_requestor_0_req_valid_0 | io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63] assign _io_mem_req_valid_T_1 = _io_mem_req_valid_T | io_requestor_2_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63] assign io_mem_req_valid_0 = _io_mem_req_valid_T_1; // @[HellaCacheArbiter.scala:10:7, :25:63] wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}] assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64] wire _io_requestor_2_req_ready_T = ~io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] assign _io_requestor_2_req_ready_T_1 = io_requestor_1_req_ready_0 & _io_requestor_2_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}] assign io_requestor_2_req_ready_0 = _io_requestor_2_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64] wire [9:0] _io_mem_req_bits_tag_T = {io_requestor_2_req_bits_tag_0, 2'h2}; // @[HellaCacheArbiter.scala:10:7, :34:35] wire _T = s1_id == 2'h1; // @[HellaCacheArbiter.scala:20:20, :51:21] wire _io_requestor_1_s2_nack_T = s2_id == 2'h1; // @[HellaCacheArbiter.scala:21:24, :51:21, :52:21, :68:58] assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_valid_0 ? 40'h0 : io_requestor_2_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] assign io_mem_req_bits_cmd_0 = io_requestor_0_req_valid_0 | io_requestor_1_req_valid_0 ? 5'h0 : io_requestor_2_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_size_0 = io_requestor_0_req_valid_0 ? 2'h3 : io_requestor_1_req_valid_0 ? 2'h0 : io_requestor_2_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] assign io_mem_req_bits_signed_0 = ~io_requestor_0_req_valid_0 & ~io_requestor_1_req_valid_0 & io_requestor_2_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_dprv_0 = io_requestor_0_req_valid_0 ? 2'h1 : io_requestor_1_req_valid_0 ? 2'h0 : io_requestor_2_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26, :51:21] assign io_mem_req_bits_dv_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_dv_0 : ~io_requestor_1_req_valid_0 & io_requestor_2_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_no_resp_0 = ~io_requestor_0_req_valid_0 & ~io_requestor_1_req_valid_0 & io_requestor_2_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? 8'h0 : io_requestor_1_req_valid_0 ? 8'h1 : _io_mem_req_bits_tag_T[7:0]; // @[HellaCacheArbiter.scala:10:7, :34:{29,35}, :50:26] wire _T_2 = s1_id == 2'h0; // @[HellaCacheArbiter.scala:20:20, :51:21] assign io_mem_s1_kill_0 = _T_2 ? io_requestor_0_s1_kill_0 : ~_T & io_requestor_2_s1_kill_0; // @[HellaCacheArbiter.scala:10:7, :38:24, :51:{21,30}] assign io_mem_s1_data_data_0 = _T_2 ? 64'h0 : _T ? io_requestor_1_s1_data_data_0 : io_requestor_2_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7, :39:24, :51:{21,30}] assign io_mem_s1_data_mask_0 = _T_2 | ~_T ? 8'h0 : io_requestor_1_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7, :38:24, :39:24, :51:{21,30}] wire _io_requestor_0_s2_nack_T = s2_id == 2'h0; // @[HellaCacheArbiter.scala:21:24, :52:21, :68:58] wire [1:0] _tag_hit_T = io_mem_resp_bits_tag_0[1:0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire [1:0] _tag_hit_T_1 = io_mem_resp_bits_tag_0[1:0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire [1:0] _tag_hit_T_2 = io_mem_resp_bits_tag_0[1:0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire tag_hit = _tag_hit_T == 2'h0; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] wire [5:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:2]; // @[HellaCacheArbiter.scala:10:7, :74:45] wire [5:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:2]; // @[HellaCacheArbiter.scala:10:7, :74:45] wire [5:0] _io_requestor_2_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:2]; // @[HellaCacheArbiter.scala:10:7, :74:45] assign io_requestor_0_resp_bits_tag_0 = {2'h0, _io_requestor_0_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] wire tag_hit_1 = _tag_hit_T_1 == 2'h1; // @[HellaCacheArbiter.scala:51:21, :60:{41,57}] assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] assign io_requestor_1_resp_bits_tag_0 = {2'h0, _io_requestor_1_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] wire tag_hit_2 = _tag_hit_T_2 == 2'h2; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_2_resp_valid_T = io_mem_resp_valid_0 & tag_hit_2; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_2_resp_valid_0 = _io_requestor_2_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] wire _io_requestor_2_s2_nack_T = s2_id == 2'h2; // @[HellaCacheArbiter.scala:21:24, :68:58] assign _io_requestor_2_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_2_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_2_s2_nack_0 = _io_requestor_2_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] assign io_requestor_2_resp_bits_tag_0 = {2'h0, _io_requestor_2_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] always @(posedge clock) begin // @[HellaCacheArbiter.scala:10:7] s1_id <= io_requestor_0_req_valid_0 ? 2'h0 : io_requestor_1_req_valid_0 ? 2'h1 : 2'h2; // @[HellaCacheArbiter.scala:10:7, :20:20, :35:15, :50:26, :51:21] s2_id <= s1_id; // @[HellaCacheArbiter.scala:20:20, :21:24] always @(posedge) assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack_cause_raw = io_requestor_0_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_uncached = io_requestor_0_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_paddr = io_requestor_0_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_cmd = io_requestor_0_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_signed = io_requestor_0_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_mask = io_requestor_0_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_replay = io_requestor_0_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_store_data = io_requestor_0_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_replay_next = io_requestor_0_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_gpa = io_requestor_0_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_release = io_requestor_0_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_tlbMiss = io_requestor_0_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_blocked = io_requestor_0_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenLoad = io_requestor_0_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenRMW = io_requestor_0_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptLoadThenLoad = io_requestor_0_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterLoad = io_requestor_0_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterStore = io_requestor_0_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack_cause_raw = io_requestor_1_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_uncached = io_requestor_1_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_paddr = io_requestor_1_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_addr = io_requestor_1_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_cmd = io_requestor_1_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_signed = io_requestor_1_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dprv = io_requestor_1_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dv = io_requestor_1_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_mask = io_requestor_1_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_replay = io_requestor_1_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_word_bypass = io_requestor_1_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_raw = io_requestor_1_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_store_data = io_requestor_1_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_replay_next = io_requestor_1_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_ld = io_requestor_1_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_st = io_requestor_1_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_ld = io_requestor_1_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_st = io_requestor_1_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_ld = io_requestor_1_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_st = io_requestor_1_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_gpa = io_requestor_1_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_release = io_requestor_1_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_tlbMiss = io_requestor_1_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_blocked = io_requestor_1_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenLoad = io_requestor_1_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenRMW = io_requestor_1_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptLoadThenLoad = io_requestor_1_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterLoad = io_requestor_1_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterStore = io_requestor_1_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_req_ready = io_requestor_2_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_nack = io_requestor_2_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_nack_cause_raw = io_requestor_2_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_uncached = io_requestor_2_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_paddr = io_requestor_2_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_valid = io_requestor_2_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_addr = io_requestor_2_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_tag = io_requestor_2_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_cmd = io_requestor_2_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_size = io_requestor_2_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_signed = io_requestor_2_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_dprv = io_requestor_2_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_dv = io_requestor_2_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_data = io_requestor_2_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_mask = io_requestor_2_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_replay = io_requestor_2_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_has_data = io_requestor_2_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_data_word_bypass = io_requestor_2_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_data_raw = io_requestor_2_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_store_data = io_requestor_2_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_replay_next = io_requestor_2_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ma_ld = io_requestor_2_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ma_st = io_requestor_2_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_pf_ld = io_requestor_2_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_pf_st = io_requestor_2_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ae_ld = io_requestor_2_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ae_st = io_requestor_2_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_gpa = io_requestor_2_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_ordered = io_requestor_2_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_store_pending = io_requestor_2_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_acquire = io_requestor_2_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_release = io_requestor_2_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_grant = io_requestor_2_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_tlbMiss = io_requestor_2_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_blocked = io_requestor_2_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_canAcceptStoreThenLoad = io_requestor_2_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_canAcceptStoreThenRMW = io_requestor_2_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_canAcceptLoadThenLoad = io_requestor_2_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_storeBufferEmptyAfterLoad = io_requestor_2_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_storeBufferEmptyAfterStore = io_requestor_2_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_cmd = io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_size = io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_signed = io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dprv = io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_phys = io_mem_req_bits_phys_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_no_resp = io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_mask = io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_keep_clock_enabled = io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] endmodule